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ixgbe: DCB: remove DCB check config
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
1da177e4 27
99f252b0 28#include <asm/system.h>
1da177e4
LT		 29#include <asm/io.h>
30#include <asm/irq.h>
31
865c652d 32#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 33#define MODULENAME "r8169"
34#define PFX MODULENAME ": "
35
36#ifdef RTL8169_DEBUG
37#define assert(expr) \
5b0384f4
FR		 38 if (!(expr)) { \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 40 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 41 }
06fa7358
JP		 42#define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 44#else
45#define assert(expr) do {} while (0)
46#define dprintk(fmt, args...) do {} while (0)
47#endif /* RTL8169_DEBUG */
48
b57b7e5a 49#define R8169_MSG_DEFAULT \
f0e837d9 50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 51
1da177e4
LT		 52#define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54
1da177e4
LT		 55/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 57static const int multicast_filter_limit = 32;
1da177e4
LT		 58
59/* MAC address length */
60#define MAC_ADDR_LEN 6
61
9c14ceaf 62#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 63#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 66#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 67#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69
70#define R8169_REGS_SIZE 256
71#define R8169_NAPI_WEIGHT 64
72#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74#define RX_BUF_SIZE 1536 /* Rx Buffer size */
75#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77
78#define RTL8169_TX_TIMEOUT (6*HZ)
79#define RTL8169_PHY_TIMEOUT (10*HZ)
80
ea8dbdd1 81#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 83#define RTL_EEPROM_SIG_ADDR 0x0000
84
1da177e4
LT		 85/* write/read MMIO register */
86#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89#define RTL_R8(reg) readb (ioaddr + (reg))
90#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 91#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 92
93enum mac_version {
f21b75e9 94 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 95 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
96 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 100 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 101 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 105 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 106 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 114 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 115 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 116 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 117 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 118 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 119 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
1da177e4
LT		 122};
123
1da177e4
LT		 124#define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126
3c6bee1d 127static const struct {
1da177e4
LT		 128 const char *name;
129 u8 mac_version;
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131} rtl_chip_info[] = {
ba6eb6ee
FR		 132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
1da177e4
LT		 159};
160#undef _R
161
bcf0bf90
FR		 162enum cfg_version {
163 RTL_CFG_0 = 0x00,
164 RTL_CFG_1,
165 RTL_CFG_2
166};
167
07ce4064
FR		 168static void rtl_hw_start_8169(struct net_device *);
169static void rtl_hw_start_8168(struct net_device *);
170static void rtl_hw_start_8101(struct net_device *);
171
a3aa1884 172static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 179 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
181 { PCI_VENDOR_ID_LINKSYS, 0x1032,
182 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 183 { 0x0001, 0x8168,
184 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 185 {0,},
186};
187
188MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
189
c0cd884a
NH		 190/*
191 * we set our copybreak very high so that we don't have
192 * to allocate 16k frames all the time (see note in
193 * rtl8169_open()
194 */
195static int rx_copybreak = 16383;
4300e8c7 196static int use_dac;
b57b7e5a
SH		 197static struct {
198 u32 msg_enable;
199} debug = { -1 };
1da177e4 200
07d3f51f
FR		 201enum rtl_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
773d2021 203 MAC4 = 4,
07d3f51f
FR		 204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3c,
216 IntrStatus = 0x3e,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4c,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5c,
228 PHYAR = 0x60,
07d3f51f
FR		 229 PHYstatus = 0x6c,
230 RxMaxSize = 0xda,
231 CPlusCmd = 0xe0,
232 IntrMitigate = 0xe2,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
235 EarlyTxThres = 0xec,
236 FuncEvent = 0xf0,
237 FuncEventMask = 0xf4,
238 FuncPresetState = 0xf8,
239 FuncForceEvent = 0xfc,
1da177e4
LT		 240};
241
f162a5d1
FR		 242enum rtl8110_registers {
243 TBICSR = 0x64,
244 TBI_ANAR = 0x68,
245 TBI_LPAR = 0x6a,
246};
247
248enum rtl8168_8101_registers {
249 CSIDR = 0x64,
250 CSIAR = 0x68,
251#define CSIAR_FLAG 0x80000000
252#define CSIAR_WRITE_CMD 0x80000000
253#define CSIAR_BYTE_ENABLE 0x0f
254#define CSIAR_BYTE_ENABLE_SHIFT 12
255#define CSIAR_ADDR_MASK 0x0fff
256
257 EPHYAR = 0x80,
258#define EPHYAR_FLAG 0x80000000
259#define EPHYAR_WRITE_CMD 0x80000000
260#define EPHYAR_REG_MASK 0x1f
261#define EPHYAR_REG_SHIFT 16
262#define EPHYAR_DATA_MASK 0xffff
263 DBG_REG = 0xd1,
264#define FIX_NAK_1 (1 << 4)
265#define FIX_NAK_2 (1 << 3)
daf9df6d 266 EFUSEAR = 0xdc,
267#define EFUSEAR_FLAG 0x80000000
268#define EFUSEAR_WRITE_CMD 0x80000000
269#define EFUSEAR_READ_CMD 0x00000000
270#define EFUSEAR_REG_MASK 0x03ff
271#define EFUSEAR_REG_SHIFT 8
272#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 273};
274
07d3f51f 275enum rtl_register_content {
1da177e4 276 /* InterruptStatusBits */
07d3f51f
FR		 277 SYSErr = 0x8000,
278 PCSTimeout = 0x4000,
279 SWInt = 0x0100,
280 TxDescUnavail = 0x0080,
281 RxFIFOOver = 0x0040,
282 LinkChg = 0x0020,
283 RxOverflow = 0x0010,
284 TxErr = 0x0008,
285 TxOK = 0x0004,
286 RxErr = 0x0002,
287 RxOK = 0x0001,
1da177e4
LT		 288
289 /* RxStatusDesc */
9dccf611
FR		 290 RxFOVF = (1 << 23),
291 RxRWT = (1 << 22),
292 RxRES = (1 << 21),
293 RxRUNT = (1 << 20),
294 RxCRC = (1 << 19),
1da177e4
LT		 295
296 /* ChipCmdBits */
07d3f51f
FR		 297 CmdReset = 0x10,
298 CmdRxEnb = 0x08,
299 CmdTxEnb = 0x04,
300 RxBufEmpty = 0x01,
1da177e4 301
275391a4
FR		 302 /* TXPoll register p.5 */
303 HPQ = 0x80, /* Poll cmd on the high prio queue */
304 NPQ = 0x40, /* Poll cmd on the low prio queue */
305 FSWInt = 0x01, /* Forced software interrupt */
306
1da177e4 307 /* Cfg9346Bits */
07d3f51f
FR		 308 Cfg9346_Lock = 0x00,
309 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 310
311 /* rx_mode_bits */
07d3f51f
FR		 312 AcceptErr = 0x20,
313 AcceptRunt = 0x10,
314 AcceptBroadcast = 0x08,
315 AcceptMulticast = 0x04,
316 AcceptMyPhys = 0x02,
317 AcceptAllPhys = 0x01,
1da177e4
LT		 318
319 /* RxConfigBits */
07d3f51f
FR		 320 RxCfgFIFOShift = 13,
321 RxCfgDMAShift = 8,
1da177e4
LT		 322
323 /* TxConfigBits */
324 TxInterFrameGapShift = 24,
325 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
326
5d06a99f 327 /* Config1 register p.24 */
f162a5d1
FR		 328 LEDS1 = (1 << 7),
329 LEDS0 = (1 << 6),
fbac58fc 330 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 331 Speed_down = (1 << 4),
332 MEMMAP = (1 << 3),
333 IOMAP = (1 << 2),
334 VPD = (1 << 1),
5d06a99f
FR		 335 PMEnable = (1 << 0), /* Power Management Enable */
336
6dccd16b
FR		 337 /* Config2 register p. 25 */
338 PCI_Clock_66MHz = 0x01,
339 PCI_Clock_33MHz = 0x00,
340
61a4dcc2
FR		 341 /* Config3 register p.25 */
342 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
343 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 344 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 345
5d06a99f 346 /* Config5 register p.27 */
61a4dcc2
FR		 347 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
348 MWF = (1 << 5), /* Accept Multicast wakeup frame */
349 UWF = (1 << 4), /* Accept Unicast wakeup frame */
350 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 351 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
352
1da177e4
LT		 353 /* TBICSR p.28 */
354 TBIReset = 0x80000000,
355 TBILoopback = 0x40000000,
356 TBINwEnable = 0x20000000,
357 TBINwRestart = 0x10000000,
358 TBILinkOk = 0x02000000,
359 TBINwComplete = 0x01000000,
360
361 /* CPlusCmd p.31 */
f162a5d1
FR		 362 EnableBist = (1 << 15), // 8168 8101
363 Mac_dbgo_oe = (1 << 14), // 8168 8101
364 Normal_mode = (1 << 13), // unused
365 Force_half_dup = (1 << 12), // 8168 8101
366 Force_rxflow_en = (1 << 11), // 8168 8101
367 Force_txflow_en = (1 << 10), // 8168 8101
368 Cxpl_dbg_sel = (1 << 9), // 8168 8101
369 ASF = (1 << 8), // 8168 8101
370 PktCntrDisable = (1 << 7), // 8168 8101
371 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 372 RxVlan = (1 << 6),
373 RxChkSum = (1 << 5),
374 PCIDAC = (1 << 4),
375 PCIMulRW = (1 << 3),
0e485150
FR		 376 INTT_0 = 0x0000, // 8168
377 INTT_1 = 0x0001, // 8168
378 INTT_2 = 0x0002, // 8168
379 INTT_3 = 0x0003, // 8168
1da177e4
LT		 380
381 /* rtl8169_PHYstatus */
07d3f51f
FR		 382 TBI_Enable = 0x80,
383 TxFlowCtrl = 0x40,
384 RxFlowCtrl = 0x20,
385 _1000bpsF = 0x10,
386 _100bps = 0x08,
387 _10bps = 0x04,
388 LinkStatus = 0x02,
389 FullDup = 0x01,
1da177e4 390
1da177e4 391 /* _TBICSRBit */
07d3f51f 392 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 393
394 /* DumpCounterCommand */
07d3f51f 395 CounterDump = 0x8,
1da177e4
LT		 396};
397
07d3f51f 398enum desc_status_bit {
1da177e4
LT		 399 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
400 RingEnd = (1 << 30), /* End of descriptor ring */
401 FirstFrag = (1 << 29), /* First segment of a packet */
402 LastFrag = (1 << 28), /* Final segment of a packet */
403
404 /* Tx private */
405 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
406 MSSShift = 16, /* MSS value position */
407 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
408 IPCS = (1 << 18), /* Calculate IP checksum */
409 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
410 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
411 TxVlanTag = (1 << 17), /* Add VLAN tag */
412
413 /* Rx private */
414 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
415 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
416
417#define RxProtoUDP (PID1)
418#define RxProtoTCP (PID0)
419#define RxProtoIP (PID1 | PID0)
420#define RxProtoMask RxProtoIP
421
422 IPFail = (1 << 16), /* IP checksum failed */
423 UDPFail = (1 << 15), /* UDP/IP checksum failed */
424 TCPFail = (1 << 14), /* TCP/IP checksum failed */
425 RxVlanTag = (1 << 16), /* VLAN tag available */
426};
427
428#define RsvdMask 0x3fffc000
429
430struct TxDesc {
6cccd6e7
REB		 431 __le32 opts1;
432 __le32 opts2;
433 __le64 addr;
1da177e4
LT		 434};
435
436struct RxDesc {
6cccd6e7
REB		 437 __le32 opts1;
438 __le32 opts2;
439 __le64 addr;
1da177e4
LT		 440};
441
442struct ring_info {
443 struct sk_buff *skb;
444 u32 len;
445 u8 __pad[sizeof(void *) - sizeof(u32)];
446};
447
f23e7fda 448enum features {
ccdffb9a
FR		 449 RTL_FEATURE_WOL = (1 << 0),
450 RTL_FEATURE_MSI = (1 << 1),
451 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 452};
453
355423d0
IV		 454struct rtl8169_counters {
455 __le64 tx_packets;
456 __le64 rx_packets;
457 __le64 tx_errors;
458 __le32 rx_errors;
459 __le16 rx_missed;
460 __le16 align_errors;
461 __le32 tx_one_collision;
462 __le32 tx_multi_collision;
463 __le64 rx_unicast;
464 __le64 rx_broadcast;
465 __le32 rx_multicast;
466 __le16 tx_aborted;
467 __le16 tx_underun;
468};
469
1da177e4
LT		 470struct rtl8169_private {
471 void __iomem *mmio_addr; /* memory map physical address */
472 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 473 struct net_device *dev;
bea3348e 474 struct napi_struct napi;
1da177e4 475 spinlock_t lock; /* spin lock flag */
b57b7e5a 476 u32 msg_enable;
1da177e4
LT		 477 int chipset;
478 int mac_version;
1da177e4
LT		 479 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
480 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
481 u32 dirty_rx;
482 u32 dirty_tx;
483 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
484 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
485 dma_addr_t TxPhyAddr;
486 dma_addr_t RxPhyAddr;
487 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
488 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 489 unsigned align;
1da177e4
LT		 490 unsigned rx_buf_sz;
491 struct timer_list timer;
492 u16 cp_cmd;
0e485150
FR		 493 u16 intr_event;
494 u16 napi_event;
1da177e4 495 u16 intr_mask;
1da177e4
LT		 496 int phy_1000_ctrl_reg;
497#ifdef CONFIG_R8169_VLAN
498 struct vlan_group *vlgrp;
499#endif
500 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 501 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 502 void (*phy_reset_enable)(void __iomem *);
07ce4064 503 void (*hw_start)(struct net_device *);
1da177e4
LT		 504 unsigned int (*phy_reset_pending)(void __iomem *);
505 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 506 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 507 int pcie_cap;
c4028958 508 struct delayed_work task;
f23e7fda 509 unsigned features;
ccdffb9a
FR		 510
511 struct mii_if_info mii;
355423d0 512 struct rtl8169_counters counters;
e1759441 513 u32 saved_wolopts;
1da177e4
LT		 514};
515
979b6c13 516MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 517MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 518module_param(rx_copybreak, int, 0);
1b7efd58 519MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4 520module_param(use_dac, int, 0);
4300e8c7 521MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 522module_param_named(debug, debug.msg_enable, int, 0);
523MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 524MODULE_LICENSE("GPL");
525MODULE_VERSION(RTL8169_VERSION);
526
527static int rtl8169_open(struct net_device *dev);
61357325
SH		 528static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
529 struct net_device *dev);
7d12e780 530static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 531static int rtl8169_init_ring(struct net_device *dev);
07ce4064 532static void rtl_hw_start(struct net_device *dev);
1da177e4 533static int rtl8169_close(struct net_device *dev);
07ce4064 534static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 535static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 536static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 537static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 538 void __iomem *, u32 budget);
4dcb7d33 539static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 540static void rtl8169_down(struct net_device *dev);
99f252b0 541static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 542static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 543
1da177e4 544static const unsigned int rtl8169_rx_config =
5b0384f4 545 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 546
07d3f51f 547static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 548{
549 int i;
550
a6baf3af 551 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 552
2371408c 553 for (i = 20; i > 0; i--) {
07d3f51f
FR		 554 /*
555 * Check if the RTL8169 has completed writing to the specified
556 * MII register.
557 */
5b0384f4 558 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 559 break;
2371408c 560 udelay(25);
1da177e4 561 }
024a07ba 562 /*
81a95f04
TT		 563 * According to hardware specs a 20us delay is required after write
564 * complete indication, but before sending next command.
024a07ba 565 */
81a95f04 566 udelay(20);
1da177e4
LT		 567}
568
07d3f51f 569static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 570{
571 int i, value = -1;
572
a6baf3af 573 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 574
2371408c 575 for (i = 20; i > 0; i--) {
07d3f51f
FR		 576 /*
577 * Check if the RTL8169 has completed retrieving data from
578 * the specified MII register.
579 */
1da177e4 580 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 581 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 582 break;
583 }
2371408c 584 udelay(25);
1da177e4 585 }
81a95f04
TT		 586 /*
587 * According to hardware specs a 20us delay is required after read
588 * complete indication, but before sending next command.
589 */
590 udelay(20);
591
1da177e4
LT		 592 return value;
593}
594
dacf8154
FR		 595static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
596{
597 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
598}
599
daf9df6d 600static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
601{
602 int val;
603
604 val = mdio_read(ioaddr, reg_addr);
605 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
606}
607
ccdffb9a
FR		 608static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
609 int val)
610{
611 struct rtl8169_private *tp = netdev_priv(dev);
612 void __iomem *ioaddr = tp->mmio_addr;
613
614 mdio_write(ioaddr, location, val);
615}
616
617static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
618{
619 struct rtl8169_private *tp = netdev_priv(dev);
620 void __iomem *ioaddr = tp->mmio_addr;
621
622 return mdio_read(ioaddr, location);
623}
624
dacf8154
FR		 625static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
626{
627 unsigned int i;
628
629 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
630 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
631
632 for (i = 0; i < 100; i++) {
633 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
634 break;
635 udelay(10);
636 }
637}
638
639static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
640{
641 u16 value = 0xffff;
642 unsigned int i;
643
644 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
645
646 for (i = 0; i < 100; i++) {
647 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
648 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
649 break;
650 }
651 udelay(10);
652 }
653
654 return value;
655}
656
657static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
658{
659 unsigned int i;
660
661 RTL_W32(CSIDR, value);
662 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
663 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
664
665 for (i = 0; i < 100; i++) {
666 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
667 break;
668 udelay(10);
669 }
670}
671
672static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
673{
674 u32 value = ~0x00;
675 unsigned int i;
676
677 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
678 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
679
680 for (i = 0; i < 100; i++) {
681 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
682 value = RTL_R32(CSIDR);
683 break;
684 }
685 udelay(10);
686 }
687
688 return value;
689}
690
daf9df6d 691static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
692{
693 u8 value = 0xff;
694 unsigned int i;
695
696 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
697
698 for (i = 0; i < 300; i++) {
699 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
700 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
701 break;
702 }
703 udelay(100);
704 }
705
706 return value;
707}
708
1da177e4
LT		 709static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
710{
711 RTL_W16(IntrMask, 0x0000);
712
713 RTL_W16(IntrStatus, 0xffff);
714}
715
716static void rtl8169_asic_down(void __iomem *ioaddr)
717{
718 RTL_W8(ChipCmd, 0x00);
719 rtl8169_irq_mask_and_ack(ioaddr);
720 RTL_R16(CPlusCmd);
721}
722
723static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
724{
725 return RTL_R32(TBICSR) & TBIReset;
726}
727
728static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
729{
64e4bfb4 730 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 731}
732
733static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
734{
735 return RTL_R32(TBICSR) & TBILinkOk;
736}
737
738static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
739{
740 return RTL_R8(PHYstatus) & LinkStatus;
741}
742
743static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
744{
745 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
746}
747
748static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
749{
750 unsigned int val;
751
9e0db8ef
FR		 752 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
753 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 754}
755
756static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 757 struct rtl8169_private *tp,
758 void __iomem *ioaddr)
1da177e4
LT		 759{
760 unsigned long flags;
761
762 spin_lock_irqsave(&tp->lock, flags);
763 if (tp->link_ok(ioaddr)) {
e1759441
RW		 764 /* This is to cancel a scheduled suspend if there's one. */
765 pm_request_resume(&tp->pci_dev->dev);
1da177e4 766 netif_carrier_on(dev);
bf82c189 767 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 768 } else {
1da177e4 769 netif_carrier_off(dev);
bf82c189 770 netif_info(tp, ifdown, dev, "link down\n");
e1759441 771 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 772 }
1da177e4
LT		 773 spin_unlock_irqrestore(&tp->lock, flags);
774}
775
e1759441
RW		 776#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
777
778static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 779{
61a4dcc2
FR		 780 void __iomem *ioaddr = tp->mmio_addr;
781 u8 options;
e1759441 782 u32 wolopts = 0;
61a4dcc2
FR		 783
784 options = RTL_R8(Config1);
785 if (!(options & PMEnable))
e1759441 786 return 0;
61a4dcc2
FR		 787
788 options = RTL_R8(Config3);
789 if (options & LinkUp)
e1759441 790 wolopts |= WAKE_PHY;
61a4dcc2 791 if (options & MagicPacket)
e1759441 792 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 793
794 options = RTL_R8(Config5);
795 if (options & UWF)
e1759441 796 wolopts |= WAKE_UCAST;
61a4dcc2 797 if (options & BWF)
e1759441 798 wolopts |= WAKE_BCAST;
61a4dcc2 799 if (options & MWF)
e1759441 800 wolopts |= WAKE_MCAST;
61a4dcc2 801
e1759441 802 return wolopts;
61a4dcc2
FR		 803}
804
e1759441 805static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 806{
807 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 808
809 spin_lock_irq(&tp->lock);
810
811 wol->supported = WAKE_ANY;
812 wol->wolopts = __rtl8169_get_wol(tp);
813
814 spin_unlock_irq(&tp->lock);
815}
816
817static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
818{
61a4dcc2 819 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 820 unsigned int i;
350f7596 821 static const struct {
61a4dcc2
FR		 822 u32 opt;
823 u16 reg;
824 u8 mask;
825 } cfg[] = {
826 { WAKE_ANY, Config1, PMEnable },
827 { WAKE_PHY, Config3, LinkUp },
828 { WAKE_MAGIC, Config3, MagicPacket },
829 { WAKE_UCAST, Config5, UWF },
830 { WAKE_BCAST, Config5, BWF },
831 { WAKE_MCAST, Config5, MWF },
832 { WAKE_ANY, Config5, LanWake }
833 };
834
61a4dcc2
FR		 835 RTL_W8(Cfg9346, Cfg9346_Unlock);
836
837 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
838 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 839 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 840 options |= cfg[i].mask;
841 RTL_W8(cfg[i].reg, options);
842 }
843
844 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 845}
846
847static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
848{
849 struct rtl8169_private *tp = netdev_priv(dev);
850
851 spin_lock_irq(&tp->lock);
61a4dcc2 852
f23e7fda
FR		 853 if (wol->wolopts)
854 tp->features |= RTL_FEATURE_WOL;
855 else
856 tp->features &= ~RTL_FEATURE_WOL;
e1759441 857 __rtl8169_set_wol(tp, wol->wolopts);
8b76ab39 858 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 859
860 spin_unlock_irq(&tp->lock);
861
862 return 0;
863}
864
1da177e4
LT		 865static void rtl8169_get_drvinfo(struct net_device *dev,
866 struct ethtool_drvinfo *info)
867{
868 struct rtl8169_private *tp = netdev_priv(dev);
869
870 strcpy(info->driver, MODULENAME);
871 strcpy(info->version, RTL8169_VERSION);
872 strcpy(info->bus_info, pci_name(tp->pci_dev));
873}
874
875static int rtl8169_get_regs_len(struct net_device *dev)
876{
877 return R8169_REGS_SIZE;
878}
879
880static int rtl8169_set_speed_tbi(struct net_device *dev,
881 u8 autoneg, u16 speed, u8 duplex)
882{
883 struct rtl8169_private *tp = netdev_priv(dev);
884 void __iomem *ioaddr = tp->mmio_addr;
885 int ret = 0;
886 u32 reg;
887
888 reg = RTL_R32(TBICSR);
889 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
890 (duplex == DUPLEX_FULL)) {
891 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
892 } else if (autoneg == AUTONEG_ENABLE)
893 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
894 else {
bf82c189
JP		 895 netif_warn(tp, link, dev,
896 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 897 ret = -EOPNOTSUPP;
898 }
899
900 return ret;
901}
902
903static int rtl8169_set_speed_xmii(struct net_device *dev,
904 u8 autoneg, u16 speed, u8 duplex)
905{
906 struct rtl8169_private *tp = netdev_priv(dev);
907 void __iomem *ioaddr = tp->mmio_addr;
3577aa1b 908 int giga_ctrl, bmcr;
1da177e4
LT		 909
910 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 911 int auto_nego;
912
913 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
64e4bfb4
FR		 914 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
915 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 916 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 917
3577aa1b 918 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
919 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 920
3577aa1b 921 /* The 8100e/8101e/8102e do Fast Ethernet only. */
922 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
923 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
924 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
925 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
926 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
927 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
928 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
929 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
930 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 931 } else {
932 netif_info(tp, link, dev,
933 "PHY does not support 1000Mbps\n");
bcf0bf90 934 }
1da177e4 935
3577aa1b 936 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
937
938 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
939 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
940 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
941 /*
942 * Wake up the PHY.
943 * Vendor specific (0x1f) and reserved (0x0e) MII
944 * registers.
945 */
946 mdio_write(ioaddr, 0x1f, 0x0000);
947 mdio_write(ioaddr, 0x0e, 0x0000);
948 }
949
950 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
951 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
952 } else {
953 giga_ctrl = 0;
954
955 if (speed == SPEED_10)
956 bmcr = 0;
957 else if (speed == SPEED_100)
958 bmcr = BMCR_SPEED100;
959 else
960 return -EINVAL;
961
962 if (duplex == DUPLEX_FULL)
963 bmcr |= BMCR_FULLDPLX;
623a1593 964
2584fbc3 965 mdio_write(ioaddr, 0x1f, 0x0000);
2584fbc3
RS		 966 }
967
1da177e4
LT		 968 tp->phy_1000_ctrl_reg = giga_ctrl;
969
3577aa1b 970 mdio_write(ioaddr, MII_BMCR, bmcr);
971
972 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
973 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
974 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
975 mdio_write(ioaddr, 0x17, 0x2138);
976 mdio_write(ioaddr, 0x0e, 0x0260);
977 } else {
978 mdio_write(ioaddr, 0x17, 0x2108);
979 mdio_write(ioaddr, 0x0e, 0x0000);
980 }
981 }
982
1da177e4
LT		 983 return 0;
984}
985
986static int rtl8169_set_speed(struct net_device *dev,
987 u8 autoneg, u16 speed, u8 duplex)
988{
989 struct rtl8169_private *tp = netdev_priv(dev);
990 int ret;
991
992 ret = tp->set_speed(dev, autoneg, speed, duplex);
993
64e4bfb4 994 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 995 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
996
997 return ret;
998}
999
1000static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1001{
1002 struct rtl8169_private *tp = netdev_priv(dev);
1003 unsigned long flags;
1004 int ret;
1005
1006 spin_lock_irqsave(&tp->lock, flags);
1007 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1008 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1009
1da177e4
LT		 1010 return ret;
1011}
1012
1013static u32 rtl8169_get_rx_csum(struct net_device *dev)
1014{
1015 struct rtl8169_private *tp = netdev_priv(dev);
1016
1017 return tp->cp_cmd & RxChkSum;
1018}
1019
1020static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1021{
1022 struct rtl8169_private *tp = netdev_priv(dev);
1023 void __iomem *ioaddr = tp->mmio_addr;
1024 unsigned long flags;
1025
1026 spin_lock_irqsave(&tp->lock, flags);
1027
1028 if (data)
1029 tp->cp_cmd |= RxChkSum;
1030 else
1031 tp->cp_cmd &= ~RxChkSum;
1032
1033 RTL_W16(CPlusCmd, tp->cp_cmd);
1034 RTL_R16(CPlusCmd);
1035
1036 spin_unlock_irqrestore(&tp->lock, flags);
1037
1038 return 0;
1039}
1040
1041#ifdef CONFIG_R8169_VLAN
1042
1043static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1044 struct sk_buff *skb)
1045{
1046 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1047 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1048}
1049
1050static void rtl8169_vlan_rx_register(struct net_device *dev,
1051 struct vlan_group *grp)
1052{
1053 struct rtl8169_private *tp = netdev_priv(dev);
1054 void __iomem *ioaddr = tp->mmio_addr;
1055 unsigned long flags;
1056
1057 spin_lock_irqsave(&tp->lock, flags);
1058 tp->vlgrp = grp;
05af2142
SW		 1059 /*
1060 * Do not disable RxVlan on 8110SCd.
1061 */
1062 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1063 tp->cp_cmd |= RxVlan;
1064 else
1065 tp->cp_cmd &= ~RxVlan;
1066 RTL_W16(CPlusCmd, tp->cp_cmd);
1067 RTL_R16(CPlusCmd);
1068 spin_unlock_irqrestore(&tp->lock, flags);
1069}
1070
1da177e4 1071static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1072 struct sk_buff *skb, int polling)
1da177e4
LT		 1073{
1074 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1075 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1076 int ret;
1077
865c652d 1078 if (vlgrp && (opts2 & RxVlanTag)) {
2edae08e
ED		 1079 u16 vtag = swab16(opts2 & 0xffff);
1080
1081 if (likely(polling))
1082 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1083 else
1084 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1da177e4
LT		 1085 ret = 0;
1086 } else
1087 ret = -1;
1088 desc->opts2 = 0;
1089 return ret;
1090}
1091
1092#else /* !CONFIG_R8169_VLAN */
1093
1094static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1095 struct sk_buff *skb)
1096{
1097 return 0;
1098}
1099
1100static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1101 struct sk_buff *skb, int polling)
1da177e4
LT		 1102{
1103 return -1;
1104}
1105
1106#endif
1107
ccdffb9a 1108static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1109{
1110 struct rtl8169_private *tp = netdev_priv(dev);
1111 void __iomem *ioaddr = tp->mmio_addr;
1112 u32 status;
1113
1114 cmd->supported =
1115 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1116 cmd->port = PORT_FIBRE;
1117 cmd->transceiver = XCVR_INTERNAL;
1118
1119 status = RTL_R32(TBICSR);
1120 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1121 cmd->autoneg = !!(status & TBINwEnable);
1122
1123 cmd->speed = SPEED_1000;
1124 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1125
1126 return 0;
1da177e4
LT		 1127}
1128
ccdffb9a 1129static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1130{
1131 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1132
1133 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1134}
1135
1136static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1137{
1138 struct rtl8169_private *tp = netdev_priv(dev);
1139 unsigned long flags;
ccdffb9a 1140 int rc;
1da177e4
LT		 1141
1142 spin_lock_irqsave(&tp->lock, flags);
1143
ccdffb9a 1144 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1145
1146 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1147 return rc;
1da177e4
LT		 1148}
1149
1150static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1151 void *p)
1152{
5b0384f4
FR		 1153 struct rtl8169_private *tp = netdev_priv(dev);
1154 unsigned long flags;
1da177e4 1155
5b0384f4
FR		 1156 if (regs->len > R8169_REGS_SIZE)
1157 regs->len = R8169_REGS_SIZE;
1da177e4 1158
5b0384f4
FR		 1159 spin_lock_irqsave(&tp->lock, flags);
1160 memcpy_fromio(p, tp->mmio_addr, regs->len);
1161 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1162}
1163
b57b7e5a
SH		 1164static u32 rtl8169_get_msglevel(struct net_device *dev)
1165{
1166 struct rtl8169_private *tp = netdev_priv(dev);
1167
1168 return tp->msg_enable;
1169}
1170
1171static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1172{
1173 struct rtl8169_private *tp = netdev_priv(dev);
1174
1175 tp->msg_enable = value;
1176}
1177
d4a3a0fc
SH		 1178static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1179 "tx_packets",
1180 "rx_packets",
1181 "tx_errors",
1182 "rx_errors",
1183 "rx_missed",
1184 "align_errors",
1185 "tx_single_collisions",
1186 "tx_multi_collisions",
1187 "unicast",
1188 "broadcast",
1189 "multicast",
1190 "tx_aborted",
1191 "tx_underrun",
1192};
1193
b9f2c044 1194static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1195{
b9f2c044
JG		 1196 switch (sset) {
1197 case ETH_SS_STATS:
1198 return ARRAY_SIZE(rtl8169_gstrings);
1199 default:
1200 return -EOPNOTSUPP;
1201 }
d4a3a0fc
SH		 1202}
1203
355423d0 1204static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1205{
1206 struct rtl8169_private *tp = netdev_priv(dev);
1207 void __iomem *ioaddr = tp->mmio_addr;
1208 struct rtl8169_counters *counters;
1209 dma_addr_t paddr;
1210 u32 cmd;
355423d0 1211 int wait = 1000;
d4a3a0fc 1212
355423d0
IV		 1213 /*
1214 * Some chips are unable to dump tally counters when the receiver
1215 * is disabled.
1216 */
1217 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1218 return;
d4a3a0fc 1219
82553bb6
SG		 1220 counters = dma_alloc_coherent(&tp->pci_dev->dev, sizeof(*counters),
1221 &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1222 if (!counters)
1223 return;
1224
1225 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1226 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1227 RTL_W32(CounterAddrLow, cmd);
1228 RTL_W32(CounterAddrLow, cmd | CounterDump);
1229
355423d0
IV		 1230 while (wait--) {
1231 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1232 /* copy updated counters */
1233 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1234 break;
355423d0
IV		 1235 }
1236 udelay(10);
d4a3a0fc
SH		 1237 }
1238
1239 RTL_W32(CounterAddrLow, 0);
1240 RTL_W32(CounterAddrHigh, 0);
1241
82553bb6
SG		 1242 dma_free_coherent(&tp->pci_dev->dev, sizeof(*counters), counters,
1243 paddr);
d4a3a0fc
SH		 1244}
1245
355423d0
IV		 1246static void rtl8169_get_ethtool_stats(struct net_device *dev,
1247 struct ethtool_stats *stats, u64 *data)
1248{
1249 struct rtl8169_private *tp = netdev_priv(dev);
1250
1251 ASSERT_RTNL();
1252
1253 rtl8169_update_counters(dev);
1254
1255 data[0] = le64_to_cpu(tp->counters.tx_packets);
1256 data[1] = le64_to_cpu(tp->counters.rx_packets);
1257 data[2] = le64_to_cpu(tp->counters.tx_errors);
1258 data[3] = le32_to_cpu(tp->counters.rx_errors);
1259 data[4] = le16_to_cpu(tp->counters.rx_missed);
1260 data[5] = le16_to_cpu(tp->counters.align_errors);
1261 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1262 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1263 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1264 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1265 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1266 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1267 data[12] = le16_to_cpu(tp->counters.tx_underun);
1268}
1269
d4a3a0fc
SH		 1270static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1271{
1272 switch(stringset) {
1273 case ETH_SS_STATS:
1274 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1275 break;
1276 }
1277}
1278
7282d491 1279static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1280 .get_drvinfo = rtl8169_get_drvinfo,
1281 .get_regs_len = rtl8169_get_regs_len,
1282 .get_link = ethtool_op_get_link,
1283 .get_settings = rtl8169_get_settings,
1284 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1285 .get_msglevel = rtl8169_get_msglevel,
1286 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1287 .get_rx_csum = rtl8169_get_rx_csum,
1288 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1289 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1290 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1291 .set_tso = ethtool_op_set_tso,
1292 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1293 .get_wol = rtl8169_get_wol,
1294 .set_wol = rtl8169_set_wol,
d4a3a0fc 1295 .get_strings = rtl8169_get_strings,
b9f2c044 1296 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1297 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1298};
1299
07d3f51f
FR		 1300static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1301 void __iomem *ioaddr)
1da177e4 1302{
0e485150
FR		 1303 /*
1304 * The driver currently handles the 8168Bf and the 8168Be identically
1305 * but they can be identified more specifically through the test below
1306 * if needed:
1307 *
1308 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1309 *
1310 * Same thing for the 8101Eb and the 8101Ec:
1311 *
1312 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1313 */
350f7596 1314 static const struct {
1da177e4 1315 u32 mask;
e3cf0cc0 1316 u32 val;
1da177e4
LT		 1317 int mac_version;
1318 } mac_info[] = {
5b538df9 1319 /* 8168D family. */
daf9df6d 1320 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1321 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1322 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1323 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1324
ef808d50 1325 /* 8168C family. */
17c99297 1326 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1327 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1328 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1329 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1330 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1331 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1332 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1333 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1334 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1335
1336 /* 8168B family. */
1337 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1338 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1339 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1340 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1341
1342 /* 8101 family. */
2857ffb7
FR		 1343 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1344 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1345 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1346 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1347 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1348 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1349 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1350 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1351 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1352 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1353 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1354 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1355 /* FIXME: where did these entries come from ? -- FR */
1356 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1357 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1358
1359 /* 8110 family. */
1360 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1361 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1362 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1363 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1364 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1365 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1366
f21b75e9
JD		 1367 /* Catch-all */
1368 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1369 }, *p = mac_info;
1370 u32 reg;
1371
e3cf0cc0
FR		 1372 reg = RTL_R32(TxConfig);
1373 while ((reg & p->mask) != p->val)
1da177e4
LT		 1374 p++;
1375 tp->mac_version = p->mac_version;
1376}
1377
1378static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1379{
bcf0bf90 1380 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1381}
1382
867763c1
FR		 1383struct phy_reg {
1384 u16 reg;
1385 u16 val;
1386};
1387
350f7596 1388static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
867763c1
FR		 1389{
1390 while (len-- > 0) {
1391 mdio_write(ioaddr, regs->reg, regs->val);
1392 regs++;
1393 }
1394}
1395
5615d9f1 1396static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1397{
350f7596 1398 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1399 { 0x1f, 0x0001 },
1400 { 0x06, 0x006e },
1401 { 0x08, 0x0708 },
1402 { 0x15, 0x4000 },
1403 { 0x18, 0x65c7 },
1da177e4 1404
0b9b571d 1405 { 0x1f, 0x0001 },
1406 { 0x03, 0x00a1 },
1407 { 0x02, 0x0008 },
1408 { 0x01, 0x0120 },
1409 { 0x00, 0x1000 },
1410 { 0x04, 0x0800 },
1411 { 0x04, 0x0000 },
1da177e4 1412
0b9b571d 1413 { 0x03, 0xff41 },
1414 { 0x02, 0xdf60 },
1415 { 0x01, 0x0140 },
1416 { 0x00, 0x0077 },
1417 { 0x04, 0x7800 },
1418 { 0x04, 0x7000 },
1419
1420 { 0x03, 0x802f },
1421 { 0x02, 0x4f02 },
1422 { 0x01, 0x0409 },
1423 { 0x00, 0xf0f9 },
1424 { 0x04, 0x9800 },
1425 { 0x04, 0x9000 },
1426
1427 { 0x03, 0xdf01 },
1428 { 0x02, 0xdf20 },
1429 { 0x01, 0xff95 },
1430 { 0x00, 0xba00 },
1431 { 0x04, 0xa800 },
1432 { 0x04, 0xa000 },
1433
1434 { 0x03, 0xff41 },
1435 { 0x02, 0xdf20 },
1436 { 0x01, 0x0140 },
1437 { 0x00, 0x00bb },
1438 { 0x04, 0xb800 },
1439 { 0x04, 0xb000 },
1440
1441 { 0x03, 0xdf41 },
1442 { 0x02, 0xdc60 },
1443 { 0x01, 0x6340 },
1444 { 0x00, 0x007d },
1445 { 0x04, 0xd800 },
1446 { 0x04, 0xd000 },
1447
1448 { 0x03, 0xdf01 },
1449 { 0x02, 0xdf20 },
1450 { 0x01, 0x100a },
1451 { 0x00, 0xa0ff },
1452 { 0x04, 0xf800 },
1453 { 0x04, 0xf000 },
1454
1455 { 0x1f, 0x0000 },
1456 { 0x0b, 0x0000 },
1457 { 0x00, 0x9200 }
1458 };
1da177e4 1459
0b9b571d 1460 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1461}
1462
5615d9f1
FR		 1463static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1464{
350f7596 1465 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1466 { 0x1f, 0x0002 },
1467 { 0x01, 0x90d0 },
1468 { 0x1f, 0x0000 }
1469 };
1470
1471 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1472}
1473
2e955856 1474static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1475 void __iomem *ioaddr)
1476{
1477 struct pci_dev *pdev = tp->pci_dev;
1478 u16 vendor_id, device_id;
1479
1480 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1481 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1482
1483 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1484 return;
1485
1486 mdio_write(ioaddr, 0x1f, 0x0001);
1487 mdio_write(ioaddr, 0x10, 0xf01b);
1488 mdio_write(ioaddr, 0x1f, 0x0000);
1489}
1490
1491static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1492 void __iomem *ioaddr)
1493{
350f7596 1494 static const struct phy_reg phy_reg_init[] = {
2e955856 1495 { 0x1f, 0x0001 },
1496 { 0x04, 0x0000 },
1497 { 0x03, 0x00a1 },
1498 { 0x02, 0x0008 },
1499 { 0x01, 0x0120 },
1500 { 0x00, 0x1000 },
1501 { 0x04, 0x0800 },
1502 { 0x04, 0x9000 },
1503 { 0x03, 0x802f },
1504 { 0x02, 0x4f02 },
1505 { 0x01, 0x0409 },
1506 { 0x00, 0xf099 },
1507 { 0x04, 0x9800 },
1508 { 0x04, 0xa000 },
1509 { 0x03, 0xdf01 },
1510 { 0x02, 0xdf20 },
1511 { 0x01, 0xff95 },
1512 { 0x00, 0xba00 },
1513 { 0x04, 0xa800 },
1514 { 0x04, 0xf000 },
1515 { 0x03, 0xdf01 },
1516 { 0x02, 0xdf20 },
1517 { 0x01, 0x101a },
1518 { 0x00, 0xa0ff },
1519 { 0x04, 0xf800 },
1520 { 0x04, 0x0000 },
1521 { 0x1f, 0x0000 },
1522
1523 { 0x1f, 0x0001 },
1524 { 0x10, 0xf41b },
1525 { 0x14, 0xfb54 },
1526 { 0x18, 0xf5c7 },
1527 { 0x1f, 0x0000 },
1528
1529 { 0x1f, 0x0001 },
1530 { 0x17, 0x0cc0 },
1531 { 0x1f, 0x0000 }
1532 };
1533
1534 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1535
1536 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1537}
1538
8c7006aa 1539static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1540{
350f7596 1541 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1542 { 0x1f, 0x0001 },
1543 { 0x04, 0x0000 },
1544 { 0x03, 0x00a1 },
1545 { 0x02, 0x0008 },
1546 { 0x01, 0x0120 },
1547 { 0x00, 0x1000 },
1548 { 0x04, 0x0800 },
1549 { 0x04, 0x9000 },
1550 { 0x03, 0x802f },
1551 { 0x02, 0x4f02 },
1552 { 0x01, 0x0409 },
1553 { 0x00, 0xf099 },
1554 { 0x04, 0x9800 },
1555 { 0x04, 0xa000 },
1556 { 0x03, 0xdf01 },
1557 { 0x02, 0xdf20 },
1558 { 0x01, 0xff95 },
1559 { 0x00, 0xba00 },
1560 { 0x04, 0xa800 },
1561 { 0x04, 0xf000 },
1562 { 0x03, 0xdf01 },
1563 { 0x02, 0xdf20 },
1564 { 0x01, 0x101a },
1565 { 0x00, 0xa0ff },
1566 { 0x04, 0xf800 },
1567 { 0x04, 0x0000 },
1568 { 0x1f, 0x0000 },
1569
1570 { 0x1f, 0x0001 },
1571 { 0x0b, 0x8480 },
1572 { 0x1f, 0x0000 },
1573
1574 { 0x1f, 0x0001 },
1575 { 0x18, 0x67c7 },
1576 { 0x04, 0x2000 },
1577 { 0x03, 0x002f },
1578 { 0x02, 0x4360 },
1579 { 0x01, 0x0109 },
1580 { 0x00, 0x3022 },
1581 { 0x04, 0x2800 },
1582 { 0x1f, 0x0000 },
1583
1584 { 0x1f, 0x0001 },
1585 { 0x17, 0x0cc0 },
1586 { 0x1f, 0x0000 }
1587 };
1588
1589 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1590}
1591
236b8082
FR		 1592static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1593{
350f7596 1594 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1595 { 0x10, 0xf41b },
1596 { 0x1f, 0x0000 }
1597 };
1598
1599 mdio_write(ioaddr, 0x1f, 0x0001);
1600 mdio_patch(ioaddr, 0x16, 1 << 0);
1601
1602 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1603}
1604
1605static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1606{
350f7596 1607 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1608 { 0x1f, 0x0001 },
1609 { 0x10, 0xf41b },
1610 { 0x1f, 0x0000 }
1611 };
1612
1613 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1614}
1615
ef3386f0 1616static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1617{
350f7596 1618 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1619 { 0x1f, 0x0000 },
1620 { 0x1d, 0x0f00 },
1621 { 0x1f, 0x0002 },
1622 { 0x0c, 0x1ec8 },
1623 { 0x1f, 0x0000 }
1624 };
1625
1626 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1627}
1628
ef3386f0
FR		 1629static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1630{
350f7596 1631 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 1632 { 0x1f, 0x0001 },
1633 { 0x1d, 0x3d98 },
1634 { 0x1f, 0x0000 }
1635 };
1636
1637 mdio_write(ioaddr, 0x1f, 0x0000);
1638 mdio_patch(ioaddr, 0x14, 1 << 5);
1639 mdio_patch(ioaddr, 0x0d, 1 << 5);
1640
1641 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1642}
1643
219a1e9d 1644static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1645{
350f7596 1646 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1647 { 0x1f, 0x0001 },
1648 { 0x12, 0x2300 },
867763c1
FR		 1649 { 0x1f, 0x0002 },
1650 { 0x00, 0x88d4 },
1651 { 0x01, 0x82b1 },
1652 { 0x03, 0x7002 },
1653 { 0x08, 0x9e30 },
1654 { 0x09, 0x01f0 },
1655 { 0x0a, 0x5500 },
1656 { 0x0c, 0x00c8 },
1657 { 0x1f, 0x0003 },
1658 { 0x12, 0xc096 },
1659 { 0x16, 0x000a },
f50d4275
FR		 1660 { 0x1f, 0x0000 },
1661 { 0x1f, 0x0000 },
1662 { 0x09, 0x2000 },
1663 { 0x09, 0x0000 }
867763c1
FR		 1664 };
1665
1666 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1667
1668 mdio_patch(ioaddr, 0x14, 1 << 5);
1669 mdio_patch(ioaddr, 0x0d, 1 << 5);
1670 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1671}
1672
219a1e9d 1673static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9 1674{
350f7596 1675 static const struct phy_reg phy_reg_init[] = {
f50d4275 1676 { 0x1f, 0x0001 },
7da97ec9 1677 { 0x12, 0x2300 },
f50d4275
FR		 1678 { 0x03, 0x802f },
1679 { 0x02, 0x4f02 },
1680 { 0x01, 0x0409 },
1681 { 0x00, 0xf099 },
1682 { 0x04, 0x9800 },
1683 { 0x04, 0x9000 },
1684 { 0x1d, 0x3d98 },
7da97ec9
FR		 1685 { 0x1f, 0x0002 },
1686 { 0x0c, 0x7eb8 },
f50d4275
FR		 1687 { 0x06, 0x0761 },
1688 { 0x1f, 0x0003 },
1689 { 0x16, 0x0f0a },
7da97ec9
FR		 1690 { 0x1f, 0x0000 }
1691 };
1692
1693 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1694
1695 mdio_patch(ioaddr, 0x16, 1 << 0);
1696 mdio_patch(ioaddr, 0x14, 1 << 5);
1697 mdio_patch(ioaddr, 0x0d, 1 << 5);
1698 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1699}
1700
197ff761
FR		 1701static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1702{
350f7596 1703 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 1704 { 0x1f, 0x0001 },
1705 { 0x12, 0x2300 },
1706 { 0x1d, 0x3d98 },
1707 { 0x1f, 0x0002 },
1708 { 0x0c, 0x7eb8 },
1709 { 0x06, 0x5461 },
1710 { 0x1f, 0x0003 },
1711 { 0x16, 0x0f0a },
1712 { 0x1f, 0x0000 }
1713 };
1714
1715 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1716
1717 mdio_patch(ioaddr, 0x16, 1 << 0);
1718 mdio_patch(ioaddr, 0x14, 1 << 5);
1719 mdio_patch(ioaddr, 0x0d, 1 << 5);
1720 mdio_write(ioaddr, 0x1f, 0x0000);
1721}
1722
6fb07058
FR		 1723static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1724{
1725 rtl8168c_3_hw_phy_config(ioaddr);
1726}
1727
daf9df6d 1728static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
5b538df9 1729{
350f7596 1730 static const struct phy_reg phy_reg_init_0[] = {
5b538df9 1731 { 0x1f, 0x0001 },
daf9df6d 1732 { 0x06, 0x4064 },
1733 { 0x07, 0x2863 },
1734 { 0x08, 0x059c },
1735 { 0x09, 0x26b4 },
1736 { 0x0a, 0x6a19 },
1737 { 0x0b, 0xdcc8 },
1738 { 0x10, 0xf06d },
1739 { 0x14, 0x7f68 },
1740 { 0x18, 0x7fd9 },
1741 { 0x1c, 0xf0ff },
1742 { 0x1d, 0x3d9c },
5b538df9 1743 { 0x1f, 0x0003 },
daf9df6d 1744 { 0x12, 0xf49f },
1745 { 0x13, 0x070b },
1746 { 0x1a, 0x05ad },
1747 { 0x14, 0x94c0 }
1748 };
350f7596 1749 static const struct phy_reg phy_reg_init_1[] = {
5b538df9 1750 { 0x1f, 0x0002 },
daf9df6d 1751 { 0x06, 0x5561 },
1752 { 0x1f, 0x0005 },
1753 { 0x05, 0x8332 },
1754 { 0x06, 0x5561 }
1755 };
350f7596 1756 static const struct phy_reg phy_reg_init_2[] = {
daf9df6d 1757 { 0x1f, 0x0005 },
1758 { 0x05, 0xffc2 },
1759 { 0x1f, 0x0005 },
1760 { 0x05, 0x8000 },
1761 { 0x06, 0xf8f9 },
1762 { 0x06, 0xfaef },
1763 { 0x06, 0x59ee },
1764 { 0x06, 0xf8ea },
1765 { 0x06, 0x00ee },
1766 { 0x06, 0xf8eb },
1767 { 0x06, 0x00e0 },
1768 { 0x06, 0xf87c },
1769 { 0x06, 0xe1f8 },
1770 { 0x06, 0x7d59 },
1771 { 0x06, 0x0fef },
1772 { 0x06, 0x0139 },
1773 { 0x06, 0x029e },
1774 { 0x06, 0x06ef },
1775 { 0x06, 0x1039 },
1776 { 0x06, 0x089f },
1777 { 0x06, 0x2aee },
1778 { 0x06, 0xf8ea },
1779 { 0x06, 0x00ee },
1780 { 0x06, 0xf8eb },
1781 { 0x06, 0x01e0 },
1782 { 0x06, 0xf87c },
1783 { 0x06, 0xe1f8 },
1784 { 0x06, 0x7d58 },
1785 { 0x06, 0x409e },
1786 { 0x06, 0x0f39 },
1787 { 0x06, 0x46aa },
1788 { 0x06, 0x0bbf },
1789 { 0x06, 0x8290 },
1790 { 0x06, 0xd682 },
1791 { 0x06, 0x9802 },
1792 { 0x06, 0x014f },
1793 { 0x06, 0xae09 },
1794 { 0x06, 0xbf82 },
1795 { 0x06, 0x98d6 },
1796 { 0x06, 0x82a0 },
1797 { 0x06, 0x0201 },
1798 { 0x06, 0x4fef },
1799 { 0x06, 0x95fe },
1800 { 0x06, 0xfdfc },
1801 { 0x06, 0x05f8 },
1802 { 0x06, 0xf9fa },
1803 { 0x06, 0xeef8 },
1804 { 0x06, 0xea00 },
1805 { 0x06, 0xeef8 },
1806 { 0x06, 0xeb00 },
1807 { 0x06, 0xe2f8 },
1808 { 0x06, 0x7ce3 },
1809 { 0x06, 0xf87d },
1810 { 0x06, 0xa511 },
1811 { 0x06, 0x1112 },
1812 { 0x06, 0xd240 },
1813 { 0x06, 0xd644 },
1814 { 0x06, 0x4402 },
1815 { 0x06, 0x8217 },
1816 { 0x06, 0xd2a0 },
1817 { 0x06, 0xd6aa },
1818 { 0x06, 0xaa02 },
1819 { 0x06, 0x8217 },
1820 { 0x06, 0xae0f },
1821 { 0x06, 0xa544 },
1822 { 0x06, 0x4402 },
1823 { 0x06, 0xae4d },
1824 { 0x06, 0xa5aa },
1825 { 0x06, 0xaa02 },
1826 { 0x06, 0xae47 },
1827 { 0x06, 0xaf82 },
1828 { 0x06, 0x13ee },
1829 { 0x06, 0x834e },
1830 { 0x06, 0x00ee },
1831 { 0x06, 0x834d },
1832 { 0x06, 0x0fee },
1833 { 0x06, 0x834c },
1834 { 0x06, 0x0fee },
1835 { 0x06, 0x834f },
1836 { 0x06, 0x00ee },
1837 { 0x06, 0x8351 },
1838 { 0x06, 0x00ee },
1839 { 0x06, 0x834a },
1840 { 0x06, 0xffee },
1841 { 0x06, 0x834b },
1842 { 0x06, 0xffe0 },
1843 { 0x06, 0x8330 },
1844 { 0x06, 0xe183 },
1845 { 0x06, 0x3158 },
1846 { 0x06, 0xfee4 },
1847 { 0x06, 0xf88a },
1848 { 0x06, 0xe5f8 },
1849 { 0x06, 0x8be0 },
1850 { 0x06, 0x8332 },
1851 { 0x06, 0xe183 },
1852 { 0x06, 0x3359 },
1853 { 0x06, 0x0fe2 },
1854 { 0x06, 0x834d },
1855 { 0x06, 0x0c24 },
1856 { 0x06, 0x5af0 },
1857 { 0x06, 0x1e12 },
1858 { 0x06, 0xe4f8 },
1859 { 0x06, 0x8ce5 },
1860 { 0x06, 0xf88d },
1861 { 0x06, 0xaf82 },
1862 { 0x06, 0x13e0 },
1863 { 0x06, 0x834f },
1864 { 0x06, 0x10e4 },
1865 { 0x06, 0x834f },
1866 { 0x06, 0xe083 },
1867 { 0x06, 0x4e78 },
1868 { 0x06, 0x009f },
1869 { 0x06, 0x0ae0 },
1870 { 0x06, 0x834f },
1871 { 0x06, 0xa010 },
1872 { 0x06, 0xa5ee },
1873 { 0x06, 0x834e },
1874 { 0x06, 0x01e0 },
1875 { 0x06, 0x834e },
1876 { 0x06, 0x7805 },
1877 { 0x06, 0x9e9a },
1878 { 0x06, 0xe083 },
1879 { 0x06, 0x4e78 },
1880 { 0x06, 0x049e },
1881 { 0x06, 0x10e0 },
1882 { 0x06, 0x834e },
1883 { 0x06, 0x7803 },
1884 { 0x06, 0x9e0f },
1885 { 0x06, 0xe083 },
1886 { 0x06, 0x4e78 },
1887 { 0x06, 0x019e },
1888 { 0x06, 0x05ae },
1889 { 0x06, 0x0caf },
1890 { 0x06, 0x81f8 },
1891 { 0x06, 0xaf81 },
1892 { 0x06, 0xa3af },
1893 { 0x06, 0x81dc },
1894 { 0x06, 0xaf82 },
1895 { 0x06, 0x13ee },
1896 { 0x06, 0x8348 },
1897 { 0x06, 0x00ee },
1898 { 0x06, 0x8349 },
1899 { 0x06, 0x00e0 },
1900 { 0x06, 0x8351 },
1901 { 0x06, 0x10e4 },
1902 { 0x06, 0x8351 },
1903 { 0x06, 0x5801 },
1904 { 0x06, 0x9fea },
1905 { 0x06, 0xd000 },
1906 { 0x06, 0xd180 },
1907 { 0x06, 0x1f66 },
1908 { 0x06, 0xe2f8 },
1909 { 0x06, 0xeae3 },
1910 { 0x06, 0xf8eb },
1911 { 0x06, 0x5af8 },
1912 { 0x06, 0x1e20 },
1913 { 0x06, 0xe6f8 },
1914 { 0x06, 0xeae5 },
1915 { 0x06, 0xf8eb },
1916 { 0x06, 0xd302 },
1917 { 0x06, 0xb3fe },
1918 { 0x06, 0xe2f8 },
1919 { 0x06, 0x7cef },
1920 { 0x06, 0x325b },
1921 { 0x06, 0x80e3 },
1922 { 0x06, 0xf87d },
1923 { 0x06, 0x9e03 },
1924 { 0x06, 0x7dff },
1925 { 0x06, 0xff0d },
1926 { 0x06, 0x581c },
1927 { 0x06, 0x551a },
1928 { 0x06, 0x6511 },
1929 { 0x06, 0xa190 },
1930 { 0x06, 0xd3e2 },
1931 { 0x06, 0x8348 },
1932 { 0x06, 0xe383 },
1933 { 0x06, 0x491b },
1934 { 0x06, 0x56ab },
1935 { 0x06, 0x08ef },
1936 { 0x06, 0x56e6 },
1937 { 0x06, 0x8348 },
1938 { 0x06, 0xe783 },
1939 { 0x06, 0x4910 },
1940 { 0x06, 0xd180 },
1941 { 0x06, 0x1f66 },
1942 { 0x06, 0xa004 },
1943 { 0x06, 0xb9e2 },
1944 { 0x06, 0x8348 },
1945 { 0x06, 0xe383 },
1946 { 0x06, 0x49ef },
1947 { 0x06, 0x65e2 },
1948 { 0x06, 0x834a },
1949 { 0x06, 0xe383 },
1950 { 0x06, 0x4b1b },
1951 { 0x06, 0x56aa },
1952 { 0x06, 0x0eef },
1953 { 0x06, 0x56e6 },
1954 { 0x06, 0x834a },
1955 { 0x06, 0xe783 },
1956 { 0x06, 0x4be2 },
1957 { 0x06, 0x834d },
1958 { 0x06, 0xe683 },
1959 { 0x06, 0x4ce0 },
1960 { 0x06, 0x834d },
1961 { 0x06, 0xa000 },
1962 { 0x06, 0x0caf },
1963 { 0x06, 0x81dc },
1964 { 0x06, 0xe083 },
1965 { 0x06, 0x4d10 },
1966 { 0x06, 0xe483 },
1967 { 0x06, 0x4dae },
1968 { 0x06, 0x0480 },
1969 { 0x06, 0xe483 },
1970 { 0x06, 0x4de0 },
1971 { 0x06, 0x834e },
1972 { 0x06, 0x7803 },
1973 { 0x06, 0x9e0b },
1974 { 0x06, 0xe083 },
1975 { 0x06, 0x4e78 },
1976 { 0x06, 0x049e },
1977 { 0x06, 0x04ee },
1978 { 0x06, 0x834e },
1979 { 0x06, 0x02e0 },
1980 { 0x06, 0x8332 },
1981 { 0x06, 0xe183 },
1982 { 0x06, 0x3359 },
1983 { 0x06, 0x0fe2 },
1984 { 0x06, 0x834d },
1985 { 0x06, 0x0c24 },
1986 { 0x06, 0x5af0 },
1987 { 0x06, 0x1e12 },
1988 { 0x06, 0xe4f8 },
1989 { 0x06, 0x8ce5 },
1990 { 0x06, 0xf88d },
1991 { 0x06, 0xe083 },
1992 { 0x06, 0x30e1 },
1993 { 0x06, 0x8331 },
1994 { 0x06, 0x6801 },
1995 { 0x06, 0xe4f8 },
1996 { 0x06, 0x8ae5 },
1997 { 0x06, 0xf88b },
1998 { 0x06, 0xae37 },
1999 { 0x06, 0xee83 },
2000 { 0x06, 0x4e03 },
2001 { 0x06, 0xe083 },
2002 { 0x06, 0x4ce1 },
2003 { 0x06, 0x834d },
2004 { 0x06, 0x1b01 },
2005 { 0x06, 0x9e04 },
2006 { 0x06, 0xaaa1 },
2007 { 0x06, 0xaea8 },
2008 { 0x06, 0xee83 },
2009 { 0x06, 0x4e04 },
2010 { 0x06, 0xee83 },
2011 { 0x06, 0x4f00 },
2012 { 0x06, 0xaeab },
2013 { 0x06, 0xe083 },
2014 { 0x06, 0x4f78 },
2015 { 0x06, 0x039f },
2016 { 0x06, 0x14ee },
2017 { 0x06, 0x834e },
2018 { 0x06, 0x05d2 },
2019 { 0x06, 0x40d6 },
2020 { 0x06, 0x5554 },
2021 { 0x06, 0x0282 },
2022 { 0x06, 0x17d2 },
2023 { 0x06, 0xa0d6 },
2024 { 0x06, 0xba00 },
2025 { 0x06, 0x0282 },
2026 { 0x06, 0x17fe },
2027 { 0x06, 0xfdfc },
2028 { 0x06, 0x05f8 },
2029 { 0x06, 0xe0f8 },
2030 { 0x06, 0x60e1 },
2031 { 0x06, 0xf861 },
2032 { 0x06, 0x6802 },
2033 { 0x06, 0xe4f8 },
2034 { 0x06, 0x60e5 },
2035 { 0x06, 0xf861 },
2036 { 0x06, 0xe0f8 },
2037 { 0x06, 0x48e1 },
2038 { 0x06, 0xf849 },
2039 { 0x06, 0x580f },
2040 { 0x06, 0x1e02 },
2041 { 0x06, 0xe4f8 },
2042 { 0x06, 0x48e5 },
2043 { 0x06, 0xf849 },
2044 { 0x06, 0xd000 },
2045 { 0x06, 0x0282 },
2046 { 0x06, 0x5bbf },
2047 { 0x06, 0x8350 },
2048 { 0x06, 0xef46 },
2049 { 0x06, 0xdc19 },
2050 { 0x06, 0xddd0 },
2051 { 0x06, 0x0102 },
2052 { 0x06, 0x825b },
2053 { 0x06, 0x0282 },
2054 { 0x06, 0x77e0 },
2055 { 0x06, 0xf860 },
2056 { 0x06, 0xe1f8 },
2057 { 0x06, 0x6158 },
2058 { 0x06, 0xfde4 },
2059 { 0x06, 0xf860 },
2060 { 0x06, 0xe5f8 },
2061 { 0x06, 0x61fc },
2062 { 0x06, 0x04f9 },
2063 { 0x06, 0xfafb },
2064 { 0x06, 0xc6bf },
2065 { 0x06, 0xf840 },
2066 { 0x06, 0xbe83 },
2067 { 0x06, 0x50a0 },
2068 { 0x06, 0x0101 },
2069 { 0x06, 0x071b },
2070 { 0x06, 0x89cf },
2071 { 0x06, 0xd208 },
2072 { 0x06, 0xebdb },
2073 { 0x06, 0x19b2 },
2074 { 0x06, 0xfbff },
2075 { 0x06, 0xfefd },
2076 { 0x06, 0x04f8 },
2077 { 0x06, 0xe0f8 },
2078 { 0x06, 0x48e1 },
2079 { 0x06, 0xf849 },
2080 { 0x06, 0x6808 },
2081 { 0x06, 0xe4f8 },
2082 { 0x06, 0x48e5 },
2083 { 0x06, 0xf849 },
2084 { 0x06, 0x58f7 },
2085 { 0x06, 0xe4f8 },
2086 { 0x06, 0x48e5 },
2087 { 0x06, 0xf849 },
2088 { 0x06, 0xfc04 },
2089 { 0x06, 0x4d20 },
2090 { 0x06, 0x0002 },
2091 { 0x06, 0x4e22 },
2092 { 0x06, 0x0002 },
2093 { 0x06, 0x4ddf },
2094 { 0x06, 0xff01 },
2095 { 0x06, 0x4edd },
2096 { 0x06, 0xff01 },
2097 { 0x05, 0x83d4 },
2098 { 0x06, 0x8000 },
2099 { 0x05, 0x83d8 },
2100 { 0x06, 0x8051 },
2101 { 0x02, 0x6010 },
2102 { 0x03, 0xdc00 },
2103 { 0x05, 0xfff6 },
2104 { 0x06, 0x00fc },
5b538df9 2105 { 0x1f, 0x0000 },
daf9df6d 2106
5b538df9 2107 { 0x1f, 0x0000 },
daf9df6d 2108 { 0x0d, 0xf880 },
2109 { 0x1f, 0x0000 }
2110 };
2111
2112 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2113
2114 mdio_write(ioaddr, 0x1f, 0x0002);
2115 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2116 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2117
2118 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2119
2120 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2121 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2122 { 0x1f, 0x0002 },
2123 { 0x05, 0x669a },
2124 { 0x1f, 0x0005 },
2125 { 0x05, 0x8330 },
2126 { 0x06, 0x669a },
2127 { 0x1f, 0x0002 }
2128 };
2129 int val;
2130
2131 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2132
2133 val = mdio_read(ioaddr, 0x0d);
2134
2135 if ((val & 0x00ff) != 0x006c) {
350f7596 2136 static const u32 set[] = {
daf9df6d 2137 0x0065, 0x0066, 0x0067, 0x0068,
2138 0x0069, 0x006a, 0x006b, 0x006c
2139 };
2140 int i;
2141
2142 mdio_write(ioaddr, 0x1f, 0x0002);
2143
2144 val &= 0xff00;
2145 for (i = 0; i < ARRAY_SIZE(set); i++)
2146 mdio_write(ioaddr, 0x0d, val | set[i]);
2147 }
2148 } else {
350f7596 2149 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2150 { 0x1f, 0x0002 },
2151 { 0x05, 0x6662 },
2152 { 0x1f, 0x0005 },
2153 { 0x05, 0x8330 },
2154 { 0x06, 0x6662 }
2155 };
2156
2157 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2158 }
2159
2160 mdio_write(ioaddr, 0x1f, 0x0002);
2161 mdio_patch(ioaddr, 0x0d, 0x0300);
2162 mdio_patch(ioaddr, 0x0f, 0x0010);
2163
2164 mdio_write(ioaddr, 0x1f, 0x0002);
2165 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2166 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2167
2168 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2169}
2170
2171static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2172{
350f7596 2173 static const struct phy_reg phy_reg_init_0[] = {
daf9df6d 2174 { 0x1f, 0x0001 },
2175 { 0x06, 0x4064 },
2176 { 0x07, 0x2863 },
2177 { 0x08, 0x059c },
2178 { 0x09, 0x26b4 },
2179 { 0x0a, 0x6a19 },
2180 { 0x0b, 0xdcc8 },
2181 { 0x10, 0xf06d },
2182 { 0x14, 0x7f68 },
2183 { 0x18, 0x7fd9 },
2184 { 0x1c, 0xf0ff },
2185 { 0x1d, 0x3d9c },
2186 { 0x1f, 0x0003 },
2187 { 0x12, 0xf49f },
2188 { 0x13, 0x070b },
2189 { 0x1a, 0x05ad },
2190 { 0x14, 0x94c0 },
2191
2192 { 0x1f, 0x0002 },
2193 { 0x06, 0x5561 },
2194 { 0x1f, 0x0005 },
2195 { 0x05, 0x8332 },
2196 { 0x06, 0x5561 }
2197 };
350f7596 2198 static const struct phy_reg phy_reg_init_1[] = {
daf9df6d 2199 { 0x1f, 0x0005 },
2200 { 0x05, 0xffc2 },
5b538df9 2201 { 0x1f, 0x0005 },
daf9df6d 2202 { 0x05, 0x8000 },
2203 { 0x06, 0xf8f9 },
2204 { 0x06, 0xfaee },
2205 { 0x06, 0xf8ea },
2206 { 0x06, 0x00ee },
2207 { 0x06, 0xf8eb },
2208 { 0x06, 0x00e2 },
2209 { 0x06, 0xf87c },
2210 { 0x06, 0xe3f8 },
2211 { 0x06, 0x7da5 },
2212 { 0x06, 0x1111 },
2213 { 0x06, 0x12d2 },
2214 { 0x06, 0x40d6 },
2215 { 0x06, 0x4444 },
2216 { 0x06, 0x0281 },
2217 { 0x06, 0xc6d2 },
2218 { 0x06, 0xa0d6 },
2219 { 0x06, 0xaaaa },
2220 { 0x06, 0x0281 },
2221 { 0x06, 0xc6ae },
2222 { 0x06, 0x0fa5 },
2223 { 0x06, 0x4444 },
2224 { 0x06, 0x02ae },
2225 { 0x06, 0x4da5 },
2226 { 0x06, 0xaaaa },
2227 { 0x06, 0x02ae },
2228 { 0x06, 0x47af },
2229 { 0x06, 0x81c2 },
2230 { 0x06, 0xee83 },
2231 { 0x06, 0x4e00 },
2232 { 0x06, 0xee83 },
2233 { 0x06, 0x4d0f },
2234 { 0x06, 0xee83 },
2235 { 0x06, 0x4c0f },
2236 { 0x06, 0xee83 },
2237 { 0x06, 0x4f00 },
2238 { 0x06, 0xee83 },
2239 { 0x06, 0x5100 },
2240 { 0x06, 0xee83 },
2241 { 0x06, 0x4aff },
2242 { 0x06, 0xee83 },
2243 { 0x06, 0x4bff },
2244 { 0x06, 0xe083 },
2245 { 0x06, 0x30e1 },
2246 { 0x06, 0x8331 },
2247 { 0x06, 0x58fe },
2248 { 0x06, 0xe4f8 },
2249 { 0x06, 0x8ae5 },
2250 { 0x06, 0xf88b },
2251 { 0x06, 0xe083 },
2252 { 0x06, 0x32e1 },
2253 { 0x06, 0x8333 },
2254 { 0x06, 0x590f },
2255 { 0x06, 0xe283 },
2256 { 0x06, 0x4d0c },
2257 { 0x06, 0x245a },
2258 { 0x06, 0xf01e },
2259 { 0x06, 0x12e4 },
2260 { 0x06, 0xf88c },
2261 { 0x06, 0xe5f8 },
2262 { 0x06, 0x8daf },
2263 { 0x06, 0x81c2 },
2264 { 0x06, 0xe083 },
2265 { 0x06, 0x4f10 },
2266 { 0x06, 0xe483 },
2267 { 0x06, 0x4fe0 },
2268 { 0x06, 0x834e },
2269 { 0x06, 0x7800 },
2270 { 0x06, 0x9f0a },
2271 { 0x06, 0xe083 },
2272 { 0x06, 0x4fa0 },
2273 { 0x06, 0x10a5 },
2274 { 0x06, 0xee83 },
2275 { 0x06, 0x4e01 },
2276 { 0x06, 0xe083 },
2277 { 0x06, 0x4e78 },
2278 { 0x06, 0x059e },
2279 { 0x06, 0x9ae0 },
2280 { 0x06, 0x834e },
2281 { 0x06, 0x7804 },
2282 { 0x06, 0x9e10 },
2283 { 0x06, 0xe083 },
2284 { 0x06, 0x4e78 },
2285 { 0x06, 0x039e },
2286 { 0x06, 0x0fe0 },
2287 { 0x06, 0x834e },
2288 { 0x06, 0x7801 },
2289 { 0x06, 0x9e05 },
2290 { 0x06, 0xae0c },
2291 { 0x06, 0xaf81 },
2292 { 0x06, 0xa7af },
2293 { 0x06, 0x8152 },
2294 { 0x06, 0xaf81 },
2295 { 0x06, 0x8baf },
2296 { 0x06, 0x81c2 },
2297 { 0x06, 0xee83 },
2298 { 0x06, 0x4800 },
2299 { 0x06, 0xee83 },
2300 { 0x06, 0x4900 },
2301 { 0x06, 0xe083 },
2302 { 0x06, 0x5110 },
2303 { 0x06, 0xe483 },
2304 { 0x06, 0x5158 },
2305 { 0x06, 0x019f },
2306 { 0x06, 0xead0 },
2307 { 0x06, 0x00d1 },
2308 { 0x06, 0x801f },
2309 { 0x06, 0x66e2 },
2310 { 0x06, 0xf8ea },
2311 { 0x06, 0xe3f8 },
2312 { 0x06, 0xeb5a },
2313 { 0x06, 0xf81e },
2314 { 0x06, 0x20e6 },
2315 { 0x06, 0xf8ea },
2316 { 0x06, 0xe5f8 },
2317 { 0x06, 0xebd3 },
2318 { 0x06, 0x02b3 },
2319 { 0x06, 0xfee2 },
2320 { 0x06, 0xf87c },
2321 { 0x06, 0xef32 },
2322 { 0x06, 0x5b80 },
2323 { 0x06, 0xe3f8 },
2324 { 0x06, 0x7d9e },
2325 { 0x06, 0x037d },
2326 { 0x06, 0xffff },
2327 { 0x06, 0x0d58 },
2328 { 0x06, 0x1c55 },
2329 { 0x06, 0x1a65 },
2330 { 0x06, 0x11a1 },
2331 { 0x06, 0x90d3 },
2332 { 0x06, 0xe283 },
2333 { 0x06, 0x48e3 },
2334 { 0x06, 0x8349 },
2335 { 0x06, 0x1b56 },
2336 { 0x06, 0xab08 },
2337 { 0x06, 0xef56 },
2338 { 0x06, 0xe683 },
2339 { 0x06, 0x48e7 },
2340 { 0x06, 0x8349 },
2341 { 0x06, 0x10d1 },
2342 { 0x06, 0x801f },
2343 { 0x06, 0x66a0 },
2344 { 0x06, 0x04b9 },
2345 { 0x06, 0xe283 },
2346 { 0x06, 0x48e3 },
2347 { 0x06, 0x8349 },
2348 { 0x06, 0xef65 },
2349 { 0x06, 0xe283 },
2350 { 0x06, 0x4ae3 },
2351 { 0x06, 0x834b },
2352 { 0x06, 0x1b56 },
2353 { 0x06, 0xaa0e },
2354 { 0x06, 0xef56 },
2355 { 0x06, 0xe683 },
2356 { 0x06, 0x4ae7 },
2357 { 0x06, 0x834b },
2358 { 0x06, 0xe283 },
2359 { 0x06, 0x4de6 },
2360 { 0x06, 0x834c },
2361 { 0x06, 0xe083 },
2362 { 0x06, 0x4da0 },
2363 { 0x06, 0x000c },
2364 { 0x06, 0xaf81 },
2365 { 0x06, 0x8be0 },
2366 { 0x06, 0x834d },
2367 { 0x06, 0x10e4 },
2368 { 0x06, 0x834d },
2369 { 0x06, 0xae04 },
2370 { 0x06, 0x80e4 },
2371 { 0x06, 0x834d },
2372 { 0x06, 0xe083 },
2373 { 0x06, 0x4e78 },
2374 { 0x06, 0x039e },
2375 { 0x06, 0x0be0 },
2376 { 0x06, 0x834e },
2377 { 0x06, 0x7804 },
2378 { 0x06, 0x9e04 },
2379 { 0x06, 0xee83 },
2380 { 0x06, 0x4e02 },
2381 { 0x06, 0xe083 },
2382 { 0x06, 0x32e1 },
2383 { 0x06, 0x8333 },
2384 { 0x06, 0x590f },
2385 { 0x06, 0xe283 },
2386 { 0x06, 0x4d0c },
2387 { 0x06, 0x245a },
2388 { 0x06, 0xf01e },
2389 { 0x06, 0x12e4 },
2390 { 0x06, 0xf88c },
2391 { 0x06, 0xe5f8 },
2392 { 0x06, 0x8de0 },
2393 { 0x06, 0x8330 },
2394 { 0x06, 0xe183 },
2395 { 0x06, 0x3168 },
2396 { 0x06, 0x01e4 },
2397 { 0x06, 0xf88a },
2398 { 0x06, 0xe5f8 },
2399 { 0x06, 0x8bae },
2400 { 0x06, 0x37ee },
2401 { 0x06, 0x834e },
2402 { 0x06, 0x03e0 },
2403 { 0x06, 0x834c },
2404 { 0x06, 0xe183 },
2405 { 0x06, 0x4d1b },
2406 { 0x06, 0x019e },
2407 { 0x06, 0x04aa },
2408 { 0x06, 0xa1ae },
2409 { 0x06, 0xa8ee },
2410 { 0x06, 0x834e },
2411 { 0x06, 0x04ee },
2412 { 0x06, 0x834f },
2413 { 0x06, 0x00ae },
2414 { 0x06, 0xabe0 },
2415 { 0x06, 0x834f },
2416 { 0x06, 0x7803 },
2417 { 0x06, 0x9f14 },
2418 { 0x06, 0xee83 },
2419 { 0x06, 0x4e05 },
2420 { 0x06, 0xd240 },
2421 { 0x06, 0xd655 },
2422 { 0x06, 0x5402 },
2423 { 0x06, 0x81c6 },
2424 { 0x06, 0xd2a0 },
2425 { 0x06, 0xd6ba },
2426 { 0x06, 0x0002 },
2427 { 0x06, 0x81c6 },
2428 { 0x06, 0xfefd },
2429 { 0x06, 0xfc05 },
2430 { 0x06, 0xf8e0 },
2431 { 0x06, 0xf860 },
2432 { 0x06, 0xe1f8 },
2433 { 0x06, 0x6168 },
2434 { 0x06, 0x02e4 },
2435 { 0x06, 0xf860 },
2436 { 0x06, 0xe5f8 },
2437 { 0x06, 0x61e0 },
2438 { 0x06, 0xf848 },
2439 { 0x06, 0xe1f8 },
2440 { 0x06, 0x4958 },
2441 { 0x06, 0x0f1e },
2442 { 0x06, 0x02e4 },
2443 { 0x06, 0xf848 },
2444 { 0x06, 0xe5f8 },
2445 { 0x06, 0x49d0 },
2446 { 0x06, 0x0002 },
2447 { 0x06, 0x820a },
2448 { 0x06, 0xbf83 },
2449 { 0x06, 0x50ef },
2450 { 0x06, 0x46dc },
2451 { 0x06, 0x19dd },
2452 { 0x06, 0xd001 },
2453 { 0x06, 0x0282 },
2454 { 0x06, 0x0a02 },
2455 { 0x06, 0x8226 },
2456 { 0x06, 0xe0f8 },
2457 { 0x06, 0x60e1 },
2458 { 0x06, 0xf861 },
2459 { 0x06, 0x58fd },
2460 { 0x06, 0xe4f8 },
2461 { 0x06, 0x60e5 },
2462 { 0x06, 0xf861 },
2463 { 0x06, 0xfc04 },
2464 { 0x06, 0xf9fa },
2465 { 0x06, 0xfbc6 },
2466 { 0x06, 0xbff8 },
2467 { 0x06, 0x40be },
2468 { 0x06, 0x8350 },
2469 { 0x06, 0xa001 },
2470 { 0x06, 0x0107 },
2471 { 0x06, 0x1b89 },
2472 { 0x06, 0xcfd2 },
2473 { 0x06, 0x08eb },
2474 { 0x06, 0xdb19 },
2475 { 0x06, 0xb2fb },
2476 { 0x06, 0xfffe },
2477 { 0x06, 0xfd04 },
2478 { 0x06, 0xf8e0 },
2479 { 0x06, 0xf848 },
2480 { 0x06, 0xe1f8 },
2481 { 0x06, 0x4968 },
2482 { 0x06, 0x08e4 },
2483 { 0x06, 0xf848 },
2484 { 0x06, 0xe5f8 },
2485 { 0x06, 0x4958 },
2486 { 0x06, 0xf7e4 },
2487 { 0x06, 0xf848 },
2488 { 0x06, 0xe5f8 },
2489 { 0x06, 0x49fc },
2490 { 0x06, 0x044d },
2491 { 0x06, 0x2000 },
2492 { 0x06, 0x024e },
2493 { 0x06, 0x2200 },
2494 { 0x06, 0x024d },
2495 { 0x06, 0xdfff },
2496 { 0x06, 0x014e },
2497 { 0x06, 0xddff },
2498 { 0x06, 0x0100 },
2499 { 0x05, 0x83d8 },
2500 { 0x06, 0x8000 },
2501 { 0x03, 0xdc00 },
2502 { 0x05, 0xfff6 },
2503 { 0x06, 0x00fc },
2504 { 0x1f, 0x0000 },
2505
2506 { 0x1f, 0x0000 },
2507 { 0x0d, 0xf880 },
2508 { 0x1f, 0x0000 }
5b538df9
FR		 2509 };
2510
2511 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2512
daf9df6d 2513 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2514 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2515 { 0x1f, 0x0002 },
2516 { 0x05, 0x669a },
5b538df9 2517 { 0x1f, 0x0005 },
daf9df6d 2518 { 0x05, 0x8330 },
2519 { 0x06, 0x669a },
2520
2521 { 0x1f, 0x0002 }
2522 };
2523 int val;
2524
2525 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2526
2527 val = mdio_read(ioaddr, 0x0d);
2528 if ((val & 0x00ff) != 0x006c) {
2529 u32 set[] = {
2530 0x0065, 0x0066, 0x0067, 0x0068,
2531 0x0069, 0x006a, 0x006b, 0x006c
2532 };
2533 int i;
2534
2535 mdio_write(ioaddr, 0x1f, 0x0002);
2536
2537 val &= 0xff00;
2538 for (i = 0; i < ARRAY_SIZE(set); i++)
2539 mdio_write(ioaddr, 0x0d, val | set[i]);
2540 }
2541 } else {
350f7596 2542 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2543 { 0x1f, 0x0002 },
2544 { 0x05, 0x2642 },
5b538df9 2545 { 0x1f, 0x0005 },
daf9df6d 2546 { 0x05, 0x8330 },
2547 { 0x06, 0x2642 }
5b538df9
FR		 2548 };
2549
daf9df6d 2550 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2551 }
2552
daf9df6d 2553 mdio_write(ioaddr, 0x1f, 0x0002);
2554 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2555 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2556
2557 mdio_write(ioaddr, 0x1f, 0x0001);
2558 mdio_write(ioaddr, 0x17, 0x0cc0);
2559
2560 mdio_write(ioaddr, 0x1f, 0x0002);
2561 mdio_patch(ioaddr, 0x0f, 0x0017);
2562
2563 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2564}
2565
2566static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2567{
350f7596 2568 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2569 { 0x1f, 0x0002 },
2570 { 0x10, 0x0008 },
2571 { 0x0d, 0x006c },
2572
2573 { 0x1f, 0x0000 },
2574 { 0x0d, 0xf880 },
2575
2576 { 0x1f, 0x0001 },
2577 { 0x17, 0x0cc0 },
2578
2579 { 0x1f, 0x0001 },
2580 { 0x0b, 0xa4d8 },
2581 { 0x09, 0x281c },
2582 { 0x07, 0x2883 },
2583 { 0x0a, 0x6b35 },
2584 { 0x1d, 0x3da4 },
2585 { 0x1c, 0xeffd },
2586 { 0x14, 0x7f52 },
2587 { 0x18, 0x7fc6 },
2588 { 0x08, 0x0601 },
2589 { 0x06, 0x4063 },
2590 { 0x10, 0xf074 },
2591 { 0x1f, 0x0003 },
2592 { 0x13, 0x0789 },
2593 { 0x12, 0xf4bd },
2594 { 0x1a, 0x04fd },
2595 { 0x14, 0x84b0 },
2596 { 0x1f, 0x0000 },
2597 { 0x00, 0x9200 },
2598
2599 { 0x1f, 0x0005 },
2600 { 0x01, 0x0340 },
2601 { 0x1f, 0x0001 },
2602 { 0x04, 0x4000 },
2603 { 0x03, 0x1d21 },
2604 { 0x02, 0x0c32 },
2605 { 0x01, 0x0200 },
2606 { 0x00, 0x5554 },
2607 { 0x04, 0x4800 },
2608 { 0x04, 0x4000 },
2609 { 0x04, 0xf000 },
2610 { 0x03, 0xdf01 },
2611 { 0x02, 0xdf20 },
2612 { 0x01, 0x101a },
2613 { 0x00, 0xa0ff },
2614 { 0x04, 0xf800 },
2615 { 0x04, 0xf000 },
2616 { 0x1f, 0x0000 },
2617
2618 { 0x1f, 0x0007 },
2619 { 0x1e, 0x0023 },
2620 { 0x16, 0x0000 },
2621 { 0x1f, 0x0000 }
2622 };
2623
2624 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2625}
2626
2857ffb7
FR		 2627static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2628{
350f7596 2629 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2630 { 0x1f, 0x0003 },
2631 { 0x08, 0x441d },
2632 { 0x01, 0x9100 },
2633 { 0x1f, 0x0000 }
2634 };
2635
2636 mdio_write(ioaddr, 0x1f, 0x0000);
2637 mdio_patch(ioaddr, 0x11, 1 << 12);
2638 mdio_patch(ioaddr, 0x19, 1 << 13);
85910a8e 2639 mdio_patch(ioaddr, 0x10, 1 << 15);
2857ffb7
FR		 2640
2641 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2642}
2643
5615d9f1
FR		 2644static void rtl_hw_phy_config(struct net_device *dev)
2645{
2646 struct rtl8169_private *tp = netdev_priv(dev);
2647 void __iomem *ioaddr = tp->mmio_addr;
2648
2649 rtl8169_print_mac_version(tp);
2650
2651 switch (tp->mac_version) {
2652 case RTL_GIGA_MAC_VER_01:
2653 break;
2654 case RTL_GIGA_MAC_VER_02:
2655 case RTL_GIGA_MAC_VER_03:
2656 rtl8169s_hw_phy_config(ioaddr);
2657 break;
2658 case RTL_GIGA_MAC_VER_04:
2659 rtl8169sb_hw_phy_config(ioaddr);
2660 break;
2e955856 2661 case RTL_GIGA_MAC_VER_05:
2662 rtl8169scd_hw_phy_config(tp, ioaddr);
2663 break;
8c7006aa 2664 case RTL_GIGA_MAC_VER_06:
2665 rtl8169sce_hw_phy_config(ioaddr);
2666 break;
2857ffb7
FR		 2667 case RTL_GIGA_MAC_VER_07:
2668 case RTL_GIGA_MAC_VER_08:
2669 case RTL_GIGA_MAC_VER_09:
2670 rtl8102e_hw_phy_config(ioaddr);
2671 break;
236b8082
FR		 2672 case RTL_GIGA_MAC_VER_11:
2673 rtl8168bb_hw_phy_config(ioaddr);
2674 break;
2675 case RTL_GIGA_MAC_VER_12:
2676 rtl8168bef_hw_phy_config(ioaddr);
2677 break;
2678 case RTL_GIGA_MAC_VER_17:
2679 rtl8168bef_hw_phy_config(ioaddr);
2680 break;
867763c1 2681 case RTL_GIGA_MAC_VER_18:
ef3386f0 2682 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 2683 break;
2684 case RTL_GIGA_MAC_VER_19:
219a1e9d 2685 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 2686 break;
7da97ec9 2687 case RTL_GIGA_MAC_VER_20:
219a1e9d 2688 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 2689 break;
197ff761
FR		 2690 case RTL_GIGA_MAC_VER_21:
2691 rtl8168c_3_hw_phy_config(ioaddr);
2692 break;
6fb07058
FR		 2693 case RTL_GIGA_MAC_VER_22:
2694 rtl8168c_4_hw_phy_config(ioaddr);
2695 break;
ef3386f0 2696 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2697 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 2698 rtl8168cp_2_hw_phy_config(ioaddr);
2699 break;
5b538df9 2700 case RTL_GIGA_MAC_VER_25:
daf9df6d 2701 rtl8168d_1_hw_phy_config(ioaddr);
2702 break;
2703 case RTL_GIGA_MAC_VER_26:
2704 rtl8168d_2_hw_phy_config(ioaddr);
2705 break;
2706 case RTL_GIGA_MAC_VER_27:
2707 rtl8168d_3_hw_phy_config(ioaddr);
5b538df9 2708 break;
ef3386f0 2709
5615d9f1
FR		 2710 default:
2711 break;
2712 }
2713}
2714
1da177e4
LT		 2715static void rtl8169_phy_timer(unsigned long __opaque)
2716{
2717 struct net_device *dev = (struct net_device *)__opaque;
2718 struct rtl8169_private *tp = netdev_priv(dev);
2719 struct timer_list *timer = &tp->timer;
2720 void __iomem *ioaddr = tp->mmio_addr;
2721 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2722
bcf0bf90 2723 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2724
64e4bfb4 2725 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2726 return;
2727
2728 spin_lock_irq(&tp->lock);
2729
2730 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 2731 /*
1da177e4
LT		 2732 * A busy loop could burn quite a few cycles on nowadays CPU.
2733 * Let's delay the execution of the timer for a few ticks.
2734 */
2735 timeout = HZ/10;
2736 goto out_mod_timer;
2737 }
2738
2739 if (tp->link_ok(ioaddr))
2740 goto out_unlock;
2741
bf82c189 2742 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4
LT		 2743
2744 tp->phy_reset_enable(ioaddr);
2745
2746out_mod_timer:
2747 mod_timer(timer, jiffies + timeout);
2748out_unlock:
2749 spin_unlock_irq(&tp->lock);
2750}
2751
2752static inline void rtl8169_delete_timer(struct net_device *dev)
2753{
2754 struct rtl8169_private *tp = netdev_priv(dev);
2755 struct timer_list *timer = &tp->timer;
2756
e179bb7b 2757 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2758 return;
2759
2760 del_timer_sync(timer);
2761}
2762
2763static inline void rtl8169_request_timer(struct net_device *dev)
2764{
2765 struct rtl8169_private *tp = netdev_priv(dev);
2766 struct timer_list *timer = &tp->timer;
2767
e179bb7b 2768 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2769 return;
2770
2efa53f3 2771 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2772}
2773
2774#ifdef CONFIG_NET_POLL_CONTROLLER
2775/*
2776 * Polling 'interrupt' - used by things like netconsole to send skbs
2777 * without having to re-enable interrupts. It's not called while
2778 * the interrupt routine is executing.
2779 */
2780static void rtl8169_netpoll(struct net_device *dev)
2781{
2782 struct rtl8169_private *tp = netdev_priv(dev);
2783 struct pci_dev *pdev = tp->pci_dev;
2784
2785 disable_irq(pdev->irq);
7d12e780 2786 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2787 enable_irq(pdev->irq);
2788}
2789#endif
2790
2791static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2792 void __iomem *ioaddr)
2793{
2794 iounmap(ioaddr);
2795 pci_release_regions(pdev);
87aeec76 2796 pci_clear_mwi(pdev);
1da177e4
LT		 2797 pci_disable_device(pdev);
2798 free_netdev(dev);
2799}
2800
bf793295
FR		 2801static void rtl8169_phy_reset(struct net_device *dev,
2802 struct rtl8169_private *tp)
2803{
2804 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2805 unsigned int i;
bf793295
FR		 2806
2807 tp->phy_reset_enable(ioaddr);
2808 for (i = 0; i < 100; i++) {
2809 if (!tp->phy_reset_pending(ioaddr))
2810 return;
2811 msleep(1);
2812 }
bf82c189 2813 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2814}
2815
4ff96fa6
FR		 2816static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2817{
2818 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2819
5615d9f1 2820 rtl_hw_phy_config(dev);
4ff96fa6 2821
77332894
MS		 2822 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2823 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2824 RTL_W8(0x82, 0x01);
2825 }
4ff96fa6 2826
6dccd16b
FR		 2827 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2828
2829 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2830 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2831
bcf0bf90 2832 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2833 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2834 RTL_W8(0x82, 0x01);
2835 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2836 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2837 }
2838
bf793295
FR		 2839 rtl8169_phy_reset(dev, tp);
2840
901dda2b
FR		 2841 /*
2842 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2843 * only 8101. Don't panic.
2844 */
2845 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2846
bf82c189
JP		 2847 if (RTL_R8(PHYstatus) & TBI_Enable)
2848 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2849}
2850
773d2021
FR		 2851static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2852{
2853 void __iomem *ioaddr = tp->mmio_addr;
2854 u32 high;
2855 u32 low;
2856
2857 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2858 high = addr[4] | (addr[5] << 8);
2859
2860 spin_lock_irq(&tp->lock);
2861
2862 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2863
773d2021 2864 RTL_W32(MAC4, high);
908ba2bf 2865 RTL_R32(MAC4);
2866
78f1cd02 2867 RTL_W32(MAC0, low);
908ba2bf 2868 RTL_R32(MAC0);
2869
773d2021
FR		 2870 RTL_W8(Cfg9346, Cfg9346_Lock);
2871
2872 spin_unlock_irq(&tp->lock);
2873}
2874
2875static int rtl_set_mac_address(struct net_device *dev, void *p)
2876{
2877 struct rtl8169_private *tp = netdev_priv(dev);
2878 struct sockaddr *addr = p;
2879
2880 if (!is_valid_ether_addr(addr->sa_data))
2881 return -EADDRNOTAVAIL;
2882
2883 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2884
2885 rtl_rar_set(tp, dev->dev_addr);
2886
2887 return 0;
2888}
2889
5f787a1a
FR		 2890static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2891{
2892 struct rtl8169_private *tp = netdev_priv(dev);
2893 struct mii_ioctl_data *data = if_mii(ifr);
2894
8b4ab28d
FR		 2895 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2896}
5f787a1a 2897
8b4ab28d
FR		 2898static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2899{
5f787a1a
FR		 2900 switch (cmd) {
2901 case SIOCGMIIPHY:
2902 data->phy_id = 32; /* Internal PHY */
2903 return 0;
2904
2905 case SIOCGMIIREG:
2906 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2907 return 0;
2908
2909 case SIOCSMIIREG:
5f787a1a
FR		 2910 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2911 return 0;
2912 }
2913 return -EOPNOTSUPP;
2914}
2915
8b4ab28d
FR		 2916static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2917{
2918 return -EOPNOTSUPP;
2919}
2920
0e485150
FR		 2921static const struct rtl_cfg_info {
2922 void (*hw_start)(struct net_device *);
2923 unsigned int region;
2924 unsigned int align;
2925 u16 intr_event;
2926 u16 napi_event;
ccdffb9a 2927 unsigned features;
f21b75e9 2928 u8 default_ver;
0e485150
FR		 2929} rtl_cfg_infos [] = {
2930 [RTL_CFG_0] = {
2931 .hw_start = rtl_hw_start_8169,
2932 .region = 1,
e9f63f30 2933 .align = 0,
0e485150
FR		 2934 .intr_event = SYSErr | LinkChg | RxOverflow |
2935 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2936 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2937 .features = RTL_FEATURE_GMII,
2938 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2939 },
2940 [RTL_CFG_1] = {
2941 .hw_start = rtl_hw_start_8168,
2942 .region = 2,
2943 .align = 8,
801e147c 2944 .intr_event = SYSErr | RxFIFOOver | LinkChg | RxOverflow |
0e485150 2945 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2946 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2947 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2948 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2949 },
2950 [RTL_CFG_2] = {
2951 .hw_start = rtl_hw_start_8101,
2952 .region = 2,
2953 .align = 8,
2954 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2955 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2956 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2957 .features = RTL_FEATURE_MSI,
2958 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2959 }
2960};
2961
fbac58fc
FR		 2962/* Cfg9346_Unlock assumed. */
2963static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2964 const struct rtl_cfg_info *cfg)
2965{
2966 unsigned msi = 0;
2967 u8 cfg2;
2968
2969 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2970 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2971 if (pci_enable_msi(pdev)) {
2972 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2973 } else {
2974 cfg2 |= MSIEnable;
2975 msi = RTL_FEATURE_MSI;
2976 }
2977 }
2978 RTL_W8(Config2, cfg2);
2979 return msi;
2980}
2981
2982static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2983{
2984 if (tp->features & RTL_FEATURE_MSI) {
2985 pci_disable_msi(pdev);
2986 tp->features &= ~RTL_FEATURE_MSI;
2987 }
2988}
2989
8b4ab28d
FR		 2990static const struct net_device_ops rtl8169_netdev_ops = {
2991 .ndo_open = rtl8169_open,
2992 .ndo_stop = rtl8169_close,
2993 .ndo_get_stats = rtl8169_get_stats,
00829823 2994 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2995 .ndo_tx_timeout = rtl8169_tx_timeout,
2996 .ndo_validate_addr = eth_validate_addr,
2997 .ndo_change_mtu = rtl8169_change_mtu,
2998 .ndo_set_mac_address = rtl_set_mac_address,
2999 .ndo_do_ioctl = rtl8169_ioctl,
3000 .ndo_set_multicast_list = rtl_set_rx_mode,
3001#ifdef CONFIG_R8169_VLAN
3002 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
3003#endif
3004#ifdef CONFIG_NET_POLL_CONTROLLER
3005 .ndo_poll_controller = rtl8169_netpoll,
3006#endif
3007
3008};
3009
1da177e4 3010static int __devinit
4ff96fa6 3011rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3012{
0e485150
FR		 3013 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3014 const unsigned int region = cfg->region;
1da177e4 3015 struct rtl8169_private *tp;
ccdffb9a 3016 struct mii_if_info *mii;
4ff96fa6
FR		 3017 struct net_device *dev;
3018 void __iomem *ioaddr;
07d3f51f
FR		 3019 unsigned int i;
3020 int rc;
1da177e4 3021
4ff96fa6
FR		 3022 if (netif_msg_drv(&debug)) {
3023 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3024 MODULENAME, RTL8169_VERSION);
3025 }
1da177e4 3026
1da177e4 3027 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3028 if (!dev) {
b57b7e5a 3029 if (netif_msg_drv(&debug))
9b91cf9d 3030 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3031 rc = -ENOMEM;
3032 goto out;
1da177e4
LT		 3033 }
3034
1da177e4 3035 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3036 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3037 tp = netdev_priv(dev);
c4028958 3038 tp->dev = dev;
21e197f2 3039 tp->pci_dev = pdev;
b57b7e5a 3040 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3041
ccdffb9a
FR		 3042 mii = &tp->mii;
3043 mii->dev = dev;
3044 mii->mdio_read = rtl_mdio_read;
3045 mii->mdio_write = rtl_mdio_write;
3046 mii->phy_id_mask = 0x1f;
3047 mii->reg_num_mask = 0x1f;
3048 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3049
1da177e4
LT		 3050 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3051 rc = pci_enable_device(pdev);
b57b7e5a 3052 if (rc < 0) {
bf82c189 3053 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3054 goto err_out_free_dev_1;
1da177e4
LT		 3055 }
3056
87aeec76 3057 if (pci_set_mwi(pdev) < 0)
3058 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3059
1da177e4 3060 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3061 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3062 netif_err(tp, probe, dev,
3063 "region #%d not an MMIO resource, aborting\n",
3064 region);
1da177e4 3065 rc = -ENODEV;
87aeec76 3066 goto err_out_mwi_2;
1da177e4 3067 }
4ff96fa6 3068
1da177e4 3069 /* check for weird/broken PCI region reporting */
bcf0bf90 3070 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3071 netif_err(tp, probe, dev,
3072 "Invalid PCI region size(s), aborting\n");
1da177e4 3073 rc = -ENODEV;
87aeec76 3074 goto err_out_mwi_2;
1da177e4
LT		 3075 }
3076
3077 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3078 if (rc < 0) {
bf82c189 3079 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3080 goto err_out_mwi_2;
1da177e4
LT		 3081 }
3082
3083 tp->cp_cmd = PCIMulRW | RxChkSum;
3084
3085 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3086 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3087 tp->cp_cmd |= PCIDAC;
3088 dev->features |= NETIF_F_HIGHDMA;
3089 } else {
284901a9 3090 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3091 if (rc < 0) {
bf82c189 3092 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3093 goto err_out_free_res_3;
1da177e4
LT		 3094 }
3095 }
3096
1da177e4 3097 /* ioremap MMIO region */
bcf0bf90 3098 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3099 if (!ioaddr) {
bf82c189 3100 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3101 rc = -EIO;
87aeec76 3102 goto err_out_free_res_3;
1da177e4
LT		 3103 }
3104
4300e8c7
DM		 3105 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3106 if (!tp->pcie_cap)
3107 netif_info(tp, probe, dev, "no PCI Express capability\n");
3108
d78ad8cb 3109 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3110
3111 /* Soft reset the chip. */
3112 RTL_W8(ChipCmd, CmdReset);
3113
3114 /* Check that the chip has finished the reset. */
07d3f51f 3115 for (i = 0; i < 100; i++) {
1da177e4
LT		 3116 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3117 break;
b518fa8e 3118 msleep_interruptible(1);
1da177e4
LT		 3119 }
3120
d78ad8cb
KW		 3121 RTL_W16(IntrStatus, 0xffff);
3122
ca52efd5 3123 pci_set_master(pdev);
3124
1da177e4
LT		 3125 /* Identify chip attached to board */
3126 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3127
f21b75e9
JD		 3128 /* Use appropriate default if unknown */
3129 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3130 netif_notice(tp, probe, dev,
3131 "unknown MAC, using family default\n");
f21b75e9
JD		 3132 tp->mac_version = cfg->default_ver;
3133 }
3134
1da177e4 3135 rtl8169_print_mac_version(tp);
1da177e4 3136
cee60c37 3137 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3138 if (tp->mac_version == rtl_chip_info[i].mac_version)
3139 break;
3140 }
cee60c37 3141 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3142 dev_err(&pdev->dev,
3143 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3144 goto err_out_msi_4;
1da177e4
LT		 3145 }
3146 tp->chipset = i;
3147
5d06a99f
FR		 3148 RTL_W8(Cfg9346, Cfg9346_Unlock);
3149 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3150 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3151 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3152 tp->features |= RTL_FEATURE_WOL;
3153 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3154 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3155 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3156 RTL_W8(Cfg9346, Cfg9346_Lock);
3157
66ec5d4f
FR		 3158 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3159 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3160 tp->set_speed = rtl8169_set_speed_tbi;
3161 tp->get_settings = rtl8169_gset_tbi;
3162 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3163 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3164 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3165 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3166
64e4bfb4 3167 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3168 } else {
3169 tp->set_speed = rtl8169_set_speed_xmii;
3170 tp->get_settings = rtl8169_gset_xmii;
3171 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3172 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3173 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3174 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3175 }
3176
df58ef51
FR		 3177 spin_lock_init(&tp->lock);
3178
738e1e69
PV		 3179 tp->mmio_addr = ioaddr;
3180
7bf6bf48 3181 /* Get MAC address */
1da177e4
LT		 3182 for (i = 0; i < MAC_ADDR_LEN; i++)
3183 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3184 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3185
1da177e4 3186 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3187 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3188 dev->irq = pdev->irq;
3189 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3190
bea3348e 3191 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3192
3193#ifdef CONFIG_R8169_VLAN
3194 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 3195#endif
2edae08e 3196 dev->features |= NETIF_F_GRO;
1da177e4
LT		 3197
3198 tp->intr_mask = 0xffff;
0e485150
FR		 3199 tp->align = cfg->align;
3200 tp->hw_start = cfg->hw_start;
3201 tp->intr_event = cfg->intr_event;
3202 tp->napi_event = cfg->napi_event;
1da177e4 3203
2efa53f3
FR		 3204 init_timer(&tp->timer);
3205 tp->timer.data = (unsigned long) dev;
3206 tp->timer.function = rtl8169_phy_timer;
3207
1da177e4 3208 rc = register_netdev(dev);
4ff96fa6 3209 if (rc < 0)
87aeec76 3210 goto err_out_msi_4;
1da177e4
LT		 3211
3212 pci_set_drvdata(pdev, dev);
3213
bf82c189
JP		 3214 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3215 rtl_chip_info[tp->chipset].name,
3216 dev->base_addr, dev->dev_addr,
3217 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3218
4ff96fa6 3219 rtl8169_init_phy(dev, tp);
05af2142
SW		 3220
3221 /*
3222 * Pretend we are using VLANs; This bypasses a nasty bug where
3223 * Interrupts stop flowing on high load on 8110SCd controllers.
3224 */
3225 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3226 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3227
8b76ab39 3228 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3229
f3ec4f87
AS		 3230 if (pci_dev_run_wake(pdev))
3231 pm_runtime_put_noidle(&pdev->dev);
e1759441 3232
4ff96fa6
FR		 3233out:
3234 return rc;
1da177e4 3235
87aeec76 3236err_out_msi_4:
fbac58fc 3237 rtl_disable_msi(pdev, tp);
4ff96fa6 3238 iounmap(ioaddr);
87aeec76 3239err_out_free_res_3:
4ff96fa6 3240 pci_release_regions(pdev);
87aeec76 3241err_out_mwi_2:
4ff96fa6 3242 pci_clear_mwi(pdev);
4ff96fa6
FR		 3243 pci_disable_device(pdev);
3244err_out_free_dev_1:
3245 free_netdev(dev);
3246 goto out;
1da177e4
LT		 3247}
3248
07d3f51f 3249static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3250{
3251 struct net_device *dev = pci_get_drvdata(pdev);
3252 struct rtl8169_private *tp = netdev_priv(dev);
3253
eb2a021c
FR		 3254 flush_scheduled_work();
3255
1da177e4 3256 unregister_netdev(dev);
cc098dc7 3257
f3ec4f87
AS		 3258 if (pci_dev_run_wake(pdev))
3259 pm_runtime_get_noresume(&pdev->dev);
e1759441 3260
cc098dc7
IV		 3261 /* restore original MAC address */
3262 rtl_rar_set(tp, dev->perm_addr);
3263
fbac58fc 3264 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3265 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3266 pci_set_drvdata(pdev, NULL);
3267}
3268
1da177e4 3269static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
c0cd884a 3270 unsigned int mtu)
1da177e4 3271{
c0cd884a
NH		 3272 unsigned int max_frame = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3273
3274 if (max_frame != 16383)
93f4d91d
NH		 3275 printk(KERN_WARNING PFX "WARNING! Changing of MTU on this "
3276 "NIC may lead to frame reception errors!\n");
1da177e4 3277
8812304c 3278 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
1da177e4
LT		 3279}
3280
3281static int rtl8169_open(struct net_device *dev)
3282{
3283 struct rtl8169_private *tp = netdev_priv(dev);
3284 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3285 int retval = -ENOMEM;
1da177e4 3286
e1759441 3287 pm_runtime_get_sync(&pdev->dev);
1da177e4 3288
c0cd884a
NH		 3289 /*
3290 * Note that we use a magic value here, its wierd I know
3291 * its done because, some subset of rtl8169 hardware suffers from
3292 * a problem in which frames received that are longer than
3293 * the size set in RxMaxSize register return garbage sizes
3294 * when received. To avoid this we need to turn off filtering,
3295 * which is done by setting a value of 16383 in the RxMaxSize register
3296 * and allocating 16k frames to handle the largest possible rx value
3297 * thats what the magic math below does.
3298 */
3299 rtl8169_set_rxbufsize(tp, 16383 - VLAN_ETH_HLEN - ETH_FCS_LEN);
1da177e4
LT		 3300
3301 /*
3302 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3303 * dma_alloc_coherent provides more.
1da177e4 3304 */
82553bb6
SG		 3305 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3306 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3307 if (!tp->TxDescArray)
e1759441 3308 goto err_pm_runtime_put;
1da177e4 3309
82553bb6
SG		 3310 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3311 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3312 if (!tp->RxDescArray)
99f252b0 3313 goto err_free_tx_0;
1da177e4
LT		 3314
3315 retval = rtl8169_init_ring(dev);
3316 if (retval < 0)
99f252b0 3317 goto err_free_rx_1;
1da177e4 3318
c4028958 3319 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3320
99f252b0
FR		 3321 smp_mb();
3322
fbac58fc
FR		 3323 retval = request_irq(dev->irq, rtl8169_interrupt,
3324 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3325 dev->name, dev);
3326 if (retval < 0)
3327 goto err_release_ring_2;
3328
bea3348e 3329 napi_enable(&tp->napi);
bea3348e 3330
07ce4064 3331 rtl_hw_start(dev);
1da177e4
LT		 3332
3333 rtl8169_request_timer(dev);
3334
e1759441
RW		 3335 tp->saved_wolopts = 0;
3336 pm_runtime_put_noidle(&pdev->dev);
3337
1da177e4
LT		 3338 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3339out:
3340 return retval;
3341
99f252b0
FR		 3342err_release_ring_2:
3343 rtl8169_rx_clear(tp);
3344err_free_rx_1:
82553bb6
SG		 3345 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3346 tp->RxPhyAddr);
e1759441 3347 tp->RxDescArray = NULL;
99f252b0 3348err_free_tx_0:
82553bb6
SG		 3349 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3350 tp->TxPhyAddr);
e1759441
RW		 3351 tp->TxDescArray = NULL;
3352err_pm_runtime_put:
3353 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3354 goto out;
3355}
3356
3357static void rtl8169_hw_reset(void __iomem *ioaddr)
3358{
3359 /* Disable interrupts */
3360 rtl8169_irq_mask_and_ack(ioaddr);
3361
3362 /* Reset the chipset */
3363 RTL_W8(ChipCmd, CmdReset);
3364
3365 /* PCI commit */
3366 RTL_R8(ChipCmd);
3367}
3368
7f796d83 3369static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3370{
3371 void __iomem *ioaddr = tp->mmio_addr;
3372 u32 cfg = rtl8169_rx_config;
3373
3374 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3375 RTL_W32(RxConfig, cfg);
3376
3377 /* Set DMA burst size and Interframe Gap Time */
3378 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3379 (InterFrameGap << TxInterFrameGapShift));
3380}
3381
07ce4064 3382static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3383{
3384 struct rtl8169_private *tp = netdev_priv(dev);
3385 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3386 unsigned int i;
1da177e4
LT		 3387
3388 /* Soft reset the chip. */
3389 RTL_W8(ChipCmd, CmdReset);
3390
3391 /* Check that the chip has finished the reset. */
07d3f51f 3392 for (i = 0; i < 100; i++) {
1da177e4
LT		 3393 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3394 break;
b518fa8e 3395 msleep_interruptible(1);
1da177e4
LT		 3396 }
3397
07ce4064
FR		 3398 tp->hw_start(dev);
3399
07ce4064
FR		 3400 netif_start_queue(dev);
3401}
3402
3403
7f796d83
FR		 3404static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3405 void __iomem *ioaddr)
3406{
3407 /*
3408 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3409 * register to be written before TxDescAddrLow to work.
3410 * Switching from MMIO to I/O access fixes the issue as well.
3411 */
3412 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3413 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3414 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3415 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3416}
3417
3418static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3419{
3420 u16 cmd;
3421
3422 cmd = RTL_R16(CPlusCmd);
3423 RTL_W16(CPlusCmd, cmd);
3424 return cmd;
3425}
3426
fdd7b4c3 3427static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3428{
3429 /* Low hurts. Let's disable the filtering. */
207d6e87 3430 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3431}
3432
6dccd16b
FR		 3433static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3434{
350f7596 3435 static const struct {
6dccd16b
FR		 3436 u32 mac_version;
3437 u32 clk;
3438 u32 val;
3439 } cfg2_info [] = {
3440 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3441 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3442 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3443 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3444 }, *p = cfg2_info;
3445 unsigned int i;
3446 u32 clk;
3447
3448 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3449 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3450 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3451 RTL_W32(0x7c, p->val);
3452 break;
3453 }
3454 }
3455}
3456
07ce4064
FR		 3457static void rtl_hw_start_8169(struct net_device *dev)
3458{
3459 struct rtl8169_private *tp = netdev_priv(dev);
3460 void __iomem *ioaddr = tp->mmio_addr;
3461 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3462
9cb427b6
FR		 3463 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3464 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3465 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3466 }
3467
1da177e4 3468 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3469 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3470 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3471 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3472 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3473 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3474
1da177e4
LT		 3475 RTL_W8(EarlyTxThres, EarlyTxThld);
3476
fdd7b4c3 3477 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
1da177e4 3478
c946b304
FR		 3479 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3480 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3481 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3482 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3483 rtl_set_rx_tx_config_registers(tp);
1da177e4 3484
7f796d83 3485 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3486
bcf0bf90
FR		 3487 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3488 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3489 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3490 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3491 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3492 }
3493
bcf0bf90
FR		 3494 RTL_W16(CPlusCmd, tp->cp_cmd);
3495
6dccd16b
FR		 3496 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3497
1da177e4
LT		 3498 /*
3499 * Undocumented corner. Supposedly:
3500 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3501 */
3502 RTL_W16(IntrMitigate, 0x0000);
3503
7f796d83 3504 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3505
c946b304
FR		 3506 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3507 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3508 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3509 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3510 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3511 rtl_set_rx_tx_config_registers(tp);
3512 }
3513
1da177e4 3514 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3515
3516 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3517 RTL_R8(IntrMask);
1da177e4
LT		 3518
3519 RTL_W32(RxMissed, 0);
3520
07ce4064 3521 rtl_set_rx_mode(dev);
1da177e4
LT		 3522
3523 /* no early-rx interrupts */
3524 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3525
3526 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3527 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3528}
1da177e4 3529
9c14ceaf 3530static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3531{
9c14ceaf
FR		 3532 struct net_device *dev = pci_get_drvdata(pdev);
3533 struct rtl8169_private *tp = netdev_priv(dev);
3534 int cap = tp->pcie_cap;
3535
3536 if (cap) {
3537 u16 ctl;
458a9f61 3538
9c14ceaf
FR		 3539 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3540 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3541 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3542 }
458a9f61
FR		 3543}
3544
dacf8154
FR		 3545static void rtl_csi_access_enable(void __iomem *ioaddr)
3546{
3547 u32 csi;
3548
3549 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3550 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3551}
3552
3553struct ephy_info {
3554 unsigned int offset;
3555 u16 mask;
3556 u16 bits;
3557};
3558
350f7596 3559static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3560{
3561 u16 w;
3562
3563 while (len-- > 0) {
3564 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3565 rtl_ephy_write(ioaddr, e->offset, w);
3566 e++;
3567 }
3568}
3569
b726e493
FR		 3570static void rtl_disable_clock_request(struct pci_dev *pdev)
3571{
3572 struct net_device *dev = pci_get_drvdata(pdev);
3573 struct rtl8169_private *tp = netdev_priv(dev);
3574 int cap = tp->pcie_cap;
3575
3576 if (cap) {
3577 u16 ctl;
3578
3579 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3580 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3581 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3582 }
3583}
3584
3585#define R8168_CPCMD_QUIRK_MASK (\
3586 EnableBist | \
3587 Mac_dbgo_oe | \
3588 Force_half_dup | \
3589 Force_rxflow_en | \
3590 Force_txflow_en | \
3591 Cxpl_dbg_sel | \
3592 ASF | \
3593 PktCntrDisable | \
3594 Mac_dbgo_sel)
3595
219a1e9d
FR		 3596static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3597{
b726e493
FR		 3598 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3599
3600 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3601
2e68ae44
FR		 3602 rtl_tx_performance_tweak(pdev,
3603 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3604}
3605
3606static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3607{
3608 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 3609
3610 RTL_W8(EarlyTxThres, EarlyTxThld);
3611
3612 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3613}
3614
3615static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3616{
b726e493
FR		 3617 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3618
3619 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3620
219a1e9d 3621 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3622
3623 rtl_disable_clock_request(pdev);
3624
3625 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3626}
3627
ef3386f0 3628static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3629{
350f7596 3630 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3631 { 0x01, 0, 0x0001 },
3632 { 0x02, 0x0800, 0x1000 },
3633 { 0x03, 0, 0x0042 },
3634 { 0x06, 0x0080, 0x0000 },
3635 { 0x07, 0, 0x2000 }
3636 };
3637
3638 rtl_csi_access_enable(ioaddr);
3639
3640 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3641
219a1e9d
FR		 3642 __rtl_hw_start_8168cp(ioaddr, pdev);
3643}
3644
ef3386f0
FR		 3645static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3646{
3647 rtl_csi_access_enable(ioaddr);
3648
3649 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3650
3651 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3652
3653 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3654}
3655
7f3e3d3a
FR		 3656static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3657{
3658 rtl_csi_access_enable(ioaddr);
3659
3660 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3661
3662 /* Magic. */
3663 RTL_W8(DBG_REG, 0x20);
3664
3665 RTL_W8(EarlyTxThres, EarlyTxThld);
3666
3667 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3668
3669 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3670}
3671
219a1e9d
FR		 3672static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3673{
350f7596 3674 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3675 { 0x02, 0x0800, 0x1000 },
3676 { 0x03, 0, 0x0002 },
3677 { 0x06, 0x0080, 0x0000 }
3678 };
3679
3680 rtl_csi_access_enable(ioaddr);
3681
3682 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3683
3684 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3685
219a1e9d
FR		 3686 __rtl_hw_start_8168cp(ioaddr, pdev);
3687}
3688
3689static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3690{
350f7596 3691 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3692 { 0x01, 0, 0x0001 },
3693 { 0x03, 0x0400, 0x0220 }
3694 };
3695
3696 rtl_csi_access_enable(ioaddr);
3697
3698 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3699
219a1e9d
FR		 3700 __rtl_hw_start_8168cp(ioaddr, pdev);
3701}
3702
197ff761
FR		 3703static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3704{
3705 rtl_hw_start_8168c_2(ioaddr, pdev);
3706}
3707
6fb07058
FR		 3708static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3709{
3710 rtl_csi_access_enable(ioaddr);
3711
3712 __rtl_hw_start_8168cp(ioaddr, pdev);
3713}
3714
5b538df9
FR		 3715static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3716{
3717 rtl_csi_access_enable(ioaddr);
3718
3719 rtl_disable_clock_request(pdev);
3720
3721 RTL_W8(EarlyTxThres, EarlyTxThld);
3722
3723 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3724
3725 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3726}
3727
07ce4064
FR		 3728static void rtl_hw_start_8168(struct net_device *dev)
3729{
2dd99530
FR		 3730 struct rtl8169_private *tp = netdev_priv(dev);
3731 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3732 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3733
3734 RTL_W8(Cfg9346, Cfg9346_Unlock);
3735
3736 RTL_W8(EarlyTxThres, EarlyTxThld);
3737
fdd7b4c3 3738 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2dd99530 3739
0e485150 3740 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3741
3742 RTL_W16(CPlusCmd, tp->cp_cmd);
3743
0e485150 3744 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3745
0e485150
FR		 3746 /* Work around for RxFIFO overflow. */
3747 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3748 tp->intr_event |= RxFIFOOver | PCSTimeout;
3749 tp->intr_event &= ~RxOverflow;
3750 }
3751
3752 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3753
b8363901
FR		 3754 rtl_set_rx_mode(dev);
3755
3756 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3757 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3758
3759 RTL_R8(IntrMask);
3760
219a1e9d
FR		 3761 switch (tp->mac_version) {
3762 case RTL_GIGA_MAC_VER_11:
3763 rtl_hw_start_8168bb(ioaddr, pdev);
3764 break;
3765
3766 case RTL_GIGA_MAC_VER_12:
3767 case RTL_GIGA_MAC_VER_17:
3768 rtl_hw_start_8168bef(ioaddr, pdev);
3769 break;
3770
3771 case RTL_GIGA_MAC_VER_18:
ef3386f0 3772 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3773 break;
3774
3775 case RTL_GIGA_MAC_VER_19:
3776 rtl_hw_start_8168c_1(ioaddr, pdev);
3777 break;
3778
3779 case RTL_GIGA_MAC_VER_20:
3780 rtl_hw_start_8168c_2(ioaddr, pdev);
3781 break;
3782
197ff761
FR		 3783 case RTL_GIGA_MAC_VER_21:
3784 rtl_hw_start_8168c_3(ioaddr, pdev);
3785 break;
3786
6fb07058
FR		 3787 case RTL_GIGA_MAC_VER_22:
3788 rtl_hw_start_8168c_4(ioaddr, pdev);
3789 break;
3790
ef3386f0
FR		 3791 case RTL_GIGA_MAC_VER_23:
3792 rtl_hw_start_8168cp_2(ioaddr, pdev);
3793 break;
3794
7f3e3d3a
FR		 3795 case RTL_GIGA_MAC_VER_24:
3796 rtl_hw_start_8168cp_3(ioaddr, pdev);
3797 break;
3798
5b538df9 3799 case RTL_GIGA_MAC_VER_25:
daf9df6d 3800 case RTL_GIGA_MAC_VER_26:
3801 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3802 rtl_hw_start_8168d(ioaddr, pdev);
3803 break;
3804
219a1e9d
FR		 3805 default:
3806 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3807 dev->name, tp->mac_version);
3808 break;
3809 }
2dd99530 3810
0e485150
FR		 3811 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3812
b8363901
FR		 3813 RTL_W8(Cfg9346, Cfg9346_Lock);
3814
2dd99530 3815 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3816
0e485150 3817 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3818}
1da177e4 3819
2857ffb7
FR		 3820#define R810X_CPCMD_QUIRK_MASK (\
3821 EnableBist | \
3822 Mac_dbgo_oe | \
3823 Force_half_dup | \
5edcc537 3824 Force_rxflow_en | \
2857ffb7
FR		 3825 Force_txflow_en | \
3826 Cxpl_dbg_sel | \
3827 ASF | \
3828 PktCntrDisable | \
3829 PCIDAC | \
3830 PCIMulRW)
3831
3832static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3833{
350f7596 3834 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3835 { 0x01, 0, 0x6e65 },
3836 { 0x02, 0, 0x091f },
3837 { 0x03, 0, 0xc2f9 },
3838 { 0x06, 0, 0xafb5 },
3839 { 0x07, 0, 0x0e00 },
3840 { 0x19, 0, 0xec80 },
3841 { 0x01, 0, 0x2e65 },
3842 { 0x01, 0, 0x6e65 }
3843 };
3844 u8 cfg1;
3845
3846 rtl_csi_access_enable(ioaddr);
3847
3848 RTL_W8(DBG_REG, FIX_NAK_1);
3849
3850 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3851
3852 RTL_W8(Config1,
3853 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3854 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3855
3856 cfg1 = RTL_R8(Config1);
3857 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3858 RTL_W8(Config1, cfg1 & ~LEDS0);
3859
3860 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3861
3862 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3863}
3864
3865static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3866{
3867 rtl_csi_access_enable(ioaddr);
3868
3869 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3870
3871 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3872 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3873
3874 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3875}
3876
3877static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3878{
3879 rtl_hw_start_8102e_2(ioaddr, pdev);
3880
3881 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3882}
3883
07ce4064
FR		 3884static void rtl_hw_start_8101(struct net_device *dev)
3885{
cdf1a608
FR		 3886 struct rtl8169_private *tp = netdev_priv(dev);
3887 void __iomem *ioaddr = tp->mmio_addr;
3888 struct pci_dev *pdev = tp->pci_dev;
3889
e3cf0cc0
FR		 3890 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3891 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3892 int cap = tp->pcie_cap;
3893
3894 if (cap) {
3895 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3896 PCI_EXP_DEVCTL_NOSNOOP_EN);
3897 }
cdf1a608
FR		 3898 }
3899
2857ffb7
FR		 3900 switch (tp->mac_version) {
3901 case RTL_GIGA_MAC_VER_07:
3902 rtl_hw_start_8102e_1(ioaddr, pdev);
3903 break;
3904
3905 case RTL_GIGA_MAC_VER_08:
3906 rtl_hw_start_8102e_3(ioaddr, pdev);
3907 break;
3908
3909 case RTL_GIGA_MAC_VER_09:
3910 rtl_hw_start_8102e_2(ioaddr, pdev);
3911 break;
cdf1a608
FR		 3912 }
3913
3914 RTL_W8(Cfg9346, Cfg9346_Unlock);
3915
3916 RTL_W8(EarlyTxThres, EarlyTxThld);
3917
fdd7b4c3 3918 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
cdf1a608
FR		 3919
3920 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3921
3922 RTL_W16(CPlusCmd, tp->cp_cmd);
3923
3924 RTL_W16(IntrMitigate, 0x0000);
3925
3926 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3927
3928 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3929 rtl_set_rx_tx_config_registers(tp);
3930
3931 RTL_W8(Cfg9346, Cfg9346_Lock);
3932
3933 RTL_R8(IntrMask);
3934
cdf1a608
FR		 3935 rtl_set_rx_mode(dev);
3936
0e485150
FR		 3937 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3938
cdf1a608 3939 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3940
0e485150 3941 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3942}
3943
3944static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3945{
3946 struct rtl8169_private *tp = netdev_priv(dev);
3947 int ret = 0;
3948
3949 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3950 return -EINVAL;
3951
3952 dev->mtu = new_mtu;
3953
3954 if (!netif_running(dev))
3955 goto out;
3956
3957 rtl8169_down(dev);
3958
c0cd884a 3959 rtl8169_set_rxbufsize(tp, dev->mtu);
1da177e4
LT		 3960
3961 ret = rtl8169_init_ring(dev);
3962 if (ret < 0)
3963 goto out;
3964
bea3348e 3965 napi_enable(&tp->napi);
1da177e4 3966
07ce4064 3967 rtl_hw_start(dev);
1da177e4
LT		 3968
3969 rtl8169_request_timer(dev);
3970
3971out:
3972 return ret;
3973}
3974
3975static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3976{
95e0918d 3977 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3978 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3979}
3980
3981static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3982 struct sk_buff **sk_buff, struct RxDesc *desc)
3983{
3984 struct pci_dev *pdev = tp->pci_dev;
3985
82553bb6 3986 dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1da177e4
LT		 3987 PCI_DMA_FROMDEVICE);
3988 dev_kfree_skb(*sk_buff);
3989 *sk_buff = NULL;
3990 rtl8169_make_unusable_by_asic(desc);
3991}
3992
3993static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3994{
3995 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3996
3997 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3998}
3999
4000static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4001 u32 rx_buf_sz)
4002{
4003 desc->addr = cpu_to_le64(mapping);
4004 wmb();
4005 rtl8169_mark_to_asic(desc, rx_buf_sz);
4006}
4007
15d31758
SH		 4008static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
4009 struct net_device *dev,
4010 struct RxDesc *desc, int rx_buf_sz,
aeb19f60 4011 unsigned int align, gfp_t gfp)
1da177e4
LT		 4012{
4013 struct sk_buff *skb;
4014 dma_addr_t mapping;
e9f63f30 4015 unsigned int pad;
1da177e4 4016
e9f63f30
FR		 4017 pad = align ? align : NET_IP_ALIGN;
4018
aeb19f60 4019 skb = __netdev_alloc_skb(dev, rx_buf_sz + pad, gfp);
1da177e4
LT		 4020 if (!skb)
4021 goto err_out;
4022
e9f63f30 4023 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 4024
82553bb6 4025 mapping = dma_map_single(&pdev->dev, skb->data, rx_buf_sz,
1da177e4
LT		 4026 PCI_DMA_FROMDEVICE);
4027
4028 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 4029out:
15d31758 4030 return skb;
1da177e4
LT		 4031
4032err_out:
1da177e4
LT		 4033 rtl8169_make_unusable_by_asic(desc);
4034 goto out;
4035}
4036
4037static void rtl8169_rx_clear(struct rtl8169_private *tp)
4038{
07d3f51f 4039 unsigned int i;
1da177e4
LT		 4040
4041 for (i = 0; i < NUM_RX_DESC; i++) {
4042 if (tp->Rx_skbuff[i]) {
4043 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
4044 tp->RxDescArray + i);
4045 }
4046 }
4047}
4048
4049static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
aeb19f60 4050 u32 start, u32 end, gfp_t gfp)
1da177e4
LT		 4051{
4052 u32 cur;
5b0384f4 4053
4ae47c2d 4054 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 4055 struct sk_buff *skb;
4056 unsigned int i = cur % NUM_RX_DESC;
1da177e4 4057
4ae47c2d
FR		 4058 WARN_ON((s32)(end - cur) < 0);
4059
1da177e4
LT		 4060 if (tp->Rx_skbuff[i])
4061 continue;
bcf0bf90 4062
15d31758
SH		 4063 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4064 tp->RxDescArray + i,
aeb19f60 4065 tp->rx_buf_sz, tp->align, gfp);
15d31758 4066 if (!skb)
1da177e4 4067 break;
15d31758
SH		 4068
4069 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 4070 }
4071 return cur - start;
4072}
4073
4074static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4075{
4076 desc->opts1 |= cpu_to_le32(RingEnd);
4077}
4078
4079static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4080{
4081 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4082}
4083
4084static int rtl8169_init_ring(struct net_device *dev)
4085{
4086 struct rtl8169_private *tp = netdev_priv(dev);
4087
4088 rtl8169_init_ring_indexes(tp);
4089
4090 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4091 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4092
aeb19f60 4093 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC, GFP_KERNEL) != NUM_RX_DESC)
1da177e4
LT		 4094 goto err_out;
4095
4096 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4097
4098 return 0;
4099
4100err_out:
4101 rtl8169_rx_clear(tp);
4102 return -ENOMEM;
4103}
4104
4105static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4106 struct TxDesc *desc)
4107{
4108 unsigned int len = tx_skb->len;
4109
82553bb6
SG		 4110 dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), len,
4111 PCI_DMA_TODEVICE);
1da177e4
LT		 4112 desc->opts1 = 0x00;
4113 desc->opts2 = 0x00;
4114 desc->addr = 0x00;
4115 tx_skb->len = 0;
4116}
4117
4118static void rtl8169_tx_clear(struct rtl8169_private *tp)
4119{
4120 unsigned int i;
4121
4122 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4123 unsigned int entry = i % NUM_TX_DESC;
4124 struct ring_info *tx_skb = tp->tx_skb + entry;
4125 unsigned int len = tx_skb->len;
4126
4127 if (len) {
4128 struct sk_buff *skb = tx_skb->skb;
4129
4130 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4131 tp->TxDescArray + entry);
4132 if (skb) {
4133 dev_kfree_skb(skb);
4134 tx_skb->skb = NULL;
4135 }
cebf8cc7 4136 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4137 }
4138 }
4139 tp->cur_tx = tp->dirty_tx = 0;
4140}
4141
c4028958 4142static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4143{
4144 struct rtl8169_private *tp = netdev_priv(dev);
4145
c4028958 4146 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4147 schedule_delayed_work(&tp->task, 4);
4148}
4149
4150static void rtl8169_wait_for_quiescence(struct net_device *dev)
4151{
4152 struct rtl8169_private *tp = netdev_priv(dev);
4153 void __iomem *ioaddr = tp->mmio_addr;
4154
4155 synchronize_irq(dev->irq);
4156
4157 /* Wait for any pending NAPI task to complete */
bea3348e 4158 napi_disable(&tp->napi);
1da177e4
LT		 4159
4160 rtl8169_irq_mask_and_ack(ioaddr);
4161
d1d08d12
DM		 4162 tp->intr_mask = 0xffff;
4163 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4164 napi_enable(&tp->napi);
1da177e4
LT		 4165}
4166
c4028958 4167static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4168{
c4028958
DH		 4169 struct rtl8169_private *tp =
4170 container_of(work, struct rtl8169_private, task.work);
4171 struct net_device *dev = tp->dev;
1da177e4
LT		 4172 int ret;
4173
eb2a021c
FR		 4174 rtnl_lock();
4175
4176 if (!netif_running(dev))
4177 goto out_unlock;
4178
4179 rtl8169_wait_for_quiescence(dev);
4180 rtl8169_close(dev);
1da177e4
LT		 4181
4182 ret = rtl8169_open(dev);
4183 if (unlikely(ret < 0)) {
bf82c189
JP		 4184 if (net_ratelimit())
4185 netif_err(tp, drv, dev,
4186 "reinit failure (status = %d). Rescheduling\n",
4187 ret);
1da177e4
LT		 4188 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4189 }
eb2a021c
FR		 4190
4191out_unlock:
4192 rtnl_unlock();
1da177e4
LT		 4193}
4194
c4028958 4195static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4196{
c4028958
DH		 4197 struct rtl8169_private *tp =
4198 container_of(work, struct rtl8169_private, task.work);
4199 struct net_device *dev = tp->dev;
1da177e4 4200
eb2a021c
FR		 4201 rtnl_lock();
4202
1da177e4 4203 if (!netif_running(dev))
eb2a021c 4204 goto out_unlock;
1da177e4
LT		 4205
4206 rtl8169_wait_for_quiescence(dev);
4207
bea3348e 4208 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4209 rtl8169_tx_clear(tp);
4210
4211 if (tp->dirty_rx == tp->cur_rx) {
4212 rtl8169_init_ring_indexes(tp);
07ce4064 4213 rtl_hw_start(dev);
1da177e4 4214 netif_wake_queue(dev);
cebf8cc7 4215 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4216 } else {
bf82c189
JP		 4217 if (net_ratelimit())
4218 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4219 rtl8169_schedule_work(dev, rtl8169_reset_task);
4220 }
eb2a021c
FR		 4221
4222out_unlock:
4223 rtnl_unlock();
1da177e4
LT		 4224}
4225
4226static void rtl8169_tx_timeout(struct net_device *dev)
4227{
4228 struct rtl8169_private *tp = netdev_priv(dev);
4229
4230 rtl8169_hw_reset(tp->mmio_addr);
4231
4232 /* Let's wait a bit while any (async) irq lands on */
4233 rtl8169_schedule_work(dev, rtl8169_reset_task);
4234}
4235
4236static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4237 u32 opts1)
4238{
4239 struct skb_shared_info *info = skb_shinfo(skb);
4240 unsigned int cur_frag, entry;
a6343afb 4241 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 4242
4243 entry = tp->cur_tx;
4244 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4245 skb_frag_t *frag = info->frags + cur_frag;
4246 dma_addr_t mapping;
4247 u32 status, len;
4248 void *addr;
4249
4250 entry = (entry + 1) % NUM_TX_DESC;
4251
4252 txd = tp->TxDescArray + entry;
4253 len = frag->size;
4254 addr = ((void *) page_address(frag->page)) + frag->page_offset;
82553bb6
SG		 4255 mapping = dma_map_single(&tp->pci_dev->dev, addr, len,
4256 PCI_DMA_TODEVICE);
1da177e4
LT		 4257
4258 /* anti gcc 2.95.3 bugware (sic) */
4259 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4260
4261 txd->opts1 = cpu_to_le32(status);
4262 txd->addr = cpu_to_le64(mapping);
4263
4264 tp->tx_skb[entry].len = len;
4265 }
4266
4267 if (cur_frag) {
4268 tp->tx_skb[entry].skb = skb;
4269 txd->opts1 |= cpu_to_le32(LastFrag);
4270 }
4271
4272 return cur_frag;
4273}
4274
4275static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4276{
4277 if (dev->features & NETIF_F_TSO) {
7967168c 4278 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4279
4280 if (mss)
4281 return LargeSend | ((mss & MSSMask) << MSSShift);
4282 }
84fa7933 4283 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4284 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4285
4286 if (ip->protocol == IPPROTO_TCP)
4287 return IPCS | TCPCS;
4288 else if (ip->protocol == IPPROTO_UDP)
4289 return IPCS | UDPCS;
4290 WARN_ON(1); /* we need a WARN() */
4291 }
4292 return 0;
4293}
4294
61357325
SH		 4295static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4296 struct net_device *dev)
1da177e4
LT		 4297{
4298 struct rtl8169_private *tp = netdev_priv(dev);
4299 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4300 struct TxDesc *txd = tp->TxDescArray + entry;
4301 void __iomem *ioaddr = tp->mmio_addr;
4302 dma_addr_t mapping;
4303 u32 status, len;
4304 u32 opts1;
5b0384f4 4305
1da177e4 4306 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4307 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
1da177e4
LT		 4308 goto err_stop;
4309 }
4310
4311 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4312 goto err_stop;
4313
4314 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4315
4316 frags = rtl8169_xmit_frags(tp, skb, opts1);
4317 if (frags) {
4318 len = skb_headlen(skb);
4319 opts1 |= FirstFrag;
4320 } else {
4321 len = skb->len;
1da177e4
LT		 4322 opts1 |= FirstFrag | LastFrag;
4323 tp->tx_skb[entry].skb = skb;
4324 }
4325
82553bb6
SG		 4326 mapping = dma_map_single(&tp->pci_dev->dev, skb->data, len,
4327 PCI_DMA_TODEVICE);
1da177e4
LT		 4328
4329 tp->tx_skb[entry].len = len;
4330 txd->addr = cpu_to_le64(mapping);
4331 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4332
4333 wmb();
4334
4335 /* anti gcc 2.95.3 bugware (sic) */
4336 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4337 txd->opts1 = cpu_to_le32(status);
4338
1da177e4
LT		 4339 tp->cur_tx += frags + 1;
4340
4c020a96 4341 wmb();
1da177e4 4342
275391a4 4343 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4344
4345 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4346 netif_stop_queue(dev);
4347 smp_rmb();
4348 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4349 netif_wake_queue(dev);
4350 }
4351
61357325 4352 return NETDEV_TX_OK;
1da177e4
LT		 4353
4354err_stop:
4355 netif_stop_queue(dev);
cebf8cc7 4356 dev->stats.tx_dropped++;
61357325 4357 return NETDEV_TX_BUSY;
1da177e4
LT		 4358}
4359
4360static void rtl8169_pcierr_interrupt(struct net_device *dev)
4361{
4362 struct rtl8169_private *tp = netdev_priv(dev);
4363 struct pci_dev *pdev = tp->pci_dev;
4364 void __iomem *ioaddr = tp->mmio_addr;
4365 u16 pci_status, pci_cmd;
4366
4367 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4368 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4369
bf82c189
JP		 4370 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4371 pci_cmd, pci_status);
1da177e4
LT		 4372
4373 /*
4374 * The recovery sequence below admits a very elaborated explanation:
4375 * - it seems to work;
d03902b8
FR		 4376 * - I did not see what else could be done;
4377 * - it makes iop3xx happy.
1da177e4
LT		 4378 *
4379 * Feel free to adjust to your needs.
4380 */
a27993f3 4381 if (pdev->broken_parity_status)
d03902b8
FR		 4382 pci_cmd &= ~PCI_COMMAND_PARITY;
4383 else
4384 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4385
4386 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4387
4388 pci_write_config_word(pdev, PCI_STATUS,
4389 pci_status & (PCI_STATUS_DETECTED_PARITY |
4390 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4391 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4392
4393 /* The infamous DAC f*ckup only happens at boot time */
4394 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
bf82c189 4395 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4396 tp->cp_cmd &= ~PCIDAC;
4397 RTL_W16(CPlusCmd, tp->cp_cmd);
4398 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4399 }
4400
4401 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 4402
4403 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4404}
4405
07d3f51f
FR		 4406static void rtl8169_tx_interrupt(struct net_device *dev,
4407 struct rtl8169_private *tp,
4408 void __iomem *ioaddr)
1da177e4
LT		 4409{
4410 unsigned int dirty_tx, tx_left;
4411
1da177e4
LT		 4412 dirty_tx = tp->dirty_tx;
4413 smp_rmb();
4414 tx_left = tp->cur_tx - dirty_tx;
4415
4416 while (tx_left > 0) {
4417 unsigned int entry = dirty_tx % NUM_TX_DESC;
4418 struct ring_info *tx_skb = tp->tx_skb + entry;
4419 u32 len = tx_skb->len;
4420 u32 status;
4421
4422 rmb();
4423 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4424 if (status & DescOwn)
4425 break;
4426
cebf8cc7
FR		 4427 dev->stats.tx_bytes += len;
4428 dev->stats.tx_packets++;
1da177e4
LT		 4429
4430 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4431
4432 if (status & LastFrag) {
87433bfc 4433 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4434 tx_skb->skb = NULL;
4435 }
4436 dirty_tx++;
4437 tx_left--;
4438 }
4439
4440 if (tp->dirty_tx != dirty_tx) {
4441 tp->dirty_tx = dirty_tx;
4442 smp_wmb();
4443 if (netif_queue_stopped(dev) &&
4444 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4445 netif_wake_queue(dev);
4446 }
d78ae2dc
FR		 4447 /*
4448 * 8168 hack: TxPoll requests are lost when the Tx packets are
4449 * too close. Let's kick an extra TxPoll request when a burst
4450 * of start_xmit activity is detected (if it is not detected,
4451 * it is slow enough). -- FR
4452 */
4453 smp_rmb();
4454 if (tp->cur_tx != dirty_tx)
4455 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4456 }
4457}
4458
126fa4b9
FR		 4459static inline int rtl8169_fragmented_frame(u32 status)
4460{
4461 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4462}
4463
adea1ac7 4464static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4465{
1da177e4
LT		 4466 u32 status = opts1 & RxProtoMask;
4467
4468 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4469 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4470 ((status == RxProtoIP) && !(opts1 & IPFail)))
4471 skb->ip_summed = CHECKSUM_UNNECESSARY;
4472 else
bc8acf2c 4473 skb_checksum_none_assert(skb);
1da177e4
LT		 4474}
4475
07d3f51f
FR		 4476static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4477 struct rtl8169_private *tp, int pkt_size,
4478 dma_addr_t addr)
1da177e4 4479{
b449655f
SH		 4480 struct sk_buff *skb;
4481 bool done = false;
1da177e4 4482
b449655f
SH		 4483 if (pkt_size >= rx_copybreak)
4484 goto out;
1da177e4 4485
89d71a66 4486 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
b449655f
SH		 4487 if (!skb)
4488 goto out;
4489
82553bb6
SG		 4490 dma_sync_single_for_cpu(&tp->pci_dev->dev, addr, pkt_size,
4491 PCI_DMA_FROMDEVICE);
b449655f
SH		 4492 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4493 *sk_buff = skb;
4494 done = true;
4495out:
4496 return done;
1da177e4
LT		 4497}
4498
630b943c
ED		 4499/*
4500 * Warning : rtl8169_rx_interrupt() might be called :
4501 * 1) from NAPI (softirq) context
4502 * (polling = 1 : we should call netif_receive_skb())
4503 * 2) from process context (rtl8169_reset_task())
4504 * (polling = 0 : we must call netif_rx() instead)
4505 */
07d3f51f
FR		 4506static int rtl8169_rx_interrupt(struct net_device *dev,
4507 struct rtl8169_private *tp,
bea3348e 4508 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4509{
4510 unsigned int cur_rx, rx_left;
4511 unsigned int delta, count;
630b943c 4512 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4513
1da177e4
LT		 4514 cur_rx = tp->cur_rx;
4515 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4516 rx_left = min(rx_left, budget);
1da177e4 4517
4dcb7d33 4518 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4519 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4520 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4521 u32 status;
4522
4523 rmb();
126fa4b9 4524 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4525
4526 if (status & DescOwn)
4527 break;
4dcb7d33 4528 if (unlikely(status & RxRES)) {
bf82c189
JP		 4529 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4530 status);
cebf8cc7 4531 dev->stats.rx_errors++;
1da177e4 4532 if (status & (RxRWT | RxRUNT))
cebf8cc7 4533 dev->stats.rx_length_errors++;
1da177e4 4534 if (status & RxCRC)
cebf8cc7 4535 dev->stats.rx_crc_errors++;
9dccf611
FR		 4536 if (status & RxFOVF) {
4537 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4538 dev->stats.rx_fifo_errors++;
9dccf611 4539 }
126fa4b9 4540 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 4541 } else {
1da177e4 4542 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 4543 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4544 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 4545 struct pci_dev *pdev = tp->pci_dev;
1da177e4 4546
126fa4b9
FR		 4547 /*
4548 * The driver does not support incoming fragmented
4549 * frames. They are seen as a symptom of over-mtu
4550 * sized frames.
4551 */
4552 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4553 dev->stats.rx_dropped++;
4554 dev->stats.rx_length_errors++;
126fa4b9 4555 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 4556 continue;
126fa4b9
FR		 4557 }
4558
07d3f51f 4559 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
82553bb6 4560 dma_sync_single_for_device(&pdev->dev, addr,
b449655f
SH		 4561 pkt_size, PCI_DMA_FROMDEVICE);
4562 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4563 } else {
82553bb6 4564 dma_unmap_single(&pdev->dev, addr, tp->rx_buf_sz,
b449655f 4565 PCI_DMA_FROMDEVICE);
1da177e4
LT		 4566 tp->Rx_skbuff[entry] = NULL;
4567 }
4568
adea1ac7 4569 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4570 skb_put(skb, pkt_size);
4571 skb->protocol = eth_type_trans(skb, dev);
4572
630b943c
ED		 4573 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4574 if (likely(polling))
2edae08e 4575 napi_gro_receive(&tp->napi, skb);
630b943c
ED		 4576 else
4577 netif_rx(skb);
4578 }
1da177e4 4579
cebf8cc7
FR		 4580 dev->stats.rx_bytes += pkt_size;
4581 dev->stats.rx_packets++;
1da177e4 4582 }
6dccd16b
FR		 4583
4584 /* Work around for AMD plateform. */
95e0918d 4585 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4586 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4587 desc->opts2 = 0;
4588 cur_rx++;
4589 }
1da177e4
LT		 4590 }
4591
4592 count = cur_rx - tp->cur_rx;
4593 tp->cur_rx = cur_rx;
4594
aeb19f60 4595 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx, GFP_ATOMIC);
bf82c189
JP		 4596 if (!delta && count)
4597 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
1da177e4
LT		 4598 tp->dirty_rx += delta;
4599
4600 /*
4601 * FIXME: until there is periodic timer to try and refill the ring,
4602 * a temporary shortage may definitely kill the Rx process.
4603 * - disable the asic to try and avoid an overflow and kick it again
4604 * after refill ?
4605 * - how do others driver handle this condition (Uh oh...).
4606 */
bf82c189
JP		 4607 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4608 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
1da177e4
LT		 4609
4610 return count;
4611}
4612
07d3f51f 4613static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4614{
07d3f51f 4615 struct net_device *dev = dev_instance;
1da177e4 4616 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4617 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4618 int handled = 0;
865c652d 4619 int status;
1da177e4 4620
f11a377b
DD		 4621 /* loop handling interrupts until we have no new ones or
4622 * we hit a invalid/hotplug case.
4623 */
865c652d 4624 status = RTL_R16(IntrStatus);
f11a377b
DD		 4625 while (status && status != 0xffff) {
4626 handled = 1;
1da177e4 4627
f11a377b
DD		 4628 /* Handle all of the error cases first. These will reset
4629 * the chip, so just exit the loop.
4630 */
4631 if (unlikely(!netif_running(dev))) {
4632 rtl8169_asic_down(ioaddr);
4633 break;
4634 }
1da177e4 4635
f11a377b 4636 /* Work around for rx fifo overflow */
801e147c 4637 if (unlikely(status & RxFIFOOver)) {
f11a377b
DD		 4638 netif_stop_queue(dev);
4639 rtl8169_tx_timeout(dev);
4640 break;
4641 }
1da177e4 4642
f11a377b
DD		 4643 if (unlikely(status & SYSErr)) {
4644 rtl8169_pcierr_interrupt(dev);
4645 break;
4646 }
1da177e4 4647
f11a377b
DD		 4648 if (status & LinkChg)
4649 rtl8169_check_link_status(dev, tp, ioaddr);
0e485150 4650
f11a377b
DD		 4651 /* We need to see the lastest version of tp->intr_mask to
4652 * avoid ignoring an MSI interrupt and having to wait for
4653 * another event which may never come.
4654 */
4655 smp_rmb();
4656 if (status & tp->intr_mask & tp->napi_event) {
4657 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4658 tp->intr_mask = ~tp->napi_event;
4659
4660 if (likely(napi_schedule_prep(&tp->napi)))
4661 __napi_schedule(&tp->napi);
bf82c189
JP		 4662 else
4663 netif_info(tp, intr, dev,
4664 "interrupt %04x in poll\n", status);
f11a377b 4665 }
1da177e4 4666
f11a377b
DD		 4667 /* We only get a new MSI interrupt when all active irq
4668 * sources on the chip have been acknowledged. So, ack
4669 * everything we've seen and check if new sources have become
4670 * active to avoid blocking all interrupts from the chip.
4671 */
4672 RTL_W16(IntrStatus,
4673 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4674 status = RTL_R16(IntrStatus);
865c652d 4675 }
1da177e4 4676
1da177e4
LT		 4677 return IRQ_RETVAL(handled);
4678}
4679
bea3348e 4680static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4681{
bea3348e
SH		 4682 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4683 struct net_device *dev = tp->dev;
1da177e4 4684 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4685 int work_done;
1da177e4 4686
bea3348e 4687 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4688 rtl8169_tx_interrupt(dev, tp, ioaddr);
4689
bea3348e 4690 if (work_done < budget) {
288379f0 4691 napi_complete(napi);
f11a377b
DD		 4692
4693 /* We need for force the visibility of tp->intr_mask
4694 * for other CPUs, as we can loose an MSI interrupt
4695 * and potentially wait for a retransmit timeout if we don't.
4696 * The posted write to IntrMask is safe, as it will
4697 * eventually make it to the chip and we won't loose anything
4698 * until it does.
1da177e4 4699 */
f11a377b 4700 tp->intr_mask = 0xffff;
4c020a96 4701 wmb();
0e485150 4702 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4703 }
4704
bea3348e 4705 return work_done;
1da177e4 4706}
1da177e4 4707
523a6094
FR		 4708static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4709{
4710 struct rtl8169_private *tp = netdev_priv(dev);
4711
4712 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4713 return;
4714
4715 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4716 RTL_W32(RxMissed, 0);
4717}
4718
1da177e4
LT		 4719static void rtl8169_down(struct net_device *dev)
4720{
4721 struct rtl8169_private *tp = netdev_priv(dev);
4722 void __iomem *ioaddr = tp->mmio_addr;
733b736c 4723 unsigned int intrmask;
1da177e4
LT		 4724
4725 rtl8169_delete_timer(dev);
4726
4727 netif_stop_queue(dev);
4728
93dd79e8 4729 napi_disable(&tp->napi);
93dd79e8 4730
1da177e4
LT		 4731core_down:
4732 spin_lock_irq(&tp->lock);
4733
4734 rtl8169_asic_down(ioaddr);
4735
523a6094 4736 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4737
4738 spin_unlock_irq(&tp->lock);
4739
4740 synchronize_irq(dev->irq);
4741
1da177e4 4742 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4743 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 4744
4745 /*
4746 * And now for the 50k$ question: are IRQ disabled or not ?
4747 *
4748 * Two paths lead here:
4749 * 1) dev->close
4750 * -> netif_running() is available to sync the current code and the
4751 * IRQ handler. See rtl8169_interrupt for details.
4752 * 2) dev->change_mtu
4753 * -> rtl8169_poll can not be issued again and re-enable the
4754 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 4755 *
4756 * No loop if hotpluged or major error (0xffff).
1da177e4 4757 */
733b736c
AP		 4758 intrmask = RTL_R16(IntrMask);
4759 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 4760 goto core_down;
4761
4762 rtl8169_tx_clear(tp);
4763
4764 rtl8169_rx_clear(tp);
4765}
4766
4767static int rtl8169_close(struct net_device *dev)
4768{
4769 struct rtl8169_private *tp = netdev_priv(dev);
4770 struct pci_dev *pdev = tp->pci_dev;
4771
e1759441
RW		 4772 pm_runtime_get_sync(&pdev->dev);
4773
355423d0
IV		 4774 /* update counters before going down */
4775 rtl8169_update_counters(dev);
4776
1da177e4
LT		 4777 rtl8169_down(dev);
4778
4779 free_irq(dev->irq, dev);
4780
82553bb6
SG		 4781 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4782 tp->RxPhyAddr);
4783 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4784 tp->TxPhyAddr);
1da177e4
LT		 4785 tp->TxDescArray = NULL;
4786 tp->RxDescArray = NULL;
4787
e1759441
RW		 4788 pm_runtime_put_sync(&pdev->dev);
4789
1da177e4
LT		 4790 return 0;
4791}
4792
07ce4064 4793static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4794{
4795 struct rtl8169_private *tp = netdev_priv(dev);
4796 void __iomem *ioaddr = tp->mmio_addr;
4797 unsigned long flags;
4798 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4799 int rx_mode;
1da177e4
LT		 4800 u32 tmp = 0;
4801
4802 if (dev->flags & IFF_PROMISC) {
4803 /* Unconditionally log net taps. */
bf82c189 4804 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4805 rx_mode =
4806 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4807 AcceptAllPhys;
4808 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4809 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4810 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4811 /* Too many to filter perfectly -- accept all multicasts. */
4812 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4813 mc_filter[1] = mc_filter[0] = 0xffffffff;
4814 } else {
22bedad3 4815 struct netdev_hw_addr *ha;
07d3f51f 4816
1da177e4
LT		 4817 rx_mode = AcceptBroadcast | AcceptMyPhys;
4818 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4819 netdev_for_each_mc_addr(ha, dev) {
4820 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4821 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4822 rx_mode |= AcceptMulticast;
4823 }
4824 }
4825
4826 spin_lock_irqsave(&tp->lock, flags);
4827
4828 tmp = rtl8169_rx_config | rx_mode |
4829 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4830
f887cce8 4831 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4832 u32 data = mc_filter[0];
4833
4834 mc_filter[0] = swab32(mc_filter[1]);
4835 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4836 }
4837
1da177e4 4838 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4839 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4840
57a9f236
FR		 4841 RTL_W32(RxConfig, tmp);
4842
1da177e4
LT		 4843 spin_unlock_irqrestore(&tp->lock, flags);
4844}
4845
4846/**
4847 * rtl8169_get_stats - Get rtl8169 read/write statistics
4848 * @dev: The Ethernet Device to get statistics for
4849 *
4850 * Get TX/RX statistics for rtl8169
4851 */
4852static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4853{
4854 struct rtl8169_private *tp = netdev_priv(dev);
4855 void __iomem *ioaddr = tp->mmio_addr;
4856 unsigned long flags;
4857
4858 if (netif_running(dev)) {
4859 spin_lock_irqsave(&tp->lock, flags);
523a6094 4860 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4861 spin_unlock_irqrestore(&tp->lock, flags);
4862 }
5b0384f4 4863
cebf8cc7 4864 return &dev->stats;
1da177e4
LT		 4865}
4866
861ab440 4867static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4868{
5d06a99f 4869 if (!netif_running(dev))
861ab440 4870 return;
5d06a99f
FR		 4871
4872 netif_device_detach(dev);
4873 netif_stop_queue(dev);
861ab440
RW		 4874}
4875
4876#ifdef CONFIG_PM
4877
4878static int rtl8169_suspend(struct device *device)
4879{
4880 struct pci_dev *pdev = to_pci_dev(device);
4881 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4882
861ab440 4883 rtl8169_net_suspend(dev);
1371fa6d 4884
5d06a99f
FR		 4885 return 0;
4886}
4887
e1759441
RW		 4888static void __rtl8169_resume(struct net_device *dev)
4889{
4890 netif_device_attach(dev);
4891 rtl8169_schedule_work(dev, rtl8169_reset_task);
4892}
4893
861ab440 4894static int rtl8169_resume(struct device *device)
5d06a99f 4895{
861ab440 4896 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 4897 struct net_device *dev = pci_get_drvdata(pdev);
4898
e1759441
RW		 4899 if (netif_running(dev))
4900 __rtl8169_resume(dev);
5d06a99f 4901
e1759441
RW		 4902 return 0;
4903}
4904
4905static int rtl8169_runtime_suspend(struct device *device)
4906{
4907 struct pci_dev *pdev = to_pci_dev(device);
4908 struct net_device *dev = pci_get_drvdata(pdev);
4909 struct rtl8169_private *tp = netdev_priv(dev);
4910
4911 if (!tp->TxDescArray)
4912 return 0;
4913
4914 spin_lock_irq(&tp->lock);
4915 tp->saved_wolopts = __rtl8169_get_wol(tp);
4916 __rtl8169_set_wol(tp, WAKE_ANY);
4917 spin_unlock_irq(&tp->lock);
4918
4919 rtl8169_net_suspend(dev);
4920
4921 return 0;
4922}
4923
4924static int rtl8169_runtime_resume(struct device *device)
4925{
4926 struct pci_dev *pdev = to_pci_dev(device);
4927 struct net_device *dev = pci_get_drvdata(pdev);
4928 struct rtl8169_private *tp = netdev_priv(dev);
4929
4930 if (!tp->TxDescArray)
4931 return 0;
4932
4933 spin_lock_irq(&tp->lock);
4934 __rtl8169_set_wol(tp, tp->saved_wolopts);
4935 tp->saved_wolopts = 0;
4936 spin_unlock_irq(&tp->lock);
4937
4938 __rtl8169_resume(dev);
5d06a99f 4939
5d06a99f
FR		 4940 return 0;
4941}
4942
e1759441
RW		 4943static int rtl8169_runtime_idle(struct device *device)
4944{
4945 struct pci_dev *pdev = to_pci_dev(device);
4946 struct net_device *dev = pci_get_drvdata(pdev);
4947 struct rtl8169_private *tp = netdev_priv(dev);
4948
4949 if (!tp->TxDescArray)
4950 return 0;
4951
4952 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4953 return -EBUSY;
4954}
4955
47145210 4956static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4957 .suspend = rtl8169_suspend,
4958 .resume = rtl8169_resume,
4959 .freeze = rtl8169_suspend,
4960 .thaw = rtl8169_resume,
4961 .poweroff = rtl8169_suspend,
4962 .restore = rtl8169_resume,
e1759441
RW		 4963 .runtime_suspend = rtl8169_runtime_suspend,
4964 .runtime_resume = rtl8169_runtime_resume,
4965 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 4966};
4967
4968#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4969
4970#else /* !CONFIG_PM */
4971
4972#define RTL8169_PM_OPS NULL
4973
4974#endif /* !CONFIG_PM */
4975
1765f95d
FR		 4976static void rtl_shutdown(struct pci_dev *pdev)
4977{
861ab440 4978 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4979 struct rtl8169_private *tp = netdev_priv(dev);
4980 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4981
4982 rtl8169_net_suspend(dev);
1765f95d 4983
cc098dc7
IV		 4984 /* restore original MAC address */
4985 rtl_rar_set(tp, dev->perm_addr);
4986
4bb3f522 4987 spin_lock_irq(&tp->lock);
4988
4989 rtl8169_asic_down(ioaddr);
4990
4991 spin_unlock_irq(&tp->lock);
4992
861ab440 4993 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4994 /* WoL fails with some 8168 when the receiver is disabled. */
4995 if (tp->features & RTL_FEATURE_WOL) {
4996 pci_clear_master(pdev);
4997
4998 RTL_W8(ChipCmd, CmdRxEnb);
4999 /* PCI commit */
5000 RTL_R8(ChipCmd);
5001 }
5002
861ab440
RW		 5003 pci_wake_from_d3(pdev, true);
5004 pci_set_power_state(pdev, PCI_D3hot);
5005 }
5006}
5d06a99f 5007
1da177e4
LT		 5008static struct pci_driver rtl8169_pci_driver = {
5009 .name = MODULENAME,
5010 .id_table = rtl8169_pci_tbl,
5011 .probe = rtl8169_init_one,
5012 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5013 .shutdown = rtl_shutdown,
861ab440 5014 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5015};
5016
07d3f51f 5017static int __init rtl8169_init_module(void)
1da177e4 5018{
29917620 5019 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5020}
5021
07d3f51f 5022static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5023{
5024 pci_unregister_driver(&rtl8169_pci_driver);
5025}
5026
5027module_init(rtl8169_init_module);
5028module_exit(rtl8169_cleanup_module);
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