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r8169: merge with version 6.001.00 of Realtek's r8169 driver
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
5b0384f4 9 2004 - Massive updates. See kernel SCM system for details.
1da177e4
LT		 10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
5b0384f4 14
1da177e4
LT		 15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
5b0384f4 21
1da177e4
LT		 22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
5b0384f4 28 exchanging Link Code Word (FLP).
1da177e4
LT		 29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
99f252b0 69#include <asm/system.h>
1da177e4
LT		 70#include <asm/io.h>
71#include <asm/irq.h>
72
f7ccf420
SH		 73#ifdef CONFIG_R8169_NAPI
74#define NAPI_SUFFIX "-NAPI"
75#else
76#define NAPI_SUFFIX ""
77#endif
78
79#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 80#define MODULENAME "r8169"
81#define PFX MODULENAME ": "
82
83#ifdef RTL8169_DEBUG
84#define assert(expr) \
5b0384f4
FR		 85 if (!(expr)) { \
86 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
87 #expr,__FILE__,__FUNCTION__,__LINE__); \
88 }
1da177e4
LT		 89#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
90#else
91#define assert(expr) do {} while (0)
92#define dprintk(fmt, args...) do {} while (0)
93#endif /* RTL8169_DEBUG */
94
b57b7e5a 95#define R8169_MSG_DEFAULT \
f0e837d9 96 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 97
1da177e4
LT		 98#define TX_BUFFS_AVAIL(tp) \
99 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
100
101#ifdef CONFIG_R8169_NAPI
102#define rtl8169_rx_skb netif_receive_skb
0b50f81d 103#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 104#define rtl8169_rx_quota(count, quota) min(count, quota)
105#else
106#define rtl8169_rx_skb netif_rx
0b50f81d 107#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 108#define rtl8169_rx_quota(count, quota) count
109#endif
110
111/* media options */
112#define MAX_UNITS 8
113static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
114static int num_media = 0;
115
116/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 117static const int max_interrupt_work = 20;
1da177e4
LT		 118
119/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
120 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 121static const int multicast_filter_limit = 32;
1da177e4
LT		 122
123/* MAC address length */
124#define MAC_ADDR_LEN 6
125
126#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
127#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
129#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
130#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
131#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
132#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
133
134#define R8169_REGS_SIZE 256
135#define R8169_NAPI_WEIGHT 64
136#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
137#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
138#define RX_BUF_SIZE 1536 /* Rx Buffer size */
139#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
140#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
141
142#define RTL8169_TX_TIMEOUT (6*HZ)
143#define RTL8169_PHY_TIMEOUT (10*HZ)
144
145/* write/read MMIO register */
146#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
147#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
148#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
149#define RTL_R8(reg) readb (ioaddr + (reg))
150#define RTL_R16(reg) readw (ioaddr + (reg))
151#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
152
153enum mac_version {
ba6eb6ee
FR		 154 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
155 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
156 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
157 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
158 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 159 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530
FR		 160 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
161 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
cdf1a608
FR		 162 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
163 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
164 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
1da177e4
LT		 165};
166
167enum phy_version {
168 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
169 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
170 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
171 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
172 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
173 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
174};
175
1da177e4
LT		 176#define _R(NAME,MAC,MASK) \
177 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
178
3c6bee1d 179static const struct {
1da177e4
LT		 180 const char *name;
181 u8 mac_version;
182 u32 RxConfigMask; /* Clears the bits supported by this chip */
183} rtl_chip_info[] = {
ba6eb6ee
FR		 184 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
185 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
186 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
187 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
188 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 189 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 190 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
191 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
192 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
193 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
194 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 195};
196#undef _R
197
bcf0bf90
FR		 198enum cfg_version {
199 RTL_CFG_0 = 0x00,
200 RTL_CFG_1,
201 RTL_CFG_2
202};
203
07ce4064
FR		 204static void rtl_hw_start_8169(struct net_device *);
205static void rtl_hw_start_8168(struct net_device *);
206static void rtl_hw_start_8101(struct net_device *);
207
bcf0bf90 208static const struct {
07ce4064 209 void (*hw_start)(struct net_device *);
bcf0bf90
FR		 210 unsigned int region;
211 unsigned int align;
212} rtl_cfg_info[] = {
07ce4064
FR		 213 [RTL_CFG_0] = { rtl_hw_start_8169, 1, NET_IP_ALIGN },
214 [RTL_CFG_1] = { rtl_hw_start_8168, 2, 8 },
215 [RTL_CFG_2] = { rtl_hw_start_8101, 2, 8 }
bcf0bf90
FR		 216};
217
1da177e4 218static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 219 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 220 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 221 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 222 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 223 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
224 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
73f5e28b 225 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 226 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
227 { PCI_VENDOR_ID_LINKSYS, 0x1032,
228 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 229 {0,},
230};
231
232MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
233
234static int rx_copybreak = 200;
235static int use_dac;
b57b7e5a
SH		 236static struct {
237 u32 msg_enable;
238} debug = { -1 };
1da177e4
LT		 239
240enum RTL8169_registers {
241 MAC0 = 0, /* Ethernet hardware address. */
242 MAR0 = 8, /* Multicast filter. */
d4a3a0fc
SH		 243 CounterAddrLow = 0x10,
244 CounterAddrHigh = 0x14,
1da177e4
LT		 245 TxDescStartAddrLow = 0x20,
246 TxDescStartAddrHigh = 0x24,
247 TxHDescStartAddrLow = 0x28,
248 TxHDescStartAddrHigh = 0x2c,
249 FLASH = 0x30,
250 ERSR = 0x36,
251 ChipCmd = 0x37,
252 TxPoll = 0x38,
253 IntrMask = 0x3C,
254 IntrStatus = 0x3E,
255 TxConfig = 0x40,
256 RxConfig = 0x44,
257 RxMissed = 0x4C,
258 Cfg9346 = 0x50,
259 Config0 = 0x51,
260 Config1 = 0x52,
261 Config2 = 0x53,
262 Config3 = 0x54,
263 Config4 = 0x55,
264 Config5 = 0x56,
265 MultiIntr = 0x5C,
266 PHYAR = 0x60,
267 TBICSR = 0x64,
268 TBI_ANAR = 0x68,
269 TBI_LPAR = 0x6A,
270 PHYstatus = 0x6C,
271 RxMaxSize = 0xDA,
272 CPlusCmd = 0xE0,
273 IntrMitigate = 0xE2,
274 RxDescAddrLow = 0xE4,
275 RxDescAddrHigh = 0xE8,
276 EarlyTxThres = 0xEC,
277 FuncEvent = 0xF0,
278 FuncEventMask = 0xF4,
279 FuncPresetState = 0xF8,
280 FuncForceEvent = 0xFC,
281};
282
283enum RTL8169_register_content {
284 /* InterruptStatusBits */
285 SYSErr = 0x8000,
286 PCSTimeout = 0x4000,
287 SWInt = 0x0100,
288 TxDescUnavail = 0x80,
289 RxFIFOOver = 0x40,
290 LinkChg = 0x20,
291 RxOverflow = 0x10,
292 TxErr = 0x08,
293 TxOK = 0x04,
294 RxErr = 0x02,
295 RxOK = 0x01,
296
297 /* RxStatusDesc */
9dccf611
FR		 298 RxFOVF = (1 << 23),
299 RxRWT = (1 << 22),
300 RxRES = (1 << 21),
301 RxRUNT = (1 << 20),
302 RxCRC = (1 << 19),
1da177e4
LT		 303
304 /* ChipCmdBits */
305 CmdReset = 0x10,
306 CmdRxEnb = 0x08,
307 CmdTxEnb = 0x04,
308 RxBufEmpty = 0x01,
309
310 /* Cfg9346Bits */
311 Cfg9346_Lock = 0x00,
312 Cfg9346_Unlock = 0xC0,
313
314 /* rx_mode_bits */
315 AcceptErr = 0x20,
316 AcceptRunt = 0x10,
317 AcceptBroadcast = 0x08,
318 AcceptMulticast = 0x04,
319 AcceptMyPhys = 0x02,
320 AcceptAllPhys = 0x01,
321
322 /* RxConfigBits */
323 RxCfgFIFOShift = 13,
324 RxCfgDMAShift = 8,
325
326 /* TxConfigBits */
327 TxInterFrameGapShift = 24,
328 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
329
5d06a99f
FR		 330 /* Config1 register p.24 */
331 PMEnable = (1 << 0), /* Power Management Enable */
332
6dccd16b
FR		 333 /* Config2 register p. 25 */
334 PCI_Clock_66MHz = 0x01,
335 PCI_Clock_33MHz = 0x00,
336
61a4dcc2
FR		 337 /* Config3 register p.25 */
338 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
339 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
340
5d06a99f 341 /* Config5 register p.27 */
61a4dcc2
FR		 342 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
343 MWF = (1 << 5), /* Accept Multicast wakeup frame */
344 UWF = (1 << 4), /* Accept Unicast wakeup frame */
345 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 346 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
347
1da177e4
LT		 348 /* TBICSR p.28 */
349 TBIReset = 0x80000000,
350 TBILoopback = 0x40000000,
351 TBINwEnable = 0x20000000,
352 TBINwRestart = 0x10000000,
353 TBILinkOk = 0x02000000,
354 TBINwComplete = 0x01000000,
355
356 /* CPlusCmd p.31 */
357 RxVlan = (1 << 6),
358 RxChkSum = (1 << 5),
359 PCIDAC = (1 << 4),
360 PCIMulRW = (1 << 3),
361
362 /* rtl8169_PHYstatus */
363 TBI_Enable = 0x80,
364 TxFlowCtrl = 0x40,
365 RxFlowCtrl = 0x20,
366 _1000bpsF = 0x10,
367 _100bps = 0x08,
368 _10bps = 0x04,
369 LinkStatus = 0x02,
370 FullDup = 0x01,
371
1da177e4
LT		 372 /* _MediaType */
373 _10_Half = 0x01,
374 _10_Full = 0x02,
375 _100_Half = 0x04,
376 _100_Full = 0x08,
377 _1000_Full = 0x10,
378
379 /* _TBICSRBit */
380 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 381
382 /* DumpCounterCommand */
383 CounterDump = 0x8,
1da177e4
LT		 384};
385
386enum _DescStatusBit {
387 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
388 RingEnd = (1 << 30), /* End of descriptor ring */
389 FirstFrag = (1 << 29), /* First segment of a packet */
390 LastFrag = (1 << 28), /* Final segment of a packet */
391
392 /* Tx private */
393 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
394 MSSShift = 16, /* MSS value position */
395 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
396 IPCS = (1 << 18), /* Calculate IP checksum */
397 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
398 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
399 TxVlanTag = (1 << 17), /* Add VLAN tag */
400
401 /* Rx private */
402 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
403 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
404
405#define RxProtoUDP (PID1)
406#define RxProtoTCP (PID0)
407#define RxProtoIP (PID1 | PID0)
408#define RxProtoMask RxProtoIP
409
410 IPFail = (1 << 16), /* IP checksum failed */
411 UDPFail = (1 << 15), /* UDP/IP checksum failed */
412 TCPFail = (1 << 14), /* TCP/IP checksum failed */
413 RxVlanTag = (1 << 16), /* VLAN tag available */
414};
415
416#define RsvdMask 0x3fffc000
417
418struct TxDesc {
419 u32 opts1;
420 u32 opts2;
421 u64 addr;
422};
423
424struct RxDesc {
425 u32 opts1;
426 u32 opts2;
427 u64 addr;
428};
429
430struct ring_info {
431 struct sk_buff *skb;
432 u32 len;
433 u8 __pad[sizeof(void *) - sizeof(u32)];
434};
435
436struct rtl8169_private {
437 void __iomem *mmio_addr; /* memory map physical address */
438 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 439 struct net_device *dev;
1da177e4
LT		 440 struct net_device_stats stats; /* statistics of net device */
441 spinlock_t lock; /* spin lock flag */
b57b7e5a 442 u32 msg_enable;
1da177e4
LT		 443 int chipset;
444 int mac_version;
445 int phy_version;
446 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
447 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
448 u32 dirty_rx;
449 u32 dirty_tx;
450 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
451 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
452 dma_addr_t TxPhyAddr;
453 dma_addr_t RxPhyAddr;
454 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
455 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 456 unsigned align;
1da177e4
LT		 457 unsigned rx_buf_sz;
458 struct timer_list timer;
459 u16 cp_cmd;
460 u16 intr_mask;
461 int phy_auto_nego_reg;
462 int phy_1000_ctrl_reg;
463#ifdef CONFIG_R8169_VLAN
464 struct vlan_group *vlgrp;
465#endif
466 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
467 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
468 void (*phy_reset_enable)(void __iomem *);
07ce4064 469 void (*hw_start)(struct net_device *);
1da177e4
LT		 470 unsigned int (*phy_reset_pending)(void __iomem *);
471 unsigned int (*link_ok)(void __iomem *);
c4028958 472 struct delayed_work task;
61a4dcc2 473 unsigned wol_enabled : 1;
1da177e4
LT		 474};
475
979b6c13 476MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4
LT		 477MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
478module_param_array(media, int, &num_media, 0);
df0a1bf6 479MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
1da177e4 480module_param(rx_copybreak, int, 0);
1b7efd58 481MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 482module_param(use_dac, int, 0);
483MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 484module_param_named(debug, debug.msg_enable, int, 0);
485MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 486MODULE_LICENSE("GPL");
487MODULE_VERSION(RTL8169_VERSION);
488
489static int rtl8169_open(struct net_device *dev);
490static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 491static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 492static int rtl8169_init_ring(struct net_device *dev);
07ce4064 493static void rtl_hw_start(struct net_device *dev);
1da177e4 494static int rtl8169_close(struct net_device *dev);
07ce4064 495static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 496static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 497static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 498static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
499 void __iomem *);
4dcb7d33 500static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 501static void rtl8169_down(struct net_device *dev);
99f252b0 502static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 503
504#ifdef CONFIG_R8169_NAPI
505static int rtl8169_poll(struct net_device *dev, int *budget);
506#endif
507
508static const u16 rtl8169_intr_mask =
509 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
510static const u16 rtl8169_napi_event =
511 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
512static const unsigned int rtl8169_rx_config =
5b0384f4 513 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4
LT		 514
515static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
516{
517 int i;
518
519 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
1da177e4 520
2371408c 521 for (i = 20; i > 0; i--) {
1da177e4 522 /* Check if the RTL8169 has completed writing to the specified MII register */
5b0384f4 523 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 524 break;
2371408c 525 udelay(25);
1da177e4
LT		 526 }
527}
528
529static int mdio_read(void __iomem *ioaddr, int RegAddr)
530{
531 int i, value = -1;
532
533 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
1da177e4 534
2371408c 535 for (i = 20; i > 0; i--) {
1da177e4
LT		 536 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
537 if (RTL_R32(PHYAR) & 0x80000000) {
538 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
539 break;
540 }
2371408c 541 udelay(25);
1da177e4
LT		 542 }
543 return value;
544}
545
546static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
547{
548 RTL_W16(IntrMask, 0x0000);
549
550 RTL_W16(IntrStatus, 0xffff);
551}
552
553static void rtl8169_asic_down(void __iomem *ioaddr)
554{
555 RTL_W8(ChipCmd, 0x00);
556 rtl8169_irq_mask_and_ack(ioaddr);
557 RTL_R16(CPlusCmd);
558}
559
560static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
561{
562 return RTL_R32(TBICSR) & TBIReset;
563}
564
565static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
566{
64e4bfb4 567 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 568}
569
570static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
571{
572 return RTL_R32(TBICSR) & TBILinkOk;
573}
574
575static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
576{
577 return RTL_R8(PHYstatus) & LinkStatus;
578}
579
580static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
581{
582 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
583}
584
585static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
586{
587 unsigned int val;
588
9e0db8ef
FR		 589 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
590 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 591}
592
593static void rtl8169_check_link_status(struct net_device *dev,
594 struct rtl8169_private *tp, void __iomem *ioaddr)
595{
596 unsigned long flags;
597
598 spin_lock_irqsave(&tp->lock, flags);
599 if (tp->link_ok(ioaddr)) {
600 netif_carrier_on(dev);
b57b7e5a
SH		 601 if (netif_msg_ifup(tp))
602 printk(KERN_INFO PFX "%s: link up\n", dev->name);
603 } else {
604 if (netif_msg_ifdown(tp))
605 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 606 netif_carrier_off(dev);
b57b7e5a 607 }
1da177e4
LT		 608 spin_unlock_irqrestore(&tp->lock, flags);
609}
610
611static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
612{
613 struct {
614 u16 speed;
615 u8 duplex;
616 u8 autoneg;
617 u8 media;
618 } link_settings[] = {
619 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
620 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
621 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
622 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
623 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
624 /* Make TBI happy */
625 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
626 }, *p;
627 unsigned char option;
5b0384f4 628
1da177e4
LT		 629 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
630
b57b7e5a 631 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
1da177e4
LT		 632 printk(KERN_WARNING PFX "media option is deprecated.\n");
633
634 for (p = link_settings; p->media != 0xff; p++) {
635 if (p->media == option)
636 break;
637 }
638 *autoneg = p->autoneg;
639 *speed = p->speed;
640 *duplex = p->duplex;
641}
642
61a4dcc2
FR		 643static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
644{
645 struct rtl8169_private *tp = netdev_priv(dev);
646 void __iomem *ioaddr = tp->mmio_addr;
647 u8 options;
648
649 wol->wolopts = 0;
650
651#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
652 wol->supported = WAKE_ANY;
653
654 spin_lock_irq(&tp->lock);
655
656 options = RTL_R8(Config1);
657 if (!(options & PMEnable))
658 goto out_unlock;
659
660 options = RTL_R8(Config3);
661 if (options & LinkUp)
662 wol->wolopts |= WAKE_PHY;
663 if (options & MagicPacket)
664 wol->wolopts |= WAKE_MAGIC;
665
666 options = RTL_R8(Config5);
667 if (options & UWF)
668 wol->wolopts |= WAKE_UCAST;
669 if (options & BWF)
5b0384f4 670 wol->wolopts |= WAKE_BCAST;
61a4dcc2 671 if (options & MWF)
5b0384f4 672 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 673
674out_unlock:
675 spin_unlock_irq(&tp->lock);
676}
677
678static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
679{
680 struct rtl8169_private *tp = netdev_priv(dev);
681 void __iomem *ioaddr = tp->mmio_addr;
682 int i;
683 static struct {
684 u32 opt;
685 u16 reg;
686 u8 mask;
687 } cfg[] = {
688 { WAKE_ANY, Config1, PMEnable },
689 { WAKE_PHY, Config3, LinkUp },
690 { WAKE_MAGIC, Config3, MagicPacket },
691 { WAKE_UCAST, Config5, UWF },
692 { WAKE_BCAST, Config5, BWF },
693 { WAKE_MCAST, Config5, MWF },
694 { WAKE_ANY, Config5, LanWake }
695 };
696
697 spin_lock_irq(&tp->lock);
698
699 RTL_W8(Cfg9346, Cfg9346_Unlock);
700
701 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
702 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
703 if (wol->wolopts & cfg[i].opt)
704 options |= cfg[i].mask;
705 RTL_W8(cfg[i].reg, options);
706 }
707
708 RTL_W8(Cfg9346, Cfg9346_Lock);
709
710 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
711
712 spin_unlock_irq(&tp->lock);
713
714 return 0;
715}
716
1da177e4
LT		 717static void rtl8169_get_drvinfo(struct net_device *dev,
718 struct ethtool_drvinfo *info)
719{
720 struct rtl8169_private *tp = netdev_priv(dev);
721
722 strcpy(info->driver, MODULENAME);
723 strcpy(info->version, RTL8169_VERSION);
724 strcpy(info->bus_info, pci_name(tp->pci_dev));
725}
726
727static int rtl8169_get_regs_len(struct net_device *dev)
728{
729 return R8169_REGS_SIZE;
730}
731
732static int rtl8169_set_speed_tbi(struct net_device *dev,
733 u8 autoneg, u16 speed, u8 duplex)
734{
735 struct rtl8169_private *tp = netdev_priv(dev);
736 void __iomem *ioaddr = tp->mmio_addr;
737 int ret = 0;
738 u32 reg;
739
740 reg = RTL_R32(TBICSR);
741 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
742 (duplex == DUPLEX_FULL)) {
743 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
744 } else if (autoneg == AUTONEG_ENABLE)
745 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
746 else {
b57b7e5a
SH		 747 if (netif_msg_link(tp)) {
748 printk(KERN_WARNING "%s: "
749 "incorrect speed setting refused in TBI mode\n",
750 dev->name);
751 }
1da177e4
LT		 752 ret = -EOPNOTSUPP;
753 }
754
755 return ret;
756}
757
758static int rtl8169_set_speed_xmii(struct net_device *dev,
759 u8 autoneg, u16 speed, u8 duplex)
760{
761 struct rtl8169_private *tp = netdev_priv(dev);
762 void __iomem *ioaddr = tp->mmio_addr;
763 int auto_nego, giga_ctrl;
764
64e4bfb4
FR		 765 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
766 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
767 ADVERTISE_100HALF | ADVERTISE_100FULL);
768 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
769 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 770
771 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 772 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
773 ADVERTISE_100HALF | ADVERTISE_100FULL);
774 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 775 } else {
776 if (speed == SPEED_10)
64e4bfb4 777 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 778 else if (speed == SPEED_100)
64e4bfb4 779 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 780 else if (speed == SPEED_1000)
64e4bfb4 781 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 782
783 if (duplex == DUPLEX_HALF)
64e4bfb4 784 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 785
786 if (duplex == DUPLEX_FULL)
64e4bfb4 787 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 788
789 /* This tweak comes straight from Realtek's driver. */
790 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
791 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
64e4bfb4 792 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 793 }
794 }
795
796 /* The 8100e/8101e do Fast Ethernet only. */
797 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
798 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
799 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
64e4bfb4 800 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 801 netif_msg_link(tp)) {
802 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
803 dev->name);
804 }
64e4bfb4 805 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 806 }
807
623a1593
FR		 808 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
809
1da177e4
LT		 810 tp->phy_auto_nego_reg = auto_nego;
811 tp->phy_1000_ctrl_reg = giga_ctrl;
812
64e4bfb4
FR		 813 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
814 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
815 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 816 return 0;
817}
818
819static int rtl8169_set_speed(struct net_device *dev,
820 u8 autoneg, u16 speed, u8 duplex)
821{
822 struct rtl8169_private *tp = netdev_priv(dev);
823 int ret;
824
825 ret = tp->set_speed(dev, autoneg, speed, duplex);
826
64e4bfb4 827 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 828 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
829
830 return ret;
831}
832
833static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
834{
835 struct rtl8169_private *tp = netdev_priv(dev);
836 unsigned long flags;
837 int ret;
838
839 spin_lock_irqsave(&tp->lock, flags);
840 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
841 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 842
1da177e4
LT		 843 return ret;
844}
845
846static u32 rtl8169_get_rx_csum(struct net_device *dev)
847{
848 struct rtl8169_private *tp = netdev_priv(dev);
849
850 return tp->cp_cmd & RxChkSum;
851}
852
853static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
854{
855 struct rtl8169_private *tp = netdev_priv(dev);
856 void __iomem *ioaddr = tp->mmio_addr;
857 unsigned long flags;
858
859 spin_lock_irqsave(&tp->lock, flags);
860
861 if (data)
862 tp->cp_cmd |= RxChkSum;
863 else
864 tp->cp_cmd &= ~RxChkSum;
865
866 RTL_W16(CPlusCmd, tp->cp_cmd);
867 RTL_R16(CPlusCmd);
868
869 spin_unlock_irqrestore(&tp->lock, flags);
870
871 return 0;
872}
873
874#ifdef CONFIG_R8169_VLAN
875
876static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
877 struct sk_buff *skb)
878{
879 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
880 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
881}
882
883static void rtl8169_vlan_rx_register(struct net_device *dev,
884 struct vlan_group *grp)
885{
886 struct rtl8169_private *tp = netdev_priv(dev);
887 void __iomem *ioaddr = tp->mmio_addr;
888 unsigned long flags;
889
890 spin_lock_irqsave(&tp->lock, flags);
891 tp->vlgrp = grp;
892 if (tp->vlgrp)
893 tp->cp_cmd |= RxVlan;
894 else
895 tp->cp_cmd &= ~RxVlan;
896 RTL_W16(CPlusCmd, tp->cp_cmd);
897 RTL_R16(CPlusCmd);
898 spin_unlock_irqrestore(&tp->lock, flags);
899}
900
1da177e4
LT		 901static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
902 struct sk_buff *skb)
903{
904 u32 opts2 = le32_to_cpu(desc->opts2);
905 int ret;
906
907 if (tp->vlgrp && (opts2 & RxVlanTag)) {
908 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
909 swab16(opts2 & 0xffff));
910 ret = 0;
911 } else
912 ret = -1;
913 desc->opts2 = 0;
914 return ret;
915}
916
917#else /* !CONFIG_R8169_VLAN */
918
919static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
920 struct sk_buff *skb)
921{
922 return 0;
923}
924
925static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
926 struct sk_buff *skb)
927{
928 return -1;
929}
930
931#endif
932
933static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
934{
935 struct rtl8169_private *tp = netdev_priv(dev);
936 void __iomem *ioaddr = tp->mmio_addr;
937 u32 status;
938
939 cmd->supported =
940 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
941 cmd->port = PORT_FIBRE;
942 cmd->transceiver = XCVR_INTERNAL;
943
944 status = RTL_R32(TBICSR);
945 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
946 cmd->autoneg = !!(status & TBINwEnable);
947
948 cmd->speed = SPEED_1000;
949 cmd->duplex = DUPLEX_FULL; /* Always set */
950}
951
952static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
953{
954 struct rtl8169_private *tp = netdev_priv(dev);
955 void __iomem *ioaddr = tp->mmio_addr;
956 u8 status;
957
958 cmd->supported = SUPPORTED_10baseT_Half |
959 SUPPORTED_10baseT_Full |
960 SUPPORTED_100baseT_Half |
961 SUPPORTED_100baseT_Full |
962 SUPPORTED_1000baseT_Full |
963 SUPPORTED_Autoneg |
5b0384f4 964 SUPPORTED_TP;
1da177e4
LT		 965
966 cmd->autoneg = 1;
967 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
968
64e4bfb4 969 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 970 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 971 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 972 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 973 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 974 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 975 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 976 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 977 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 978 cmd->advertising |= ADVERTISED_1000baseT_Full;
979
980 status = RTL_R8(PHYstatus);
981
982 if (status & _1000bpsF)
983 cmd->speed = SPEED_1000;
984 else if (status & _100bps)
985 cmd->speed = SPEED_100;
986 else if (status & _10bps)
987 cmd->speed = SPEED_10;
988
623a1593
FR		 989 if (status & TxFlowCtrl)
990 cmd->advertising |= ADVERTISED_Asym_Pause;
991 if (status & RxFlowCtrl)
992 cmd->advertising |= ADVERTISED_Pause;
993
1da177e4
LT		 994 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
995 DUPLEX_FULL : DUPLEX_HALF;
996}
997
998static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
999{
1000 struct rtl8169_private *tp = netdev_priv(dev);
1001 unsigned long flags;
1002
1003 spin_lock_irqsave(&tp->lock, flags);
1004
1005 tp->get_settings(dev, cmd);
1006
1007 spin_unlock_irqrestore(&tp->lock, flags);
1008 return 0;
1009}
1010
1011static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1012 void *p)
1013{
5b0384f4
FR		 1014 struct rtl8169_private *tp = netdev_priv(dev);
1015 unsigned long flags;
1da177e4 1016
5b0384f4
FR		 1017 if (regs->len > R8169_REGS_SIZE)
1018 regs->len = R8169_REGS_SIZE;
1da177e4 1019
5b0384f4
FR		 1020 spin_lock_irqsave(&tp->lock, flags);
1021 memcpy_fromio(p, tp->mmio_addr, regs->len);
1022 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1023}
1024
b57b7e5a
SH		 1025static u32 rtl8169_get_msglevel(struct net_device *dev)
1026{
1027 struct rtl8169_private *tp = netdev_priv(dev);
1028
1029 return tp->msg_enable;
1030}
1031
1032static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1033{
1034 struct rtl8169_private *tp = netdev_priv(dev);
1035
1036 tp->msg_enable = value;
1037}
1038
d4a3a0fc
SH		 1039static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1040 "tx_packets",
1041 "rx_packets",
1042 "tx_errors",
1043 "rx_errors",
1044 "rx_missed",
1045 "align_errors",
1046 "tx_single_collisions",
1047 "tx_multi_collisions",
1048 "unicast",
1049 "broadcast",
1050 "multicast",
1051 "tx_aborted",
1052 "tx_underrun",
1053};
1054
1055struct rtl8169_counters {
1056 u64 tx_packets;
1057 u64 rx_packets;
1058 u64 tx_errors;
1059 u32 rx_errors;
1060 u16 rx_missed;
1061 u16 align_errors;
1062 u32 tx_one_collision;
1063 u32 tx_multi_collision;
1064 u64 rx_unicast;
1065 u64 rx_broadcast;
1066 u32 rx_multicast;
1067 u16 tx_aborted;
1068 u16 tx_underun;
1069};
1070
1071static int rtl8169_get_stats_count(struct net_device *dev)
1072{
1073 return ARRAY_SIZE(rtl8169_gstrings);
1074}
1075
1076static void rtl8169_get_ethtool_stats(struct net_device *dev,
1077 struct ethtool_stats *stats, u64 *data)
1078{
1079 struct rtl8169_private *tp = netdev_priv(dev);
1080 void __iomem *ioaddr = tp->mmio_addr;
1081 struct rtl8169_counters *counters;
1082 dma_addr_t paddr;
1083 u32 cmd;
1084
1085 ASSERT_RTNL();
1086
1087 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1088 if (!counters)
1089 return;
1090
1091 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1092 cmd = (u64)paddr & DMA_32BIT_MASK;
1093 RTL_W32(CounterAddrLow, cmd);
1094 RTL_W32(CounterAddrLow, cmd | CounterDump);
1095
1096 while (RTL_R32(CounterAddrLow) & CounterDump) {
1097 if (msleep_interruptible(1))
1098 break;
1099 }
1100
1101 RTL_W32(CounterAddrLow, 0);
1102 RTL_W32(CounterAddrHigh, 0);
1103
5b0384f4 1104 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1105 data[1] = le64_to_cpu(counters->rx_packets);
1106 data[2] = le64_to_cpu(counters->tx_errors);
1107 data[3] = le32_to_cpu(counters->rx_errors);
1108 data[4] = le16_to_cpu(counters->rx_missed);
1109 data[5] = le16_to_cpu(counters->align_errors);
1110 data[6] = le32_to_cpu(counters->tx_one_collision);
1111 data[7] = le32_to_cpu(counters->tx_multi_collision);
1112 data[8] = le64_to_cpu(counters->rx_unicast);
1113 data[9] = le64_to_cpu(counters->rx_broadcast);
1114 data[10] = le32_to_cpu(counters->rx_multicast);
1115 data[11] = le16_to_cpu(counters->tx_aborted);
1116 data[12] = le16_to_cpu(counters->tx_underun);
1117
1118 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1119}
1120
1121static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1122{
1123 switch(stringset) {
1124 case ETH_SS_STATS:
1125 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1126 break;
1127 }
1128}
1129
1130
7282d491 1131static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1132 .get_drvinfo = rtl8169_get_drvinfo,
1133 .get_regs_len = rtl8169_get_regs_len,
1134 .get_link = ethtool_op_get_link,
1135 .get_settings = rtl8169_get_settings,
1136 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1137 .get_msglevel = rtl8169_get_msglevel,
1138 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1139 .get_rx_csum = rtl8169_get_rx_csum,
1140 .set_rx_csum = rtl8169_set_rx_csum,
1141 .get_tx_csum = ethtool_op_get_tx_csum,
1142 .set_tx_csum = ethtool_op_set_tx_csum,
1143 .get_sg = ethtool_op_get_sg,
1144 .set_sg = ethtool_op_set_sg,
1145 .get_tso = ethtool_op_get_tso,
1146 .set_tso = ethtool_op_set_tso,
1147 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1148 .get_wol = rtl8169_get_wol,
1149 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1150 .get_strings = rtl8169_get_strings,
1151 .get_stats_count = rtl8169_get_stats_count,
1152 .get_ethtool_stats = rtl8169_get_ethtool_stats,
6d6525b7 1153 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1154};
1155
1156static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1157 int bitval)
1158{
1159 int val;
1160
1161 val = mdio_read(ioaddr, reg);
1162 val = (bitval == 1) ?
1163 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1164 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1165}
1166
1167static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1168{
1169 const struct {
1170 u32 mask;
1171 int mac_version;
1172 } mac_info[] = {
bcf0bf90
FR		 1173 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1174 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1175 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1176 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1177 { 0x30000000, RTL_GIGA_MAC_VER_11 },
6dccd16b 1178 { 0x98000000, RTL_GIGA_MAC_VER_06 },
bcf0bf90
FR		 1179 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1180 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1181 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1182 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1183 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1184 }, *p = mac_info;
1185 u32 reg;
1186
6dccd16b 1187 reg = RTL_R32(TxConfig) & 0xfc800000;
1da177e4
LT		 1188 while ((reg & p->mask) != p->mask)
1189 p++;
1190 tp->mac_version = p->mac_version;
1191}
1192
1193static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1194{
bcf0bf90 1195 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1196}
1197
1198static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1199{
1200 const struct {
1201 u16 mask;
1202 u16 set;
1203 int phy_version;
1204 } phy_info[] = {
1205 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1206 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1207 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1208 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1209 }, *p = phy_info;
1210 u16 reg;
1211
64e4bfb4 1212 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1da177e4
LT		 1213 while ((reg & p->mask) != p->set)
1214 p++;
1215 tp->phy_version = p->phy_version;
1216}
1217
1218static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1219{
1220 struct {
1221 int version;
1222 char *msg;
1223 u32 reg;
1224 } phy_print[] = {
1225 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1226 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1227 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1228 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1229 { 0, NULL, 0x0000 }
1230 }, *p;
1231
1232 for (p = phy_print; p->msg; p++) {
1233 if (tp->phy_version == p->version) {
1234 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1235 return;
1236 }
1237 }
1238 dprintk("phy_version == Unknown\n");
1239}
1240
1241static void rtl8169_hw_phy_config(struct net_device *dev)
1242{
1243 struct rtl8169_private *tp = netdev_priv(dev);
1244 void __iomem *ioaddr = tp->mmio_addr;
1245 struct {
1246 u16 regs[5]; /* Beware of bit-sign propagation */
1247 } phy_magic[5] = { {
1248 { 0x0000, //w 4 15 12 0
1249 0x00a1, //w 3 15 0 00a1
1250 0x0008, //w 2 15 0 0008
1251 0x1020, //w 1 15 0 1020
1252 0x1000 } },{ //w 0 15 0 1000
1253 { 0x7000, //w 4 15 12 7
1254 0xff41, //w 3 15 0 ff41
1255 0xde60, //w 2 15 0 de60
1256 0x0140, //w 1 15 0 0140
1257 0x0077 } },{ //w 0 15 0 0077
1258 { 0xa000, //w 4 15 12 a
1259 0xdf01, //w 3 15 0 df01
1260 0xdf20, //w 2 15 0 df20
1261 0xff95, //w 1 15 0 ff95
1262 0xfa00 } },{ //w 0 15 0 fa00
1263 { 0xb000, //w 4 15 12 b
1264 0xff41, //w 3 15 0 ff41
1265 0xde20, //w 2 15 0 de20
1266 0x0140, //w 1 15 0 0140
1267 0x00bb } },{ //w 0 15 0 00bb
1268 { 0xf000, //w 4 15 12 f
1269 0xdf01, //w 3 15 0 df01
1270 0xdf20, //w 2 15 0 df20
1271 0xff95, //w 1 15 0 ff95
1272 0xbf00 } //w 0 15 0 bf00
1273 }
1274 }, *p = phy_magic;
1275 int i;
1276
1277 rtl8169_print_mac_version(tp);
1278 rtl8169_print_phy_version(tp);
1279
bcf0bf90 1280 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1281 return;
1282 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1283 return;
1284
1285 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1286 dprintk("Do final_reg2.cfg\n");
1287
1288 /* Shazam ! */
1289
bcf0bf90 1290 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1291 mdio_write(ioaddr, 31, 0x0002);
1292 mdio_write(ioaddr, 1, 0x90d0);
1293 mdio_write(ioaddr, 31, 0x0000);
1294 return;
1295 }
1296
1297 /* phy config for RTL8169s mac_version C chip */
1298 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1299 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1300 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1301 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1302
1303 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1304 int val, pos = 4;
1305
1306 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1307 mdio_write(ioaddr, pos, val);
1308 while (--pos >= 0)
1309 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1310 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1311 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1312 }
1313 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1314}
1315
1316static void rtl8169_phy_timer(unsigned long __opaque)
1317{
1318 struct net_device *dev = (struct net_device *)__opaque;
1319 struct rtl8169_private *tp = netdev_priv(dev);
1320 struct timer_list *timer = &tp->timer;
1321 void __iomem *ioaddr = tp->mmio_addr;
1322 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1323
bcf0bf90 1324 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1325 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1326
64e4bfb4 1327 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1328 return;
1329
1330 spin_lock_irq(&tp->lock);
1331
1332 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1333 /*
1da177e4
LT		 1334 * A busy loop could burn quite a few cycles on nowadays CPU.
1335 * Let's delay the execution of the timer for a few ticks.
1336 */
1337 timeout = HZ/10;
1338 goto out_mod_timer;
1339 }
1340
1341 if (tp->link_ok(ioaddr))
1342 goto out_unlock;
1343
b57b7e5a
SH		 1344 if (netif_msg_link(tp))
1345 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1346
1347 tp->phy_reset_enable(ioaddr);
1348
1349out_mod_timer:
1350 mod_timer(timer, jiffies + timeout);
1351out_unlock:
1352 spin_unlock_irq(&tp->lock);
1353}
1354
1355static inline void rtl8169_delete_timer(struct net_device *dev)
1356{
1357 struct rtl8169_private *tp = netdev_priv(dev);
1358 struct timer_list *timer = &tp->timer;
1359
bcf0bf90 1360 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1361 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1362 return;
1363
1364 del_timer_sync(timer);
1365}
1366
1367static inline void rtl8169_request_timer(struct net_device *dev)
1368{
1369 struct rtl8169_private *tp = netdev_priv(dev);
1370 struct timer_list *timer = &tp->timer;
1371
bcf0bf90 1372 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1373 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1374 return;
1375
2efa53f3 1376 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1377}
1378
1379#ifdef CONFIG_NET_POLL_CONTROLLER
1380/*
1381 * Polling 'interrupt' - used by things like netconsole to send skbs
1382 * without having to re-enable interrupts. It's not called while
1383 * the interrupt routine is executing.
1384 */
1385static void rtl8169_netpoll(struct net_device *dev)
1386{
1387 struct rtl8169_private *tp = netdev_priv(dev);
1388 struct pci_dev *pdev = tp->pci_dev;
1389
1390 disable_irq(pdev->irq);
7d12e780 1391 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1392 enable_irq(pdev->irq);
1393}
1394#endif
1395
1396static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1397 void __iomem *ioaddr)
1398{
1399 iounmap(ioaddr);
1400 pci_release_regions(pdev);
1401 pci_disable_device(pdev);
1402 free_netdev(dev);
1403}
1404
bf793295
FR		 1405static void rtl8169_phy_reset(struct net_device *dev,
1406 struct rtl8169_private *tp)
1407{
1408 void __iomem *ioaddr = tp->mmio_addr;
1409 int i;
1410
1411 tp->phy_reset_enable(ioaddr);
1412 for (i = 0; i < 100; i++) {
1413 if (!tp->phy_reset_pending(ioaddr))
1414 return;
1415 msleep(1);
1416 }
1417 if (netif_msg_link(tp))
1418 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1419}
1420
4ff96fa6
FR		 1421static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1422{
1423 void __iomem *ioaddr = tp->mmio_addr;
1424 static int board_idx = -1;
1425 u8 autoneg, duplex;
1426 u16 speed;
1427
1428 board_idx++;
1429
1430 rtl8169_hw_phy_config(dev);
1431
1432 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1433 RTL_W8(0x82, 0x01);
1434
6dccd16b
FR		 1435 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1436
1437 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1438 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1439
bcf0bf90 1440 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1441 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1442 RTL_W8(0x82, 0x01);
1443 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1444 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1445 }
1446
1447 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1448
bf793295
FR		 1449 rtl8169_phy_reset(dev, tp);
1450
4ff96fa6
FR		 1451 rtl8169_set_speed(dev, autoneg, speed, duplex);
1452
1453 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1454 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1455}
1456
5f787a1a
FR		 1457static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1458{
1459 struct rtl8169_private *tp = netdev_priv(dev);
1460 struct mii_ioctl_data *data = if_mii(ifr);
1461
1462 if (!netif_running(dev))
1463 return -ENODEV;
1464
1465 switch (cmd) {
1466 case SIOCGMIIPHY:
1467 data->phy_id = 32; /* Internal PHY */
1468 return 0;
1469
1470 case SIOCGMIIREG:
1471 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1472 return 0;
1473
1474 case SIOCSMIIREG:
1475 if (!capable(CAP_NET_ADMIN))
1476 return -EPERM;
1477 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1478 return 0;
1479 }
1480 return -EOPNOTSUPP;
1481}
1482
1da177e4 1483static int __devinit
4ff96fa6 1484rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1485{
bcf0bf90 1486 const unsigned int region = rtl_cfg_info[ent->driver_data].region;
1da177e4 1487 struct rtl8169_private *tp;
4ff96fa6
FR		 1488 struct net_device *dev;
1489 void __iomem *ioaddr;
315917d2
FR		 1490 unsigned int pm_cap;
1491 int i, rc;
1da177e4 1492
4ff96fa6
FR		 1493 if (netif_msg_drv(&debug)) {
1494 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1495 MODULENAME, RTL8169_VERSION);
1496 }
1da177e4 1497
1da177e4 1498 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1499 if (!dev) {
b57b7e5a 1500 if (netif_msg_drv(&debug))
9b91cf9d 1501 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1502 rc = -ENOMEM;
1503 goto out;
1da177e4
LT		 1504 }
1505
1506 SET_MODULE_OWNER(dev);
1507 SET_NETDEV_DEV(dev, &pdev->dev);
1508 tp = netdev_priv(dev);
c4028958 1509 tp->dev = dev;
b57b7e5a 1510 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1511
1512 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1513 rc = pci_enable_device(pdev);
b57b7e5a 1514 if (rc < 0) {
2e8a538d 1515 if (netif_msg_probe(tp))
9b91cf9d 1516 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1517 goto err_out_free_dev_1;
1da177e4
LT		 1518 }
1519
1520 rc = pci_set_mwi(pdev);
1521 if (rc < 0)
4ff96fa6 1522 goto err_out_disable_2;
1da177e4
LT		 1523
1524 /* save power state before pci_enable_device overwrites it */
1525 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1526 if (pm_cap) {
4ff96fa6 1527 u16 pwr_command, acpi_idle_state;
1da177e4
LT		 1528
1529 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1530 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1531 } else {
4ff96fa6 1532 if (netif_msg_probe(tp)) {
9b91cf9d 1533 dev_err(&pdev->dev,
4ff96fa6
FR		 1534 "PowerManagement capability not found.\n");
1535 }
1da177e4
LT		 1536 }
1537
1538 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1539 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1540 if (netif_msg_probe(tp)) {
9b91cf9d 1541 dev_err(&pdev->dev,
bcf0bf90
FR		 1542 "region #%d not an MMIO resource, aborting\n",
1543 region);
4ff96fa6 1544 }
1da177e4 1545 rc = -ENODEV;
4ff96fa6 1546 goto err_out_mwi_3;
1da177e4 1547 }
4ff96fa6 1548
1da177e4 1549 /* check for weird/broken PCI region reporting */
bcf0bf90 1550 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1551 if (netif_msg_probe(tp)) {
9b91cf9d 1552 dev_err(&pdev->dev,
4ff96fa6
FR		 1553 "Invalid PCI region size(s), aborting\n");
1554 }
1da177e4 1555 rc = -ENODEV;
4ff96fa6 1556 goto err_out_mwi_3;
1da177e4
LT		 1557 }
1558
1559 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1560 if (rc < 0) {
2e8a538d 1561 if (netif_msg_probe(tp))
9b91cf9d 1562 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1563 goto err_out_mwi_3;
1da177e4
LT		 1564 }
1565
1566 tp->cp_cmd = PCIMulRW | RxChkSum;
1567
1568 if ((sizeof(dma_addr_t) > 4) &&
1569 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1570 tp->cp_cmd |= PCIDAC;
1571 dev->features |= NETIF_F_HIGHDMA;
1572 } else {
1573 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1574 if (rc < 0) {
4ff96fa6 1575 if (netif_msg_probe(tp)) {
9b91cf9d 1576 dev_err(&pdev->dev,
4ff96fa6
FR		 1577 "DMA configuration failed.\n");
1578 }
1579 goto err_out_free_res_4;
1da177e4
LT		 1580 }
1581 }
1582
1583 pci_set_master(pdev);
1584
1585 /* ioremap MMIO region */
bcf0bf90 1586 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1587 if (!ioaddr) {
b57b7e5a 1588 if (netif_msg_probe(tp))
9b91cf9d 1589 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1590 rc = -EIO;
4ff96fa6 1591 goto err_out_free_res_4;
1da177e4
LT		 1592 }
1593
1594 /* Unneeded ? Don't mess with Mrs. Murphy. */
1595 rtl8169_irq_mask_and_ack(ioaddr);
1596
1597 /* Soft reset the chip. */
1598 RTL_W8(ChipCmd, CmdReset);
1599
1600 /* Check that the chip has finished the reset. */
b518fa8e 1601 for (i = 100; i > 0; i--) {
1da177e4
LT		 1602 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1603 break;
b518fa8e 1604 msleep_interruptible(1);
1da177e4
LT		 1605 }
1606
1607 /* Identify chip attached to board */
1608 rtl8169_get_mac_version(tp, ioaddr);
1609 rtl8169_get_phy_version(tp, ioaddr);
1610
1611 rtl8169_print_mac_version(tp);
1612 rtl8169_print_phy_version(tp);
1613
1614 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1615 if (tp->mac_version == rtl_chip_info[i].mac_version)
1616 break;
1617 }
1618 if (i < 0) {
1619 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1620 if (netif_msg_probe(tp)) {
2e8a538d 1621 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1622 "unknown chip version, assuming %s\n",
1623 rtl_chip_info[0].name);
b57b7e5a 1624 }
1da177e4
LT		 1625 i++;
1626 }
1627 tp->chipset = i;
1628
5d06a99f
FR		 1629 RTL_W8(Cfg9346, Cfg9346_Unlock);
1630 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1631 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1632 RTL_W8(Cfg9346, Cfg9346_Lock);
1633
1da177e4
LT		 1634 if (RTL_R8(PHYstatus) & TBI_Enable) {
1635 tp->set_speed = rtl8169_set_speed_tbi;
1636 tp->get_settings = rtl8169_gset_tbi;
1637 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1638 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1639 tp->link_ok = rtl8169_tbi_link_ok;
1640
64e4bfb4 1641 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1642 } else {
1643 tp->set_speed = rtl8169_set_speed_xmii;
1644 tp->get_settings = rtl8169_gset_xmii;
1645 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1646 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1647 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1648
1649 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1650 }
1651
1652 /* Get MAC address. FIXME: read EEPROM */
1653 for (i = 0; i < MAC_ADDR_LEN; i++)
1654 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1655 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1656
1657 dev->open = rtl8169_open;
1658 dev->hard_start_xmit = rtl8169_start_xmit;
1659 dev->get_stats = rtl8169_get_stats;
1660 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1661 dev->stop = rtl8169_close;
1662 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1663 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1664 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1665 dev->irq = pdev->irq;
1666 dev->base_addr = (unsigned long) ioaddr;
1667 dev->change_mtu = rtl8169_change_mtu;
1668
1669#ifdef CONFIG_R8169_NAPI
1670 dev->poll = rtl8169_poll;
1671 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1672#endif
1673
1674#ifdef CONFIG_R8169_VLAN
1675 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1676 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1677#endif
1678
1679#ifdef CONFIG_NET_POLL_CONTROLLER
1680 dev->poll_controller = rtl8169_netpoll;
1681#endif
1682
1683 tp->intr_mask = 0xffff;
1684 tp->pci_dev = pdev;
1685 tp->mmio_addr = ioaddr;
bcf0bf90 1686 tp->align = rtl_cfg_info[ent->driver_data].align;
1da177e4 1687
2efa53f3
FR		 1688 init_timer(&tp->timer);
1689 tp->timer.data = (unsigned long) dev;
1690 tp->timer.function = rtl8169_phy_timer;
1691
07ce4064
FR		 1692 tp->hw_start = rtl_cfg_info[ent->driver_data].hw_start;
1693
1da177e4
LT		 1694 spin_lock_init(&tp->lock);
1695
1696 rc = register_netdev(dev);
4ff96fa6
FR		 1697 if (rc < 0)
1698 goto err_out_unmap_5;
1da177e4
LT		 1699
1700 pci_set_drvdata(pdev, dev);
1701
b57b7e5a
SH		 1702 if (netif_msg_probe(tp)) {
1703 printk(KERN_INFO "%s: %s at 0x%lx, "
1704 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1705 "IRQ %d\n",
1706 dev->name,
bcf0bf90 1707 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1708 dev->base_addr,
1709 dev->dev_addr[0], dev->dev_addr[1],
1710 dev->dev_addr[2], dev->dev_addr[3],
1711 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1712 }
1da177e4 1713
4ff96fa6 1714 rtl8169_init_phy(dev, tp);
1da177e4 1715
4ff96fa6
FR		 1716out:
1717 return rc;
1da177e4 1718
4ff96fa6
FR		 1719err_out_unmap_5:
1720 iounmap(ioaddr);
1721err_out_free_res_4:
1722 pci_release_regions(pdev);
1723err_out_mwi_3:
1724 pci_clear_mwi(pdev);
1725err_out_disable_2:
1726 pci_disable_device(pdev);
1727err_out_free_dev_1:
1728 free_netdev(dev);
1729 goto out;
1da177e4
LT		 1730}
1731
1732static void __devexit
1733rtl8169_remove_one(struct pci_dev *pdev)
1734{
1735 struct net_device *dev = pci_get_drvdata(pdev);
1736 struct rtl8169_private *tp = netdev_priv(dev);
1737
1738 assert(dev != NULL);
1739 assert(tp != NULL);
1740
eb2a021c
FR		 1741 flush_scheduled_work();
1742
1da177e4
LT		 1743 unregister_netdev(dev);
1744 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1745 pci_set_drvdata(pdev, NULL);
1746}
1747
1da177e4
LT		 1748static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1749 struct net_device *dev)
1750{
1751 unsigned int mtu = dev->mtu;
1752
1753 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1754}
1755
1756static int rtl8169_open(struct net_device *dev)
1757{
1758 struct rtl8169_private *tp = netdev_priv(dev);
1759 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1760 int retval = -ENOMEM;
1da177e4 1761
1da177e4 1762
99f252b0 1763 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1764
1765 /*
1766 * Rx and Tx desscriptors needs 256 bytes alignment.
1767 * pci_alloc_consistent provides more.
1768 */
1769 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1770 &tp->TxPhyAddr);
1771 if (!tp->TxDescArray)
99f252b0 1772 goto out;
1da177e4
LT		 1773
1774 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1775 &tp->RxPhyAddr);
1776 if (!tp->RxDescArray)
99f252b0 1777 goto err_free_tx_0;
1da177e4
LT		 1778
1779 retval = rtl8169_init_ring(dev);
1780 if (retval < 0)
99f252b0 1781 goto err_free_rx_1;
1da177e4 1782
c4028958 1783 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1784
99f252b0
FR		 1785 smp_mb();
1786
1787 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1788 dev->name, dev);
1789 if (retval < 0)
1790 goto err_release_ring_2;
1791
07ce4064 1792 rtl_hw_start(dev);
1da177e4
LT		 1793
1794 rtl8169_request_timer(dev);
1795
1796 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1797out:
1798 return retval;
1799
99f252b0
FR		 1800err_release_ring_2:
1801 rtl8169_rx_clear(tp);
1802err_free_rx_1:
1da177e4
LT		 1803 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1804 tp->RxPhyAddr);
99f252b0 1805err_free_tx_0:
1da177e4
LT		 1806 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1807 tp->TxPhyAddr);
1da177e4
LT		 1808 goto out;
1809}
1810
1811static void rtl8169_hw_reset(void __iomem *ioaddr)
1812{
1813 /* Disable interrupts */
1814 rtl8169_irq_mask_and_ack(ioaddr);
1815
1816 /* Reset the chipset */
1817 RTL_W8(ChipCmd, CmdReset);
1818
1819 /* PCI commit */
1820 RTL_R8(ChipCmd);
1821}
1822
7f796d83 1823static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1824{
1825 void __iomem *ioaddr = tp->mmio_addr;
1826 u32 cfg = rtl8169_rx_config;
1827
1828 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1829 RTL_W32(RxConfig, cfg);
1830
1831 /* Set DMA burst size and Interframe Gap Time */
1832 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1833 (InterFrameGap << TxInterFrameGapShift));
1834}
1835
07ce4064 1836static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1837{
1838 struct rtl8169_private *tp = netdev_priv(dev);
1839 void __iomem *ioaddr = tp->mmio_addr;
1840 u32 i;
1841
1842 /* Soft reset the chip. */
1843 RTL_W8(ChipCmd, CmdReset);
1844
1845 /* Check that the chip has finished the reset. */
b518fa8e 1846 for (i = 100; i > 0; i--) {
1da177e4
LT		 1847 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1848 break;
b518fa8e 1849 msleep_interruptible(1);
1da177e4
LT		 1850 }
1851
07ce4064
FR		 1852 tp->hw_start(dev);
1853
07ce4064
FR		 1854 netif_start_queue(dev);
1855}
1856
1857
7f796d83
FR		 1858static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1859 void __iomem *ioaddr)
1860{
1861 /*
1862 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1863 * register to be written before TxDescAddrLow to work.
1864 * Switching from MMIO to I/O access fixes the issue as well.
1865 */
1866 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1867 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1868 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1869 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1870}
1871
1872static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1873{
1874 u16 cmd;
1875
1876 cmd = RTL_R16(CPlusCmd);
1877 RTL_W16(CPlusCmd, cmd);
1878 return cmd;
1879}
1880
1881static void rtl_set_rx_max_size(void __iomem *ioaddr)
1882{
1883 /* Low hurts. Let's disable the filtering. */
1884 RTL_W16(RxMaxSize, 16383);
1885}
1886
6dccd16b
FR		 1887static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1888{
1889 struct {
1890 u32 mac_version;
1891 u32 clk;
1892 u32 val;
1893 } cfg2_info [] = {
1894 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1895 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1896 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1897 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1898 }, *p = cfg2_info;
1899 unsigned int i;
1900 u32 clk;
1901
1902 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1903 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1904 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1905 RTL_W32(0x7c, p->val);
1906 break;
1907 }
1908 }
1909}
1910
07ce4064
FR		 1911static void rtl_hw_start_8169(struct net_device *dev)
1912{
1913 struct rtl8169_private *tp = netdev_priv(dev);
1914 void __iomem *ioaddr = tp->mmio_addr;
1915 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1916
9cb427b6
FR		 1917 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1918 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1919 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1920 }
1921
1da177e4 1922 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1923 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1924 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1925 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1926 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1927 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1928
1da177e4
LT		 1929 RTL_W8(EarlyTxThres, EarlyTxThld);
1930
7f796d83 1931 rtl_set_rx_max_size(ioaddr);
1da177e4 1932
6dccd16b 1933 rtl_set_rx_tx_config_registers(tp);
1da177e4 1934
7f796d83 1935 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 1936
bcf0bf90
FR		 1937 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1938 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1da177e4
LT		 1939 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1940 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1941 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1942 }
1943
bcf0bf90
FR		 1944 RTL_W16(CPlusCmd, tp->cp_cmd);
1945
6dccd16b
FR		 1946 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1947
1da177e4
LT		 1948 /*
1949 * Undocumented corner. Supposedly:
1950 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1951 */
1952 RTL_W16(IntrMitigate, 0x0000);
1953
7f796d83 1954 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 1955
1da177e4 1956 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 1957
1958 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1959 RTL_R8(IntrMask);
1da177e4
LT		 1960
1961 RTL_W32(RxMissed, 0);
1962
07ce4064 1963 rtl_set_rx_mode(dev);
1da177e4
LT		 1964
1965 /* no early-rx interrupts */
1966 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 1967
1968 /* Enable all known interrupts by setting the interrupt mask. */
1969 RTL_W16(IntrMask, rtl8169_intr_mask);
1970
1971 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
07ce4064 1972}
1da177e4 1973
07ce4064
FR		 1974static void rtl_hw_start_8168(struct net_device *dev)
1975{
2dd99530
FR		 1976 struct rtl8169_private *tp = netdev_priv(dev);
1977 void __iomem *ioaddr = tp->mmio_addr;
1978
1979 RTL_W8(Cfg9346, Cfg9346_Unlock);
1980
1981 RTL_W8(EarlyTxThres, EarlyTxThld);
1982
1983 rtl_set_rx_max_size(ioaddr);
1984
1985 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1986
1987 RTL_W16(CPlusCmd, tp->cp_cmd);
1988
1989 RTL_W16(IntrMitigate, 0x0000);
1990
1991 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1992
1993 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1994 rtl_set_rx_tx_config_registers(tp);
1995
1996 RTL_W8(Cfg9346, Cfg9346_Lock);
1997
1998 RTL_R8(IntrMask);
1999
2000 RTL_W32(RxMissed, 0);
2001
2002 rtl_set_rx_mode(dev);
2003
2004 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2005
2006 RTL_W16(IntrMask, rtl8169_intr_mask);
07ce4064 2007}
1da177e4 2008
07ce4064
FR		 2009static void rtl_hw_start_8101(struct net_device *dev)
2010{
cdf1a608
FR		 2011 struct rtl8169_private *tp = netdev_priv(dev);
2012 void __iomem *ioaddr = tp->mmio_addr;
2013 struct pci_dev *pdev = tp->pci_dev;
2014
2015 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2016 pci_write_config_word(pdev, 0x68, 0x00);
2017 pci_write_config_word(pdev, 0x69, 0x08);
2018 }
2019
2020 RTL_W8(Cfg9346, Cfg9346_Unlock);
2021
2022 RTL_W8(EarlyTxThres, EarlyTxThld);
2023
2024 rtl_set_rx_max_size(ioaddr);
2025
2026 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2027
2028 RTL_W16(CPlusCmd, tp->cp_cmd);
2029
2030 RTL_W16(IntrMitigate, 0x0000);
2031
2032 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2033
2034 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2035 rtl_set_rx_tx_config_registers(tp);
2036
2037 RTL_W8(Cfg9346, Cfg9346_Lock);
2038
2039 RTL_R8(IntrMask);
2040
2041 RTL_W32(RxMissed, 0);
2042
2043 rtl_set_rx_mode(dev);
2044
2045 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b
FR		 2046
2047 RTL_W16(IntrMask, rtl8169_intr_mask);
1da177e4
LT		 2048}
2049
2050static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2051{
2052 struct rtl8169_private *tp = netdev_priv(dev);
2053 int ret = 0;
2054
2055 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2056 return -EINVAL;
2057
2058 dev->mtu = new_mtu;
2059
2060 if (!netif_running(dev))
2061 goto out;
2062
2063 rtl8169_down(dev);
2064
2065 rtl8169_set_rxbufsize(tp, dev);
2066
2067 ret = rtl8169_init_ring(dev);
2068 if (ret < 0)
2069 goto out;
2070
2071 netif_poll_enable(dev);
2072
07ce4064 2073 rtl_hw_start(dev);
1da177e4
LT		 2074
2075 rtl8169_request_timer(dev);
2076
2077out:
2078 return ret;
2079}
2080
2081static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2082{
2083 desc->addr = 0x0badbadbadbadbadull;
2084 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2085}
2086
2087static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2088 struct sk_buff **sk_buff, struct RxDesc *desc)
2089{
2090 struct pci_dev *pdev = tp->pci_dev;
2091
2092 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2093 PCI_DMA_FROMDEVICE);
2094 dev_kfree_skb(*sk_buff);
2095 *sk_buff = NULL;
2096 rtl8169_make_unusable_by_asic(desc);
2097}
2098
2099static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2100{
2101 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2102
2103 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2104}
2105
2106static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2107 u32 rx_buf_sz)
2108{
2109 desc->addr = cpu_to_le64(mapping);
2110 wmb();
2111 rtl8169_mark_to_asic(desc, rx_buf_sz);
2112}
2113
15d31758
SH		 2114static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2115 struct net_device *dev,
2116 struct RxDesc *desc, int rx_buf_sz,
2117 unsigned int align)
1da177e4
LT		 2118{
2119 struct sk_buff *skb;
2120 dma_addr_t mapping;
1da177e4 2121
15d31758 2122 skb = netdev_alloc_skb(dev, rx_buf_sz + align);
1da177e4
LT		 2123 if (!skb)
2124 goto err_out;
2125
dcb92f88 2126 skb_reserve(skb, (align - 1) & (unsigned long)skb->data);
1da177e4 2127
689be439 2128 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2129 PCI_DMA_FROMDEVICE);
2130
2131 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2132out:
15d31758 2133 return skb;
1da177e4
LT		 2134
2135err_out:
1da177e4
LT		 2136 rtl8169_make_unusable_by_asic(desc);
2137 goto out;
2138}
2139
2140static void rtl8169_rx_clear(struct rtl8169_private *tp)
2141{
2142 int i;
2143
2144 for (i = 0; i < NUM_RX_DESC; i++) {
2145 if (tp->Rx_skbuff[i]) {
2146 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2147 tp->RxDescArray + i);
2148 }
2149 }
2150}
2151
2152static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2153 u32 start, u32 end)
2154{
2155 u32 cur;
5b0384f4 2156
4ae47c2d 2157 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2158 struct sk_buff *skb;
2159 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2160
4ae47c2d
FR		 2161 WARN_ON((s32)(end - cur) < 0);
2162
1da177e4
LT		 2163 if (tp->Rx_skbuff[i])
2164 continue;
bcf0bf90 2165
15d31758
SH		 2166 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2167 tp->RxDescArray + i,
2168 tp->rx_buf_sz, tp->align);
2169 if (!skb)
1da177e4 2170 break;
15d31758
SH		 2171
2172 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2173 }
2174 return cur - start;
2175}
2176
2177static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2178{
2179 desc->opts1 |= cpu_to_le32(RingEnd);
2180}
2181
2182static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2183{
2184 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2185}
2186
2187static int rtl8169_init_ring(struct net_device *dev)
2188{
2189 struct rtl8169_private *tp = netdev_priv(dev);
2190
2191 rtl8169_init_ring_indexes(tp);
2192
2193 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2194 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2195
2196 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2197 goto err_out;
2198
2199 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2200
2201 return 0;
2202
2203err_out:
2204 rtl8169_rx_clear(tp);
2205 return -ENOMEM;
2206}
2207
2208static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2209 struct TxDesc *desc)
2210{
2211 unsigned int len = tx_skb->len;
2212
2213 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2214 desc->opts1 = 0x00;
2215 desc->opts2 = 0x00;
2216 desc->addr = 0x00;
2217 tx_skb->len = 0;
2218}
2219
2220static void rtl8169_tx_clear(struct rtl8169_private *tp)
2221{
2222 unsigned int i;
2223
2224 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2225 unsigned int entry = i % NUM_TX_DESC;
2226 struct ring_info *tx_skb = tp->tx_skb + entry;
2227 unsigned int len = tx_skb->len;
2228
2229 if (len) {
2230 struct sk_buff *skb = tx_skb->skb;
2231
2232 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2233 tp->TxDescArray + entry);
2234 if (skb) {
2235 dev_kfree_skb(skb);
2236 tx_skb->skb = NULL;
2237 }
2238 tp->stats.tx_dropped++;
2239 }
2240 }
2241 tp->cur_tx = tp->dirty_tx = 0;
2242}
2243
c4028958 2244static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2245{
2246 struct rtl8169_private *tp = netdev_priv(dev);
2247
c4028958 2248 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2249 schedule_delayed_work(&tp->task, 4);
2250}
2251
2252static void rtl8169_wait_for_quiescence(struct net_device *dev)
2253{
2254 struct rtl8169_private *tp = netdev_priv(dev);
2255 void __iomem *ioaddr = tp->mmio_addr;
2256
2257 synchronize_irq(dev->irq);
2258
2259 /* Wait for any pending NAPI task to complete */
2260 netif_poll_disable(dev);
2261
2262 rtl8169_irq_mask_and_ack(ioaddr);
2263
2264 netif_poll_enable(dev);
2265}
2266
c4028958 2267static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2268{
c4028958
DH		 2269 struct rtl8169_private *tp =
2270 container_of(work, struct rtl8169_private, task.work);
2271 struct net_device *dev = tp->dev;
1da177e4
LT		 2272 int ret;
2273
eb2a021c
FR		 2274 rtnl_lock();
2275
2276 if (!netif_running(dev))
2277 goto out_unlock;
2278
2279 rtl8169_wait_for_quiescence(dev);
2280 rtl8169_close(dev);
1da177e4
LT		 2281
2282 ret = rtl8169_open(dev);
2283 if (unlikely(ret < 0)) {
2284 if (net_ratelimit()) {
b57b7e5a
SH		 2285 struct rtl8169_private *tp = netdev_priv(dev);
2286
2287 if (netif_msg_drv(tp)) {
2288 printk(PFX KERN_ERR
2289 "%s: reinit failure (status = %d)."
2290 " Rescheduling.\n", dev->name, ret);
2291 }
1da177e4
LT		 2292 }
2293 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2294 }
eb2a021c
FR		 2295
2296out_unlock:
2297 rtnl_unlock();
1da177e4
LT		 2298}
2299
c4028958 2300static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2301{
c4028958
DH		 2302 struct rtl8169_private *tp =
2303 container_of(work, struct rtl8169_private, task.work);
2304 struct net_device *dev = tp->dev;
1da177e4 2305
eb2a021c
FR		 2306 rtnl_lock();
2307
1da177e4 2308 if (!netif_running(dev))
eb2a021c 2309 goto out_unlock;
1da177e4
LT		 2310
2311 rtl8169_wait_for_quiescence(dev);
2312
2313 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2314 rtl8169_tx_clear(tp);
2315
2316 if (tp->dirty_rx == tp->cur_rx) {
2317 rtl8169_init_ring_indexes(tp);
07ce4064 2318 rtl_hw_start(dev);
1da177e4
LT		 2319 netif_wake_queue(dev);
2320 } else {
2321 if (net_ratelimit()) {
b57b7e5a
SH		 2322 struct rtl8169_private *tp = netdev_priv(dev);
2323
2324 if (netif_msg_intr(tp)) {
2325 printk(PFX KERN_EMERG
2326 "%s: Rx buffers shortage\n", dev->name);
2327 }
1da177e4
LT		 2328 }
2329 rtl8169_schedule_work(dev, rtl8169_reset_task);
2330 }
eb2a021c
FR		 2331
2332out_unlock:
2333 rtnl_unlock();
1da177e4
LT		 2334}
2335
2336static void rtl8169_tx_timeout(struct net_device *dev)
2337{
2338 struct rtl8169_private *tp = netdev_priv(dev);
2339
2340 rtl8169_hw_reset(tp->mmio_addr);
2341
2342 /* Let's wait a bit while any (async) irq lands on */
2343 rtl8169_schedule_work(dev, rtl8169_reset_task);
2344}
2345
2346static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2347 u32 opts1)
2348{
2349 struct skb_shared_info *info = skb_shinfo(skb);
2350 unsigned int cur_frag, entry;
2351 struct TxDesc *txd;
2352
2353 entry = tp->cur_tx;
2354 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2355 skb_frag_t *frag = info->frags + cur_frag;
2356 dma_addr_t mapping;
2357 u32 status, len;
2358 void *addr;
2359
2360 entry = (entry + 1) % NUM_TX_DESC;
2361
2362 txd = tp->TxDescArray + entry;
2363 len = frag->size;
2364 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2365 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2366
2367 /* anti gcc 2.95.3 bugware (sic) */
2368 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2369
2370 txd->opts1 = cpu_to_le32(status);
2371 txd->addr = cpu_to_le64(mapping);
2372
2373 tp->tx_skb[entry].len = len;
2374 }
2375
2376 if (cur_frag) {
2377 tp->tx_skb[entry].skb = skb;
2378 txd->opts1 |= cpu_to_le32(LastFrag);
2379 }
2380
2381 return cur_frag;
2382}
2383
2384static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2385{
2386 if (dev->features & NETIF_F_TSO) {
7967168c 2387 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2388
2389 if (mss)
2390 return LargeSend | ((mss & MSSMask) << MSSShift);
2391 }
84fa7933 2392 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2393 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2394
2395 if (ip->protocol == IPPROTO_TCP)
2396 return IPCS | TCPCS;
2397 else if (ip->protocol == IPPROTO_UDP)
2398 return IPCS | UDPCS;
2399 WARN_ON(1); /* we need a WARN() */
2400 }
2401 return 0;
2402}
2403
2404static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2405{
2406 struct rtl8169_private *tp = netdev_priv(dev);
2407 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2408 struct TxDesc *txd = tp->TxDescArray + entry;
2409 void __iomem *ioaddr = tp->mmio_addr;
2410 dma_addr_t mapping;
2411 u32 status, len;
2412 u32 opts1;
188f4af0 2413 int ret = NETDEV_TX_OK;
5b0384f4 2414
1da177e4 2415 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2416 if (netif_msg_drv(tp)) {
2417 printk(KERN_ERR
2418 "%s: BUG! Tx Ring full when queue awake!\n",
2419 dev->name);
2420 }
1da177e4
LT		 2421 goto err_stop;
2422 }
2423
2424 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2425 goto err_stop;
2426
2427 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2428
2429 frags = rtl8169_xmit_frags(tp, skb, opts1);
2430 if (frags) {
2431 len = skb_headlen(skb);
2432 opts1 |= FirstFrag;
2433 } else {
2434 len = skb->len;
2435
2436 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2437 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2438 goto err_update_stats;
2439 len = ETH_ZLEN;
2440 }
2441
2442 opts1 |= FirstFrag | LastFrag;
2443 tp->tx_skb[entry].skb = skb;
2444 }
2445
2446 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2447
2448 tp->tx_skb[entry].len = len;
2449 txd->addr = cpu_to_le64(mapping);
2450 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2451
2452 wmb();
2453
2454 /* anti gcc 2.95.3 bugware (sic) */
2455 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2456 txd->opts1 = cpu_to_le32(status);
2457
2458 dev->trans_start = jiffies;
2459
2460 tp->cur_tx += frags + 1;
2461
2462 smp_wmb();
2463
2464 RTL_W8(TxPoll, 0x40); /* set polling bit */
2465
2466 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2467 netif_stop_queue(dev);
2468 smp_rmb();
2469 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2470 netif_wake_queue(dev);
2471 }
2472
2473out:
2474 return ret;
2475
2476err_stop:
2477 netif_stop_queue(dev);
188f4af0 2478 ret = NETDEV_TX_BUSY;
1da177e4
LT		 2479err_update_stats:
2480 tp->stats.tx_dropped++;
2481 goto out;
2482}
2483
2484static void rtl8169_pcierr_interrupt(struct net_device *dev)
2485{
2486 struct rtl8169_private *tp = netdev_priv(dev);
2487 struct pci_dev *pdev = tp->pci_dev;
2488 void __iomem *ioaddr = tp->mmio_addr;
2489 u16 pci_status, pci_cmd;
2490
2491 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2492 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2493
b57b7e5a
SH		 2494 if (netif_msg_intr(tp)) {
2495 printk(KERN_ERR
2496 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2497 dev->name, pci_cmd, pci_status);
2498 }
1da177e4
LT		 2499
2500 /*
2501 * The recovery sequence below admits a very elaborated explanation:
2502 * - it seems to work;
d03902b8
FR		 2503 * - I did not see what else could be done;
2504 * - it makes iop3xx happy.
1da177e4
LT		 2505 *
2506 * Feel free to adjust to your needs.
2507 */
a27993f3 2508 if (pdev->broken_parity_status)
d03902b8
FR		 2509 pci_cmd &= ~PCI_COMMAND_PARITY;
2510 else
2511 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2512
2513 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2514
2515 pci_write_config_word(pdev, PCI_STATUS,
2516 pci_status & (PCI_STATUS_DETECTED_PARITY |
2517 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2518 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2519
2520 /* The infamous DAC f*ckup only happens at boot time */
2521 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2522 if (netif_msg_intr(tp))
2523 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2524 tp->cp_cmd &= ~PCIDAC;
2525 RTL_W16(CPlusCmd, tp->cp_cmd);
2526 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2527 }
2528
2529 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2530
2531 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2532}
2533
2534static void
2535rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2536 void __iomem *ioaddr)
2537{
2538 unsigned int dirty_tx, tx_left;
2539
2540 assert(dev != NULL);
2541 assert(tp != NULL);
2542 assert(ioaddr != NULL);
2543
2544 dirty_tx = tp->dirty_tx;
2545 smp_rmb();
2546 tx_left = tp->cur_tx - dirty_tx;
2547
2548 while (tx_left > 0) {
2549 unsigned int entry = dirty_tx % NUM_TX_DESC;
2550 struct ring_info *tx_skb = tp->tx_skb + entry;
2551 u32 len = tx_skb->len;
2552 u32 status;
2553
2554 rmb();
2555 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2556 if (status & DescOwn)
2557 break;
2558
2559 tp->stats.tx_bytes += len;
2560 tp->stats.tx_packets++;
2561
2562 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2563
2564 if (status & LastFrag) {
2565 dev_kfree_skb_irq(tx_skb->skb);
2566 tx_skb->skb = NULL;
2567 }
2568 dirty_tx++;
2569 tx_left--;
2570 }
2571
2572 if (tp->dirty_tx != dirty_tx) {
2573 tp->dirty_tx = dirty_tx;
2574 smp_wmb();
2575 if (netif_queue_stopped(dev) &&
2576 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2577 netif_wake_queue(dev);
2578 }
2579 }
2580}
2581
126fa4b9
FR		 2582static inline int rtl8169_fragmented_frame(u32 status)
2583{
2584 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2585}
2586
1da177e4
LT		 2587static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2588{
2589 u32 opts1 = le32_to_cpu(desc->opts1);
2590 u32 status = opts1 & RxProtoMask;
2591
2592 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2593 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2594 ((status == RxProtoIP) && !(opts1 & IPFail)))
2595 skb->ip_summed = CHECKSUM_UNNECESSARY;
2596 else
2597 skb->ip_summed = CHECKSUM_NONE;
2598}
2599
b449655f
SH		 2600static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2601 struct pci_dev *pdev, dma_addr_t addr,
2602 unsigned int align)
1da177e4 2603{
b449655f
SH		 2604 struct sk_buff *skb;
2605 bool done = false;
1da177e4 2606
b449655f
SH		 2607 if (pkt_size >= rx_copybreak)
2608 goto out;
1da177e4 2609
b449655f
SH		 2610 skb = dev_alloc_skb(pkt_size + align);
2611 if (!skb)
2612 goto out;
2613
2614 pci_dma_sync_single_for_cpu(pdev, addr, pkt_size, PCI_DMA_FROMDEVICE);
2615 skb_reserve(skb, (align - 1) & (unsigned long)skb->data);
2616 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2617 *sk_buff = skb;
2618 done = true;
2619out:
2620 return done;
1da177e4
LT		 2621}
2622
2623static int
2624rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2625 void __iomem *ioaddr)
2626{
2627 unsigned int cur_rx, rx_left;
2628 unsigned int delta, count;
2629
2630 assert(dev != NULL);
2631 assert(tp != NULL);
2632 assert(ioaddr != NULL);
2633
2634 cur_rx = tp->cur_rx;
2635 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2636 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2637
4dcb7d33 2638 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2639 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2640 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2641 u32 status;
2642
2643 rmb();
126fa4b9 2644 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2645
2646 if (status & DescOwn)
2647 break;
4dcb7d33 2648 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2649 if (netif_msg_rx_err(tp)) {
2650 printk(KERN_INFO
2651 "%s: Rx ERROR. status = %08x\n",
2652 dev->name, status);
2653 }
1da177e4
LT		 2654 tp->stats.rx_errors++;
2655 if (status & (RxRWT | RxRUNT))
2656 tp->stats.rx_length_errors++;
2657 if (status & RxCRC)
2658 tp->stats.rx_crc_errors++;
9dccf611
FR		 2659 if (status & RxFOVF) {
2660 rtl8169_schedule_work(dev, rtl8169_reset_task);
2661 tp->stats.rx_fifo_errors++;
2662 }
126fa4b9 2663 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2664 } else {
1da177e4 2665 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2666 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2667 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2668 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2669
126fa4b9
FR		 2670 /*
2671 * The driver does not support incoming fragmented
2672 * frames. They are seen as a symptom of over-mtu
2673 * sized frames.
2674 */
2675 if (unlikely(rtl8169_fragmented_frame(status))) {
2676 tp->stats.rx_dropped++;
2677 tp->stats.rx_length_errors++;
2678 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2679 continue;
126fa4b9
FR		 2680 }
2681
1da177e4 2682 rtl8169_rx_csum(skb, desc);
bcf0bf90 2683
b449655f
SH		 2684 if (rtl8169_try_rx_copy(&skb, pkt_size, pdev, addr,
2685 tp->align)) {
2686 pci_dma_sync_single_for_device(pdev, addr,
2687 pkt_size, PCI_DMA_FROMDEVICE);
2688 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2689 } else {
2690 pci_unmap_single(pdev, addr, pkt_size,
2691 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2692 tp->Rx_skbuff[entry] = NULL;
2693 }
2694
1da177e4
LT		 2695 skb_put(skb, pkt_size);
2696 skb->protocol = eth_type_trans(skb, dev);
2697
2698 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2699 rtl8169_rx_skb(skb);
2700
2701 dev->last_rx = jiffies;
2702 tp->stats.rx_bytes += pkt_size;
2703 tp->stats.rx_packets++;
2704 }
6dccd16b
FR		 2705
2706 /* Work around for AMD plateform. */
2707 if ((desc->opts2 & 0xfffe000) &&
2708 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2709 desc->opts2 = 0;
2710 cur_rx++;
2711 }
1da177e4
LT		 2712 }
2713
2714 count = cur_rx - tp->cur_rx;
2715 tp->cur_rx = cur_rx;
2716
2717 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2718 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2719 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2720 tp->dirty_rx += delta;
2721
2722 /*
2723 * FIXME: until there is periodic timer to try and refill the ring,
2724 * a temporary shortage may definitely kill the Rx process.
2725 * - disable the asic to try and avoid an overflow and kick it again
2726 * after refill ?
2727 * - how do others driver handle this condition (Uh oh...).
2728 */
b57b7e5a 2729 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2730 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2731
2732 return count;
2733}
2734
2735/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2736static irqreturn_t
7d12e780 2737rtl8169_interrupt(int irq, void *dev_instance)
1da177e4
LT		 2738{
2739 struct net_device *dev = (struct net_device *) dev_instance;
2740 struct rtl8169_private *tp = netdev_priv(dev);
2741 int boguscnt = max_interrupt_work;
2742 void __iomem *ioaddr = tp->mmio_addr;
2743 int status;
2744 int handled = 0;
2745
2746 do {
2747 status = RTL_R16(IntrStatus);
2748
2749 /* hotplug/major error/no more work/shared irq */
2750 if ((status == 0xFFFF) || !status)
2751 break;
2752
2753 handled = 1;
2754
2755 if (unlikely(!netif_running(dev))) {
2756 rtl8169_asic_down(ioaddr);
2757 goto out;
2758 }
2759
2760 status &= tp->intr_mask;
2761 RTL_W16(IntrStatus,
2762 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2763
2764 if (!(status & rtl8169_intr_mask))
2765 break;
2766
2767 if (unlikely(status & SYSErr)) {
2768 rtl8169_pcierr_interrupt(dev);
2769 break;
2770 }
2771
2772 if (status & LinkChg)
2773 rtl8169_check_link_status(dev, tp, ioaddr);
2774
2775#ifdef CONFIG_R8169_NAPI
2776 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2777 tp->intr_mask = ~rtl8169_napi_event;
2778
2779 if (likely(netif_rx_schedule_prep(dev)))
2780 __netif_rx_schedule(dev);
b57b7e5a 2781 else if (netif_msg_intr(tp)) {
1da177e4 2782 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
5b0384f4 2783 dev->name, status);
1da177e4
LT		 2784 }
2785 break;
2786#else
2787 /* Rx interrupt */
2788 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2789 rtl8169_rx_interrupt(dev, tp, ioaddr);
2790 }
2791 /* Tx interrupt */
2792 if (status & (TxOK | TxErr))
2793 rtl8169_tx_interrupt(dev, tp, ioaddr);
2794#endif
2795
2796 boguscnt--;
2797 } while (boguscnt > 0);
2798
2799 if (boguscnt <= 0) {
7c8b2eb4 2800 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2801 printk(KERN_WARNING
2802 "%s: Too much work at interrupt!\n", dev->name);
2803 }
1da177e4
LT		 2804 /* Clear all interrupt sources. */
2805 RTL_W16(IntrStatus, 0xffff);
2806 }
2807out:
2808 return IRQ_RETVAL(handled);
2809}
2810
2811#ifdef CONFIG_R8169_NAPI
2812static int rtl8169_poll(struct net_device *dev, int *budget)
2813{
2814 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2815 struct rtl8169_private *tp = netdev_priv(dev);
2816 void __iomem *ioaddr = tp->mmio_addr;
2817
2818 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2819 rtl8169_tx_interrupt(dev, tp, ioaddr);
2820
2821 *budget -= work_done;
2822 dev->quota -= work_done;
2823
2824 if (work_done < work_to_do) {
2825 netif_rx_complete(dev);
2826 tp->intr_mask = 0xffff;
2827 /*
2828 * 20040426: the barrier is not strictly required but the
2829 * behavior of the irq handler could be less predictable
2830 * without it. Btw, the lack of flush for the posted pci
2831 * write is safe - FR
2832 */
2833 smp_wmb();
2834 RTL_W16(IntrMask, rtl8169_intr_mask);
2835 }
2836
2837 return (work_done >= work_to_do);
2838}
2839#endif
2840
2841static void rtl8169_down(struct net_device *dev)
2842{
2843 struct rtl8169_private *tp = netdev_priv(dev);
2844 void __iomem *ioaddr = tp->mmio_addr;
2845 unsigned int poll_locked = 0;
733b736c 2846 unsigned int intrmask;
1da177e4
LT		 2847
2848 rtl8169_delete_timer(dev);
2849
2850 netif_stop_queue(dev);
2851
1da177e4
LT		 2852core_down:
2853 spin_lock_irq(&tp->lock);
2854
2855 rtl8169_asic_down(ioaddr);
2856
2857 /* Update the error counts. */
2858 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2859 RTL_W32(RxMissed, 0);
2860
2861 spin_unlock_irq(&tp->lock);
2862
2863 synchronize_irq(dev->irq);
2864
2865 if (!poll_locked) {
2866 netif_poll_disable(dev);
2867 poll_locked++;
2868 }
2869
2870 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2871 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2872
2873 /*
2874 * And now for the 50k$ question: are IRQ disabled or not ?
2875 *
2876 * Two paths lead here:
2877 * 1) dev->close
2878 * -> netif_running() is available to sync the current code and the
2879 * IRQ handler. See rtl8169_interrupt for details.
2880 * 2) dev->change_mtu
2881 * -> rtl8169_poll can not be issued again and re-enable the
2882 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2883 *
2884 * No loop if hotpluged or major error (0xffff).
1da177e4 2885 */
733b736c
AP		 2886 intrmask = RTL_R16(IntrMask);
2887 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2888 goto core_down;
2889
2890 rtl8169_tx_clear(tp);
2891
2892 rtl8169_rx_clear(tp);
2893}
2894
2895static int rtl8169_close(struct net_device *dev)
2896{
2897 struct rtl8169_private *tp = netdev_priv(dev);
2898 struct pci_dev *pdev = tp->pci_dev;
2899
2900 rtl8169_down(dev);
2901
2902 free_irq(dev->irq, dev);
2903
2904 netif_poll_enable(dev);
2905
2906 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2907 tp->RxPhyAddr);
2908 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2909 tp->TxPhyAddr);
2910 tp->TxDescArray = NULL;
2911 tp->RxDescArray = NULL;
2912
2913 return 0;
2914}
2915
07ce4064 2916static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 2917{
2918 struct rtl8169_private *tp = netdev_priv(dev);
2919 void __iomem *ioaddr = tp->mmio_addr;
2920 unsigned long flags;
2921 u32 mc_filter[2]; /* Multicast hash filter */
2922 int i, rx_mode;
2923 u32 tmp = 0;
2924
2925 if (dev->flags & IFF_PROMISC) {
2926 /* Unconditionally log net taps. */
b57b7e5a
SH		 2927 if (netif_msg_link(tp)) {
2928 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2929 dev->name);
2930 }
1da177e4
LT		 2931 rx_mode =
2932 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2933 AcceptAllPhys;
2934 mc_filter[1] = mc_filter[0] = 0xffffffff;
2935 } else if ((dev->mc_count > multicast_filter_limit)
2936 || (dev->flags & IFF_ALLMULTI)) {
2937 /* Too many to filter perfectly -- accept all multicasts. */
2938 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2939 mc_filter[1] = mc_filter[0] = 0xffffffff;
2940 } else {
2941 struct dev_mc_list *mclist;
2942 rx_mode = AcceptBroadcast | AcceptMyPhys;
2943 mc_filter[1] = mc_filter[0] = 0;
2944 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2945 i++, mclist = mclist->next) {
2946 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2947 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2948 rx_mode |= AcceptMulticast;
2949 }
2950 }
2951
2952 spin_lock_irqsave(&tp->lock, flags);
2953
2954 tmp = rtl8169_rx_config | rx_mode |
2955 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2956
bcf0bf90
FR		 2957 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2958 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2959 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2960 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2961 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2962 mc_filter[0] = 0xffffffff;
2963 mc_filter[1] = 0xffffffff;
2964 }
2965
1da177e4
LT		 2966 RTL_W32(RxConfig, tmp);
2967 RTL_W32(MAR0 + 0, mc_filter[0]);
2968 RTL_W32(MAR0 + 4, mc_filter[1]);
2969
2970 spin_unlock_irqrestore(&tp->lock, flags);
2971}
2972
2973/**
2974 * rtl8169_get_stats - Get rtl8169 read/write statistics
2975 * @dev: The Ethernet Device to get statistics for
2976 *
2977 * Get TX/RX statistics for rtl8169
2978 */
2979static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2980{
2981 struct rtl8169_private *tp = netdev_priv(dev);
2982 void __iomem *ioaddr = tp->mmio_addr;
2983 unsigned long flags;
2984
2985 if (netif_running(dev)) {
2986 spin_lock_irqsave(&tp->lock, flags);
2987 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2988 RTL_W32(RxMissed, 0);
2989 spin_unlock_irqrestore(&tp->lock, flags);
2990 }
5b0384f4 2991
1da177e4
LT		 2992 return &tp->stats;
2993}
2994
5d06a99f
FR		 2995#ifdef CONFIG_PM
2996
2997static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2998{
2999 struct net_device *dev = pci_get_drvdata(pdev);
3000 struct rtl8169_private *tp = netdev_priv(dev);
3001 void __iomem *ioaddr = tp->mmio_addr;
3002
3003 if (!netif_running(dev))
1371fa6d 3004 goto out_pci_suspend;
5d06a99f
FR		 3005
3006 netif_device_detach(dev);
3007 netif_stop_queue(dev);
3008
3009 spin_lock_irq(&tp->lock);
3010
3011 rtl8169_asic_down(ioaddr);
3012
3013 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3014 RTL_W32(RxMissed, 0);
3015
3016 spin_unlock_irq(&tp->lock);
3017
1371fa6d 3018out_pci_suspend:
5d06a99f 3019 pci_save_state(pdev);
61a4dcc2 3020 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f 3021 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3022
5d06a99f
FR		 3023 return 0;
3024}
3025
3026static int rtl8169_resume(struct pci_dev *pdev)
3027{
3028 struct net_device *dev = pci_get_drvdata(pdev);
3029
1371fa6d
FR		 3030 pci_set_power_state(pdev, PCI_D0);
3031 pci_restore_state(pdev);
3032 pci_enable_wake(pdev, PCI_D0, 0);
3033
5d06a99f
FR		 3034 if (!netif_running(dev))
3035 goto out;
3036
3037 netif_device_attach(dev);
3038
5d06a99f
FR		 3039 rtl8169_schedule_work(dev, rtl8169_reset_task);
3040out:
3041 return 0;
3042}
3043
3044#endif /* CONFIG_PM */
3045
1da177e4
LT		 3046static struct pci_driver rtl8169_pci_driver = {
3047 .name = MODULENAME,
3048 .id_table = rtl8169_pci_tbl,
3049 .probe = rtl8169_init_one,
3050 .remove = __devexit_p(rtl8169_remove_one),
3051#ifdef CONFIG_PM
3052 .suspend = rtl8169_suspend,
3053 .resume = rtl8169_resume,
3054#endif
3055};
3056
3057static int __init
3058rtl8169_init_module(void)
3059{
29917620 3060 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3061}
3062
3063static void __exit
3064rtl8169_cleanup_module(void)
3065{
3066 pci_unregister_driver(&rtl8169_pci_driver);
3067}
3068
3069module_init(rtl8169_init_module);
3070module_exit(rtl8169_cleanup_module);
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