]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/r8169.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
r8169: Fix rtl8169_rx_interrupt()
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
1da177e4 27
99f252b0 28#include <asm/system.h>
1da177e4
LT		 29#include <asm/io.h>
30#include <asm/irq.h>
31
865c652d 32#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 33#define MODULENAME "r8169"
34#define PFX MODULENAME ": "
35
36#ifdef RTL8169_DEBUG
37#define assert(expr) \
5b0384f4
FR		 38 if (!(expr)) { \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 40 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 41 }
06fa7358
JP		 42#define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 44#else
45#define assert(expr) do {} while (0)
46#define dprintk(fmt, args...) do {} while (0)
47#endif /* RTL8169_DEBUG */
48
b57b7e5a 49#define R8169_MSG_DEFAULT \
f0e837d9 50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 51
1da177e4
LT		 52#define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54
1da177e4
LT		 55/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
56 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 57static const int multicast_filter_limit = 32;
1da177e4
LT		 58
59/* MAC address length */
60#define MAC_ADDR_LEN 6
61
9c14ceaf 62#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 63#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
64#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 66#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 67#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
68#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69
70#define R8169_REGS_SIZE 256
71#define R8169_NAPI_WEIGHT 64
72#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
73#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
74#define RX_BUF_SIZE 1536 /* Rx Buffer size */
75#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77
78#define RTL8169_TX_TIMEOUT (6*HZ)
79#define RTL8169_PHY_TIMEOUT (10*HZ)
80
ea8dbdd1 81#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
82#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 83#define RTL_EEPROM_SIG_ADDR 0x0000
84
1da177e4
LT		 85/* write/read MMIO register */
86#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89#define RTL_R8(reg) readb (ioaddr + (reg))
90#define RTL_R16(reg) readw (ioaddr + (reg))
91#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
92
93enum mac_version {
f21b75e9 94 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 95 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
96 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
97 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
98 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
99 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 100 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 101 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
102 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
103 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
104 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 105 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 106 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
107 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
108 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
109 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
110 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
111 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
112 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
113 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 114 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 115 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 116 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 117 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 118 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 119 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
120 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
121 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
1da177e4
LT		 122};
123
1da177e4
LT		 124#define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126
3c6bee1d 127static const struct {
1da177e4
LT		 128 const char *name;
129 u8 mac_version;
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131} rtl_chip_info[] = {
ba6eb6ee
FR		 132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
158 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
1da177e4
LT		 159};
160#undef _R
161
bcf0bf90
FR		 162enum cfg_version {
163 RTL_CFG_0 = 0x00,
164 RTL_CFG_1,
165 RTL_CFG_2
166};
167
07ce4064
FR		 168static void rtl_hw_start_8169(struct net_device *);
169static void rtl_hw_start_8168(struct net_device *);
170static void rtl_hw_start_8101(struct net_device *);
171
a3aa1884 172static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 179 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 180 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
181 { PCI_VENDOR_ID_LINKSYS, 0x1032,
182 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 183 { 0x0001, 0x8168,
184 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 185 {0,},
186};
187
188MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
189
190static int rx_copybreak = 200;
35317688 191static int use_dac = -1;
b57b7e5a
SH		 192static struct {
193 u32 msg_enable;
194} debug = { -1 };
1da177e4 195
07d3f51f
FR		 196enum rtl_registers {
197 MAC0 = 0, /* Ethernet hardware address. */
773d2021 198 MAC4 = 4,
07d3f51f
FR		 199 MAR0 = 8, /* Multicast filter. */
200 CounterAddrLow = 0x10,
201 CounterAddrHigh = 0x14,
202 TxDescStartAddrLow = 0x20,
203 TxDescStartAddrHigh = 0x24,
204 TxHDescStartAddrLow = 0x28,
205 TxHDescStartAddrHigh = 0x2c,
206 FLASH = 0x30,
207 ERSR = 0x36,
208 ChipCmd = 0x37,
209 TxPoll = 0x38,
210 IntrMask = 0x3c,
211 IntrStatus = 0x3e,
212 TxConfig = 0x40,
213 RxConfig = 0x44,
214 RxMissed = 0x4c,
215 Cfg9346 = 0x50,
216 Config0 = 0x51,
217 Config1 = 0x52,
218 Config2 = 0x53,
219 Config3 = 0x54,
220 Config4 = 0x55,
221 Config5 = 0x56,
222 MultiIntr = 0x5c,
223 PHYAR = 0x60,
07d3f51f
FR		 224 PHYstatus = 0x6c,
225 RxMaxSize = 0xda,
226 CPlusCmd = 0xe0,
227 IntrMitigate = 0xe2,
228 RxDescAddrLow = 0xe4,
229 RxDescAddrHigh = 0xe8,
230 EarlyTxThres = 0xec,
231 FuncEvent = 0xf0,
232 FuncEventMask = 0xf4,
233 FuncPresetState = 0xf8,
234 FuncForceEvent = 0xfc,
1da177e4
LT		 235};
236
f162a5d1
FR		 237enum rtl8110_registers {
238 TBICSR = 0x64,
239 TBI_ANAR = 0x68,
240 TBI_LPAR = 0x6a,
241};
242
243enum rtl8168_8101_registers {
244 CSIDR = 0x64,
245 CSIAR = 0x68,
246#define CSIAR_FLAG 0x80000000
247#define CSIAR_WRITE_CMD 0x80000000
248#define CSIAR_BYTE_ENABLE 0x0f
249#define CSIAR_BYTE_ENABLE_SHIFT 12
250#define CSIAR_ADDR_MASK 0x0fff
251
252 EPHYAR = 0x80,
253#define EPHYAR_FLAG 0x80000000
254#define EPHYAR_WRITE_CMD 0x80000000
255#define EPHYAR_REG_MASK 0x1f
256#define EPHYAR_REG_SHIFT 16
257#define EPHYAR_DATA_MASK 0xffff
258 DBG_REG = 0xd1,
259#define FIX_NAK_1 (1 << 4)
260#define FIX_NAK_2 (1 << 3)
daf9df6d 261 EFUSEAR = 0xdc,
262#define EFUSEAR_FLAG 0x80000000
263#define EFUSEAR_WRITE_CMD 0x80000000
264#define EFUSEAR_READ_CMD 0x00000000
265#define EFUSEAR_REG_MASK 0x03ff
266#define EFUSEAR_REG_SHIFT 8
267#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 268};
269
07d3f51f 270enum rtl_register_content {
1da177e4 271 /* InterruptStatusBits */
07d3f51f
FR		 272 SYSErr = 0x8000,
273 PCSTimeout = 0x4000,
274 SWInt = 0x0100,
275 TxDescUnavail = 0x0080,
276 RxFIFOOver = 0x0040,
277 LinkChg = 0x0020,
278 RxOverflow = 0x0010,
279 TxErr = 0x0008,
280 TxOK = 0x0004,
281 RxErr = 0x0002,
282 RxOK = 0x0001,
1da177e4
LT		 283
284 /* RxStatusDesc */
9dccf611
FR		 285 RxFOVF = (1 << 23),
286 RxRWT = (1 << 22),
287 RxRES = (1 << 21),
288 RxRUNT = (1 << 20),
289 RxCRC = (1 << 19),
1da177e4
LT		 290
291 /* ChipCmdBits */
07d3f51f
FR		 292 CmdReset = 0x10,
293 CmdRxEnb = 0x08,
294 CmdTxEnb = 0x04,
295 RxBufEmpty = 0x01,
1da177e4 296
275391a4
FR		 297 /* TXPoll register p.5 */
298 HPQ = 0x80, /* Poll cmd on the high prio queue */
299 NPQ = 0x40, /* Poll cmd on the low prio queue */
300 FSWInt = 0x01, /* Forced software interrupt */
301
1da177e4 302 /* Cfg9346Bits */
07d3f51f
FR		 303 Cfg9346_Lock = 0x00,
304 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 305
306 /* rx_mode_bits */
07d3f51f
FR		 307 AcceptErr = 0x20,
308 AcceptRunt = 0x10,
309 AcceptBroadcast = 0x08,
310 AcceptMulticast = 0x04,
311 AcceptMyPhys = 0x02,
312 AcceptAllPhys = 0x01,
1da177e4
LT		 313
314 /* RxConfigBits */
07d3f51f
FR		 315 RxCfgFIFOShift = 13,
316 RxCfgDMAShift = 8,
1da177e4
LT		 317
318 /* TxConfigBits */
319 TxInterFrameGapShift = 24,
320 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
321
5d06a99f 322 /* Config1 register p.24 */
f162a5d1
FR		 323 LEDS1 = (1 << 7),
324 LEDS0 = (1 << 6),
fbac58fc 325 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 326 Speed_down = (1 << 4),
327 MEMMAP = (1 << 3),
328 IOMAP = (1 << 2),
329 VPD = (1 << 1),
5d06a99f
FR		 330 PMEnable = (1 << 0), /* Power Management Enable */
331
6dccd16b
FR		 332 /* Config2 register p. 25 */
333 PCI_Clock_66MHz = 0x01,
334 PCI_Clock_33MHz = 0x00,
335
61a4dcc2
FR		 336 /* Config3 register p.25 */
337 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
338 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 339 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 340
5d06a99f 341 /* Config5 register p.27 */
61a4dcc2
FR		 342 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
343 MWF = (1 << 5), /* Accept Multicast wakeup frame */
344 UWF = (1 << 4), /* Accept Unicast wakeup frame */
345 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 346 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
347
1da177e4
LT		 348 /* TBICSR p.28 */
349 TBIReset = 0x80000000,
350 TBILoopback = 0x40000000,
351 TBINwEnable = 0x20000000,
352 TBINwRestart = 0x10000000,
353 TBILinkOk = 0x02000000,
354 TBINwComplete = 0x01000000,
355
356 /* CPlusCmd p.31 */
f162a5d1
FR		 357 EnableBist = (1 << 15), // 8168 8101
358 Mac_dbgo_oe = (1 << 14), // 8168 8101
359 Normal_mode = (1 << 13), // unused
360 Force_half_dup = (1 << 12), // 8168 8101
361 Force_rxflow_en = (1 << 11), // 8168 8101
362 Force_txflow_en = (1 << 10), // 8168 8101
363 Cxpl_dbg_sel = (1 << 9), // 8168 8101
364 ASF = (1 << 8), // 8168 8101
365 PktCntrDisable = (1 << 7), // 8168 8101
366 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 367 RxVlan = (1 << 6),
368 RxChkSum = (1 << 5),
369 PCIDAC = (1 << 4),
370 PCIMulRW = (1 << 3),
0e485150
FR		 371 INTT_0 = 0x0000, // 8168
372 INTT_1 = 0x0001, // 8168
373 INTT_2 = 0x0002, // 8168
374 INTT_3 = 0x0003, // 8168
1da177e4
LT		 375
376 /* rtl8169_PHYstatus */
07d3f51f
FR		 377 TBI_Enable = 0x80,
378 TxFlowCtrl = 0x40,
379 RxFlowCtrl = 0x20,
380 _1000bpsF = 0x10,
381 _100bps = 0x08,
382 _10bps = 0x04,
383 LinkStatus = 0x02,
384 FullDup = 0x01,
1da177e4 385
1da177e4 386 /* _TBICSRBit */
07d3f51f 387 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 388
389 /* DumpCounterCommand */
07d3f51f 390 CounterDump = 0x8,
1da177e4
LT		 391};
392
07d3f51f 393enum desc_status_bit {
1da177e4
LT		 394 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
395 RingEnd = (1 << 30), /* End of descriptor ring */
396 FirstFrag = (1 << 29), /* First segment of a packet */
397 LastFrag = (1 << 28), /* Final segment of a packet */
398
399 /* Tx private */
400 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
401 MSSShift = 16, /* MSS value position */
402 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
403 IPCS = (1 << 18), /* Calculate IP checksum */
404 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
405 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
406 TxVlanTag = (1 << 17), /* Add VLAN tag */
407
408 /* Rx private */
409 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
410 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
411
412#define RxProtoUDP (PID1)
413#define RxProtoTCP (PID0)
414#define RxProtoIP (PID1 | PID0)
415#define RxProtoMask RxProtoIP
416
417 IPFail = (1 << 16), /* IP checksum failed */
418 UDPFail = (1 << 15), /* UDP/IP checksum failed */
419 TCPFail = (1 << 14), /* TCP/IP checksum failed */
420 RxVlanTag = (1 << 16), /* VLAN tag available */
421};
422
423#define RsvdMask 0x3fffc000
424
425struct TxDesc {
6cccd6e7
REB		 426 __le32 opts1;
427 __le32 opts2;
428 __le64 addr;
1da177e4
LT		 429};
430
431struct RxDesc {
6cccd6e7
REB		 432 __le32 opts1;
433 __le32 opts2;
434 __le64 addr;
1da177e4
LT		 435};
436
437struct ring_info {
438 struct sk_buff *skb;
439 u32 len;
440 u8 __pad[sizeof(void *) - sizeof(u32)];
441};
442
f23e7fda 443enum features {
ccdffb9a
FR		 444 RTL_FEATURE_WOL = (1 << 0),
445 RTL_FEATURE_MSI = (1 << 1),
446 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 447};
448
355423d0
IV		 449struct rtl8169_counters {
450 __le64 tx_packets;
451 __le64 rx_packets;
452 __le64 tx_errors;
453 __le32 rx_errors;
454 __le16 rx_missed;
455 __le16 align_errors;
456 __le32 tx_one_collision;
457 __le32 tx_multi_collision;
458 __le64 rx_unicast;
459 __le64 rx_broadcast;
460 __le32 rx_multicast;
461 __le16 tx_aborted;
462 __le16 tx_underun;
463};
464
1da177e4
LT		 465struct rtl8169_private {
466 void __iomem *mmio_addr; /* memory map physical address */
467 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 468 struct net_device *dev;
bea3348e 469 struct napi_struct napi;
1da177e4 470 spinlock_t lock; /* spin lock flag */
b57b7e5a 471 u32 msg_enable;
1da177e4
LT		 472 int chipset;
473 int mac_version;
1da177e4
LT		 474 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
475 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
476 u32 dirty_rx;
477 u32 dirty_tx;
478 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
479 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
480 dma_addr_t TxPhyAddr;
481 dma_addr_t RxPhyAddr;
482 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
483 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 484 unsigned align;
1da177e4
LT		 485 unsigned rx_buf_sz;
486 struct timer_list timer;
487 u16 cp_cmd;
0e485150
FR		 488 u16 intr_event;
489 u16 napi_event;
1da177e4 490 u16 intr_mask;
1da177e4
LT		 491 int phy_1000_ctrl_reg;
492#ifdef CONFIG_R8169_VLAN
493 struct vlan_group *vlgrp;
494#endif
495 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 496 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 497 void (*phy_reset_enable)(void __iomem *);
07ce4064 498 void (*hw_start)(struct net_device *);
1da177e4
LT		 499 unsigned int (*phy_reset_pending)(void __iomem *);
500 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 501 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 502 int pcie_cap;
c4028958 503 struct delayed_work task;
f23e7fda 504 unsigned features;
ccdffb9a
FR		 505
506 struct mii_if_info mii;
355423d0 507 struct rtl8169_counters counters;
e1759441 508 u32 saved_wolopts;
1da177e4
LT		 509};
510
979b6c13 511MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 512MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 513module_param(rx_copybreak, int, 0);
1b7efd58 514MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4 515module_param(use_dac, int, 0);
35317688
RH		 516MODULE_PARM_DESC(use_dac, "Enable PCI DAC. -1 defaults on for PCI Express only."
517" Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 518module_param_named(debug, debug.msg_enable, int, 0);
519MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 520MODULE_LICENSE("GPL");
521MODULE_VERSION(RTL8169_VERSION);
522
523static int rtl8169_open(struct net_device *dev);
61357325
SH		 524static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
525 struct net_device *dev);
7d12e780 526static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 527static int rtl8169_init_ring(struct net_device *dev);
07ce4064 528static void rtl_hw_start(struct net_device *dev);
1da177e4 529static int rtl8169_close(struct net_device *dev);
07ce4064 530static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 531static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 532static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 533static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 534 void __iomem *, u32 budget);
4dcb7d33 535static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 536static void rtl8169_down(struct net_device *dev);
99f252b0 537static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 538static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 539
1da177e4 540static const unsigned int rtl8169_rx_config =
5b0384f4 541 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 542
07d3f51f 543static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 544{
545 int i;
546
a6baf3af 547 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 548
2371408c 549 for (i = 20; i > 0; i--) {
07d3f51f
FR		 550 /*
551 * Check if the RTL8169 has completed writing to the specified
552 * MII register.
553 */
5b0384f4 554 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 555 break;
2371408c 556 udelay(25);
1da177e4
LT		 557 }
558}
559
07d3f51f 560static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 561{
562 int i, value = -1;
563
a6baf3af 564 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 565
2371408c 566 for (i = 20; i > 0; i--) {
07d3f51f
FR		 567 /*
568 * Check if the RTL8169 has completed retrieving data from
569 * the specified MII register.
570 */
1da177e4 571 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 572 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 573 break;
574 }
2371408c 575 udelay(25);
1da177e4
LT		 576 }
577 return value;
578}
579
dacf8154
FR		 580static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
581{
582 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
583}
584
daf9df6d 585static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
586{
587 int val;
588
589 val = mdio_read(ioaddr, reg_addr);
590 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
591}
592
ccdffb9a
FR		 593static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
594 int val)
595{
596 struct rtl8169_private *tp = netdev_priv(dev);
597 void __iomem *ioaddr = tp->mmio_addr;
598
599 mdio_write(ioaddr, location, val);
600}
601
602static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
603{
604 struct rtl8169_private *tp = netdev_priv(dev);
605 void __iomem *ioaddr = tp->mmio_addr;
606
607 return mdio_read(ioaddr, location);
608}
609
dacf8154
FR		 610static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
611{
612 unsigned int i;
613
614 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
615 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
616
617 for (i = 0; i < 100; i++) {
618 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
619 break;
620 udelay(10);
621 }
622}
623
624static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
625{
626 u16 value = 0xffff;
627 unsigned int i;
628
629 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
630
631 for (i = 0; i < 100; i++) {
632 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
633 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
634 break;
635 }
636 udelay(10);
637 }
638
639 return value;
640}
641
642static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
643{
644 unsigned int i;
645
646 RTL_W32(CSIDR, value);
647 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
648 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
649
650 for (i = 0; i < 100; i++) {
651 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
652 break;
653 udelay(10);
654 }
655}
656
657static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
658{
659 u32 value = ~0x00;
660 unsigned int i;
661
662 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
663 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
664
665 for (i = 0; i < 100; i++) {
666 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
667 value = RTL_R32(CSIDR);
668 break;
669 }
670 udelay(10);
671 }
672
673 return value;
674}
675
daf9df6d 676static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
677{
678 u8 value = 0xff;
679 unsigned int i;
680
681 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
682
683 for (i = 0; i < 300; i++) {
684 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
685 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
686 break;
687 }
688 udelay(100);
689 }
690
691 return value;
692}
693
1da177e4
LT		 694static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
695{
696 RTL_W16(IntrMask, 0x0000);
697
698 RTL_W16(IntrStatus, 0xffff);
699}
700
701static void rtl8169_asic_down(void __iomem *ioaddr)
702{
703 RTL_W8(ChipCmd, 0x00);
704 rtl8169_irq_mask_and_ack(ioaddr);
705 RTL_R16(CPlusCmd);
706}
707
708static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
709{
710 return RTL_R32(TBICSR) & TBIReset;
711}
712
713static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
714{
64e4bfb4 715 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 716}
717
718static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
719{
720 return RTL_R32(TBICSR) & TBILinkOk;
721}
722
723static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
724{
725 return RTL_R8(PHYstatus) & LinkStatus;
726}
727
728static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
729{
730 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
731}
732
733static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
734{
735 unsigned int val;
736
9e0db8ef
FR		 737 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
738 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 739}
740
741static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 742 struct rtl8169_private *tp,
743 void __iomem *ioaddr)
1da177e4
LT		 744{
745 unsigned long flags;
746
747 spin_lock_irqsave(&tp->lock, flags);
748 if (tp->link_ok(ioaddr)) {
e1759441
RW		 749 /* This is to cancel a scheduled suspend if there's one. */
750 pm_request_resume(&tp->pci_dev->dev);
1da177e4 751 netif_carrier_on(dev);
bf82c189 752 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 753 } else {
1da177e4 754 netif_carrier_off(dev);
bf82c189 755 netif_info(tp, ifdown, dev, "link down\n");
e1759441 756 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 757 }
1da177e4
LT		 758 spin_unlock_irqrestore(&tp->lock, flags);
759}
760
e1759441
RW		 761#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
762
763static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 764{
61a4dcc2
FR		 765 void __iomem *ioaddr = tp->mmio_addr;
766 u8 options;
e1759441 767 u32 wolopts = 0;
61a4dcc2
FR		 768
769 options = RTL_R8(Config1);
770 if (!(options & PMEnable))
e1759441 771 return 0;
61a4dcc2
FR		 772
773 options = RTL_R8(Config3);
774 if (options & LinkUp)
e1759441 775 wolopts |= WAKE_PHY;
61a4dcc2 776 if (options & MagicPacket)
e1759441 777 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 778
779 options = RTL_R8(Config5);
780 if (options & UWF)
e1759441 781 wolopts |= WAKE_UCAST;
61a4dcc2 782 if (options & BWF)
e1759441 783 wolopts |= WAKE_BCAST;
61a4dcc2 784 if (options & MWF)
e1759441 785 wolopts |= WAKE_MCAST;
61a4dcc2 786
e1759441 787 return wolopts;
61a4dcc2
FR		 788}
789
e1759441 790static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 791{
792 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 793
794 spin_lock_irq(&tp->lock);
795
796 wol->supported = WAKE_ANY;
797 wol->wolopts = __rtl8169_get_wol(tp);
798
799 spin_unlock_irq(&tp->lock);
800}
801
802static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
803{
61a4dcc2 804 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 805 unsigned int i;
350f7596 806 static const struct {
61a4dcc2
FR		 807 u32 opt;
808 u16 reg;
809 u8 mask;
810 } cfg[] = {
811 { WAKE_ANY, Config1, PMEnable },
812 { WAKE_PHY, Config3, LinkUp },
813 { WAKE_MAGIC, Config3, MagicPacket },
814 { WAKE_UCAST, Config5, UWF },
815 { WAKE_BCAST, Config5, BWF },
816 { WAKE_MCAST, Config5, MWF },
817 { WAKE_ANY, Config5, LanWake }
818 };
819
61a4dcc2
FR		 820 RTL_W8(Cfg9346, Cfg9346_Unlock);
821
822 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
823 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 824 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 825 options |= cfg[i].mask;
826 RTL_W8(cfg[i].reg, options);
827 }
828
829 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 830}
831
832static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
833{
834 struct rtl8169_private *tp = netdev_priv(dev);
835
836 spin_lock_irq(&tp->lock);
61a4dcc2 837
f23e7fda
FR		 838 if (wol->wolopts)
839 tp->features |= RTL_FEATURE_WOL;
840 else
841 tp->features &= ~RTL_FEATURE_WOL;
e1759441 842 __rtl8169_set_wol(tp, wol->wolopts);
8b76ab39 843 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 844
845 spin_unlock_irq(&tp->lock);
846
847 return 0;
848}
849
1da177e4
LT		 850static void rtl8169_get_drvinfo(struct net_device *dev,
851 struct ethtool_drvinfo *info)
852{
853 struct rtl8169_private *tp = netdev_priv(dev);
854
855 strcpy(info->driver, MODULENAME);
856 strcpy(info->version, RTL8169_VERSION);
857 strcpy(info->bus_info, pci_name(tp->pci_dev));
858}
859
860static int rtl8169_get_regs_len(struct net_device *dev)
861{
862 return R8169_REGS_SIZE;
863}
864
865static int rtl8169_set_speed_tbi(struct net_device *dev,
866 u8 autoneg, u16 speed, u8 duplex)
867{
868 struct rtl8169_private *tp = netdev_priv(dev);
869 void __iomem *ioaddr = tp->mmio_addr;
870 int ret = 0;
871 u32 reg;
872
873 reg = RTL_R32(TBICSR);
874 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
875 (duplex == DUPLEX_FULL)) {
876 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
877 } else if (autoneg == AUTONEG_ENABLE)
878 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
879 else {
bf82c189
JP		 880 netif_warn(tp, link, dev,
881 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 882 ret = -EOPNOTSUPP;
883 }
884
885 return ret;
886}
887
888static int rtl8169_set_speed_xmii(struct net_device *dev,
889 u8 autoneg, u16 speed, u8 duplex)
890{
891 struct rtl8169_private *tp = netdev_priv(dev);
892 void __iomem *ioaddr = tp->mmio_addr;
3577aa1b 893 int giga_ctrl, bmcr;
1da177e4
LT		 894
895 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 896 int auto_nego;
897
898 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
64e4bfb4
FR		 899 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
900 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 901 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 902
3577aa1b 903 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
904 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 905
3577aa1b 906 /* The 8100e/8101e/8102e do Fast Ethernet only. */
907 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
908 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
909 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
910 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
911 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
912 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
913 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
914 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
915 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 916 } else {
917 netif_info(tp, link, dev,
918 "PHY does not support 1000Mbps\n");
bcf0bf90 919 }
1da177e4 920
3577aa1b 921 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
922
923 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
924 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
925 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
926 /*
927 * Wake up the PHY.
928 * Vendor specific (0x1f) and reserved (0x0e) MII
929 * registers.
930 */
931 mdio_write(ioaddr, 0x1f, 0x0000);
932 mdio_write(ioaddr, 0x0e, 0x0000);
933 }
934
935 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
936 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
937 } else {
938 giga_ctrl = 0;
939
940 if (speed == SPEED_10)
941 bmcr = 0;
942 else if (speed == SPEED_100)
943 bmcr = BMCR_SPEED100;
944 else
945 return -EINVAL;
946
947 if (duplex == DUPLEX_FULL)
948 bmcr |= BMCR_FULLDPLX;
623a1593 949
2584fbc3 950 mdio_write(ioaddr, 0x1f, 0x0000);
2584fbc3
RS		 951 }
952
1da177e4
LT		 953 tp->phy_1000_ctrl_reg = giga_ctrl;
954
3577aa1b 955 mdio_write(ioaddr, MII_BMCR, bmcr);
956
957 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
958 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
959 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
960 mdio_write(ioaddr, 0x17, 0x2138);
961 mdio_write(ioaddr, 0x0e, 0x0260);
962 } else {
963 mdio_write(ioaddr, 0x17, 0x2108);
964 mdio_write(ioaddr, 0x0e, 0x0000);
965 }
966 }
967
1da177e4
LT		 968 return 0;
969}
970
971static int rtl8169_set_speed(struct net_device *dev,
972 u8 autoneg, u16 speed, u8 duplex)
973{
974 struct rtl8169_private *tp = netdev_priv(dev);
975 int ret;
976
977 ret = tp->set_speed(dev, autoneg, speed, duplex);
978
64e4bfb4 979 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 980 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
981
982 return ret;
983}
984
985static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
986{
987 struct rtl8169_private *tp = netdev_priv(dev);
988 unsigned long flags;
989 int ret;
990
991 spin_lock_irqsave(&tp->lock, flags);
992 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
993 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 994
1da177e4
LT		 995 return ret;
996}
997
998static u32 rtl8169_get_rx_csum(struct net_device *dev)
999{
1000 struct rtl8169_private *tp = netdev_priv(dev);
1001
1002 return tp->cp_cmd & RxChkSum;
1003}
1004
1005static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1006{
1007 struct rtl8169_private *tp = netdev_priv(dev);
1008 void __iomem *ioaddr = tp->mmio_addr;
1009 unsigned long flags;
1010
1011 spin_lock_irqsave(&tp->lock, flags);
1012
1013 if (data)
1014 tp->cp_cmd |= RxChkSum;
1015 else
1016 tp->cp_cmd &= ~RxChkSum;
1017
1018 RTL_W16(CPlusCmd, tp->cp_cmd);
1019 RTL_R16(CPlusCmd);
1020
1021 spin_unlock_irqrestore(&tp->lock, flags);
1022
1023 return 0;
1024}
1025
1026#ifdef CONFIG_R8169_VLAN
1027
1028static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1029 struct sk_buff *skb)
1030{
1031 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1032 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1033}
1034
1035static void rtl8169_vlan_rx_register(struct net_device *dev,
1036 struct vlan_group *grp)
1037{
1038 struct rtl8169_private *tp = netdev_priv(dev);
1039 void __iomem *ioaddr = tp->mmio_addr;
1040 unsigned long flags;
1041
1042 spin_lock_irqsave(&tp->lock, flags);
1043 tp->vlgrp = grp;
05af2142
SW		 1044 /*
1045 * Do not disable RxVlan on 8110SCd.
1046 */
1047 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1048 tp->cp_cmd |= RxVlan;
1049 else
1050 tp->cp_cmd &= ~RxVlan;
1051 RTL_W16(CPlusCmd, tp->cp_cmd);
1052 RTL_R16(CPlusCmd);
1053 spin_unlock_irqrestore(&tp->lock, flags);
1054}
1055
1da177e4 1056static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1057 struct sk_buff *skb, int polling)
1da177e4
LT		 1058{
1059 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1060 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1061 int ret;
1062
865c652d 1063 if (vlgrp && (opts2 & RxVlanTag)) {
630b943c 1064 __vlan_hwaccel_rx(skb, vlgrp, swab16(opts2 & 0xffff), polling);
1da177e4
LT		 1065 ret = 0;
1066 } else
1067 ret = -1;
1068 desc->opts2 = 0;
1069 return ret;
1070}
1071
1072#else /* !CONFIG_R8169_VLAN */
1073
1074static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1075 struct sk_buff *skb)
1076{
1077 return 0;
1078}
1079
1080static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1081 struct sk_buff *skb, int polling)
1da177e4
LT		 1082{
1083 return -1;
1084}
1085
1086#endif
1087
ccdffb9a 1088static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1089{
1090 struct rtl8169_private *tp = netdev_priv(dev);
1091 void __iomem *ioaddr = tp->mmio_addr;
1092 u32 status;
1093
1094 cmd->supported =
1095 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1096 cmd->port = PORT_FIBRE;
1097 cmd->transceiver = XCVR_INTERNAL;
1098
1099 status = RTL_R32(TBICSR);
1100 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1101 cmd->autoneg = !!(status & TBINwEnable);
1102
1103 cmd->speed = SPEED_1000;
1104 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1105
1106 return 0;
1da177e4
LT		 1107}
1108
ccdffb9a 1109static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1110{
1111 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1112
1113 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1114}
1115
1116static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1117{
1118 struct rtl8169_private *tp = netdev_priv(dev);
1119 unsigned long flags;
ccdffb9a 1120 int rc;
1da177e4
LT		 1121
1122 spin_lock_irqsave(&tp->lock, flags);
1123
ccdffb9a 1124 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1125
1126 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1127 return rc;
1da177e4
LT		 1128}
1129
1130static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1131 void *p)
1132{
5b0384f4
FR		 1133 struct rtl8169_private *tp = netdev_priv(dev);
1134 unsigned long flags;
1da177e4 1135
5b0384f4
FR		 1136 if (regs->len > R8169_REGS_SIZE)
1137 regs->len = R8169_REGS_SIZE;
1da177e4 1138
5b0384f4
FR		 1139 spin_lock_irqsave(&tp->lock, flags);
1140 memcpy_fromio(p, tp->mmio_addr, regs->len);
1141 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1142}
1143
b57b7e5a
SH		 1144static u32 rtl8169_get_msglevel(struct net_device *dev)
1145{
1146 struct rtl8169_private *tp = netdev_priv(dev);
1147
1148 return tp->msg_enable;
1149}
1150
1151static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1152{
1153 struct rtl8169_private *tp = netdev_priv(dev);
1154
1155 tp->msg_enable = value;
1156}
1157
d4a3a0fc
SH		 1158static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1159 "tx_packets",
1160 "rx_packets",
1161 "tx_errors",
1162 "rx_errors",
1163 "rx_missed",
1164 "align_errors",
1165 "tx_single_collisions",
1166 "tx_multi_collisions",
1167 "unicast",
1168 "broadcast",
1169 "multicast",
1170 "tx_aborted",
1171 "tx_underrun",
1172};
1173
b9f2c044 1174static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1175{
b9f2c044
JG		 1176 switch (sset) {
1177 case ETH_SS_STATS:
1178 return ARRAY_SIZE(rtl8169_gstrings);
1179 default:
1180 return -EOPNOTSUPP;
1181 }
d4a3a0fc
SH		 1182}
1183
355423d0 1184static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1185{
1186 struct rtl8169_private *tp = netdev_priv(dev);
1187 void __iomem *ioaddr = tp->mmio_addr;
1188 struct rtl8169_counters *counters;
1189 dma_addr_t paddr;
1190 u32 cmd;
355423d0 1191 int wait = 1000;
d4a3a0fc 1192
355423d0
IV		 1193 /*
1194 * Some chips are unable to dump tally counters when the receiver
1195 * is disabled.
1196 */
1197 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1198 return;
d4a3a0fc
SH		 1199
1200 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1201 if (!counters)
1202 return;
1203
1204 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1205 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1206 RTL_W32(CounterAddrLow, cmd);
1207 RTL_W32(CounterAddrLow, cmd | CounterDump);
1208
355423d0
IV		 1209 while (wait--) {
1210 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1211 /* copy updated counters */
1212 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1213 break;
355423d0
IV		 1214 }
1215 udelay(10);
d4a3a0fc
SH		 1216 }
1217
1218 RTL_W32(CounterAddrLow, 0);
1219 RTL_W32(CounterAddrHigh, 0);
1220
d4a3a0fc
SH		 1221 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1222}
1223
355423d0
IV		 1224static void rtl8169_get_ethtool_stats(struct net_device *dev,
1225 struct ethtool_stats *stats, u64 *data)
1226{
1227 struct rtl8169_private *tp = netdev_priv(dev);
1228
1229 ASSERT_RTNL();
1230
1231 rtl8169_update_counters(dev);
1232
1233 data[0] = le64_to_cpu(tp->counters.tx_packets);
1234 data[1] = le64_to_cpu(tp->counters.rx_packets);
1235 data[2] = le64_to_cpu(tp->counters.tx_errors);
1236 data[3] = le32_to_cpu(tp->counters.rx_errors);
1237 data[4] = le16_to_cpu(tp->counters.rx_missed);
1238 data[5] = le16_to_cpu(tp->counters.align_errors);
1239 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1240 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1241 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1242 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1243 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1244 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1245 data[12] = le16_to_cpu(tp->counters.tx_underun);
1246}
1247
d4a3a0fc
SH		 1248static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1249{
1250 switch(stringset) {
1251 case ETH_SS_STATS:
1252 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1253 break;
1254 }
1255}
1256
7282d491 1257static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1258 .get_drvinfo = rtl8169_get_drvinfo,
1259 .get_regs_len = rtl8169_get_regs_len,
1260 .get_link = ethtool_op_get_link,
1261 .get_settings = rtl8169_get_settings,
1262 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1263 .get_msglevel = rtl8169_get_msglevel,
1264 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1265 .get_rx_csum = rtl8169_get_rx_csum,
1266 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1267 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1268 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1269 .set_tso = ethtool_op_set_tso,
1270 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1271 .get_wol = rtl8169_get_wol,
1272 .set_wol = rtl8169_set_wol,
d4a3a0fc 1273 .get_strings = rtl8169_get_strings,
b9f2c044 1274 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1275 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1276};
1277
07d3f51f
FR		 1278static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1279 void __iomem *ioaddr)
1da177e4 1280{
0e485150
FR		 1281 /*
1282 * The driver currently handles the 8168Bf and the 8168Be identically
1283 * but they can be identified more specifically through the test below
1284 * if needed:
1285 *
1286 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1287 *
1288 * Same thing for the 8101Eb and the 8101Ec:
1289 *
1290 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1291 */
350f7596 1292 static const struct {
1da177e4 1293 u32 mask;
e3cf0cc0 1294 u32 val;
1da177e4
LT		 1295 int mac_version;
1296 } mac_info[] = {
5b538df9 1297 /* 8168D family. */
daf9df6d 1298 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1299 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1300 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1301 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1302
ef808d50 1303 /* 8168C family. */
7f3e3d3a 1304 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1305 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1306 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1307 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1308 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1309 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1310 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1311 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1312 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1313
1314 /* 8168B family. */
1315 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1316 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1317 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1318 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1319
1320 /* 8101 family. */
2857ffb7
FR		 1321 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1322 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1323 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1324 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1325 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1326 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1327 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1328 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1329 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1330 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1331 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1332 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1333 /* FIXME: where did these entries come from ? -- FR */
1334 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1335 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1336
1337 /* 8110 family. */
1338 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1339 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1340 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1341 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1342 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1343 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1344
f21b75e9
JD		 1345 /* Catch-all */
1346 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1347 }, *p = mac_info;
1348 u32 reg;
1349
e3cf0cc0
FR		 1350 reg = RTL_R32(TxConfig);
1351 while ((reg & p->mask) != p->val)
1da177e4
LT		 1352 p++;
1353 tp->mac_version = p->mac_version;
1354}
1355
1356static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1357{
bcf0bf90 1358 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1359}
1360
867763c1
FR		 1361struct phy_reg {
1362 u16 reg;
1363 u16 val;
1364};
1365
350f7596 1366static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
867763c1
FR		 1367{
1368 while (len-- > 0) {
1369 mdio_write(ioaddr, regs->reg, regs->val);
1370 regs++;
1371 }
1372}
1373
5615d9f1 1374static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1375{
350f7596 1376 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1377 { 0x1f, 0x0001 },
1378 { 0x06, 0x006e },
1379 { 0x08, 0x0708 },
1380 { 0x15, 0x4000 },
1381 { 0x18, 0x65c7 },
1da177e4 1382
0b9b571d 1383 { 0x1f, 0x0001 },
1384 { 0x03, 0x00a1 },
1385 { 0x02, 0x0008 },
1386 { 0x01, 0x0120 },
1387 { 0x00, 0x1000 },
1388 { 0x04, 0x0800 },
1389 { 0x04, 0x0000 },
1da177e4 1390
0b9b571d 1391 { 0x03, 0xff41 },
1392 { 0x02, 0xdf60 },
1393 { 0x01, 0x0140 },
1394 { 0x00, 0x0077 },
1395 { 0x04, 0x7800 },
1396 { 0x04, 0x7000 },
1397
1398 { 0x03, 0x802f },
1399 { 0x02, 0x4f02 },
1400 { 0x01, 0x0409 },
1401 { 0x00, 0xf0f9 },
1402 { 0x04, 0x9800 },
1403 { 0x04, 0x9000 },
1404
1405 { 0x03, 0xdf01 },
1406 { 0x02, 0xdf20 },
1407 { 0x01, 0xff95 },
1408 { 0x00, 0xba00 },
1409 { 0x04, 0xa800 },
1410 { 0x04, 0xa000 },
1411
1412 { 0x03, 0xff41 },
1413 { 0x02, 0xdf20 },
1414 { 0x01, 0x0140 },
1415 { 0x00, 0x00bb },
1416 { 0x04, 0xb800 },
1417 { 0x04, 0xb000 },
1418
1419 { 0x03, 0xdf41 },
1420 { 0x02, 0xdc60 },
1421 { 0x01, 0x6340 },
1422 { 0x00, 0x007d },
1423 { 0x04, 0xd800 },
1424 { 0x04, 0xd000 },
1425
1426 { 0x03, 0xdf01 },
1427 { 0x02, 0xdf20 },
1428 { 0x01, 0x100a },
1429 { 0x00, 0xa0ff },
1430 { 0x04, 0xf800 },
1431 { 0x04, 0xf000 },
1432
1433 { 0x1f, 0x0000 },
1434 { 0x0b, 0x0000 },
1435 { 0x00, 0x9200 }
1436 };
1da177e4 1437
0b9b571d 1438 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1439}
1440
5615d9f1
FR		 1441static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1442{
350f7596 1443 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1444 { 0x1f, 0x0002 },
1445 { 0x01, 0x90d0 },
1446 { 0x1f, 0x0000 }
1447 };
1448
1449 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1450}
1451
2e955856 1452static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1453 void __iomem *ioaddr)
1454{
1455 struct pci_dev *pdev = tp->pci_dev;
1456 u16 vendor_id, device_id;
1457
1458 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1459 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1460
1461 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1462 return;
1463
1464 mdio_write(ioaddr, 0x1f, 0x0001);
1465 mdio_write(ioaddr, 0x10, 0xf01b);
1466 mdio_write(ioaddr, 0x1f, 0x0000);
1467}
1468
1469static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1470 void __iomem *ioaddr)
1471{
350f7596 1472 static const struct phy_reg phy_reg_init[] = {
2e955856 1473 { 0x1f, 0x0001 },
1474 { 0x04, 0x0000 },
1475 { 0x03, 0x00a1 },
1476 { 0x02, 0x0008 },
1477 { 0x01, 0x0120 },
1478 { 0x00, 0x1000 },
1479 { 0x04, 0x0800 },
1480 { 0x04, 0x9000 },
1481 { 0x03, 0x802f },
1482 { 0x02, 0x4f02 },
1483 { 0x01, 0x0409 },
1484 { 0x00, 0xf099 },
1485 { 0x04, 0x9800 },
1486 { 0x04, 0xa000 },
1487 { 0x03, 0xdf01 },
1488 { 0x02, 0xdf20 },
1489 { 0x01, 0xff95 },
1490 { 0x00, 0xba00 },
1491 { 0x04, 0xa800 },
1492 { 0x04, 0xf000 },
1493 { 0x03, 0xdf01 },
1494 { 0x02, 0xdf20 },
1495 { 0x01, 0x101a },
1496 { 0x00, 0xa0ff },
1497 { 0x04, 0xf800 },
1498 { 0x04, 0x0000 },
1499 { 0x1f, 0x0000 },
1500
1501 { 0x1f, 0x0001 },
1502 { 0x10, 0xf41b },
1503 { 0x14, 0xfb54 },
1504 { 0x18, 0xf5c7 },
1505 { 0x1f, 0x0000 },
1506
1507 { 0x1f, 0x0001 },
1508 { 0x17, 0x0cc0 },
1509 { 0x1f, 0x0000 }
1510 };
1511
1512 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1513
1514 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1515}
1516
8c7006aa 1517static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1518{
350f7596 1519 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1520 { 0x1f, 0x0001 },
1521 { 0x04, 0x0000 },
1522 { 0x03, 0x00a1 },
1523 { 0x02, 0x0008 },
1524 { 0x01, 0x0120 },
1525 { 0x00, 0x1000 },
1526 { 0x04, 0x0800 },
1527 { 0x04, 0x9000 },
1528 { 0x03, 0x802f },
1529 { 0x02, 0x4f02 },
1530 { 0x01, 0x0409 },
1531 { 0x00, 0xf099 },
1532 { 0x04, 0x9800 },
1533 { 0x04, 0xa000 },
1534 { 0x03, 0xdf01 },
1535 { 0x02, 0xdf20 },
1536 { 0x01, 0xff95 },
1537 { 0x00, 0xba00 },
1538 { 0x04, 0xa800 },
1539 { 0x04, 0xf000 },
1540 { 0x03, 0xdf01 },
1541 { 0x02, 0xdf20 },
1542 { 0x01, 0x101a },
1543 { 0x00, 0xa0ff },
1544 { 0x04, 0xf800 },
1545 { 0x04, 0x0000 },
1546 { 0x1f, 0x0000 },
1547
1548 { 0x1f, 0x0001 },
1549 { 0x0b, 0x8480 },
1550 { 0x1f, 0x0000 },
1551
1552 { 0x1f, 0x0001 },
1553 { 0x18, 0x67c7 },
1554 { 0x04, 0x2000 },
1555 { 0x03, 0x002f },
1556 { 0x02, 0x4360 },
1557 { 0x01, 0x0109 },
1558 { 0x00, 0x3022 },
1559 { 0x04, 0x2800 },
1560 { 0x1f, 0x0000 },
1561
1562 { 0x1f, 0x0001 },
1563 { 0x17, 0x0cc0 },
1564 { 0x1f, 0x0000 }
1565 };
1566
1567 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1568}
1569
236b8082
FR		 1570static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1571{
350f7596 1572 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1573 { 0x10, 0xf41b },
1574 { 0x1f, 0x0000 }
1575 };
1576
1577 mdio_write(ioaddr, 0x1f, 0x0001);
1578 mdio_patch(ioaddr, 0x16, 1 << 0);
1579
1580 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1581}
1582
1583static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1584{
350f7596 1585 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1586 { 0x1f, 0x0001 },
1587 { 0x10, 0xf41b },
1588 { 0x1f, 0x0000 }
1589 };
1590
1591 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1592}
1593
ef3386f0 1594static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1595{
350f7596 1596 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1597 { 0x1f, 0x0000 },
1598 { 0x1d, 0x0f00 },
1599 { 0x1f, 0x0002 },
1600 { 0x0c, 0x1ec8 },
1601 { 0x1f, 0x0000 }
1602 };
1603
1604 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1605}
1606
ef3386f0
FR		 1607static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1608{
350f7596 1609 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 1610 { 0x1f, 0x0001 },
1611 { 0x1d, 0x3d98 },
1612 { 0x1f, 0x0000 }
1613 };
1614
1615 mdio_write(ioaddr, 0x1f, 0x0000);
1616 mdio_patch(ioaddr, 0x14, 1 << 5);
1617 mdio_patch(ioaddr, 0x0d, 1 << 5);
1618
1619 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1620}
1621
219a1e9d 1622static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1 1623{
350f7596 1624 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1625 { 0x1f, 0x0001 },
1626 { 0x12, 0x2300 },
867763c1
FR		 1627 { 0x1f, 0x0002 },
1628 { 0x00, 0x88d4 },
1629 { 0x01, 0x82b1 },
1630 { 0x03, 0x7002 },
1631 { 0x08, 0x9e30 },
1632 { 0x09, 0x01f0 },
1633 { 0x0a, 0x5500 },
1634 { 0x0c, 0x00c8 },
1635 { 0x1f, 0x0003 },
1636 { 0x12, 0xc096 },
1637 { 0x16, 0x000a },
f50d4275
FR		 1638 { 0x1f, 0x0000 },
1639 { 0x1f, 0x0000 },
1640 { 0x09, 0x2000 },
1641 { 0x09, 0x0000 }
867763c1
FR		 1642 };
1643
1644 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1645
1646 mdio_patch(ioaddr, 0x14, 1 << 5);
1647 mdio_patch(ioaddr, 0x0d, 1 << 5);
1648 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1649}
1650
219a1e9d 1651static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9 1652{
350f7596 1653 static const struct phy_reg phy_reg_init[] = {
f50d4275 1654 { 0x1f, 0x0001 },
7da97ec9 1655 { 0x12, 0x2300 },
f50d4275
FR		 1656 { 0x03, 0x802f },
1657 { 0x02, 0x4f02 },
1658 { 0x01, 0x0409 },
1659 { 0x00, 0xf099 },
1660 { 0x04, 0x9800 },
1661 { 0x04, 0x9000 },
1662 { 0x1d, 0x3d98 },
7da97ec9
FR		 1663 { 0x1f, 0x0002 },
1664 { 0x0c, 0x7eb8 },
f50d4275
FR		 1665 { 0x06, 0x0761 },
1666 { 0x1f, 0x0003 },
1667 { 0x16, 0x0f0a },
7da97ec9
FR		 1668 { 0x1f, 0x0000 }
1669 };
1670
1671 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1672
1673 mdio_patch(ioaddr, 0x16, 1 << 0);
1674 mdio_patch(ioaddr, 0x14, 1 << 5);
1675 mdio_patch(ioaddr, 0x0d, 1 << 5);
1676 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1677}
1678
197ff761
FR		 1679static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1680{
350f7596 1681 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 1682 { 0x1f, 0x0001 },
1683 { 0x12, 0x2300 },
1684 { 0x1d, 0x3d98 },
1685 { 0x1f, 0x0002 },
1686 { 0x0c, 0x7eb8 },
1687 { 0x06, 0x5461 },
1688 { 0x1f, 0x0003 },
1689 { 0x16, 0x0f0a },
1690 { 0x1f, 0x0000 }
1691 };
1692
1693 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1694
1695 mdio_patch(ioaddr, 0x16, 1 << 0);
1696 mdio_patch(ioaddr, 0x14, 1 << 5);
1697 mdio_patch(ioaddr, 0x0d, 1 << 5);
1698 mdio_write(ioaddr, 0x1f, 0x0000);
1699}
1700
6fb07058
FR		 1701static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1702{
1703 rtl8168c_3_hw_phy_config(ioaddr);
1704}
1705
daf9df6d 1706static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
5b538df9 1707{
350f7596 1708 static const struct phy_reg phy_reg_init_0[] = {
5b538df9 1709 { 0x1f, 0x0001 },
daf9df6d 1710 { 0x06, 0x4064 },
1711 { 0x07, 0x2863 },
1712 { 0x08, 0x059c },
1713 { 0x09, 0x26b4 },
1714 { 0x0a, 0x6a19 },
1715 { 0x0b, 0xdcc8 },
1716 { 0x10, 0xf06d },
1717 { 0x14, 0x7f68 },
1718 { 0x18, 0x7fd9 },
1719 { 0x1c, 0xf0ff },
1720 { 0x1d, 0x3d9c },
5b538df9 1721 { 0x1f, 0x0003 },
daf9df6d 1722 { 0x12, 0xf49f },
1723 { 0x13, 0x070b },
1724 { 0x1a, 0x05ad },
1725 { 0x14, 0x94c0 }
1726 };
350f7596 1727 static const struct phy_reg phy_reg_init_1[] = {
5b538df9 1728 { 0x1f, 0x0002 },
daf9df6d 1729 { 0x06, 0x5561 },
1730 { 0x1f, 0x0005 },
1731 { 0x05, 0x8332 },
1732 { 0x06, 0x5561 }
1733 };
350f7596 1734 static const struct phy_reg phy_reg_init_2[] = {
daf9df6d 1735 { 0x1f, 0x0005 },
1736 { 0x05, 0xffc2 },
1737 { 0x1f, 0x0005 },
1738 { 0x05, 0x8000 },
1739 { 0x06, 0xf8f9 },
1740 { 0x06, 0xfaef },
1741 { 0x06, 0x59ee },
1742 { 0x06, 0xf8ea },
1743 { 0x06, 0x00ee },
1744 { 0x06, 0xf8eb },
1745 { 0x06, 0x00e0 },
1746 { 0x06, 0xf87c },
1747 { 0x06, 0xe1f8 },
1748 { 0x06, 0x7d59 },
1749 { 0x06, 0x0fef },
1750 { 0x06, 0x0139 },
1751 { 0x06, 0x029e },
1752 { 0x06, 0x06ef },
1753 { 0x06, 0x1039 },
1754 { 0x06, 0x089f },
1755 { 0x06, 0x2aee },
1756 { 0x06, 0xf8ea },
1757 { 0x06, 0x00ee },
1758 { 0x06, 0xf8eb },
1759 { 0x06, 0x01e0 },
1760 { 0x06, 0xf87c },
1761 { 0x06, 0xe1f8 },
1762 { 0x06, 0x7d58 },
1763 { 0x06, 0x409e },
1764 { 0x06, 0x0f39 },
1765 { 0x06, 0x46aa },
1766 { 0x06, 0x0bbf },
1767 { 0x06, 0x8290 },
1768 { 0x06, 0xd682 },
1769 { 0x06, 0x9802 },
1770 { 0x06, 0x014f },
1771 { 0x06, 0xae09 },
1772 { 0x06, 0xbf82 },
1773 { 0x06, 0x98d6 },
1774 { 0x06, 0x82a0 },
1775 { 0x06, 0x0201 },
1776 { 0x06, 0x4fef },
1777 { 0x06, 0x95fe },
1778 { 0x06, 0xfdfc },
1779 { 0x06, 0x05f8 },
1780 { 0x06, 0xf9fa },
1781 { 0x06, 0xeef8 },
1782 { 0x06, 0xea00 },
1783 { 0x06, 0xeef8 },
1784 { 0x06, 0xeb00 },
1785 { 0x06, 0xe2f8 },
1786 { 0x06, 0x7ce3 },
1787 { 0x06, 0xf87d },
1788 { 0x06, 0xa511 },
1789 { 0x06, 0x1112 },
1790 { 0x06, 0xd240 },
1791 { 0x06, 0xd644 },
1792 { 0x06, 0x4402 },
1793 { 0x06, 0x8217 },
1794 { 0x06, 0xd2a0 },
1795 { 0x06, 0xd6aa },
1796 { 0x06, 0xaa02 },
1797 { 0x06, 0x8217 },
1798 { 0x06, 0xae0f },
1799 { 0x06, 0xa544 },
1800 { 0x06, 0x4402 },
1801 { 0x06, 0xae4d },
1802 { 0x06, 0xa5aa },
1803 { 0x06, 0xaa02 },
1804 { 0x06, 0xae47 },
1805 { 0x06, 0xaf82 },
1806 { 0x06, 0x13ee },
1807 { 0x06, 0x834e },
1808 { 0x06, 0x00ee },
1809 { 0x06, 0x834d },
1810 { 0x06, 0x0fee },
1811 { 0x06, 0x834c },
1812 { 0x06, 0x0fee },
1813 { 0x06, 0x834f },
1814 { 0x06, 0x00ee },
1815 { 0x06, 0x8351 },
1816 { 0x06, 0x00ee },
1817 { 0x06, 0x834a },
1818 { 0x06, 0xffee },
1819 { 0x06, 0x834b },
1820 { 0x06, 0xffe0 },
1821 { 0x06, 0x8330 },
1822 { 0x06, 0xe183 },
1823 { 0x06, 0x3158 },
1824 { 0x06, 0xfee4 },
1825 { 0x06, 0xf88a },
1826 { 0x06, 0xe5f8 },
1827 { 0x06, 0x8be0 },
1828 { 0x06, 0x8332 },
1829 { 0x06, 0xe183 },
1830 { 0x06, 0x3359 },
1831 { 0x06, 0x0fe2 },
1832 { 0x06, 0x834d },
1833 { 0x06, 0x0c24 },
1834 { 0x06, 0x5af0 },
1835 { 0x06, 0x1e12 },
1836 { 0x06, 0xe4f8 },
1837 { 0x06, 0x8ce5 },
1838 { 0x06, 0xf88d },
1839 { 0x06, 0xaf82 },
1840 { 0x06, 0x13e0 },
1841 { 0x06, 0x834f },
1842 { 0x06, 0x10e4 },
1843 { 0x06, 0x834f },
1844 { 0x06, 0xe083 },
1845 { 0x06, 0x4e78 },
1846 { 0x06, 0x009f },
1847 { 0x06, 0x0ae0 },
1848 { 0x06, 0x834f },
1849 { 0x06, 0xa010 },
1850 { 0x06, 0xa5ee },
1851 { 0x06, 0x834e },
1852 { 0x06, 0x01e0 },
1853 { 0x06, 0x834e },
1854 { 0x06, 0x7805 },
1855 { 0x06, 0x9e9a },
1856 { 0x06, 0xe083 },
1857 { 0x06, 0x4e78 },
1858 { 0x06, 0x049e },
1859 { 0x06, 0x10e0 },
1860 { 0x06, 0x834e },
1861 { 0x06, 0x7803 },
1862 { 0x06, 0x9e0f },
1863 { 0x06, 0xe083 },
1864 { 0x06, 0x4e78 },
1865 { 0x06, 0x019e },
1866 { 0x06, 0x05ae },
1867 { 0x06, 0x0caf },
1868 { 0x06, 0x81f8 },
1869 { 0x06, 0xaf81 },
1870 { 0x06, 0xa3af },
1871 { 0x06, 0x81dc },
1872 { 0x06, 0xaf82 },
1873 { 0x06, 0x13ee },
1874 { 0x06, 0x8348 },
1875 { 0x06, 0x00ee },
1876 { 0x06, 0x8349 },
1877 { 0x06, 0x00e0 },
1878 { 0x06, 0x8351 },
1879 { 0x06, 0x10e4 },
1880 { 0x06, 0x8351 },
1881 { 0x06, 0x5801 },
1882 { 0x06, 0x9fea },
1883 { 0x06, 0xd000 },
1884 { 0x06, 0xd180 },
1885 { 0x06, 0x1f66 },
1886 { 0x06, 0xe2f8 },
1887 { 0x06, 0xeae3 },
1888 { 0x06, 0xf8eb },
1889 { 0x06, 0x5af8 },
1890 { 0x06, 0x1e20 },
1891 { 0x06, 0xe6f8 },
1892 { 0x06, 0xeae5 },
1893 { 0x06, 0xf8eb },
1894 { 0x06, 0xd302 },
1895 { 0x06, 0xb3fe },
1896 { 0x06, 0xe2f8 },
1897 { 0x06, 0x7cef },
1898 { 0x06, 0x325b },
1899 { 0x06, 0x80e3 },
1900 { 0x06, 0xf87d },
1901 { 0x06, 0x9e03 },
1902 { 0x06, 0x7dff },
1903 { 0x06, 0xff0d },
1904 { 0x06, 0x581c },
1905 { 0x06, 0x551a },
1906 { 0x06, 0x6511 },
1907 { 0x06, 0xa190 },
1908 { 0x06, 0xd3e2 },
1909 { 0x06, 0x8348 },
1910 { 0x06, 0xe383 },
1911 { 0x06, 0x491b },
1912 { 0x06, 0x56ab },
1913 { 0x06, 0x08ef },
1914 { 0x06, 0x56e6 },
1915 { 0x06, 0x8348 },
1916 { 0x06, 0xe783 },
1917 { 0x06, 0x4910 },
1918 { 0x06, 0xd180 },
1919 { 0x06, 0x1f66 },
1920 { 0x06, 0xa004 },
1921 { 0x06, 0xb9e2 },
1922 { 0x06, 0x8348 },
1923 { 0x06, 0xe383 },
1924 { 0x06, 0x49ef },
1925 { 0x06, 0x65e2 },
1926 { 0x06, 0x834a },
1927 { 0x06, 0xe383 },
1928 { 0x06, 0x4b1b },
1929 { 0x06, 0x56aa },
1930 { 0x06, 0x0eef },
1931 { 0x06, 0x56e6 },
1932 { 0x06, 0x834a },
1933 { 0x06, 0xe783 },
1934 { 0x06, 0x4be2 },
1935 { 0x06, 0x834d },
1936 { 0x06, 0xe683 },
1937 { 0x06, 0x4ce0 },
1938 { 0x06, 0x834d },
1939 { 0x06, 0xa000 },
1940 { 0x06, 0x0caf },
1941 { 0x06, 0x81dc },
1942 { 0x06, 0xe083 },
1943 { 0x06, 0x4d10 },
1944 { 0x06, 0xe483 },
1945 { 0x06, 0x4dae },
1946 { 0x06, 0x0480 },
1947 { 0x06, 0xe483 },
1948 { 0x06, 0x4de0 },
1949 { 0x06, 0x834e },
1950 { 0x06, 0x7803 },
1951 { 0x06, 0x9e0b },
1952 { 0x06, 0xe083 },
1953 { 0x06, 0x4e78 },
1954 { 0x06, 0x049e },
1955 { 0x06, 0x04ee },
1956 { 0x06, 0x834e },
1957 { 0x06, 0x02e0 },
1958 { 0x06, 0x8332 },
1959 { 0x06, 0xe183 },
1960 { 0x06, 0x3359 },
1961 { 0x06, 0x0fe2 },
1962 { 0x06, 0x834d },
1963 { 0x06, 0x0c24 },
1964 { 0x06, 0x5af0 },
1965 { 0x06, 0x1e12 },
1966 { 0x06, 0xe4f8 },
1967 { 0x06, 0x8ce5 },
1968 { 0x06, 0xf88d },
1969 { 0x06, 0xe083 },
1970 { 0x06, 0x30e1 },
1971 { 0x06, 0x8331 },
1972 { 0x06, 0x6801 },
1973 { 0x06, 0xe4f8 },
1974 { 0x06, 0x8ae5 },
1975 { 0x06, 0xf88b },
1976 { 0x06, 0xae37 },
1977 { 0x06, 0xee83 },
1978 { 0x06, 0x4e03 },
1979 { 0x06, 0xe083 },
1980 { 0x06, 0x4ce1 },
1981 { 0x06, 0x834d },
1982 { 0x06, 0x1b01 },
1983 { 0x06, 0x9e04 },
1984 { 0x06, 0xaaa1 },
1985 { 0x06, 0xaea8 },
1986 { 0x06, 0xee83 },
1987 { 0x06, 0x4e04 },
1988 { 0x06, 0xee83 },
1989 { 0x06, 0x4f00 },
1990 { 0x06, 0xaeab },
1991 { 0x06, 0xe083 },
1992 { 0x06, 0x4f78 },
1993 { 0x06, 0x039f },
1994 { 0x06, 0x14ee },
1995 { 0x06, 0x834e },
1996 { 0x06, 0x05d2 },
1997 { 0x06, 0x40d6 },
1998 { 0x06, 0x5554 },
1999 { 0x06, 0x0282 },
2000 { 0x06, 0x17d2 },
2001 { 0x06, 0xa0d6 },
2002 { 0x06, 0xba00 },
2003 { 0x06, 0x0282 },
2004 { 0x06, 0x17fe },
2005 { 0x06, 0xfdfc },
2006 { 0x06, 0x05f8 },
2007 { 0x06, 0xe0f8 },
2008 { 0x06, 0x60e1 },
2009 { 0x06, 0xf861 },
2010 { 0x06, 0x6802 },
2011 { 0x06, 0xe4f8 },
2012 { 0x06, 0x60e5 },
2013 { 0x06, 0xf861 },
2014 { 0x06, 0xe0f8 },
2015 { 0x06, 0x48e1 },
2016 { 0x06, 0xf849 },
2017 { 0x06, 0x580f },
2018 { 0x06, 0x1e02 },
2019 { 0x06, 0xe4f8 },
2020 { 0x06, 0x48e5 },
2021 { 0x06, 0xf849 },
2022 { 0x06, 0xd000 },
2023 { 0x06, 0x0282 },
2024 { 0x06, 0x5bbf },
2025 { 0x06, 0x8350 },
2026 { 0x06, 0xef46 },
2027 { 0x06, 0xdc19 },
2028 { 0x06, 0xddd0 },
2029 { 0x06, 0x0102 },
2030 { 0x06, 0x825b },
2031 { 0x06, 0x0282 },
2032 { 0x06, 0x77e0 },
2033 { 0x06, 0xf860 },
2034 { 0x06, 0xe1f8 },
2035 { 0x06, 0x6158 },
2036 { 0x06, 0xfde4 },
2037 { 0x06, 0xf860 },
2038 { 0x06, 0xe5f8 },
2039 { 0x06, 0x61fc },
2040 { 0x06, 0x04f9 },
2041 { 0x06, 0xfafb },
2042 { 0x06, 0xc6bf },
2043 { 0x06, 0xf840 },
2044 { 0x06, 0xbe83 },
2045 { 0x06, 0x50a0 },
2046 { 0x06, 0x0101 },
2047 { 0x06, 0x071b },
2048 { 0x06, 0x89cf },
2049 { 0x06, 0xd208 },
2050 { 0x06, 0xebdb },
2051 { 0x06, 0x19b2 },
2052 { 0x06, 0xfbff },
2053 { 0x06, 0xfefd },
2054 { 0x06, 0x04f8 },
2055 { 0x06, 0xe0f8 },
2056 { 0x06, 0x48e1 },
2057 { 0x06, 0xf849 },
2058 { 0x06, 0x6808 },
2059 { 0x06, 0xe4f8 },
2060 { 0x06, 0x48e5 },
2061 { 0x06, 0xf849 },
2062 { 0x06, 0x58f7 },
2063 { 0x06, 0xe4f8 },
2064 { 0x06, 0x48e5 },
2065 { 0x06, 0xf849 },
2066 { 0x06, 0xfc04 },
2067 { 0x06, 0x4d20 },
2068 { 0x06, 0x0002 },
2069 { 0x06, 0x4e22 },
2070 { 0x06, 0x0002 },
2071 { 0x06, 0x4ddf },
2072 { 0x06, 0xff01 },
2073 { 0x06, 0x4edd },
2074 { 0x06, 0xff01 },
2075 { 0x05, 0x83d4 },
2076 { 0x06, 0x8000 },
2077 { 0x05, 0x83d8 },
2078 { 0x06, 0x8051 },
2079 { 0x02, 0x6010 },
2080 { 0x03, 0xdc00 },
2081 { 0x05, 0xfff6 },
2082 { 0x06, 0x00fc },
5b538df9 2083 { 0x1f, 0x0000 },
daf9df6d 2084
5b538df9 2085 { 0x1f, 0x0000 },
daf9df6d 2086 { 0x0d, 0xf880 },
2087 { 0x1f, 0x0000 }
2088 };
2089
2090 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2091
2092 mdio_write(ioaddr, 0x1f, 0x0002);
2093 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2094 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2095
2096 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2097
2098 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2099 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2100 { 0x1f, 0x0002 },
2101 { 0x05, 0x669a },
2102 { 0x1f, 0x0005 },
2103 { 0x05, 0x8330 },
2104 { 0x06, 0x669a },
2105 { 0x1f, 0x0002 }
2106 };
2107 int val;
2108
2109 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2110
2111 val = mdio_read(ioaddr, 0x0d);
2112
2113 if ((val & 0x00ff) != 0x006c) {
350f7596 2114 static const u32 set[] = {
daf9df6d 2115 0x0065, 0x0066, 0x0067, 0x0068,
2116 0x0069, 0x006a, 0x006b, 0x006c
2117 };
2118 int i;
2119
2120 mdio_write(ioaddr, 0x1f, 0x0002);
2121
2122 val &= 0xff00;
2123 for (i = 0; i < ARRAY_SIZE(set); i++)
2124 mdio_write(ioaddr, 0x0d, val | set[i]);
2125 }
2126 } else {
350f7596 2127 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2128 { 0x1f, 0x0002 },
2129 { 0x05, 0x6662 },
2130 { 0x1f, 0x0005 },
2131 { 0x05, 0x8330 },
2132 { 0x06, 0x6662 }
2133 };
2134
2135 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2136 }
2137
2138 mdio_write(ioaddr, 0x1f, 0x0002);
2139 mdio_patch(ioaddr, 0x0d, 0x0300);
2140 mdio_patch(ioaddr, 0x0f, 0x0010);
2141
2142 mdio_write(ioaddr, 0x1f, 0x0002);
2143 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2144 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2145
2146 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2147}
2148
2149static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2150{
350f7596 2151 static const struct phy_reg phy_reg_init_0[] = {
daf9df6d 2152 { 0x1f, 0x0001 },
2153 { 0x06, 0x4064 },
2154 { 0x07, 0x2863 },
2155 { 0x08, 0x059c },
2156 { 0x09, 0x26b4 },
2157 { 0x0a, 0x6a19 },
2158 { 0x0b, 0xdcc8 },
2159 { 0x10, 0xf06d },
2160 { 0x14, 0x7f68 },
2161 { 0x18, 0x7fd9 },
2162 { 0x1c, 0xf0ff },
2163 { 0x1d, 0x3d9c },
2164 { 0x1f, 0x0003 },
2165 { 0x12, 0xf49f },
2166 { 0x13, 0x070b },
2167 { 0x1a, 0x05ad },
2168 { 0x14, 0x94c0 },
2169
2170 { 0x1f, 0x0002 },
2171 { 0x06, 0x5561 },
2172 { 0x1f, 0x0005 },
2173 { 0x05, 0x8332 },
2174 { 0x06, 0x5561 }
2175 };
350f7596 2176 static const struct phy_reg phy_reg_init_1[] = {
daf9df6d 2177 { 0x1f, 0x0005 },
2178 { 0x05, 0xffc2 },
5b538df9 2179 { 0x1f, 0x0005 },
daf9df6d 2180 { 0x05, 0x8000 },
2181 { 0x06, 0xf8f9 },
2182 { 0x06, 0xfaee },
2183 { 0x06, 0xf8ea },
2184 { 0x06, 0x00ee },
2185 { 0x06, 0xf8eb },
2186 { 0x06, 0x00e2 },
2187 { 0x06, 0xf87c },
2188 { 0x06, 0xe3f8 },
2189 { 0x06, 0x7da5 },
2190 { 0x06, 0x1111 },
2191 { 0x06, 0x12d2 },
2192 { 0x06, 0x40d6 },
2193 { 0x06, 0x4444 },
2194 { 0x06, 0x0281 },
2195 { 0x06, 0xc6d2 },
2196 { 0x06, 0xa0d6 },
2197 { 0x06, 0xaaaa },
2198 { 0x06, 0x0281 },
2199 { 0x06, 0xc6ae },
2200 { 0x06, 0x0fa5 },
2201 { 0x06, 0x4444 },
2202 { 0x06, 0x02ae },
2203 { 0x06, 0x4da5 },
2204 { 0x06, 0xaaaa },
2205 { 0x06, 0x02ae },
2206 { 0x06, 0x47af },
2207 { 0x06, 0x81c2 },
2208 { 0x06, 0xee83 },
2209 { 0x06, 0x4e00 },
2210 { 0x06, 0xee83 },
2211 { 0x06, 0x4d0f },
2212 { 0x06, 0xee83 },
2213 { 0x06, 0x4c0f },
2214 { 0x06, 0xee83 },
2215 { 0x06, 0x4f00 },
2216 { 0x06, 0xee83 },
2217 { 0x06, 0x5100 },
2218 { 0x06, 0xee83 },
2219 { 0x06, 0x4aff },
2220 { 0x06, 0xee83 },
2221 { 0x06, 0x4bff },
2222 { 0x06, 0xe083 },
2223 { 0x06, 0x30e1 },
2224 { 0x06, 0x8331 },
2225 { 0x06, 0x58fe },
2226 { 0x06, 0xe4f8 },
2227 { 0x06, 0x8ae5 },
2228 { 0x06, 0xf88b },
2229 { 0x06, 0xe083 },
2230 { 0x06, 0x32e1 },
2231 { 0x06, 0x8333 },
2232 { 0x06, 0x590f },
2233 { 0x06, 0xe283 },
2234 { 0x06, 0x4d0c },
2235 { 0x06, 0x245a },
2236 { 0x06, 0xf01e },
2237 { 0x06, 0x12e4 },
2238 { 0x06, 0xf88c },
2239 { 0x06, 0xe5f8 },
2240 { 0x06, 0x8daf },
2241 { 0x06, 0x81c2 },
2242 { 0x06, 0xe083 },
2243 { 0x06, 0x4f10 },
2244 { 0x06, 0xe483 },
2245 { 0x06, 0x4fe0 },
2246 { 0x06, 0x834e },
2247 { 0x06, 0x7800 },
2248 { 0x06, 0x9f0a },
2249 { 0x06, 0xe083 },
2250 { 0x06, 0x4fa0 },
2251 { 0x06, 0x10a5 },
2252 { 0x06, 0xee83 },
2253 { 0x06, 0x4e01 },
2254 { 0x06, 0xe083 },
2255 { 0x06, 0x4e78 },
2256 { 0x06, 0x059e },
2257 { 0x06, 0x9ae0 },
2258 { 0x06, 0x834e },
2259 { 0x06, 0x7804 },
2260 { 0x06, 0x9e10 },
2261 { 0x06, 0xe083 },
2262 { 0x06, 0x4e78 },
2263 { 0x06, 0x039e },
2264 { 0x06, 0x0fe0 },
2265 { 0x06, 0x834e },
2266 { 0x06, 0x7801 },
2267 { 0x06, 0x9e05 },
2268 { 0x06, 0xae0c },
2269 { 0x06, 0xaf81 },
2270 { 0x06, 0xa7af },
2271 { 0x06, 0x8152 },
2272 { 0x06, 0xaf81 },
2273 { 0x06, 0x8baf },
2274 { 0x06, 0x81c2 },
2275 { 0x06, 0xee83 },
2276 { 0x06, 0x4800 },
2277 { 0x06, 0xee83 },
2278 { 0x06, 0x4900 },
2279 { 0x06, 0xe083 },
2280 { 0x06, 0x5110 },
2281 { 0x06, 0xe483 },
2282 { 0x06, 0x5158 },
2283 { 0x06, 0x019f },
2284 { 0x06, 0xead0 },
2285 { 0x06, 0x00d1 },
2286 { 0x06, 0x801f },
2287 { 0x06, 0x66e2 },
2288 { 0x06, 0xf8ea },
2289 { 0x06, 0xe3f8 },
2290 { 0x06, 0xeb5a },
2291 { 0x06, 0xf81e },
2292 { 0x06, 0x20e6 },
2293 { 0x06, 0xf8ea },
2294 { 0x06, 0xe5f8 },
2295 { 0x06, 0xebd3 },
2296 { 0x06, 0x02b3 },
2297 { 0x06, 0xfee2 },
2298 { 0x06, 0xf87c },
2299 { 0x06, 0xef32 },
2300 { 0x06, 0x5b80 },
2301 { 0x06, 0xe3f8 },
2302 { 0x06, 0x7d9e },
2303 { 0x06, 0x037d },
2304 { 0x06, 0xffff },
2305 { 0x06, 0x0d58 },
2306 { 0x06, 0x1c55 },
2307 { 0x06, 0x1a65 },
2308 { 0x06, 0x11a1 },
2309 { 0x06, 0x90d3 },
2310 { 0x06, 0xe283 },
2311 { 0x06, 0x48e3 },
2312 { 0x06, 0x8349 },
2313 { 0x06, 0x1b56 },
2314 { 0x06, 0xab08 },
2315 { 0x06, 0xef56 },
2316 { 0x06, 0xe683 },
2317 { 0x06, 0x48e7 },
2318 { 0x06, 0x8349 },
2319 { 0x06, 0x10d1 },
2320 { 0x06, 0x801f },
2321 { 0x06, 0x66a0 },
2322 { 0x06, 0x04b9 },
2323 { 0x06, 0xe283 },
2324 { 0x06, 0x48e3 },
2325 { 0x06, 0x8349 },
2326 { 0x06, 0xef65 },
2327 { 0x06, 0xe283 },
2328 { 0x06, 0x4ae3 },
2329 { 0x06, 0x834b },
2330 { 0x06, 0x1b56 },
2331 { 0x06, 0xaa0e },
2332 { 0x06, 0xef56 },
2333 { 0x06, 0xe683 },
2334 { 0x06, 0x4ae7 },
2335 { 0x06, 0x834b },
2336 { 0x06, 0xe283 },
2337 { 0x06, 0x4de6 },
2338 { 0x06, 0x834c },
2339 { 0x06, 0xe083 },
2340 { 0x06, 0x4da0 },
2341 { 0x06, 0x000c },
2342 { 0x06, 0xaf81 },
2343 { 0x06, 0x8be0 },
2344 { 0x06, 0x834d },
2345 { 0x06, 0x10e4 },
2346 { 0x06, 0x834d },
2347 { 0x06, 0xae04 },
2348 { 0x06, 0x80e4 },
2349 { 0x06, 0x834d },
2350 { 0x06, 0xe083 },
2351 { 0x06, 0x4e78 },
2352 { 0x06, 0x039e },
2353 { 0x06, 0x0be0 },
2354 { 0x06, 0x834e },
2355 { 0x06, 0x7804 },
2356 { 0x06, 0x9e04 },
2357 { 0x06, 0xee83 },
2358 { 0x06, 0x4e02 },
2359 { 0x06, 0xe083 },
2360 { 0x06, 0x32e1 },
2361 { 0x06, 0x8333 },
2362 { 0x06, 0x590f },
2363 { 0x06, 0xe283 },
2364 { 0x06, 0x4d0c },
2365 { 0x06, 0x245a },
2366 { 0x06, 0xf01e },
2367 { 0x06, 0x12e4 },
2368 { 0x06, 0xf88c },
2369 { 0x06, 0xe5f8 },
2370 { 0x06, 0x8de0 },
2371 { 0x06, 0x8330 },
2372 { 0x06, 0xe183 },
2373 { 0x06, 0x3168 },
2374 { 0x06, 0x01e4 },
2375 { 0x06, 0xf88a },
2376 { 0x06, 0xe5f8 },
2377 { 0x06, 0x8bae },
2378 { 0x06, 0x37ee },
2379 { 0x06, 0x834e },
2380 { 0x06, 0x03e0 },
2381 { 0x06, 0x834c },
2382 { 0x06, 0xe183 },
2383 { 0x06, 0x4d1b },
2384 { 0x06, 0x019e },
2385 { 0x06, 0x04aa },
2386 { 0x06, 0xa1ae },
2387 { 0x06, 0xa8ee },
2388 { 0x06, 0x834e },
2389 { 0x06, 0x04ee },
2390 { 0x06, 0x834f },
2391 { 0x06, 0x00ae },
2392 { 0x06, 0xabe0 },
2393 { 0x06, 0x834f },
2394 { 0x06, 0x7803 },
2395 { 0x06, 0x9f14 },
2396 { 0x06, 0xee83 },
2397 { 0x06, 0x4e05 },
2398 { 0x06, 0xd240 },
2399 { 0x06, 0xd655 },
2400 { 0x06, 0x5402 },
2401 { 0x06, 0x81c6 },
2402 { 0x06, 0xd2a0 },
2403 { 0x06, 0xd6ba },
2404 { 0x06, 0x0002 },
2405 { 0x06, 0x81c6 },
2406 { 0x06, 0xfefd },
2407 { 0x06, 0xfc05 },
2408 { 0x06, 0xf8e0 },
2409 { 0x06, 0xf860 },
2410 { 0x06, 0xe1f8 },
2411 { 0x06, 0x6168 },
2412 { 0x06, 0x02e4 },
2413 { 0x06, 0xf860 },
2414 { 0x06, 0xe5f8 },
2415 { 0x06, 0x61e0 },
2416 { 0x06, 0xf848 },
2417 { 0x06, 0xe1f8 },
2418 { 0x06, 0x4958 },
2419 { 0x06, 0x0f1e },
2420 { 0x06, 0x02e4 },
2421 { 0x06, 0xf848 },
2422 { 0x06, 0xe5f8 },
2423 { 0x06, 0x49d0 },
2424 { 0x06, 0x0002 },
2425 { 0x06, 0x820a },
2426 { 0x06, 0xbf83 },
2427 { 0x06, 0x50ef },
2428 { 0x06, 0x46dc },
2429 { 0x06, 0x19dd },
2430 { 0x06, 0xd001 },
2431 { 0x06, 0x0282 },
2432 { 0x06, 0x0a02 },
2433 { 0x06, 0x8226 },
2434 { 0x06, 0xe0f8 },
2435 { 0x06, 0x60e1 },
2436 { 0x06, 0xf861 },
2437 { 0x06, 0x58fd },
2438 { 0x06, 0xe4f8 },
2439 { 0x06, 0x60e5 },
2440 { 0x06, 0xf861 },
2441 { 0x06, 0xfc04 },
2442 { 0x06, 0xf9fa },
2443 { 0x06, 0xfbc6 },
2444 { 0x06, 0xbff8 },
2445 { 0x06, 0x40be },
2446 { 0x06, 0x8350 },
2447 { 0x06, 0xa001 },
2448 { 0x06, 0x0107 },
2449 { 0x06, 0x1b89 },
2450 { 0x06, 0xcfd2 },
2451 { 0x06, 0x08eb },
2452 { 0x06, 0xdb19 },
2453 { 0x06, 0xb2fb },
2454 { 0x06, 0xfffe },
2455 { 0x06, 0xfd04 },
2456 { 0x06, 0xf8e0 },
2457 { 0x06, 0xf848 },
2458 { 0x06, 0xe1f8 },
2459 { 0x06, 0x4968 },
2460 { 0x06, 0x08e4 },
2461 { 0x06, 0xf848 },
2462 { 0x06, 0xe5f8 },
2463 { 0x06, 0x4958 },
2464 { 0x06, 0xf7e4 },
2465 { 0x06, 0xf848 },
2466 { 0x06, 0xe5f8 },
2467 { 0x06, 0x49fc },
2468 { 0x06, 0x044d },
2469 { 0x06, 0x2000 },
2470 { 0x06, 0x024e },
2471 { 0x06, 0x2200 },
2472 { 0x06, 0x024d },
2473 { 0x06, 0xdfff },
2474 { 0x06, 0x014e },
2475 { 0x06, 0xddff },
2476 { 0x06, 0x0100 },
2477 { 0x05, 0x83d8 },
2478 { 0x06, 0x8000 },
2479 { 0x03, 0xdc00 },
2480 { 0x05, 0xfff6 },
2481 { 0x06, 0x00fc },
2482 { 0x1f, 0x0000 },
2483
2484 { 0x1f, 0x0000 },
2485 { 0x0d, 0xf880 },
2486 { 0x1f, 0x0000 }
5b538df9
FR		 2487 };
2488
2489 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2490
daf9df6d 2491 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2492 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2493 { 0x1f, 0x0002 },
2494 { 0x05, 0x669a },
5b538df9 2495 { 0x1f, 0x0005 },
daf9df6d 2496 { 0x05, 0x8330 },
2497 { 0x06, 0x669a },
2498
2499 { 0x1f, 0x0002 }
2500 };
2501 int val;
2502
2503 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2504
2505 val = mdio_read(ioaddr, 0x0d);
2506 if ((val & 0x00ff) != 0x006c) {
2507 u32 set[] = {
2508 0x0065, 0x0066, 0x0067, 0x0068,
2509 0x0069, 0x006a, 0x006b, 0x006c
2510 };
2511 int i;
2512
2513 mdio_write(ioaddr, 0x1f, 0x0002);
2514
2515 val &= 0xff00;
2516 for (i = 0; i < ARRAY_SIZE(set); i++)
2517 mdio_write(ioaddr, 0x0d, val | set[i]);
2518 }
2519 } else {
350f7596 2520 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2521 { 0x1f, 0x0002 },
2522 { 0x05, 0x2642 },
5b538df9 2523 { 0x1f, 0x0005 },
daf9df6d 2524 { 0x05, 0x8330 },
2525 { 0x06, 0x2642 }
5b538df9
FR		 2526 };
2527
daf9df6d 2528 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2529 }
2530
daf9df6d 2531 mdio_write(ioaddr, 0x1f, 0x0002);
2532 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2533 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2534
2535 mdio_write(ioaddr, 0x1f, 0x0001);
2536 mdio_write(ioaddr, 0x17, 0x0cc0);
2537
2538 mdio_write(ioaddr, 0x1f, 0x0002);
2539 mdio_patch(ioaddr, 0x0f, 0x0017);
2540
2541 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2542}
2543
2544static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2545{
350f7596 2546 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2547 { 0x1f, 0x0002 },
2548 { 0x10, 0x0008 },
2549 { 0x0d, 0x006c },
2550
2551 { 0x1f, 0x0000 },
2552 { 0x0d, 0xf880 },
2553
2554 { 0x1f, 0x0001 },
2555 { 0x17, 0x0cc0 },
2556
2557 { 0x1f, 0x0001 },
2558 { 0x0b, 0xa4d8 },
2559 { 0x09, 0x281c },
2560 { 0x07, 0x2883 },
2561 { 0x0a, 0x6b35 },
2562 { 0x1d, 0x3da4 },
2563 { 0x1c, 0xeffd },
2564 { 0x14, 0x7f52 },
2565 { 0x18, 0x7fc6 },
2566 { 0x08, 0x0601 },
2567 { 0x06, 0x4063 },
2568 { 0x10, 0xf074 },
2569 { 0x1f, 0x0003 },
2570 { 0x13, 0x0789 },
2571 { 0x12, 0xf4bd },
2572 { 0x1a, 0x04fd },
2573 { 0x14, 0x84b0 },
2574 { 0x1f, 0x0000 },
2575 { 0x00, 0x9200 },
2576
2577 { 0x1f, 0x0005 },
2578 { 0x01, 0x0340 },
2579 { 0x1f, 0x0001 },
2580 { 0x04, 0x4000 },
2581 { 0x03, 0x1d21 },
2582 { 0x02, 0x0c32 },
2583 { 0x01, 0x0200 },
2584 { 0x00, 0x5554 },
2585 { 0x04, 0x4800 },
2586 { 0x04, 0x4000 },
2587 { 0x04, 0xf000 },
2588 { 0x03, 0xdf01 },
2589 { 0x02, 0xdf20 },
2590 { 0x01, 0x101a },
2591 { 0x00, 0xa0ff },
2592 { 0x04, 0xf800 },
2593 { 0x04, 0xf000 },
2594 { 0x1f, 0x0000 },
2595
2596 { 0x1f, 0x0007 },
2597 { 0x1e, 0x0023 },
2598 { 0x16, 0x0000 },
2599 { 0x1f, 0x0000 }
2600 };
2601
2602 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2603}
2604
2857ffb7
FR		 2605static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2606{
350f7596 2607 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2608 { 0x1f, 0x0003 },
2609 { 0x08, 0x441d },
2610 { 0x01, 0x9100 },
2611 { 0x1f, 0x0000 }
2612 };
2613
2614 mdio_write(ioaddr, 0x1f, 0x0000);
2615 mdio_patch(ioaddr, 0x11, 1 << 12);
2616 mdio_patch(ioaddr, 0x19, 1 << 13);
85910a8e 2617 mdio_patch(ioaddr, 0x10, 1 << 15);
2857ffb7
FR		 2618
2619 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2620}
2621
5615d9f1
FR		 2622static void rtl_hw_phy_config(struct net_device *dev)
2623{
2624 struct rtl8169_private *tp = netdev_priv(dev);
2625 void __iomem *ioaddr = tp->mmio_addr;
2626
2627 rtl8169_print_mac_version(tp);
2628
2629 switch (tp->mac_version) {
2630 case RTL_GIGA_MAC_VER_01:
2631 break;
2632 case RTL_GIGA_MAC_VER_02:
2633 case RTL_GIGA_MAC_VER_03:
2634 rtl8169s_hw_phy_config(ioaddr);
2635 break;
2636 case RTL_GIGA_MAC_VER_04:
2637 rtl8169sb_hw_phy_config(ioaddr);
2638 break;
2e955856 2639 case RTL_GIGA_MAC_VER_05:
2640 rtl8169scd_hw_phy_config(tp, ioaddr);
2641 break;
8c7006aa 2642 case RTL_GIGA_MAC_VER_06:
2643 rtl8169sce_hw_phy_config(ioaddr);
2644 break;
2857ffb7
FR		 2645 case RTL_GIGA_MAC_VER_07:
2646 case RTL_GIGA_MAC_VER_08:
2647 case RTL_GIGA_MAC_VER_09:
2648 rtl8102e_hw_phy_config(ioaddr);
2649 break;
236b8082
FR		 2650 case RTL_GIGA_MAC_VER_11:
2651 rtl8168bb_hw_phy_config(ioaddr);
2652 break;
2653 case RTL_GIGA_MAC_VER_12:
2654 rtl8168bef_hw_phy_config(ioaddr);
2655 break;
2656 case RTL_GIGA_MAC_VER_17:
2657 rtl8168bef_hw_phy_config(ioaddr);
2658 break;
867763c1 2659 case RTL_GIGA_MAC_VER_18:
ef3386f0 2660 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 2661 break;
2662 case RTL_GIGA_MAC_VER_19:
219a1e9d 2663 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 2664 break;
7da97ec9 2665 case RTL_GIGA_MAC_VER_20:
219a1e9d 2666 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 2667 break;
197ff761
FR		 2668 case RTL_GIGA_MAC_VER_21:
2669 rtl8168c_3_hw_phy_config(ioaddr);
2670 break;
6fb07058
FR		 2671 case RTL_GIGA_MAC_VER_22:
2672 rtl8168c_4_hw_phy_config(ioaddr);
2673 break;
ef3386f0 2674 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2675 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 2676 rtl8168cp_2_hw_phy_config(ioaddr);
2677 break;
5b538df9 2678 case RTL_GIGA_MAC_VER_25:
daf9df6d 2679 rtl8168d_1_hw_phy_config(ioaddr);
2680 break;
2681 case RTL_GIGA_MAC_VER_26:
2682 rtl8168d_2_hw_phy_config(ioaddr);
2683 break;
2684 case RTL_GIGA_MAC_VER_27:
2685 rtl8168d_3_hw_phy_config(ioaddr);
5b538df9 2686 break;
ef3386f0 2687
5615d9f1
FR		 2688 default:
2689 break;
2690 }
2691}
2692
1da177e4
LT		 2693static void rtl8169_phy_timer(unsigned long __opaque)
2694{
2695 struct net_device *dev = (struct net_device *)__opaque;
2696 struct rtl8169_private *tp = netdev_priv(dev);
2697 struct timer_list *timer = &tp->timer;
2698 void __iomem *ioaddr = tp->mmio_addr;
2699 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2700
bcf0bf90 2701 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2702
64e4bfb4 2703 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2704 return;
2705
2706 spin_lock_irq(&tp->lock);
2707
2708 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 2709 /*
1da177e4
LT		 2710 * A busy loop could burn quite a few cycles on nowadays CPU.
2711 * Let's delay the execution of the timer for a few ticks.
2712 */
2713 timeout = HZ/10;
2714 goto out_mod_timer;
2715 }
2716
2717 if (tp->link_ok(ioaddr))
2718 goto out_unlock;
2719
bf82c189 2720 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4
LT		 2721
2722 tp->phy_reset_enable(ioaddr);
2723
2724out_mod_timer:
2725 mod_timer(timer, jiffies + timeout);
2726out_unlock:
2727 spin_unlock_irq(&tp->lock);
2728}
2729
2730static inline void rtl8169_delete_timer(struct net_device *dev)
2731{
2732 struct rtl8169_private *tp = netdev_priv(dev);
2733 struct timer_list *timer = &tp->timer;
2734
e179bb7b 2735 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2736 return;
2737
2738 del_timer_sync(timer);
2739}
2740
2741static inline void rtl8169_request_timer(struct net_device *dev)
2742{
2743 struct rtl8169_private *tp = netdev_priv(dev);
2744 struct timer_list *timer = &tp->timer;
2745
e179bb7b 2746 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2747 return;
2748
2efa53f3 2749 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2750}
2751
2752#ifdef CONFIG_NET_POLL_CONTROLLER
2753/*
2754 * Polling 'interrupt' - used by things like netconsole to send skbs
2755 * without having to re-enable interrupts. It's not called while
2756 * the interrupt routine is executing.
2757 */
2758static void rtl8169_netpoll(struct net_device *dev)
2759{
2760 struct rtl8169_private *tp = netdev_priv(dev);
2761 struct pci_dev *pdev = tp->pci_dev;
2762
2763 disable_irq(pdev->irq);
7d12e780 2764 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2765 enable_irq(pdev->irq);
2766}
2767#endif
2768
2769static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2770 void __iomem *ioaddr)
2771{
2772 iounmap(ioaddr);
2773 pci_release_regions(pdev);
2774 pci_disable_device(pdev);
2775 free_netdev(dev);
2776}
2777
bf793295
FR		 2778static void rtl8169_phy_reset(struct net_device *dev,
2779 struct rtl8169_private *tp)
2780{
2781 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2782 unsigned int i;
bf793295
FR		 2783
2784 tp->phy_reset_enable(ioaddr);
2785 for (i = 0; i < 100; i++) {
2786 if (!tp->phy_reset_pending(ioaddr))
2787 return;
2788 msleep(1);
2789 }
bf82c189 2790 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2791}
2792
4ff96fa6
FR		 2793static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2794{
2795 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2796
5615d9f1 2797 rtl_hw_phy_config(dev);
4ff96fa6 2798
77332894
MS		 2799 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2800 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2801 RTL_W8(0x82, 0x01);
2802 }
4ff96fa6 2803
6dccd16b
FR		 2804 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2805
2806 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2807 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2808
bcf0bf90 2809 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2810 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2811 RTL_W8(0x82, 0x01);
2812 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2813 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2814 }
2815
bf793295
FR		 2816 rtl8169_phy_reset(dev, tp);
2817
901dda2b
FR		 2818 /*
2819 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2820 * only 8101. Don't panic.
2821 */
2822 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2823
bf82c189
JP		 2824 if (RTL_R8(PHYstatus) & TBI_Enable)
2825 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2826}
2827
773d2021
FR		 2828static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2829{
2830 void __iomem *ioaddr = tp->mmio_addr;
2831 u32 high;
2832 u32 low;
2833
2834 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2835 high = addr[4] | (addr[5] << 8);
2836
2837 spin_lock_irq(&tp->lock);
2838
2839 RTL_W8(Cfg9346, Cfg9346_Unlock);
2840 RTL_W32(MAC0, low);
2841 RTL_W32(MAC4, high);
2842 RTL_W8(Cfg9346, Cfg9346_Lock);
2843
2844 spin_unlock_irq(&tp->lock);
2845}
2846
2847static int rtl_set_mac_address(struct net_device *dev, void *p)
2848{
2849 struct rtl8169_private *tp = netdev_priv(dev);
2850 struct sockaddr *addr = p;
2851
2852 if (!is_valid_ether_addr(addr->sa_data))
2853 return -EADDRNOTAVAIL;
2854
2855 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2856
2857 rtl_rar_set(tp, dev->dev_addr);
2858
2859 return 0;
2860}
2861
5f787a1a
FR		 2862static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2863{
2864 struct rtl8169_private *tp = netdev_priv(dev);
2865 struct mii_ioctl_data *data = if_mii(ifr);
2866
8b4ab28d
FR		 2867 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2868}
5f787a1a 2869
8b4ab28d
FR		 2870static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2871{
5f787a1a
FR		 2872 switch (cmd) {
2873 case SIOCGMIIPHY:
2874 data->phy_id = 32; /* Internal PHY */
2875 return 0;
2876
2877 case SIOCGMIIREG:
2878 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2879 return 0;
2880
2881 case SIOCSMIIREG:
5f787a1a
FR		 2882 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2883 return 0;
2884 }
2885 return -EOPNOTSUPP;
2886}
2887
8b4ab28d
FR		 2888static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2889{
2890 return -EOPNOTSUPP;
2891}
2892
0e485150
FR		 2893static const struct rtl_cfg_info {
2894 void (*hw_start)(struct net_device *);
2895 unsigned int region;
2896 unsigned int align;
2897 u16 intr_event;
2898 u16 napi_event;
ccdffb9a 2899 unsigned features;
f21b75e9 2900 u8 default_ver;
0e485150
FR		 2901} rtl_cfg_infos [] = {
2902 [RTL_CFG_0] = {
2903 .hw_start = rtl_hw_start_8169,
2904 .region = 1,
e9f63f30 2905 .align = 0,
0e485150
FR		 2906 .intr_event = SYSErr | LinkChg | RxOverflow |
2907 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2908 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2909 .features = RTL_FEATURE_GMII,
2910 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2911 },
2912 [RTL_CFG_1] = {
2913 .hw_start = rtl_hw_start_8168,
2914 .region = 2,
2915 .align = 8,
2916 .intr_event = SYSErr | LinkChg | RxOverflow |
2917 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2918 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2919 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2920 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2921 },
2922 [RTL_CFG_2] = {
2923 .hw_start = rtl_hw_start_8101,
2924 .region = 2,
2925 .align = 8,
2926 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2927 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2928 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2929 .features = RTL_FEATURE_MSI,
2930 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2931 }
2932};
2933
fbac58fc
FR		 2934/* Cfg9346_Unlock assumed. */
2935static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2936 const struct rtl_cfg_info *cfg)
2937{
2938 unsigned msi = 0;
2939 u8 cfg2;
2940
2941 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2942 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2943 if (pci_enable_msi(pdev)) {
2944 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2945 } else {
2946 cfg2 |= MSIEnable;
2947 msi = RTL_FEATURE_MSI;
2948 }
2949 }
2950 RTL_W8(Config2, cfg2);
2951 return msi;
2952}
2953
2954static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2955{
2956 if (tp->features & RTL_FEATURE_MSI) {
2957 pci_disable_msi(pdev);
2958 tp->features &= ~RTL_FEATURE_MSI;
2959 }
2960}
2961
8b4ab28d
FR		 2962static const struct net_device_ops rtl8169_netdev_ops = {
2963 .ndo_open = rtl8169_open,
2964 .ndo_stop = rtl8169_close,
2965 .ndo_get_stats = rtl8169_get_stats,
00829823 2966 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2967 .ndo_tx_timeout = rtl8169_tx_timeout,
2968 .ndo_validate_addr = eth_validate_addr,
2969 .ndo_change_mtu = rtl8169_change_mtu,
2970 .ndo_set_mac_address = rtl_set_mac_address,
2971 .ndo_do_ioctl = rtl8169_ioctl,
2972 .ndo_set_multicast_list = rtl_set_rx_mode,
2973#ifdef CONFIG_R8169_VLAN
2974 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2975#endif
2976#ifdef CONFIG_NET_POLL_CONTROLLER
2977 .ndo_poll_controller = rtl8169_netpoll,
2978#endif
2979
2980};
2981
1da177e4 2982static int __devinit
4ff96fa6 2983rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2984{
0e485150
FR		 2985 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2986 const unsigned int region = cfg->region;
1da177e4 2987 struct rtl8169_private *tp;
ccdffb9a 2988 struct mii_if_info *mii;
4ff96fa6
FR		 2989 struct net_device *dev;
2990 void __iomem *ioaddr;
07d3f51f
FR		 2991 unsigned int i;
2992 int rc;
35317688 2993 int this_use_dac = use_dac;
1da177e4 2994
4ff96fa6
FR		 2995 if (netif_msg_drv(&debug)) {
2996 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2997 MODULENAME, RTL8169_VERSION);
2998 }
1da177e4 2999
1da177e4 3000 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3001 if (!dev) {
b57b7e5a 3002 if (netif_msg_drv(&debug))
9b91cf9d 3003 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3004 rc = -ENOMEM;
3005 goto out;
1da177e4
LT		 3006 }
3007
1da177e4 3008 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3009 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3010 tp = netdev_priv(dev);
c4028958 3011 tp->dev = dev;
21e197f2 3012 tp->pci_dev = pdev;
b57b7e5a 3013 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3014
ccdffb9a
FR		 3015 mii = &tp->mii;
3016 mii->dev = dev;
3017 mii->mdio_read = rtl_mdio_read;
3018 mii->mdio_write = rtl_mdio_write;
3019 mii->phy_id_mask = 0x1f;
3020 mii->reg_num_mask = 0x1f;
3021 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3022
1da177e4
LT		 3023 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3024 rc = pci_enable_device(pdev);
b57b7e5a 3025 if (rc < 0) {
bf82c189 3026 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3027 goto err_out_free_dev_1;
1da177e4
LT		 3028 }
3029
3030 rc = pci_set_mwi(pdev);
3031 if (rc < 0)
4ff96fa6 3032 goto err_out_disable_2;
1da177e4 3033
1da177e4 3034 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3035 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3036 netif_err(tp, probe, dev,
3037 "region #%d not an MMIO resource, aborting\n",
3038 region);
1da177e4 3039 rc = -ENODEV;
4ff96fa6 3040 goto err_out_mwi_3;
1da177e4 3041 }
4ff96fa6 3042
1da177e4 3043 /* check for weird/broken PCI region reporting */
bcf0bf90 3044 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3045 netif_err(tp, probe, dev,
3046 "Invalid PCI region size(s), aborting\n");
1da177e4 3047 rc = -ENODEV;
4ff96fa6 3048 goto err_out_mwi_3;
1da177e4
LT		 3049 }
3050
3051 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3052 if (rc < 0) {
bf82c189 3053 netif_err(tp, probe, dev, "could not request regions\n");
4ff96fa6 3054 goto err_out_mwi_3;
1da177e4
LT		 3055 }
3056
3057 tp->cp_cmd = PCIMulRW | RxChkSum;
3058
35317688
RH		 3059 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3060 if (!tp->pcie_cap)
3061 netif_info(tp, probe, dev, "no PCI Express capability\n");
3062
3063 if (this_use_dac < 0)
3064 this_use_dac = tp->pcie_cap != 0;
3065
1da177e4 3066 if ((sizeof(dma_addr_t) > 4) &&
35317688
RH		 3067 this_use_dac &&
3068 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3069 netif_info(tp, probe, dev, "using 64-bit DMA\n");
1da177e4
LT		 3070 tp->cp_cmd |= PCIDAC;
3071 dev->features |= NETIF_F_HIGHDMA;
3072 } else {
284901a9 3073 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3074 if (rc < 0) {
bf82c189 3075 netif_err(tp, probe, dev, "DMA configuration failed\n");
4ff96fa6 3076 goto err_out_free_res_4;
1da177e4
LT		 3077 }
3078 }
3079
1da177e4 3080 /* ioremap MMIO region */
bcf0bf90 3081 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3082 if (!ioaddr) {
bf82c189 3083 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3084 rc = -EIO;
4ff96fa6 3085 goto err_out_free_res_4;
1da177e4
LT		 3086 }
3087
d78ad8cb 3088 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3089
3090 /* Soft reset the chip. */
3091 RTL_W8(ChipCmd, CmdReset);
3092
3093 /* Check that the chip has finished the reset. */
07d3f51f 3094 for (i = 0; i < 100; i++) {
1da177e4
LT		 3095 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3096 break;
b518fa8e 3097 msleep_interruptible(1);
1da177e4
LT		 3098 }
3099
d78ad8cb
KW		 3100 RTL_W16(IntrStatus, 0xffff);
3101
ca52efd5 3102 pci_set_master(pdev);
3103
1da177e4
LT		 3104 /* Identify chip attached to board */
3105 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3106
f21b75e9
JD		 3107 /* Use appropriate default if unknown */
3108 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3109 netif_notice(tp, probe, dev,
3110 "unknown MAC, using family default\n");
f21b75e9
JD		 3111 tp->mac_version = cfg->default_ver;
3112 }
3113
1da177e4 3114 rtl8169_print_mac_version(tp);
1da177e4 3115
cee60c37 3116 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3117 if (tp->mac_version == rtl_chip_info[i].mac_version)
3118 break;
3119 }
cee60c37 3120 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3121 dev_err(&pdev->dev,
3122 "driver bug, MAC version not found in rtl_chip_info\n");
3123 goto err_out_msi_5;
1da177e4
LT		 3124 }
3125 tp->chipset = i;
3126
5d06a99f
FR		 3127 RTL_W8(Cfg9346, Cfg9346_Unlock);
3128 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3129 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3130 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3131 tp->features |= RTL_FEATURE_WOL;
3132 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3133 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3134 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3135 RTL_W8(Cfg9346, Cfg9346_Lock);
3136
66ec5d4f
FR		 3137 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3138 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3139 tp->set_speed = rtl8169_set_speed_tbi;
3140 tp->get_settings = rtl8169_gset_tbi;
3141 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3142 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3143 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3144 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3145
64e4bfb4 3146 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3147 } else {
3148 tp->set_speed = rtl8169_set_speed_xmii;
3149 tp->get_settings = rtl8169_gset_xmii;
3150 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3151 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3152 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3153 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3154 }
3155
df58ef51
FR		 3156 spin_lock_init(&tp->lock);
3157
738e1e69
PV		 3158 tp->mmio_addr = ioaddr;
3159
7bf6bf48 3160 /* Get MAC address */
1da177e4
LT		 3161 for (i = 0; i < MAC_ADDR_LEN; i++)
3162 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3163 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3164
1da177e4 3165 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3166 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3167 dev->irq = pdev->irq;
3168 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3169
bea3348e 3170 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3171
3172#ifdef CONFIG_R8169_VLAN
3173 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3174#endif
3175
3176 tp->intr_mask = 0xffff;
0e485150
FR		 3177 tp->align = cfg->align;
3178 tp->hw_start = cfg->hw_start;
3179 tp->intr_event = cfg->intr_event;
3180 tp->napi_event = cfg->napi_event;
1da177e4 3181
2efa53f3
FR		 3182 init_timer(&tp->timer);
3183 tp->timer.data = (unsigned long) dev;
3184 tp->timer.function = rtl8169_phy_timer;
3185
1da177e4 3186 rc = register_netdev(dev);
4ff96fa6 3187 if (rc < 0)
fbac58fc 3188 goto err_out_msi_5;
1da177e4
LT		 3189
3190 pci_set_drvdata(pdev, dev);
3191
bf82c189
JP		 3192 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3193 rtl_chip_info[tp->chipset].name,
3194 dev->base_addr, dev->dev_addr,
3195 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3196
4ff96fa6 3197 rtl8169_init_phy(dev, tp);
05af2142
SW		 3198
3199 /*
3200 * Pretend we are using VLANs; This bypasses a nasty bug where
3201 * Interrupts stop flowing on high load on 8110SCd controllers.
3202 */
3203 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3204 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3205
8b76ab39 3206 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3207
e1759441
RW		 3208 if (pci_dev_run_wake(pdev)) {
3209 pm_runtime_set_active(&pdev->dev);
3210 pm_runtime_enable(&pdev->dev);
3211 }
3212 pm_runtime_idle(&pdev->dev);
3213
4ff96fa6
FR		 3214out:
3215 return rc;
1da177e4 3216
fbac58fc
FR		 3217err_out_msi_5:
3218 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 3219 iounmap(ioaddr);
3220err_out_free_res_4:
3221 pci_release_regions(pdev);
3222err_out_mwi_3:
3223 pci_clear_mwi(pdev);
3224err_out_disable_2:
3225 pci_disable_device(pdev);
3226err_out_free_dev_1:
3227 free_netdev(dev);
3228 goto out;
1da177e4
LT		 3229}
3230
07d3f51f 3231static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3232{
3233 struct net_device *dev = pci_get_drvdata(pdev);
3234 struct rtl8169_private *tp = netdev_priv(dev);
3235
e1759441
RW		 3236 pm_runtime_get_sync(&pdev->dev);
3237
eb2a021c
FR		 3238 flush_scheduled_work();
3239
1da177e4 3240 unregister_netdev(dev);
cc098dc7 3241
e1759441
RW		 3242 if (pci_dev_run_wake(pdev)) {
3243 pm_runtime_disable(&pdev->dev);
3244 pm_runtime_set_suspended(&pdev->dev);
3245 }
3246 pm_runtime_put_noidle(&pdev->dev);
3247
cc098dc7
IV		 3248 /* restore original MAC address */
3249 rtl_rar_set(tp, dev->perm_addr);
3250
fbac58fc 3251 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3252 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3253 pci_set_drvdata(pdev, NULL);
3254}
3255
1da177e4
LT		 3256static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3257 struct net_device *dev)
3258{
8812304c 3259 unsigned int max_frame = dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
1da177e4 3260
8812304c 3261 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
1da177e4
LT		 3262}
3263
3264static int rtl8169_open(struct net_device *dev)
3265{
3266 struct rtl8169_private *tp = netdev_priv(dev);
3267 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3268 int retval = -ENOMEM;
1da177e4 3269
e1759441 3270 pm_runtime_get_sync(&pdev->dev);
1da177e4 3271
99f252b0 3272 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 3273
3274 /*
3275 * Rx and Tx desscriptors needs 256 bytes alignment.
3276 * pci_alloc_consistent provides more.
3277 */
3278 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3279 &tp->TxPhyAddr);
3280 if (!tp->TxDescArray)
e1759441 3281 goto err_pm_runtime_put;
1da177e4
LT		 3282
3283 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3284 &tp->RxPhyAddr);
3285 if (!tp->RxDescArray)
99f252b0 3286 goto err_free_tx_0;
1da177e4
LT		 3287
3288 retval = rtl8169_init_ring(dev);
3289 if (retval < 0)
99f252b0 3290 goto err_free_rx_1;
1da177e4 3291
c4028958 3292 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3293
99f252b0
FR		 3294 smp_mb();
3295
fbac58fc
FR		 3296 retval = request_irq(dev->irq, rtl8169_interrupt,
3297 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3298 dev->name, dev);
3299 if (retval < 0)
3300 goto err_release_ring_2;
3301
bea3348e 3302 napi_enable(&tp->napi);
bea3348e 3303
07ce4064 3304 rtl_hw_start(dev);
1da177e4
LT		 3305
3306 rtl8169_request_timer(dev);
3307
e1759441
RW		 3308 tp->saved_wolopts = 0;
3309 pm_runtime_put_noidle(&pdev->dev);
3310
1da177e4
LT		 3311 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3312out:
3313 return retval;
3314
99f252b0
FR		 3315err_release_ring_2:
3316 rtl8169_rx_clear(tp);
3317err_free_rx_1:
1da177e4
LT		 3318 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3319 tp->RxPhyAddr);
e1759441 3320 tp->RxDescArray = NULL;
99f252b0 3321err_free_tx_0:
1da177e4
LT		 3322 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3323 tp->TxPhyAddr);
e1759441
RW		 3324 tp->TxDescArray = NULL;
3325err_pm_runtime_put:
3326 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3327 goto out;
3328}
3329
3330static void rtl8169_hw_reset(void __iomem *ioaddr)
3331{
3332 /* Disable interrupts */
3333 rtl8169_irq_mask_and_ack(ioaddr);
3334
3335 /* Reset the chipset */
3336 RTL_W8(ChipCmd, CmdReset);
3337
3338 /* PCI commit */
3339 RTL_R8(ChipCmd);
3340}
3341
7f796d83 3342static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3343{
3344 void __iomem *ioaddr = tp->mmio_addr;
3345 u32 cfg = rtl8169_rx_config;
3346
3347 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3348 RTL_W32(RxConfig, cfg);
3349
3350 /* Set DMA burst size and Interframe Gap Time */
3351 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3352 (InterFrameGap << TxInterFrameGapShift));
3353}
3354
07ce4064 3355static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3356{
3357 struct rtl8169_private *tp = netdev_priv(dev);
3358 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3359 unsigned int i;
1da177e4
LT		 3360
3361 /* Soft reset the chip. */
3362 RTL_W8(ChipCmd, CmdReset);
3363
3364 /* Check that the chip has finished the reset. */
07d3f51f 3365 for (i = 0; i < 100; i++) {
1da177e4
LT		 3366 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3367 break;
b518fa8e 3368 msleep_interruptible(1);
1da177e4
LT		 3369 }
3370
07ce4064
FR		 3371 tp->hw_start(dev);
3372
07ce4064
FR		 3373 netif_start_queue(dev);
3374}
3375
3376
7f796d83
FR		 3377static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3378 void __iomem *ioaddr)
3379{
3380 /*
3381 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3382 * register to be written before TxDescAddrLow to work.
3383 * Switching from MMIO to I/O access fixes the issue as well.
3384 */
3385 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3386 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3387 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3388 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3389}
3390
3391static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3392{
3393 u16 cmd;
3394
3395 cmd = RTL_R16(CPlusCmd);
3396 RTL_W16(CPlusCmd, cmd);
3397 return cmd;
3398}
3399
fdd7b4c3 3400static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3401{
3402 /* Low hurts. Let's disable the filtering. */
207d6e87 3403 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3404}
3405
6dccd16b
FR		 3406static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3407{
350f7596 3408 static const struct {
6dccd16b
FR		 3409 u32 mac_version;
3410 u32 clk;
3411 u32 val;
3412 } cfg2_info [] = {
3413 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3414 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3415 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3416 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3417 }, *p = cfg2_info;
3418 unsigned int i;
3419 u32 clk;
3420
3421 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3422 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3423 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3424 RTL_W32(0x7c, p->val);
3425 break;
3426 }
3427 }
3428}
3429
07ce4064
FR		 3430static void rtl_hw_start_8169(struct net_device *dev)
3431{
3432 struct rtl8169_private *tp = netdev_priv(dev);
3433 void __iomem *ioaddr = tp->mmio_addr;
3434 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3435
9cb427b6
FR		 3436 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3437 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3438 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3439 }
3440
1da177e4 3441 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3442 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3443 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3444 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3445 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3446 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3447
1da177e4
LT		 3448 RTL_W8(EarlyTxThres, EarlyTxThld);
3449
fdd7b4c3 3450 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
1da177e4 3451
c946b304
FR		 3452 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3453 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3454 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3455 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3456 rtl_set_rx_tx_config_registers(tp);
1da177e4 3457
7f796d83 3458 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3459
bcf0bf90
FR		 3460 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3461 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3462 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3463 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3464 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3465 }
3466
bcf0bf90
FR		 3467 RTL_W16(CPlusCmd, tp->cp_cmd);
3468
6dccd16b
FR		 3469 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3470
1da177e4
LT		 3471 /*
3472 * Undocumented corner. Supposedly:
3473 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3474 */
3475 RTL_W16(IntrMitigate, 0x0000);
3476
7f796d83 3477 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3478
c946b304
FR		 3479 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3480 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3481 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3482 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3483 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3484 rtl_set_rx_tx_config_registers(tp);
3485 }
3486
1da177e4 3487 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3488
3489 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3490 RTL_R8(IntrMask);
1da177e4
LT		 3491
3492 RTL_W32(RxMissed, 0);
3493
07ce4064 3494 rtl_set_rx_mode(dev);
1da177e4
LT		 3495
3496 /* no early-rx interrupts */
3497 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3498
3499 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3500 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3501}
1da177e4 3502
9c14ceaf 3503static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3504{
9c14ceaf
FR		 3505 struct net_device *dev = pci_get_drvdata(pdev);
3506 struct rtl8169_private *tp = netdev_priv(dev);
3507 int cap = tp->pcie_cap;
3508
3509 if (cap) {
3510 u16 ctl;
458a9f61 3511
9c14ceaf
FR		 3512 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3513 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3514 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3515 }
458a9f61
FR		 3516}
3517
dacf8154
FR		 3518static void rtl_csi_access_enable(void __iomem *ioaddr)
3519{
3520 u32 csi;
3521
3522 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3523 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3524}
3525
3526struct ephy_info {
3527 unsigned int offset;
3528 u16 mask;
3529 u16 bits;
3530};
3531
350f7596 3532static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3533{
3534 u16 w;
3535
3536 while (len-- > 0) {
3537 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3538 rtl_ephy_write(ioaddr, e->offset, w);
3539 e++;
3540 }
3541}
3542
b726e493
FR		 3543static void rtl_disable_clock_request(struct pci_dev *pdev)
3544{
3545 struct net_device *dev = pci_get_drvdata(pdev);
3546 struct rtl8169_private *tp = netdev_priv(dev);
3547 int cap = tp->pcie_cap;
3548
3549 if (cap) {
3550 u16 ctl;
3551
3552 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3553 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3554 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3555 }
3556}
3557
3558#define R8168_CPCMD_QUIRK_MASK (\
3559 EnableBist | \
3560 Mac_dbgo_oe | \
3561 Force_half_dup | \
3562 Force_rxflow_en | \
3563 Force_txflow_en | \
3564 Cxpl_dbg_sel | \
3565 ASF | \
3566 PktCntrDisable | \
3567 Mac_dbgo_sel)
3568
219a1e9d
FR		 3569static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3570{
b726e493
FR		 3571 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3572
3573 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3574
2e68ae44
FR		 3575 rtl_tx_performance_tweak(pdev,
3576 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3577}
3578
3579static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3580{
3581 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 3582
3583 RTL_W8(EarlyTxThres, EarlyTxThld);
3584
3585 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3586}
3587
3588static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3589{
b726e493
FR		 3590 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3591
3592 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3593
219a1e9d 3594 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3595
3596 rtl_disable_clock_request(pdev);
3597
3598 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3599}
3600
ef3386f0 3601static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3602{
350f7596 3603 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3604 { 0x01, 0, 0x0001 },
3605 { 0x02, 0x0800, 0x1000 },
3606 { 0x03, 0, 0x0042 },
3607 { 0x06, 0x0080, 0x0000 },
3608 { 0x07, 0, 0x2000 }
3609 };
3610
3611 rtl_csi_access_enable(ioaddr);
3612
3613 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3614
219a1e9d
FR		 3615 __rtl_hw_start_8168cp(ioaddr, pdev);
3616}
3617
ef3386f0
FR		 3618static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3619{
3620 rtl_csi_access_enable(ioaddr);
3621
3622 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3623
3624 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3625
3626 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3627}
3628
7f3e3d3a
FR		 3629static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3630{
3631 rtl_csi_access_enable(ioaddr);
3632
3633 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3634
3635 /* Magic. */
3636 RTL_W8(DBG_REG, 0x20);
3637
3638 RTL_W8(EarlyTxThres, EarlyTxThld);
3639
3640 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3641
3642 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3643}
3644
219a1e9d
FR		 3645static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3646{
350f7596 3647 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3648 { 0x02, 0x0800, 0x1000 },
3649 { 0x03, 0, 0x0002 },
3650 { 0x06, 0x0080, 0x0000 }
3651 };
3652
3653 rtl_csi_access_enable(ioaddr);
3654
3655 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3656
3657 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3658
219a1e9d
FR		 3659 __rtl_hw_start_8168cp(ioaddr, pdev);
3660}
3661
3662static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3663{
350f7596 3664 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3665 { 0x01, 0, 0x0001 },
3666 { 0x03, 0x0400, 0x0220 }
3667 };
3668
3669 rtl_csi_access_enable(ioaddr);
3670
3671 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3672
219a1e9d
FR		 3673 __rtl_hw_start_8168cp(ioaddr, pdev);
3674}
3675
197ff761
FR		 3676static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3677{
3678 rtl_hw_start_8168c_2(ioaddr, pdev);
3679}
3680
6fb07058
FR		 3681static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3682{
3683 rtl_csi_access_enable(ioaddr);
3684
3685 __rtl_hw_start_8168cp(ioaddr, pdev);
3686}
3687
5b538df9
FR		 3688static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3689{
3690 rtl_csi_access_enable(ioaddr);
3691
3692 rtl_disable_clock_request(pdev);
3693
3694 RTL_W8(EarlyTxThres, EarlyTxThld);
3695
3696 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3697
3698 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3699}
3700
07ce4064
FR		 3701static void rtl_hw_start_8168(struct net_device *dev)
3702{
2dd99530
FR		 3703 struct rtl8169_private *tp = netdev_priv(dev);
3704 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3705 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3706
3707 RTL_W8(Cfg9346, Cfg9346_Unlock);
3708
3709 RTL_W8(EarlyTxThres, EarlyTxThld);
3710
fdd7b4c3 3711 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2dd99530 3712
0e485150 3713 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3714
3715 RTL_W16(CPlusCmd, tp->cp_cmd);
3716
0e485150 3717 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3718
0e485150
FR		 3719 /* Work around for RxFIFO overflow. */
3720 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3721 tp->intr_event |= RxFIFOOver | PCSTimeout;
3722 tp->intr_event &= ~RxOverflow;
3723 }
3724
3725 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3726
b8363901
FR		 3727 rtl_set_rx_mode(dev);
3728
3729 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3730 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3731
3732 RTL_R8(IntrMask);
3733
219a1e9d
FR		 3734 switch (tp->mac_version) {
3735 case RTL_GIGA_MAC_VER_11:
3736 rtl_hw_start_8168bb(ioaddr, pdev);
3737 break;
3738
3739 case RTL_GIGA_MAC_VER_12:
3740 case RTL_GIGA_MAC_VER_17:
3741 rtl_hw_start_8168bef(ioaddr, pdev);
3742 break;
3743
3744 case RTL_GIGA_MAC_VER_18:
ef3386f0 3745 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3746 break;
3747
3748 case RTL_GIGA_MAC_VER_19:
3749 rtl_hw_start_8168c_1(ioaddr, pdev);
3750 break;
3751
3752 case RTL_GIGA_MAC_VER_20:
3753 rtl_hw_start_8168c_2(ioaddr, pdev);
3754 break;
3755
197ff761
FR		 3756 case RTL_GIGA_MAC_VER_21:
3757 rtl_hw_start_8168c_3(ioaddr, pdev);
3758 break;
3759
6fb07058
FR		 3760 case RTL_GIGA_MAC_VER_22:
3761 rtl_hw_start_8168c_4(ioaddr, pdev);
3762 break;
3763
ef3386f0
FR		 3764 case RTL_GIGA_MAC_VER_23:
3765 rtl_hw_start_8168cp_2(ioaddr, pdev);
3766 break;
3767
7f3e3d3a
FR		 3768 case RTL_GIGA_MAC_VER_24:
3769 rtl_hw_start_8168cp_3(ioaddr, pdev);
3770 break;
3771
5b538df9 3772 case RTL_GIGA_MAC_VER_25:
daf9df6d 3773 case RTL_GIGA_MAC_VER_26:
3774 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3775 rtl_hw_start_8168d(ioaddr, pdev);
3776 break;
3777
219a1e9d
FR		 3778 default:
3779 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3780 dev->name, tp->mac_version);
3781 break;
3782 }
2dd99530 3783
0e485150
FR		 3784 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3785
b8363901
FR		 3786 RTL_W8(Cfg9346, Cfg9346_Lock);
3787
2dd99530 3788 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3789
0e485150 3790 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3791}
1da177e4 3792
2857ffb7
FR		 3793#define R810X_CPCMD_QUIRK_MASK (\
3794 EnableBist | \
3795 Mac_dbgo_oe | \
3796 Force_half_dup | \
5edcc537 3797 Force_rxflow_en | \
2857ffb7
FR		 3798 Force_txflow_en | \
3799 Cxpl_dbg_sel | \
3800 ASF | \
3801 PktCntrDisable | \
3802 PCIDAC | \
3803 PCIMulRW)
3804
3805static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3806{
350f7596 3807 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3808 { 0x01, 0, 0x6e65 },
3809 { 0x02, 0, 0x091f },
3810 { 0x03, 0, 0xc2f9 },
3811 { 0x06, 0, 0xafb5 },
3812 { 0x07, 0, 0x0e00 },
3813 { 0x19, 0, 0xec80 },
3814 { 0x01, 0, 0x2e65 },
3815 { 0x01, 0, 0x6e65 }
3816 };
3817 u8 cfg1;
3818
3819 rtl_csi_access_enable(ioaddr);
3820
3821 RTL_W8(DBG_REG, FIX_NAK_1);
3822
3823 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3824
3825 RTL_W8(Config1,
3826 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3827 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3828
3829 cfg1 = RTL_R8(Config1);
3830 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3831 RTL_W8(Config1, cfg1 & ~LEDS0);
3832
3833 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3834
3835 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3836}
3837
3838static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3839{
3840 rtl_csi_access_enable(ioaddr);
3841
3842 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3843
3844 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3845 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3846
3847 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3848}
3849
3850static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3851{
3852 rtl_hw_start_8102e_2(ioaddr, pdev);
3853
3854 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3855}
3856
07ce4064
FR		 3857static void rtl_hw_start_8101(struct net_device *dev)
3858{
cdf1a608
FR		 3859 struct rtl8169_private *tp = netdev_priv(dev);
3860 void __iomem *ioaddr = tp->mmio_addr;
3861 struct pci_dev *pdev = tp->pci_dev;
3862
e3cf0cc0
FR		 3863 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3864 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3865 int cap = tp->pcie_cap;
3866
3867 if (cap) {
3868 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3869 PCI_EXP_DEVCTL_NOSNOOP_EN);
3870 }
cdf1a608
FR		 3871 }
3872
2857ffb7
FR		 3873 switch (tp->mac_version) {
3874 case RTL_GIGA_MAC_VER_07:
3875 rtl_hw_start_8102e_1(ioaddr, pdev);
3876 break;
3877
3878 case RTL_GIGA_MAC_VER_08:
3879 rtl_hw_start_8102e_3(ioaddr, pdev);
3880 break;
3881
3882 case RTL_GIGA_MAC_VER_09:
3883 rtl_hw_start_8102e_2(ioaddr, pdev);
3884 break;
cdf1a608
FR		 3885 }
3886
3887 RTL_W8(Cfg9346, Cfg9346_Unlock);
3888
3889 RTL_W8(EarlyTxThres, EarlyTxThld);
3890
fdd7b4c3 3891 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
cdf1a608
FR		 3892
3893 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3894
3895 RTL_W16(CPlusCmd, tp->cp_cmd);
3896
3897 RTL_W16(IntrMitigate, 0x0000);
3898
3899 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3900
3901 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3902 rtl_set_rx_tx_config_registers(tp);
3903
3904 RTL_W8(Cfg9346, Cfg9346_Lock);
3905
3906 RTL_R8(IntrMask);
3907
cdf1a608
FR		 3908 rtl_set_rx_mode(dev);
3909
0e485150
FR		 3910 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3911
cdf1a608 3912 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3913
0e485150 3914 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3915}
3916
3917static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3918{
3919 struct rtl8169_private *tp = netdev_priv(dev);
3920 int ret = 0;
3921
3922 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3923 return -EINVAL;
3924
3925 dev->mtu = new_mtu;
3926
3927 if (!netif_running(dev))
3928 goto out;
3929
3930 rtl8169_down(dev);
3931
3932 rtl8169_set_rxbufsize(tp, dev);
3933
3934 ret = rtl8169_init_ring(dev);
3935 if (ret < 0)
3936 goto out;
3937
bea3348e 3938 napi_enable(&tp->napi);
1da177e4 3939
07ce4064 3940 rtl_hw_start(dev);
1da177e4
LT		 3941
3942 rtl8169_request_timer(dev);
3943
3944out:
3945 return ret;
3946}
3947
3948static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3949{
95e0918d 3950 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3951 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3952}
3953
3954static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3955 struct sk_buff **sk_buff, struct RxDesc *desc)
3956{
3957 struct pci_dev *pdev = tp->pci_dev;
3958
3959 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3960 PCI_DMA_FROMDEVICE);
3961 dev_kfree_skb(*sk_buff);
3962 *sk_buff = NULL;
3963 rtl8169_make_unusable_by_asic(desc);
3964}
3965
3966static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3967{
3968 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3969
3970 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3971}
3972
3973static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3974 u32 rx_buf_sz)
3975{
3976 desc->addr = cpu_to_le64(mapping);
3977 wmb();
3978 rtl8169_mark_to_asic(desc, rx_buf_sz);
3979}
3980
15d31758
SH		 3981static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3982 struct net_device *dev,
3983 struct RxDesc *desc, int rx_buf_sz,
3984 unsigned int align)
1da177e4
LT		 3985{
3986 struct sk_buff *skb;
3987 dma_addr_t mapping;
e9f63f30 3988 unsigned int pad;
1da177e4 3989
e9f63f30
FR		 3990 pad = align ? align : NET_IP_ALIGN;
3991
3992 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 3993 if (!skb)
3994 goto err_out;
3995
e9f63f30 3996 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 3997
689be439 3998 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 3999 PCI_DMA_FROMDEVICE);
4000
4001 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 4002out:
15d31758 4003 return skb;
1da177e4
LT		 4004
4005err_out:
1da177e4
LT		 4006 rtl8169_make_unusable_by_asic(desc);
4007 goto out;
4008}
4009
4010static void rtl8169_rx_clear(struct rtl8169_private *tp)
4011{
07d3f51f 4012 unsigned int i;
1da177e4
LT		 4013
4014 for (i = 0; i < NUM_RX_DESC; i++) {
4015 if (tp->Rx_skbuff[i]) {
4016 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
4017 tp->RxDescArray + i);
4018 }
4019 }
4020}
4021
4022static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4023 u32 start, u32 end)
4024{
4025 u32 cur;
5b0384f4 4026
4ae47c2d 4027 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 4028 struct sk_buff *skb;
4029 unsigned int i = cur % NUM_RX_DESC;
1da177e4 4030
4ae47c2d
FR		 4031 WARN_ON((s32)(end - cur) < 0);
4032
1da177e4
LT		 4033 if (tp->Rx_skbuff[i])
4034 continue;
bcf0bf90 4035
15d31758
SH		 4036 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4037 tp->RxDescArray + i,
4038 tp->rx_buf_sz, tp->align);
4039 if (!skb)
1da177e4 4040 break;
15d31758
SH		 4041
4042 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 4043 }
4044 return cur - start;
4045}
4046
4047static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4048{
4049 desc->opts1 |= cpu_to_le32(RingEnd);
4050}
4051
4052static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4053{
4054 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4055}
4056
4057static int rtl8169_init_ring(struct net_device *dev)
4058{
4059 struct rtl8169_private *tp = netdev_priv(dev);
4060
4061 rtl8169_init_ring_indexes(tp);
4062
4063 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4064 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4065
4066 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4067 goto err_out;
4068
4069 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4070
4071 return 0;
4072
4073err_out:
4074 rtl8169_rx_clear(tp);
4075 return -ENOMEM;
4076}
4077
4078static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4079 struct TxDesc *desc)
4080{
4081 unsigned int len = tx_skb->len;
4082
4083 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4084 desc->opts1 = 0x00;
4085 desc->opts2 = 0x00;
4086 desc->addr = 0x00;
4087 tx_skb->len = 0;
4088}
4089
4090static void rtl8169_tx_clear(struct rtl8169_private *tp)
4091{
4092 unsigned int i;
4093
4094 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4095 unsigned int entry = i % NUM_TX_DESC;
4096 struct ring_info *tx_skb = tp->tx_skb + entry;
4097 unsigned int len = tx_skb->len;
4098
4099 if (len) {
4100 struct sk_buff *skb = tx_skb->skb;
4101
4102 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4103 tp->TxDescArray + entry);
4104 if (skb) {
4105 dev_kfree_skb(skb);
4106 tx_skb->skb = NULL;
4107 }
cebf8cc7 4108 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4109 }
4110 }
4111 tp->cur_tx = tp->dirty_tx = 0;
4112}
4113
c4028958 4114static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4115{
4116 struct rtl8169_private *tp = netdev_priv(dev);
4117
c4028958 4118 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4119 schedule_delayed_work(&tp->task, 4);
4120}
4121
4122static void rtl8169_wait_for_quiescence(struct net_device *dev)
4123{
4124 struct rtl8169_private *tp = netdev_priv(dev);
4125 void __iomem *ioaddr = tp->mmio_addr;
4126
4127 synchronize_irq(dev->irq);
4128
4129 /* Wait for any pending NAPI task to complete */
bea3348e 4130 napi_disable(&tp->napi);
1da177e4
LT		 4131
4132 rtl8169_irq_mask_and_ack(ioaddr);
4133
d1d08d12
DM		 4134 tp->intr_mask = 0xffff;
4135 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4136 napi_enable(&tp->napi);
1da177e4
LT		 4137}
4138
c4028958 4139static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4140{
c4028958
DH		 4141 struct rtl8169_private *tp =
4142 container_of(work, struct rtl8169_private, task.work);
4143 struct net_device *dev = tp->dev;
1da177e4
LT		 4144 int ret;
4145
eb2a021c
FR		 4146 rtnl_lock();
4147
4148 if (!netif_running(dev))
4149 goto out_unlock;
4150
4151 rtl8169_wait_for_quiescence(dev);
4152 rtl8169_close(dev);
1da177e4
LT		 4153
4154 ret = rtl8169_open(dev);
4155 if (unlikely(ret < 0)) {
bf82c189
JP		 4156 if (net_ratelimit())
4157 netif_err(tp, drv, dev,
4158 "reinit failure (status = %d). Rescheduling\n",
4159 ret);
1da177e4
LT		 4160 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4161 }
eb2a021c
FR		 4162
4163out_unlock:
4164 rtnl_unlock();
1da177e4
LT		 4165}
4166
c4028958 4167static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4168{
c4028958
DH		 4169 struct rtl8169_private *tp =
4170 container_of(work, struct rtl8169_private, task.work);
4171 struct net_device *dev = tp->dev;
1da177e4 4172
eb2a021c
FR		 4173 rtnl_lock();
4174
1da177e4 4175 if (!netif_running(dev))
eb2a021c 4176 goto out_unlock;
1da177e4
LT		 4177
4178 rtl8169_wait_for_quiescence(dev);
4179
bea3348e 4180 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4181 rtl8169_tx_clear(tp);
4182
4183 if (tp->dirty_rx == tp->cur_rx) {
4184 rtl8169_init_ring_indexes(tp);
07ce4064 4185 rtl_hw_start(dev);
1da177e4 4186 netif_wake_queue(dev);
cebf8cc7 4187 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4188 } else {
bf82c189
JP		 4189 if (net_ratelimit())
4190 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4191 rtl8169_schedule_work(dev, rtl8169_reset_task);
4192 }
eb2a021c
FR		 4193
4194out_unlock:
4195 rtnl_unlock();
1da177e4
LT		 4196}
4197
4198static void rtl8169_tx_timeout(struct net_device *dev)
4199{
4200 struct rtl8169_private *tp = netdev_priv(dev);
4201
4202 rtl8169_hw_reset(tp->mmio_addr);
4203
4204 /* Let's wait a bit while any (async) irq lands on */
4205 rtl8169_schedule_work(dev, rtl8169_reset_task);
4206}
4207
4208static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4209 u32 opts1)
4210{
4211 struct skb_shared_info *info = skb_shinfo(skb);
4212 unsigned int cur_frag, entry;
a6343afb 4213 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 4214
4215 entry = tp->cur_tx;
4216 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4217 skb_frag_t *frag = info->frags + cur_frag;
4218 dma_addr_t mapping;
4219 u32 status, len;
4220 void *addr;
4221
4222 entry = (entry + 1) % NUM_TX_DESC;
4223
4224 txd = tp->TxDescArray + entry;
4225 len = frag->size;
4226 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4227 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4228
4229 /* anti gcc 2.95.3 bugware (sic) */
4230 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4231
4232 txd->opts1 = cpu_to_le32(status);
4233 txd->addr = cpu_to_le64(mapping);
4234
4235 tp->tx_skb[entry].len = len;
4236 }
4237
4238 if (cur_frag) {
4239 tp->tx_skb[entry].skb = skb;
4240 txd->opts1 |= cpu_to_le32(LastFrag);
4241 }
4242
4243 return cur_frag;
4244}
4245
4246static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4247{
4248 if (dev->features & NETIF_F_TSO) {
7967168c 4249 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4250
4251 if (mss)
4252 return LargeSend | ((mss & MSSMask) << MSSShift);
4253 }
84fa7933 4254 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4255 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4256
4257 if (ip->protocol == IPPROTO_TCP)
4258 return IPCS | TCPCS;
4259 else if (ip->protocol == IPPROTO_UDP)
4260 return IPCS | UDPCS;
4261 WARN_ON(1); /* we need a WARN() */
4262 }
4263 return 0;
4264}
4265
61357325
SH		 4266static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4267 struct net_device *dev)
1da177e4
LT		 4268{
4269 struct rtl8169_private *tp = netdev_priv(dev);
4270 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4271 struct TxDesc *txd = tp->TxDescArray + entry;
4272 void __iomem *ioaddr = tp->mmio_addr;
4273 dma_addr_t mapping;
4274 u32 status, len;
4275 u32 opts1;
5b0384f4 4276
1da177e4 4277 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4278 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
1da177e4
LT		 4279 goto err_stop;
4280 }
4281
4282 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4283 goto err_stop;
4284
4285 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4286
4287 frags = rtl8169_xmit_frags(tp, skb, opts1);
4288 if (frags) {
4289 len = skb_headlen(skb);
4290 opts1 |= FirstFrag;
4291 } else {
4292 len = skb->len;
1da177e4
LT		 4293 opts1 |= FirstFrag | LastFrag;
4294 tp->tx_skb[entry].skb = skb;
4295 }
4296
4297 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4298
4299 tp->tx_skb[entry].len = len;
4300 txd->addr = cpu_to_le64(mapping);
4301 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4302
4303 wmb();
4304
4305 /* anti gcc 2.95.3 bugware (sic) */
4306 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4307 txd->opts1 = cpu_to_le32(status);
4308
1da177e4
LT		 4309 tp->cur_tx += frags + 1;
4310
4c020a96 4311 wmb();
1da177e4 4312
275391a4 4313 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4314
4315 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4316 netif_stop_queue(dev);
4317 smp_rmb();
4318 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4319 netif_wake_queue(dev);
4320 }
4321
61357325 4322 return NETDEV_TX_OK;
1da177e4
LT		 4323
4324err_stop:
4325 netif_stop_queue(dev);
cebf8cc7 4326 dev->stats.tx_dropped++;
61357325 4327 return NETDEV_TX_BUSY;
1da177e4
LT		 4328}
4329
4330static void rtl8169_pcierr_interrupt(struct net_device *dev)
4331{
4332 struct rtl8169_private *tp = netdev_priv(dev);
4333 struct pci_dev *pdev = tp->pci_dev;
4334 void __iomem *ioaddr = tp->mmio_addr;
4335 u16 pci_status, pci_cmd;
4336
4337 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4338 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4339
bf82c189
JP		 4340 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4341 pci_cmd, pci_status);
1da177e4
LT		 4342
4343 /*
4344 * The recovery sequence below admits a very elaborated explanation:
4345 * - it seems to work;
d03902b8
FR		 4346 * - I did not see what else could be done;
4347 * - it makes iop3xx happy.
1da177e4
LT		 4348 *
4349 * Feel free to adjust to your needs.
4350 */
a27993f3 4351 if (pdev->broken_parity_status)
d03902b8
FR		 4352 pci_cmd &= ~PCI_COMMAND_PARITY;
4353 else
4354 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4355
4356 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4357
4358 pci_write_config_word(pdev, PCI_STATUS,
4359 pci_status & (PCI_STATUS_DETECTED_PARITY |
4360 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4361 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4362
4363 /* The infamous DAC f*ckup only happens at boot time */
4364 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
bf82c189 4365 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4366 tp->cp_cmd &= ~PCIDAC;
4367 RTL_W16(CPlusCmd, tp->cp_cmd);
4368 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4369 }
4370
4371 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 4372
4373 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4374}
4375
07d3f51f
FR		 4376static void rtl8169_tx_interrupt(struct net_device *dev,
4377 struct rtl8169_private *tp,
4378 void __iomem *ioaddr)
1da177e4
LT		 4379{
4380 unsigned int dirty_tx, tx_left;
4381
1da177e4
LT		 4382 dirty_tx = tp->dirty_tx;
4383 smp_rmb();
4384 tx_left = tp->cur_tx - dirty_tx;
4385
4386 while (tx_left > 0) {
4387 unsigned int entry = dirty_tx % NUM_TX_DESC;
4388 struct ring_info *tx_skb = tp->tx_skb + entry;
4389 u32 len = tx_skb->len;
4390 u32 status;
4391
4392 rmb();
4393 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4394 if (status & DescOwn)
4395 break;
4396
cebf8cc7
FR		 4397 dev->stats.tx_bytes += len;
4398 dev->stats.tx_packets++;
1da177e4
LT		 4399
4400 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4401
4402 if (status & LastFrag) {
87433bfc 4403 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4404 tx_skb->skb = NULL;
4405 }
4406 dirty_tx++;
4407 tx_left--;
4408 }
4409
4410 if (tp->dirty_tx != dirty_tx) {
4411 tp->dirty_tx = dirty_tx;
4412 smp_wmb();
4413 if (netif_queue_stopped(dev) &&
4414 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4415 netif_wake_queue(dev);
4416 }
d78ae2dc
FR		 4417 /*
4418 * 8168 hack: TxPoll requests are lost when the Tx packets are
4419 * too close. Let's kick an extra TxPoll request when a burst
4420 * of start_xmit activity is detected (if it is not detected,
4421 * it is slow enough). -- FR
4422 */
4423 smp_rmb();
4424 if (tp->cur_tx != dirty_tx)
4425 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4426 }
4427}
4428
126fa4b9
FR		 4429static inline int rtl8169_fragmented_frame(u32 status)
4430{
4431 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4432}
4433
1da177e4
LT		 4434static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4435{
4436 u32 opts1 = le32_to_cpu(desc->opts1);
4437 u32 status = opts1 & RxProtoMask;
4438
4439 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4440 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4441 ((status == RxProtoIP) && !(opts1 & IPFail)))
4442 skb->ip_summed = CHECKSUM_UNNECESSARY;
4443 else
4444 skb->ip_summed = CHECKSUM_NONE;
4445}
4446
07d3f51f
FR		 4447static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4448 struct rtl8169_private *tp, int pkt_size,
4449 dma_addr_t addr)
1da177e4 4450{
b449655f
SH		 4451 struct sk_buff *skb;
4452 bool done = false;
1da177e4 4453
b449655f
SH		 4454 if (pkt_size >= rx_copybreak)
4455 goto out;
1da177e4 4456
89d71a66 4457 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
b449655f
SH		 4458 if (!skb)
4459 goto out;
4460
07d3f51f
FR		 4461 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4462 PCI_DMA_FROMDEVICE);
b449655f
SH		 4463 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4464 *sk_buff = skb;
4465 done = true;
4466out:
4467 return done;
1da177e4
LT		 4468}
4469
630b943c
ED		 4470/*
4471 * Warning : rtl8169_rx_interrupt() might be called :
4472 * 1) from NAPI (softirq) context
4473 * (polling = 1 : we should call netif_receive_skb())
4474 * 2) from process context (rtl8169_reset_task())
4475 * (polling = 0 : we must call netif_rx() instead)
4476 */
07d3f51f
FR		 4477static int rtl8169_rx_interrupt(struct net_device *dev,
4478 struct rtl8169_private *tp,
bea3348e 4479 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4480{
4481 unsigned int cur_rx, rx_left;
4482 unsigned int delta, count;
630b943c 4483 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4484
1da177e4
LT		 4485 cur_rx = tp->cur_rx;
4486 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4487 rx_left = min(rx_left, budget);
1da177e4 4488
4dcb7d33 4489 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4490 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4491 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4492 u32 status;
4493
4494 rmb();
126fa4b9 4495 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4496
4497 if (status & DescOwn)
4498 break;
4dcb7d33 4499 if (unlikely(status & RxRES)) {
bf82c189
JP		 4500 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4501 status);
cebf8cc7 4502 dev->stats.rx_errors++;
1da177e4 4503 if (status & (RxRWT | RxRUNT))
cebf8cc7 4504 dev->stats.rx_length_errors++;
1da177e4 4505 if (status & RxCRC)
cebf8cc7 4506 dev->stats.rx_crc_errors++;
9dccf611
FR		 4507 if (status & RxFOVF) {
4508 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4509 dev->stats.rx_fifo_errors++;
9dccf611 4510 }
126fa4b9 4511 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 4512 } else {
1da177e4 4513 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 4514 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4515 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 4516 struct pci_dev *pdev = tp->pci_dev;
1da177e4 4517
126fa4b9
FR		 4518 /*
4519 * The driver does not support incoming fragmented
4520 * frames. They are seen as a symptom of over-mtu
4521 * sized frames.
4522 */
4523 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4524 dev->stats.rx_dropped++;
4525 dev->stats.rx_length_errors++;
126fa4b9 4526 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 4527 continue;
126fa4b9
FR		 4528 }
4529
1da177e4 4530 rtl8169_rx_csum(skb, desc);
bcf0bf90 4531
07d3f51f 4532 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 4533 pci_dma_sync_single_for_device(pdev, addr,
4534 pkt_size, PCI_DMA_FROMDEVICE);
4535 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4536 } else {
a866bbf6 4537 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 4538 PCI_DMA_FROMDEVICE);
1da177e4
LT		 4539 tp->Rx_skbuff[entry] = NULL;
4540 }
4541
1da177e4
LT		 4542 skb_put(skb, pkt_size);
4543 skb->protocol = eth_type_trans(skb, dev);
4544
630b943c
ED		 4545 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4546 if (likely(polling))
4547 netif_receive_skb(skb);
4548 else
4549 netif_rx(skb);
4550 }
1da177e4 4551
cebf8cc7
FR		 4552 dev->stats.rx_bytes += pkt_size;
4553 dev->stats.rx_packets++;
1da177e4 4554 }
6dccd16b
FR		 4555
4556 /* Work around for AMD plateform. */
95e0918d 4557 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4558 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4559 desc->opts2 = 0;
4560 cur_rx++;
4561 }
1da177e4
LT		 4562 }
4563
4564 count = cur_rx - tp->cur_rx;
4565 tp->cur_rx = cur_rx;
4566
4567 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
bf82c189
JP		 4568 if (!delta && count)
4569 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
1da177e4
LT		 4570 tp->dirty_rx += delta;
4571
4572 /*
4573 * FIXME: until there is periodic timer to try and refill the ring,
4574 * a temporary shortage may definitely kill the Rx process.
4575 * - disable the asic to try and avoid an overflow and kick it again
4576 * after refill ?
4577 * - how do others driver handle this condition (Uh oh...).
4578 */
bf82c189
JP		 4579 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4580 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
1da177e4
LT		 4581
4582 return count;
4583}
4584
07d3f51f 4585static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4586{
07d3f51f 4587 struct net_device *dev = dev_instance;
1da177e4 4588 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4589 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4590 int handled = 0;
865c652d 4591 int status;
1da177e4 4592
f11a377b
DD		 4593 /* loop handling interrupts until we have no new ones or
4594 * we hit a invalid/hotplug case.
4595 */
865c652d 4596 status = RTL_R16(IntrStatus);
f11a377b
DD		 4597 while (status && status != 0xffff) {
4598 handled = 1;
1da177e4 4599
f11a377b
DD		 4600 /* Handle all of the error cases first. These will reset
4601 * the chip, so just exit the loop.
4602 */
4603 if (unlikely(!netif_running(dev))) {
4604 rtl8169_asic_down(ioaddr);
4605 break;
4606 }
1da177e4 4607
f11a377b
DD		 4608 /* Work around for rx fifo overflow */
4609 if (unlikely(status & RxFIFOOver) &&
4610 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4611 netif_stop_queue(dev);
4612 rtl8169_tx_timeout(dev);
4613 break;
4614 }
1da177e4 4615
f11a377b
DD		 4616 if (unlikely(status & SYSErr)) {
4617 rtl8169_pcierr_interrupt(dev);
4618 break;
4619 }
1da177e4 4620
f11a377b
DD		 4621 if (status & LinkChg)
4622 rtl8169_check_link_status(dev, tp, ioaddr);
0e485150 4623
f11a377b
DD		 4624 /* We need to see the lastest version of tp->intr_mask to
4625 * avoid ignoring an MSI interrupt and having to wait for
4626 * another event which may never come.
4627 */
4628 smp_rmb();
4629 if (status & tp->intr_mask & tp->napi_event) {
4630 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4631 tp->intr_mask = ~tp->napi_event;
4632
4633 if (likely(napi_schedule_prep(&tp->napi)))
4634 __napi_schedule(&tp->napi);
bf82c189
JP		 4635 else
4636 netif_info(tp, intr, dev,
4637 "interrupt %04x in poll\n", status);
f11a377b 4638 }
1da177e4 4639
f11a377b
DD		 4640 /* We only get a new MSI interrupt when all active irq
4641 * sources on the chip have been acknowledged. So, ack
4642 * everything we've seen and check if new sources have become
4643 * active to avoid blocking all interrupts from the chip.
4644 */
4645 RTL_W16(IntrStatus,
4646 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4647 status = RTL_R16(IntrStatus);
865c652d 4648 }
1da177e4 4649
1da177e4
LT		 4650 return IRQ_RETVAL(handled);
4651}
4652
bea3348e 4653static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4654{
bea3348e
SH		 4655 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4656 struct net_device *dev = tp->dev;
1da177e4 4657 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4658 int work_done;
1da177e4 4659
bea3348e 4660 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4661 rtl8169_tx_interrupt(dev, tp, ioaddr);
4662
bea3348e 4663 if (work_done < budget) {
288379f0 4664 napi_complete(napi);
f11a377b
DD		 4665
4666 /* We need for force the visibility of tp->intr_mask
4667 * for other CPUs, as we can loose an MSI interrupt
4668 * and potentially wait for a retransmit timeout if we don't.
4669 * The posted write to IntrMask is safe, as it will
4670 * eventually make it to the chip and we won't loose anything
4671 * until it does.
1da177e4 4672 */
f11a377b 4673 tp->intr_mask = 0xffff;
4c020a96 4674 wmb();
0e485150 4675 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4676 }
4677
bea3348e 4678 return work_done;
1da177e4 4679}
1da177e4 4680
523a6094
FR		 4681static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4682{
4683 struct rtl8169_private *tp = netdev_priv(dev);
4684
4685 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4686 return;
4687
4688 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4689 RTL_W32(RxMissed, 0);
4690}
4691
1da177e4
LT		 4692static void rtl8169_down(struct net_device *dev)
4693{
4694 struct rtl8169_private *tp = netdev_priv(dev);
4695 void __iomem *ioaddr = tp->mmio_addr;
733b736c 4696 unsigned int intrmask;
1da177e4
LT		 4697
4698 rtl8169_delete_timer(dev);
4699
4700 netif_stop_queue(dev);
4701
93dd79e8 4702 napi_disable(&tp->napi);
93dd79e8 4703
1da177e4
LT		 4704core_down:
4705 spin_lock_irq(&tp->lock);
4706
4707 rtl8169_asic_down(ioaddr);
4708
523a6094 4709 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4710
4711 spin_unlock_irq(&tp->lock);
4712
4713 synchronize_irq(dev->irq);
4714
1da177e4 4715 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4716 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 4717
4718 /*
4719 * And now for the 50k$ question: are IRQ disabled or not ?
4720 *
4721 * Two paths lead here:
4722 * 1) dev->close
4723 * -> netif_running() is available to sync the current code and the
4724 * IRQ handler. See rtl8169_interrupt for details.
4725 * 2) dev->change_mtu
4726 * -> rtl8169_poll can not be issued again and re-enable the
4727 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 4728 *
4729 * No loop if hotpluged or major error (0xffff).
1da177e4 4730 */
733b736c
AP		 4731 intrmask = RTL_R16(IntrMask);
4732 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 4733 goto core_down;
4734
4735 rtl8169_tx_clear(tp);
4736
4737 rtl8169_rx_clear(tp);
4738}
4739
4740static int rtl8169_close(struct net_device *dev)
4741{
4742 struct rtl8169_private *tp = netdev_priv(dev);
4743 struct pci_dev *pdev = tp->pci_dev;
4744
e1759441
RW		 4745 pm_runtime_get_sync(&pdev->dev);
4746
355423d0
IV		 4747 /* update counters before going down */
4748 rtl8169_update_counters(dev);
4749
1da177e4
LT		 4750 rtl8169_down(dev);
4751
4752 free_irq(dev->irq, dev);
4753
1da177e4
LT		 4754 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4755 tp->RxPhyAddr);
4756 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4757 tp->TxPhyAddr);
4758 tp->TxDescArray = NULL;
4759 tp->RxDescArray = NULL;
4760
e1759441
RW		 4761 pm_runtime_put_sync(&pdev->dev);
4762
1da177e4
LT		 4763 return 0;
4764}
4765
07ce4064 4766static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4767{
4768 struct rtl8169_private *tp = netdev_priv(dev);
4769 void __iomem *ioaddr = tp->mmio_addr;
4770 unsigned long flags;
4771 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4772 int rx_mode;
1da177e4
LT		 4773 u32 tmp = 0;
4774
4775 if (dev->flags & IFF_PROMISC) {
4776 /* Unconditionally log net taps. */
bf82c189 4777 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4778 rx_mode =
4779 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4780 AcceptAllPhys;
4781 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4782 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4783 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4784 /* Too many to filter perfectly -- accept all multicasts. */
4785 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4786 mc_filter[1] = mc_filter[0] = 0xffffffff;
4787 } else {
4788 struct dev_mc_list *mclist;
07d3f51f 4789
1da177e4
LT		 4790 rx_mode = AcceptBroadcast | AcceptMyPhys;
4791 mc_filter[1] = mc_filter[0] = 0;
f9dcbcc9 4792 netdev_for_each_mc_addr(mclist, dev) {
1da177e4
LT		 4793 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4794 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4795 rx_mode |= AcceptMulticast;
4796 }
4797 }
4798
4799 spin_lock_irqsave(&tp->lock, flags);
4800
4801 tmp = rtl8169_rx_config | rx_mode |
4802 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4803
f887cce8 4804 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4805 u32 data = mc_filter[0];
4806
4807 mc_filter[0] = swab32(mc_filter[1]);
4808 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4809 }
4810
1da177e4
LT		 4811 RTL_W32(MAR0 + 0, mc_filter[0]);
4812 RTL_W32(MAR0 + 4, mc_filter[1]);
4813
57a9f236
FR		 4814 RTL_W32(RxConfig, tmp);
4815
1da177e4
LT		 4816 spin_unlock_irqrestore(&tp->lock, flags);
4817}
4818
4819/**
4820 * rtl8169_get_stats - Get rtl8169 read/write statistics
4821 * @dev: The Ethernet Device to get statistics for
4822 *
4823 * Get TX/RX statistics for rtl8169
4824 */
4825static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4826{
4827 struct rtl8169_private *tp = netdev_priv(dev);
4828 void __iomem *ioaddr = tp->mmio_addr;
4829 unsigned long flags;
4830
4831 if (netif_running(dev)) {
4832 spin_lock_irqsave(&tp->lock, flags);
523a6094 4833 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4834 spin_unlock_irqrestore(&tp->lock, flags);
4835 }
5b0384f4 4836
cebf8cc7 4837 return &dev->stats;
1da177e4
LT		 4838}
4839
861ab440 4840static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4841{
5d06a99f 4842 if (!netif_running(dev))
861ab440 4843 return;
5d06a99f
FR		 4844
4845 netif_device_detach(dev);
4846 netif_stop_queue(dev);
861ab440
RW		 4847}
4848
4849#ifdef CONFIG_PM
4850
4851static int rtl8169_suspend(struct device *device)
4852{
4853 struct pci_dev *pdev = to_pci_dev(device);
4854 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4855
861ab440 4856 rtl8169_net_suspend(dev);
1371fa6d 4857
5d06a99f
FR		 4858 return 0;
4859}
4860
e1759441
RW		 4861static void __rtl8169_resume(struct net_device *dev)
4862{
4863 netif_device_attach(dev);
4864 rtl8169_schedule_work(dev, rtl8169_reset_task);
4865}
4866
861ab440 4867static int rtl8169_resume(struct device *device)
5d06a99f 4868{
861ab440 4869 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 4870 struct net_device *dev = pci_get_drvdata(pdev);
4871
e1759441
RW		 4872 if (netif_running(dev))
4873 __rtl8169_resume(dev);
5d06a99f 4874
e1759441
RW		 4875 return 0;
4876}
4877
4878static int rtl8169_runtime_suspend(struct device *device)
4879{
4880 struct pci_dev *pdev = to_pci_dev(device);
4881 struct net_device *dev = pci_get_drvdata(pdev);
4882 struct rtl8169_private *tp = netdev_priv(dev);
4883
4884 if (!tp->TxDescArray)
4885 return 0;
4886
4887 spin_lock_irq(&tp->lock);
4888 tp->saved_wolopts = __rtl8169_get_wol(tp);
4889 __rtl8169_set_wol(tp, WAKE_ANY);
4890 spin_unlock_irq(&tp->lock);
4891
4892 rtl8169_net_suspend(dev);
4893
4894 return 0;
4895}
4896
4897static int rtl8169_runtime_resume(struct device *device)
4898{
4899 struct pci_dev *pdev = to_pci_dev(device);
4900 struct net_device *dev = pci_get_drvdata(pdev);
4901 struct rtl8169_private *tp = netdev_priv(dev);
4902
4903 if (!tp->TxDescArray)
4904 return 0;
4905
4906 spin_lock_irq(&tp->lock);
4907 __rtl8169_set_wol(tp, tp->saved_wolopts);
4908 tp->saved_wolopts = 0;
4909 spin_unlock_irq(&tp->lock);
4910
4911 __rtl8169_resume(dev);
5d06a99f 4912
5d06a99f
FR		 4913 return 0;
4914}
4915
e1759441
RW		 4916static int rtl8169_runtime_idle(struct device *device)
4917{
4918 struct pci_dev *pdev = to_pci_dev(device);
4919 struct net_device *dev = pci_get_drvdata(pdev);
4920 struct rtl8169_private *tp = netdev_priv(dev);
4921
4922 if (!tp->TxDescArray)
4923 return 0;
4924
4925 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4926 return -EBUSY;
4927}
4928
47145210 4929static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4930 .suspend = rtl8169_suspend,
4931 .resume = rtl8169_resume,
4932 .freeze = rtl8169_suspend,
4933 .thaw = rtl8169_resume,
4934 .poweroff = rtl8169_suspend,
4935 .restore = rtl8169_resume,
e1759441
RW		 4936 .runtime_suspend = rtl8169_runtime_suspend,
4937 .runtime_resume = rtl8169_runtime_resume,
4938 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 4939};
4940
4941#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4942
4943#else /* !CONFIG_PM */
4944
4945#define RTL8169_PM_OPS NULL
4946
4947#endif /* !CONFIG_PM */
4948
1765f95d
FR		 4949static void rtl_shutdown(struct pci_dev *pdev)
4950{
861ab440 4951 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4952 struct rtl8169_private *tp = netdev_priv(dev);
4953 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4954
4955 rtl8169_net_suspend(dev);
1765f95d 4956
cc098dc7
IV		 4957 /* restore original MAC address */
4958 rtl_rar_set(tp, dev->perm_addr);
4959
4bb3f522 4960 spin_lock_irq(&tp->lock);
4961
4962 rtl8169_asic_down(ioaddr);
4963
4964 spin_unlock_irq(&tp->lock);
4965
861ab440 4966 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4967 /* WoL fails with some 8168 when the receiver is disabled. */
4968 if (tp->features & RTL_FEATURE_WOL) {
4969 pci_clear_master(pdev);
4970
4971 RTL_W8(ChipCmd, CmdRxEnb);
4972 /* PCI commit */
4973 RTL_R8(ChipCmd);
4974 }
4975
861ab440
RW		 4976 pci_wake_from_d3(pdev, true);
4977 pci_set_power_state(pdev, PCI_D3hot);
4978 }
4979}
5d06a99f 4980
1da177e4
LT		 4981static struct pci_driver rtl8169_pci_driver = {
4982 .name = MODULENAME,
4983 .id_table = rtl8169_pci_tbl,
4984 .probe = rtl8169_init_one,
4985 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4986 .shutdown = rtl_shutdown,
861ab440 4987 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 4988};
4989
07d3f51f 4990static int __init rtl8169_init_module(void)
1da177e4 4991{
29917620 4992 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 4993}
4994
07d3f51f 4995static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 4996{
4997 pci_unregister_driver(&rtl8169_pci_driver);
4998}
4999
5000module_init(rtl8169_init_module);
5001module_exit(rtl8169_cleanup_module);
Clone of davem's net-next-2.6 tree