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KVM: i8259: simplify pic_irq_request() calling sequence
[net-next-2.6.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
221d059d 7 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
6aa8b732 34
63d1142f 35#include <asm/virtext.h>
229456fc 36#include "trace.h"
63d1142f 37
4ecac3fd
AK		 38#define __ex(x) __kvm_handle_fault_on_reboot(x)
39
6aa8b732
AK		 40MODULE_AUTHOR("Qumranet");
41MODULE_LICENSE("GPL");
42
43#define IOPM_ALLOC_ORDER 2
44#define MSRPM_ALLOC_ORDER 1
45
6aa8b732
AK		 46#define SEG_TYPE_LDT 2
47#define SEG_TYPE_BUSY_TSS16 3
48
6bc31bdc
AP		 49#define SVM_FEATURE_NPT (1 << 0)
50#define SVM_FEATURE_LBRV (1 << 1)
51#define SVM_FEATURE_SVML (1 << 2)
52#define SVM_FEATURE_NRIP (1 << 3)
53#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 54
410e4d57
JR		 55#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
56#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
57#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
58
24e09cbf
JR		 59#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
60
67ec6607
JR		 61static bool erratum_383_found __read_mostly;
62
6c8166a7
AK		 63static const u32 host_save_user_msrs[] = {
64#ifdef CONFIG_X86_64
65 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
66 MSR_FS_BASE,
67#endif
68 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
69};
70
71#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
72
73struct kvm_vcpu;
74
e6aa9abd
JR		 75struct nested_state {
76 struct vmcb *hsave;
77 u64 hsave_msr;
4a810181 78 u64 vm_cr_msr;
e6aa9abd
JR		 79 u64 vmcb;
80
81 /* These are the merged vectors */
82 u32 *msrpm;
83
84 /* gpa pointers to the real vectors */
85 u64 vmcb_msrpm;
ce2ac085 86 u64 vmcb_iopm;
aad42c64 87
cd3ff653
JR		 88 /* A VMEXIT is required but not yet emulated */
89 bool exit_required;
90
aad42c64
JR		 91 /* cache for intercepts of the guest */
92 u16 intercept_cr_read;
93 u16 intercept_cr_write;
94 u16 intercept_dr_read;
95 u16 intercept_dr_write;
96 u32 intercept_exceptions;
97 u64 intercept;
98
e6aa9abd
JR		 99};
100
323c3d80
JR		 101#define MSRPM_OFFSETS 16
102static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
103
6c8166a7
AK		 104struct vcpu_svm {
105 struct kvm_vcpu vcpu;
106 struct vmcb *vmcb;
107 unsigned long vmcb_pa;
108 struct svm_cpu_data *svm_data;
109 uint64_t asid_generation;
110 uint64_t sysenter_esp;
111 uint64_t sysenter_eip;
112
113 u64 next_rip;
114
115 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
116 u64 host_gs_base;
6c8166a7
AK		 117
118 u32 *msrpm;
6c8166a7 119
e6aa9abd 120 struct nested_state nested;
6be7d306
JK		 121
122 bool nmi_singlestep;
66b7138f
JK		 123
124 unsigned int3_injected;
125 unsigned long int3_rip;
6c8166a7
AK		 126};
127
455716fa
JR		 128#define MSR_INVALID 0xffffffffU
129
ac72a9b7
JR		 130static struct svm_direct_access_msrs {
131 u32 index; /* Index of the MSR */
132 bool always; /* True if intercept is always on */
133} direct_access_msrs[] = {
134 { .index = MSR_K6_STAR, .always = true },
135 { .index = MSR_IA32_SYSENTER_CS, .always = true },
136#ifdef CONFIG_X86_64
137 { .index = MSR_GS_BASE, .always = true },
138 { .index = MSR_FS_BASE, .always = true },
139 { .index = MSR_KERNEL_GS_BASE, .always = true },
140 { .index = MSR_LSTAR, .always = true },
141 { .index = MSR_CSTAR, .always = true },
142 { .index = MSR_SYSCALL_MASK, .always = true },
143#endif
144 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
145 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
146 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
147 { .index = MSR_IA32_LASTINTTOIP, .always = false },
148 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 149};
150
709ddebf
JR		 151/* enable NPT for AMD64 and X86 with PAE */
152#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
153static bool npt_enabled = true;
154#else
e0231715 155static bool npt_enabled;
709ddebf 156#endif
6c7dac72
JR		 157static int npt = 1;
158
159module_param(npt, int, S_IRUGO);
e3da3acd 160
4b6e4dca 161static int nested = 1;
236de055
AG		 162module_param(nested, int, S_IRUGO);
163
44874f84 164static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 165static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 166
410e4d57 167static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 168static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 169static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 170static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
171 bool has_error_code, u32 error_code);
172
a2fa3e9f
GH		 173static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
174{
fb3f0f51 175 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 176}
177
3d6368ef
AG		 178static inline bool is_nested(struct vcpu_svm *svm)
179{
e6aa9abd 180 return svm->nested.vmcb;
3d6368ef
AG		 181}
182
2af9194d
JR		 183static inline void enable_gif(struct vcpu_svm *svm)
184{
185 svm->vcpu.arch.hflags |= HF_GIF_MASK;
186}
187
188static inline void disable_gif(struct vcpu_svm *svm)
189{
190 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
191}
192
193static inline bool gif_set(struct vcpu_svm *svm)
194{
195 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
196}
197
4866d5e3 198static unsigned long iopm_base;
6aa8b732
AK		 199
200struct kvm_ldttss_desc {
201 u16 limit0;
202 u16 base0;
e0231715
JR		 203 unsigned base1:8, type:5, dpl:2, p:1;
204 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 205 u32 base3;
206 u32 zero1;
207} __attribute__((packed));
208
209struct svm_cpu_data {
210 int cpu;
211
5008fdf5
AK		 212 u64 asid_generation;
213 u32 max_asid;
214 u32 next_asid;
6aa8b732
AK		 215 struct kvm_ldttss_desc *tss_desc;
216
217 struct page *save_area;
218};
219
220static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 221static uint32_t svm_features;
6aa8b732
AK		 222
223struct svm_init_data {
224 int cpu;
225 int r;
226};
227
228static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
229
9d8f549d 230#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 231#define MSRS_RANGE_SIZE 2048
232#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
233
455716fa
JR		 234static u32 svm_msrpm_offset(u32 msr)
235{
236 u32 offset;
237 int i;
238
239 for (i = 0; i < NUM_MSR_MAPS; i++) {
240 if (msr < msrpm_ranges[i] ||
241 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
242 continue;
243
244 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
245 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
246
247 /* Now we have the u8 offset - but need the u32 offset */
248 return offset / 4;
249 }
250
251 /* MSR not in any range */
252 return MSR_INVALID;
253}
254
6aa8b732
AK		 255#define MAX_INST_SIZE 15
256
80b7706e
JR		 257static inline u32 svm_has(u32 feat)
258{
259 return svm_features & feat;
260}
261
6aa8b732
AK		 262static inline void clgi(void)
263{
4ecac3fd 264 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 265}
266
267static inline void stgi(void)
268{
4ecac3fd 269 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 270}
271
272static inline void invlpga(unsigned long addr, u32 asid)
273{
e0231715 274 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 275}
276
6aa8b732
AK		 277static inline void force_new_asid(struct kvm_vcpu *vcpu)
278{
a2fa3e9f 279 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 280}
281
282static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
283{
284 force_new_asid(vcpu);
285}
286
287static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
288{
6dc696d4 289 vcpu->arch.efer = efer;
709ddebf 290 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 291 efer &= ~EFER_LME;
6aa8b732 292
9962d032 293 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 294}
295
6aa8b732
AK		 296static int is_external_interrupt(u32 info)
297{
298 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
299 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
300}
301
2809f5d2
GC		 302static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
303{
304 struct vcpu_svm *svm = to_svm(vcpu);
305 u32 ret = 0;
306
307 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 308 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 309 return ret & mask;
310}
311
312static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
313{
314 struct vcpu_svm *svm = to_svm(vcpu);
315
316 if (mask == 0)
317 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
318 else
319 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
320
321}
322
6aa8b732
AK		 323static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
324{
a2fa3e9f
GH		 325 struct vcpu_svm *svm = to_svm(vcpu);
326
6bc31bdc
AP		 327 if (svm->vmcb->control.next_rip != 0)
328 svm->next_rip = svm->vmcb->control.next_rip;
329
a2fa3e9f 330 if (!svm->next_rip) {
851ba692 331 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 332 EMULATE_DONE)
333 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 334 return;
335 }
5fdbf976
MT		 336 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
337 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
338 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 339
5fdbf976 340 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 341 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 342}
343
116a4752 344static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 345 bool has_error_code, u32 error_code,
346 bool reinject)
116a4752
JK		 347{
348 struct vcpu_svm *svm = to_svm(vcpu);
349
e0231715
JR		 350 /*
351 * If we are within a nested VM we'd better #VMEXIT and let the guest
352 * handle the exception
353 */
ce7ddec4
JR		 354 if (!reinject &&
355 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 356 return;
357
66b7138f
JK		 358 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
359 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
360
361 /*
362 * For guest debugging where we have to reinject #BP if some
363 * INT3 is guest-owned:
364 * Emulate nRIP by moving RIP forward. Will fail if injection
365 * raises a fault that is not intercepted. Still better than
366 * failing in all cases.
367 */
368 skip_emulated_instruction(&svm->vcpu);
369 rip = kvm_rip_read(&svm->vcpu);
370 svm->int3_rip = rip + svm->vmcb->save.cs.base;
371 svm->int3_injected = rip - old_rip;
372 }
373
116a4752
JK		 374 svm->vmcb->control.event_inj = nr
375 | SVM_EVTINJ_VALID
376 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
377 | SVM_EVTINJ_TYPE_EXEPT;
378 svm->vmcb->control.event_inj_err = error_code;
379}
380
67ec6607
JR		 381static void svm_init_erratum_383(void)
382{
383 u32 low, high;
384 int err;
385 u64 val;
386
387 /* Only Fam10h is affected */
388 if (boot_cpu_data.x86 != 0x10)
389 return;
390
391 /* Use _safe variants to not break nested virtualization */
392 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
393 if (err)
394 return;
395
396 val |= (1ULL << 47);
397
398 low = lower_32_bits(val);
399 high = upper_32_bits(val);
400
401 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
402
403 erratum_383_found = true;
404}
405
6aa8b732
AK		 406static int has_svm(void)
407{
63d1142f 408 const char *msg;
6aa8b732 409
63d1142f 410 if (!cpu_has_svm(&msg)) {
ff81ff10 411 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 412 return 0;
413 }
414
6aa8b732
AK		 415 return 1;
416}
417
418static void svm_hardware_disable(void *garbage)
419{
2c8dceeb 420 cpu_svm_disable();
6aa8b732
AK		 421}
422
10474ae8 423static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 424{
425
0fe1e009 426 struct svm_cpu_data *sd;
6aa8b732 427 uint64_t efer;
89a27f4d 428 struct desc_ptr gdt_descr;
6aa8b732
AK		 429 struct desc_struct *gdt;
430 int me = raw_smp_processor_id();
431
10474ae8
AG		 432 rdmsrl(MSR_EFER, efer);
433 if (efer & EFER_SVME)
434 return -EBUSY;
435
6aa8b732 436 if (!has_svm()) {
e6732a5a
ZA		 437 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
438 me);
10474ae8 439 return -EINVAL;
6aa8b732 440 }
0fe1e009 441 sd = per_cpu(svm_data, me);
6aa8b732 442
0fe1e009 443 if (!sd) {
e6732a5a 444 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 445 me);
10474ae8 446 return -EINVAL;
6aa8b732
AK		 447 }
448
0fe1e009
TH		 449 sd->asid_generation = 1;
450 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
451 sd->next_asid = sd->max_asid + 1;
6aa8b732 452
d6ab1ed4 453 native_store_gdt(&gdt_descr);
89a27f4d 454 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 455 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 456
9962d032 457 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 458
d0316554 459 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 460
67ec6607
JR		 461 svm_init_erratum_383();
462
10474ae8 463 return 0;
6aa8b732
AK		 464}
465
0da1db75
JR		 466static void svm_cpu_uninit(int cpu)
467{
0fe1e009 468 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 469
0fe1e009 470 if (!sd)
0da1db75
JR		 471 return;
472
473 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 474 __free_page(sd->save_area);
475 kfree(sd);
0da1db75
JR		 476}
477
6aa8b732
AK		 478static int svm_cpu_init(int cpu)
479{
0fe1e009 480 struct svm_cpu_data *sd;
6aa8b732
AK		 481 int r;
482
0fe1e009
TH		 483 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
484 if (!sd)
6aa8b732 485 return -ENOMEM;
0fe1e009
TH		 486 sd->cpu = cpu;
487 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 488 r = -ENOMEM;
0fe1e009 489 if (!sd->save_area)
6aa8b732
AK		 490 goto err_1;
491
0fe1e009 492 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 493
494 return 0;
495
496err_1:
0fe1e009 497 kfree(sd);
6aa8b732
AK		 498 return r;
499
500}
501
ac72a9b7
JR		 502static bool valid_msr_intercept(u32 index)
503{
504 int i;
505
506 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
507 if (direct_access_msrs[i].index == index)
508 return true;
509
510 return false;
511}
512
bfc733a7
RR		 513static void set_msr_interception(u32 *msrpm, unsigned msr,
514 int read, int write)
6aa8b732 515{
455716fa
JR		 516 u8 bit_read, bit_write;
517 unsigned long tmp;
518 u32 offset;
6aa8b732 519
ac72a9b7
JR		 520 /*
521 * If this warning triggers extend the direct_access_msrs list at the
522 * beginning of the file
523 */
524 WARN_ON(!valid_msr_intercept(msr));
525
455716fa
JR		 526 offset = svm_msrpm_offset(msr);
527 bit_read = 2 * (msr & 0x0f);
528 bit_write = 2 * (msr & 0x0f) + 1;
529 tmp = msrpm[offset];
530
531 BUG_ON(offset == MSR_INVALID);
532
533 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
534 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
535
536 msrpm[offset] = tmp;
6aa8b732
AK		 537}
538
f65c229c 539static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 540{
541 int i;
542
f65c229c
JR		 543 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
544
ac72a9b7
JR		 545 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
546 if (!direct_access_msrs[i].always)
547 continue;
548
549 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
550 }
f65c229c
JR		 551}
552
323c3d80
JR		 553static void add_msr_offset(u32 offset)
554{
555 int i;
556
557 for (i = 0; i < MSRPM_OFFSETS; ++i) {
558
559 /* Offset already in list? */
560 if (msrpm_offsets[i] == offset)
bfc733a7 561 return;
323c3d80
JR		 562
563 /* Slot used by another offset? */
564 if (msrpm_offsets[i] != MSR_INVALID)
565 continue;
566
567 /* Add offset to list */
568 msrpm_offsets[i] = offset;
569
570 return;
6aa8b732 571 }
323c3d80
JR		 572
573 /*
574 * If this BUG triggers the msrpm_offsets table has an overflow. Just
575 * increase MSRPM_OFFSETS in this case.
576 */
bfc733a7 577 BUG();
6aa8b732
AK		 578}
579
323c3d80 580static void init_msrpm_offsets(void)
f65c229c 581{
323c3d80 582 int i;
f65c229c 583
323c3d80
JR		 584 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
585
586 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
587 u32 offset;
588
589 offset = svm_msrpm_offset(direct_access_msrs[i].index);
590 BUG_ON(offset == MSR_INVALID);
591
592 add_msr_offset(offset);
593 }
f65c229c
JR		 594}
595
24e09cbf
JR		 596static void svm_enable_lbrv(struct vcpu_svm *svm)
597{
598 u32 *msrpm = svm->msrpm;
599
600 svm->vmcb->control.lbr_ctl = 1;
601 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
602 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
603 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
604 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
605}
606
607static void svm_disable_lbrv(struct vcpu_svm *svm)
608{
609 u32 *msrpm = svm->msrpm;
610
611 svm->vmcb->control.lbr_ctl = 0;
612 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
613 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
614 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
615 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
616}
617
6aa8b732
AK		 618static __init int svm_hardware_setup(void)
619{
620 int cpu;
621 struct page *iopm_pages;
f65c229c 622 void *iopm_va;
6aa8b732
AK		 623 int r;
624
6aa8b732
AK		 625 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
626
627 if (!iopm_pages)
628 return -ENOMEM;
c8681339
AL		 629
630 iopm_va = page_address(iopm_pages);
631 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 632 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
633
323c3d80
JR		 634 init_msrpm_offsets();
635
50a37eb4
JR		 636 if (boot_cpu_has(X86_FEATURE_NX))
637 kvm_enable_efer_bits(EFER_NX);
638
1b2fd70c
AG		 639 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
640 kvm_enable_efer_bits(EFER_FFXSR);
641
236de055
AG		 642 if (nested) {
643 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 644 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 645 }
646
3230bb47 647 for_each_possible_cpu(cpu) {
6aa8b732
AK		 648 r = svm_cpu_init(cpu);
649 if (r)
f65c229c 650 goto err;
6aa8b732 651 }
33bd6a0b
JR		 652
653 svm_features = cpuid_edx(SVM_CPUID_FUNC);
654
e3da3acd
JR		 655 if (!svm_has(SVM_FEATURE_NPT))
656 npt_enabled = false;
657
6c7dac72
JR		 658 if (npt_enabled && !npt) {
659 printk(KERN_INFO "kvm: Nested Paging disabled\n");
660 npt_enabled = false;
661 }
662
18552672 663 if (npt_enabled) {
e3da3acd 664 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 665 kvm_enable_tdp();
5f4cb662
JR		 666 } else
667 kvm_disable_tdp();
e3da3acd 668
6aa8b732
AK		 669 return 0;
670
f65c229c 671err:
6aa8b732
AK		 672 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
673 iopm_base = 0;
674 return r;
675}
676
677static __exit void svm_hardware_unsetup(void)
678{
0da1db75
JR		 679 int cpu;
680
3230bb47 681 for_each_possible_cpu(cpu)
0da1db75
JR		 682 svm_cpu_uninit(cpu);
683
6aa8b732 684 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 685 iopm_base = 0;
6aa8b732
AK		 686}
687
688static void init_seg(struct vmcb_seg *seg)
689{
690 seg->selector = 0;
691 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 692 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 693 seg->limit = 0xffff;
694 seg->base = 0;
695}
696
697static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
698{
699 seg->selector = 0;
700 seg->attrib = SVM_SELECTOR_P_MASK | type;
701 seg->limit = 0xffff;
702 seg->base = 0;
703}
704
e6101a96 705static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 706{
e6101a96
JR		 707 struct vmcb_control_area *control = &svm->vmcb->control;
708 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 709
bff78274
AK		 710 svm->vcpu.fpu_active = 1;
711
e0231715 712 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 713 INTERCEPT_CR3_MASK |
649d6864 714 INTERCEPT_CR4_MASK;
6aa8b732 715
e0231715 716 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 717 INTERCEPT_CR3_MASK |
80a8119c
AK		 718 INTERCEPT_CR4_MASK |
719 INTERCEPT_CR8_MASK;
6aa8b732 720
e0231715 721 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 722 INTERCEPT_DR1_MASK |
723 INTERCEPT_DR2_MASK |
727f5a23
JK		 724 INTERCEPT_DR3_MASK |
725 INTERCEPT_DR4_MASK |
726 INTERCEPT_DR5_MASK |
727 INTERCEPT_DR6_MASK |
728 INTERCEPT_DR7_MASK;
6aa8b732 729
e0231715 730 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 731 INTERCEPT_DR1_MASK |
732 INTERCEPT_DR2_MASK |
733 INTERCEPT_DR3_MASK |
727f5a23 734 INTERCEPT_DR4_MASK |
6aa8b732 735 INTERCEPT_DR5_MASK |
727f5a23 736 INTERCEPT_DR6_MASK |
6aa8b732
AK		 737 INTERCEPT_DR7_MASK;
738
7aa81cc0 739 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 740 (1 << UD_VECTOR) |
741 (1 << MC_VECTOR);
6aa8b732
AK		 742
743
e0231715 744 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 745 (1ULL << INTERCEPT_NMI) |
0152527b 746 (1ULL << INTERCEPT_SMI) |
d225157b 747 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 748 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 749 (1ULL << INTERCEPT_INVD) |
6aa8b732 750 (1ULL << INTERCEPT_HLT) |
a7052897 751 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 752 (1ULL << INTERCEPT_INVLPGA) |
753 (1ULL << INTERCEPT_IOIO_PROT) |
754 (1ULL << INTERCEPT_MSR_PROT) |
755 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 756 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 757 (1ULL << INTERCEPT_VMRUN) |
758 (1ULL << INTERCEPT_VMMCALL) |
759 (1ULL << INTERCEPT_VMLOAD) |
760 (1ULL << INTERCEPT_VMSAVE) |
761 (1ULL << INTERCEPT_STGI) |
762 (1ULL << INTERCEPT_CLGI) |
916ce236 763 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 764 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 765 (1ULL << INTERCEPT_MONITOR) |
766 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 767
768 control->iopm_base_pa = iopm_base;
f65c229c 769 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 770 control->tsc_offset = 0;
6aa8b732
AK		 771 control->int_ctl = V_INTR_MASKING_MASK;
772
773 init_seg(&save->es);
774 init_seg(&save->ss);
775 init_seg(&save->ds);
776 init_seg(&save->fs);
777 init_seg(&save->gs);
778
779 save->cs.selector = 0xf000;
780 /* Executable/Readable Code Segment */
781 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
782 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
783 save->cs.limit = 0xffff;
d92899a0
AK		 784 /*
785 * cs.base should really be 0xffff0000, but vmx can't handle that, so
786 * be consistent with it.
787 *
788 * Replace when we have real mode working for vmx.
789 */
790 save->cs.base = 0xf0000;
6aa8b732
AK		 791
792 save->gdtr.limit = 0xffff;
793 save->idtr.limit = 0xffff;
794
795 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
796 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
797
9962d032 798 save->efer = EFER_SVME;
d77c26fc 799 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 800 save->dr7 = 0x400;
801 save->rflags = 2;
802 save->rip = 0x0000fff0;
5fdbf976 803 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 804
e0231715
JR		 805 /*
806 * This is the guest-visible cr0 value.
18fa000a 807 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 808 */
18fa000a 809 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
49a9b07e 810 (void)kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
18fa000a 811
66aee91a 812 save->cr4 = X86_CR4_PAE;
6aa8b732 813 /* rdx = ?? */
709ddebf
JR		 814
815 if (npt_enabled) {
816 /* Setup VMCB for Nested Paging */
817 control->nested_ctl = 1;
a7052897
MT		 818 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
819 (1ULL << INTERCEPT_INVLPG));
709ddebf 820 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 821 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
822 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 823 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 824 save->cr3 = 0;
825 save->cr4 = 0;
826 }
a79d2f18 827 force_new_asid(&svm->vcpu);
1371d904 828
e6aa9abd 829 svm->nested.vmcb = 0;
2af9194d
JR		 830 svm->vcpu.arch.hflags = 0;
831
565d0998
ML		 832 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
833 control->pause_filter_count = 3000;
834 control->intercept |= (1ULL << INTERCEPT_PAUSE);
835 }
836
2af9194d 837 enable_gif(svm);
6aa8b732
AK		 838}
839
e00c8cf2 840static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 841{
842 struct vcpu_svm *svm = to_svm(vcpu);
843
e6101a96 844 init_vmcb(svm);
70433389 845
c5af89b6 846 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 847 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 848 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
849 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 850 }
5fdbf976
MT		 851 vcpu->arch.regs_avail = ~0;
852 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 853
854 return 0;
04d2cc77
AK		 855}
856
fb3f0f51 857static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 858{
a2fa3e9f 859 struct vcpu_svm *svm;
6aa8b732 860 struct page *page;
f65c229c 861 struct page *msrpm_pages;
b286d5d8 862 struct page *hsave_page;
3d6368ef 863 struct page *nested_msrpm_pages;
fb3f0f51 864 int err;
6aa8b732 865
c16f862d 866 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 867 if (!svm) {
868 err = -ENOMEM;
869 goto out;
870 }
871
872 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
873 if (err)
874 goto free_svm;
875
b7af4043 876 err = -ENOMEM;
6aa8b732 877 page = alloc_page(GFP_KERNEL);
b7af4043 878 if (!page)
fb3f0f51 879 goto uninit;
6aa8b732 880
f65c229c
JR		 881 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
882 if (!msrpm_pages)
b7af4043 883 goto free_page1;
3d6368ef
AG		 884
885 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
886 if (!nested_msrpm_pages)
b7af4043 887 goto free_page2;
f65c229c 888
b286d5d8
AG		 889 hsave_page = alloc_page(GFP_KERNEL);
890 if (!hsave_page)
b7af4043
TY		 891 goto free_page3;
892
e6aa9abd 893 svm->nested.hsave = page_address(hsave_page);
b286d5d8 894
b7af4043
TY		 895 svm->msrpm = page_address(msrpm_pages);
896 svm_vcpu_init_msrpm(svm->msrpm);
897
e6aa9abd 898 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 899 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 900
a2fa3e9f
GH		 901 svm->vmcb = page_address(page);
902 clear_page(svm->vmcb);
903 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
904 svm->asid_generation = 0;
e6101a96 905 init_vmcb(svm);
a2fa3e9f 906
10ab25cd
JK		 907 err = fx_init(&svm->vcpu);
908 if (err)
909 goto free_page4;
910
ad312c7c 911 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 912 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 913 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 914
fb3f0f51 915 return &svm->vcpu;
36241b8c 916
10ab25cd
JK		 917free_page4:
918 __free_page(hsave_page);
b7af4043
TY		 919free_page3:
920 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
921free_page2:
922 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
923free_page1:
924 __free_page(page);
fb3f0f51
RR		 925uninit:
926 kvm_vcpu_uninit(&svm->vcpu);
927free_svm:
a4770347 928 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 929out:
930 return ERR_PTR(err);
6aa8b732
AK		 931}
932
933static void svm_free_vcpu(struct kvm_vcpu *vcpu)
934{
a2fa3e9f
GH		 935 struct vcpu_svm *svm = to_svm(vcpu);
936
fb3f0f51 937 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 938 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 939 __free_page(virt_to_page(svm->nested.hsave));
940 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 941 kvm_vcpu_uninit(vcpu);
a4770347 942 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 943}
944
15ad7146 945static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 946{
a2fa3e9f 947 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 948 int i;
0cc5064d 949
0cc5064d 950 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 951 u64 delta;
0cc5064d 952
953899b6
JR		 953 if (check_tsc_unstable()) {
954 /*
955 * Make sure that the guest sees a monotonically
956 * increasing TSC.
957 */
958 delta = vcpu->arch.host_tsc - native_read_tsc();
959 svm->vmcb->control.tsc_offset += delta;
960 if (is_nested(svm))
961 svm->nested.hsave->control.tsc_offset += delta;
962 }
0cc5064d 963 vcpu->cpu = cpu;
2f599714 964 kvm_migrate_timers(vcpu);
4b656b12 965 svm->asid_generation = 0;
0cc5064d 966 }
94dfbdb3
AL		 967
968 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 969 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 970}
971
972static void svm_vcpu_put(struct kvm_vcpu *vcpu)
973{
a2fa3e9f 974 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 975 int i;
976
e1beb1d3 977 ++vcpu->stat.host_state_reload;
94dfbdb3 978 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 979 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 980
e935d48e 981 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 982}
983
6aa8b732
AK		 984static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
985{
a2fa3e9f 986 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 987}
988
989static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
990{
a2fa3e9f 991 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 992}
993
6de4f3ad
AK		 994static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
995{
996 switch (reg) {
997 case VCPU_EXREG_PDPTR:
998 BUG_ON(!npt_enabled);
999 load_pdptrs(vcpu, vcpu->arch.cr3);
1000 break;
1001 default:
1002 BUG();
1003 }
1004}
1005
f0b85051
AG		 1006static void svm_set_vintr(struct vcpu_svm *svm)
1007{
1008 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1009}
1010
1011static void svm_clear_vintr(struct vcpu_svm *svm)
1012{
1013 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1014}
1015
6aa8b732
AK		 1016static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1017{
a2fa3e9f 1018 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1019
1020 switch (seg) {
1021 case VCPU_SREG_CS: return &save->cs;
1022 case VCPU_SREG_DS: return &save->ds;
1023 case VCPU_SREG_ES: return &save->es;
1024 case VCPU_SREG_FS: return &save->fs;
1025 case VCPU_SREG_GS: return &save->gs;
1026 case VCPU_SREG_SS: return &save->ss;
1027 case VCPU_SREG_TR: return &save->tr;
1028 case VCPU_SREG_LDTR: return &save->ldtr;
1029 }
1030 BUG();
8b6d44c7 1031 return NULL;
6aa8b732
AK		 1032}
1033
1034static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1035{
1036 struct vmcb_seg *s = svm_seg(vcpu, seg);
1037
1038 return s->base;
1039}
1040
1041static void svm_get_segment(struct kvm_vcpu *vcpu,
1042 struct kvm_segment *var, int seg)
1043{
1044 struct vmcb_seg *s = svm_seg(vcpu, seg);
1045
1046 var->base = s->base;
1047 var->limit = s->limit;
1048 var->selector = s->selector;
1049 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1050 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1051 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1052 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1053 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1054 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1055 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1056 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1057
e0231715
JR		 1058 /*
1059 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1060 * for cross vendor migration purposes by "not present"
1061 */
1062 var->unusable = !var->present || (var->type == 0);
1063
1fbdc7a5
AP		 1064 switch (seg) {
1065 case VCPU_SREG_CS:
1066 /*
1067 * SVM always stores 0 for the 'G' bit in the CS selector in
1068 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1069 * Intel's VMENTRY has a check on the 'G' bit.
1070 */
25022acc 1071 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1072 break;
1073 case VCPU_SREG_TR:
1074 /*
1075 * Work around a bug where the busy flag in the tr selector
1076 * isn't exposed
1077 */
c0d09828 1078 var->type |= 0x2;
1fbdc7a5
AP		 1079 break;
1080 case VCPU_SREG_DS:
1081 case VCPU_SREG_ES:
1082 case VCPU_SREG_FS:
1083 case VCPU_SREG_GS:
1084 /*
1085 * The accessed bit must always be set in the segment
1086 * descriptor cache, although it can be cleared in the
1087 * descriptor, the cached bit always remains at 1. Since
1088 * Intel has a check on this, set it here to support
1089 * cross-vendor migration.
1090 */
1091 if (!var->unusable)
1092 var->type |= 0x1;
1093 break;
b586eb02 1094 case VCPU_SREG_SS:
e0231715
JR		 1095 /*
1096 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1097 * descriptor is left as 1, although the whole segment has
1098 * been made unusable. Clear it here to pass an Intel VMX
1099 * entry check when cross vendor migrating.
1100 */
1101 if (var->unusable)
1102 var->db = 0;
1103 break;
1fbdc7a5 1104 }
6aa8b732
AK		 1105}
1106
2e4d2653
IE		 1107static int svm_get_cpl(struct kvm_vcpu *vcpu)
1108{
1109 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1110
1111 return save->cpl;
1112}
1113
89a27f4d 1114static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1115{
a2fa3e9f
GH		 1116 struct vcpu_svm *svm = to_svm(vcpu);
1117
89a27f4d
GN		 1118 dt->size = svm->vmcb->save.idtr.limit;
1119 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1120}
1121
89a27f4d 1122static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1123{
a2fa3e9f
GH		 1124 struct vcpu_svm *svm = to_svm(vcpu);
1125
89a27f4d
GN		 1126 svm->vmcb->save.idtr.limit = dt->size;
1127 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1128}
1129
89a27f4d 1130static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1131{
a2fa3e9f
GH		 1132 struct vcpu_svm *svm = to_svm(vcpu);
1133
89a27f4d
GN		 1134 dt->size = svm->vmcb->save.gdtr.limit;
1135 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1136}
1137
89a27f4d 1138static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1139{
a2fa3e9f
GH		 1140 struct vcpu_svm *svm = to_svm(vcpu);
1141
89a27f4d
GN		 1142 svm->vmcb->save.gdtr.limit = dt->size;
1143 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1144}
1145
e8467fda
AK		 1146static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1147{
1148}
1149
25c4c276 1150static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1151{
1152}
1153
d225157b
AK		 1154static void update_cr0_intercept(struct vcpu_svm *svm)
1155{
66a562f7 1156 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1157 ulong gcr0 = svm->vcpu.arch.cr0;
1158 u64 *hcr0 = &svm->vmcb->save.cr0;
1159
1160 if (!svm->vcpu.fpu_active)
1161 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1162 else
1163 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1164 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1165
1166
1167 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1168 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1169 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1170 if (is_nested(svm)) {
1171 struct vmcb *hsave = svm->nested.hsave;
1172
1173 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1174 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1175 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1176 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1177 }
d225157b
AK		 1178 } else {
1179 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1180 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1181 if (is_nested(svm)) {
1182 struct vmcb *hsave = svm->nested.hsave;
1183
1184 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1185 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1186 }
d225157b
AK		 1187 }
1188}
1189
6aa8b732
AK		 1190static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1191{
a2fa3e9f
GH		 1192 struct vcpu_svm *svm = to_svm(vcpu);
1193
7f5d8b56
JR		 1194 if (is_nested(svm)) {
1195 /*
1196 * We are here because we run in nested mode, the host kvm
1197 * intercepts cr0 writes but the l1 hypervisor does not.
1198 * But the L1 hypervisor may intercept selective cr0 writes.
1199 * This needs to be checked here.
1200 */
1201 unsigned long old, new;
1202
1203 /* Remove bits that would trigger a real cr0 write intercept */
1204 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1205 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1206
1207 if (old == new) {
1208 /* cr0 write with ts and mp unchanged */
1209 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1210 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1211 return;
1212 }
1213 }
1214
05b3e0c2 1215#ifdef CONFIG_X86_64
f6801dff 1216 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1217 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1218 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1219 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1220 }
1221
d77c26fc 1222 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1223 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1224 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1225 }
1226 }
1227#endif
ad312c7c 1228 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1229
1230 if (!npt_enabled)
1231 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1232
1233 if (!vcpu->fpu_active)
334df50a 1234 cr0 |= X86_CR0_TS;
709ddebf
JR		 1235 /*
1236 * re-enable caching here because the QEMU bios
1237 * does not do it - this results in some delay at
1238 * reboot
1239 */
1240 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1241 svm->vmcb->save.cr0 = cr0;
d225157b 1242 update_cr0_intercept(svm);
6aa8b732
AK		 1243}
1244
1245static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1246{
6394b649 1247 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1248 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1249
1250 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1251 force_new_asid(vcpu);
6394b649 1252
ec077263
JR		 1253 vcpu->arch.cr4 = cr4;
1254 if (!npt_enabled)
1255 cr4 |= X86_CR4_PAE;
6394b649 1256 cr4 |= host_cr4_mce;
ec077263 1257 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1258}
1259
1260static void svm_set_segment(struct kvm_vcpu *vcpu,
1261 struct kvm_segment *var, int seg)
1262{
a2fa3e9f 1263 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1264 struct vmcb_seg *s = svm_seg(vcpu, seg);
1265
1266 s->base = var->base;
1267 s->limit = var->limit;
1268 s->selector = var->selector;
1269 if (var->unusable)
1270 s->attrib = 0;
1271 else {
1272 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1273 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1274 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1275 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1276 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1277 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1278 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1279 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1280 }
1281 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1282 svm->vmcb->save.cpl
1283 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1284 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1285
1286}
1287
44c11430 1288static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1289{
d0bfb940
JK		 1290 struct vcpu_svm *svm = to_svm(vcpu);
1291
d0bfb940
JK		 1292 svm->vmcb->control.intercept_exceptions &=
1293 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1294
6be7d306 1295 if (svm->nmi_singlestep)
44c11430
GN		 1296 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1297
d0bfb940
JK		 1298 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1299 if (vcpu->guest_debug &
1300 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1301 svm->vmcb->control.intercept_exceptions |=
1302 1 << DB_VECTOR;
1303 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1304 svm->vmcb->control.intercept_exceptions |=
1305 1 << BP_VECTOR;
1306 } else
1307 vcpu->guest_debug = 0;
44c11430
GN		 1308}
1309
355be0b9 1310static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1311{
44c11430
GN		 1312 struct vcpu_svm *svm = to_svm(vcpu);
1313
ae675ef0
JK		 1314 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1315 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1316 else
1317 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1318
355be0b9 1319 update_db_intercept(vcpu);
6aa8b732
AK		 1320}
1321
1322static void load_host_msrs(struct kvm_vcpu *vcpu)
1323{
94dfbdb3 1324#ifdef CONFIG_X86_64
a2fa3e9f 1325 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1326#endif
6aa8b732
AK		 1327}
1328
1329static void save_host_msrs(struct kvm_vcpu *vcpu)
1330{
94dfbdb3 1331#ifdef CONFIG_X86_64
a2fa3e9f 1332 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1333#endif
6aa8b732
AK		 1334}
1335
0fe1e009 1336static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1337{
0fe1e009
TH		 1338 if (sd->next_asid > sd->max_asid) {
1339 ++sd->asid_generation;
1340 sd->next_asid = 1;
a2fa3e9f 1341 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1342 }
1343
0fe1e009
TH		 1344 svm->asid_generation = sd->asid_generation;
1345 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1346}
1347
020df079 1348static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1349{
42dbaa5a 1350 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1351
020df079 1352 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1353}
1354
851ba692 1355static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1356{
6aa8b732
AK		 1357 u64 fault_address;
1358 u32 error_code;
6aa8b732 1359
a2fa3e9f
GH		 1360 fault_address = svm->vmcb->control.exit_info_2;
1361 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1362
229456fc 1363 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1364 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1365 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1366 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1367}
1368
851ba692 1369static int db_interception(struct vcpu_svm *svm)
d0bfb940 1370{
851ba692
AK		 1371 struct kvm_run *kvm_run = svm->vcpu.run;
1372
d0bfb940 1373 if (!(svm->vcpu.guest_debug &
44c11430 1374 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1375 !svm->nmi_singlestep) {
d0bfb940
JK		 1376 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1377 return 1;
1378 }
44c11430 1379
6be7d306
JK		 1380 if (svm->nmi_singlestep) {
1381 svm->nmi_singlestep = false;
44c11430
GN		 1382 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1383 svm->vmcb->save.rflags &=
1384 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1385 update_db_intercept(&svm->vcpu);
1386 }
1387
1388 if (svm->vcpu.guest_debug &
e0231715 1389 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1390 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1391 kvm_run->debug.arch.pc =
1392 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1393 kvm_run->debug.arch.exception = DB_VECTOR;
1394 return 0;
1395 }
1396
1397 return 1;
d0bfb940
JK		 1398}
1399
851ba692 1400static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1401{
851ba692
AK		 1402 struct kvm_run *kvm_run = svm->vcpu.run;
1403
d0bfb940
JK		 1404 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1405 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1406 kvm_run->debug.arch.exception = BP_VECTOR;
1407 return 0;
1408}
1409
851ba692 1410static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1411{
1412 int er;
1413
851ba692 1414 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1415 if (er != EMULATE_DONE)
7ee5d940 1416 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1417 return 1;
1418}
1419
6b52d186 1420static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1421{
6b52d186 1422 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1423 u32 excp;
1424
1425 if (is_nested(svm)) {
1426 u32 h_excp, n_excp;
1427
1428 h_excp = svm->nested.hsave->control.intercept_exceptions;
1429 n_excp = svm->nested.intercept_exceptions;
1430 h_excp &= ~(1 << NM_VECTOR);
1431 excp = h_excp | n_excp;
1432 } else {
1433 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1434 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1435 }
1436
1437 svm->vmcb->control.intercept_exceptions = excp;
1438
e756fc62 1439 svm->vcpu.fpu_active = 1;
d225157b 1440 update_cr0_intercept(svm);
6b52d186 1441}
a2fa3e9f 1442
6b52d186
AK		 1443static int nm_interception(struct vcpu_svm *svm)
1444{
1445 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1446 return 1;
7807fa6c
AL		 1447}
1448
67ec6607
JR		 1449static bool is_erratum_383(void)
1450{
1451 int err, i;
1452 u64 value;
1453
1454 if (!erratum_383_found)
1455 return false;
1456
1457 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1458 if (err)
1459 return false;
1460
1461 /* Bit 62 may or may not be set for this mce */
1462 value &= ~(1ULL << 62);
1463
1464 if (value != 0xb600000000010015ULL)
1465 return false;
1466
1467 /* Clear MCi_STATUS registers */
1468 for (i = 0; i < 6; ++i)
1469 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1470
1471 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1472 if (!err) {
1473 u32 low, high;
1474
1475 value &= ~(1ULL << 2);
1476 low = lower_32_bits(value);
1477 high = upper_32_bits(value);
1478
1479 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1480 }
1481
1482 /* Flush tlb to evict multi-match entries */
1483 __flush_tlb_all();
1484
1485 return true;
1486}
1487
fe5913e4 1488static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1489{
67ec6607
JR		 1490 if (is_erratum_383()) {
1491 /*
1492 * Erratum 383 triggered. Guest state is corrupt so kill the
1493 * guest.
1494 */
1495 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1496
1497 set_bit(KVM_REQ_TRIPLE_FAULT, &svm->vcpu.requests);
1498
1499 return;
1500 }
1501
53371b50
JR		 1502 /*
1503 * On an #MC intercept the MCE handler is not called automatically in
1504 * the host. So do it by hand here.
1505 */
1506 asm volatile (
1507 "int $0x12\n");
1508 /* not sure if we ever come back to this point */
1509
fe5913e4
JR		 1510 return;
1511}
1512
1513static int mc_interception(struct vcpu_svm *svm)
1514{
53371b50
JR		 1515 return 1;
1516}
1517
851ba692 1518static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1519{
851ba692
AK		 1520 struct kvm_run *kvm_run = svm->vcpu.run;
1521
46fe4ddd
JR		 1522 /*
1523 * VMCB is undefined after a SHUTDOWN intercept
1524 * so reinitialize it.
1525 */
a2fa3e9f 1526 clear_page(svm->vmcb);
e6101a96 1527 init_vmcb(svm);
46fe4ddd
JR		 1528
1529 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1530 return 0;
1531}
1532
851ba692 1533static int io_interception(struct vcpu_svm *svm)
6aa8b732 1534{
cf8f70bf 1535 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1536 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1537 int size, in, string;
039576c0 1538 unsigned port;
6aa8b732 1539
e756fc62 1540 ++svm->vcpu.stat.io_exits;
e70669ab 1541 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1542 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1543 if (string || in)
6d77dbfc 1544 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1545
039576c0
AK		 1546 port = io_info >> 16;
1547 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1548 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1549 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1550
1551 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1552}
1553
851ba692 1554static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1555{
1556 return 1;
1557}
1558
851ba692 1559static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1560{
1561 ++svm->vcpu.stat.irq_exits;
1562 return 1;
1563}
1564
851ba692 1565static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1566{
1567 return 1;
1568}
1569
851ba692 1570static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1571{
5fdbf976 1572 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1573 skip_emulated_instruction(&svm->vcpu);
1574 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1575}
1576
851ba692 1577static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1578{
5fdbf976 1579 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1580 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1581 kvm_emulate_hypercall(&svm->vcpu);
1582 return 1;
02e235bc
AK		 1583}
1584
c0725420
AG		 1585static int nested_svm_check_permissions(struct vcpu_svm *svm)
1586{
f6801dff 1587 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1588 || !is_paging(&svm->vcpu)) {
1589 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1590 return 1;
1591 }
1592
1593 if (svm->vmcb->save.cpl) {
1594 kvm_inject_gp(&svm->vcpu, 0);
1595 return 1;
1596 }
1597
1598 return 0;
1599}
1600
cf74a78b
AG		 1601static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1602 bool has_error_code, u32 error_code)
1603{
b8e88bc8
JR		 1604 int vmexit;
1605
0295ad7d
JR		 1606 if (!is_nested(svm))
1607 return 0;
cf74a78b 1608
0295ad7d
JR		 1609 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1610 svm->vmcb->control.exit_code_hi = 0;
1611 svm->vmcb->control.exit_info_1 = error_code;
1612 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1613
b8e88bc8
JR		 1614 vmexit = nested_svm_intercept(svm);
1615 if (vmexit == NESTED_EXIT_DONE)
1616 svm->nested.exit_required = true;
1617
1618 return vmexit;
cf74a78b
AG		 1619}
1620
8fe54654
JR		 1621/* This function returns true if it is save to enable the irq window */
1622static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1623{
26666957 1624 if (!is_nested(svm))
8fe54654 1625 return true;
cf74a78b 1626
26666957 1627 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1628 return true;
cf74a78b 1629
26666957 1630 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1631 return false;
cf74a78b 1632
197717d5
JR		 1633 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1634 svm->vmcb->control.exit_info_1 = 0;
1635 svm->vmcb->control.exit_info_2 = 0;
26666957 1636
cd3ff653
JR		 1637 if (svm->nested.intercept & 1ULL) {
1638 /*
1639 * The #vmexit can't be emulated here directly because this
1640 * code path runs with irqs and preemtion disabled. A
1641 * #vmexit emulation might sleep. Only signal request for
1642 * the #vmexit here.
1643 */
1644 svm->nested.exit_required = true;
236649de 1645 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1646 return false;
cf74a78b
AG		 1647 }
1648
8fe54654 1649 return true;
cf74a78b
AG		 1650}
1651
887f500c
JR		 1652/* This function returns true if it is save to enable the nmi window */
1653static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1654{
1655 if (!is_nested(svm))
1656 return true;
1657
1658 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1659 return true;
1660
1661 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1662 svm->nested.exit_required = true;
1663
1664 return false;
cf74a78b
AG		 1665}
1666
7597f129 1667static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1668{
1669 struct page *page;
1670
6c3bd3d7
JR		 1671 might_sleep();
1672
34f80cfa 1673 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1674 if (is_error_page(page))
1675 goto error;
1676
7597f129
JR		 1677 *_page = page;
1678
1679 return kmap(page);
34f80cfa
JR		 1680
1681error:
1682 kvm_release_page_clean(page);
1683 kvm_inject_gp(&svm->vcpu, 0);
1684
1685 return NULL;
1686}
1687
7597f129 1688static void nested_svm_unmap(struct page *page)
34f80cfa 1689{
7597f129 1690 kunmap(page);
34f80cfa
JR		 1691 kvm_release_page_dirty(page);
1692}
34f80cfa 1693
ce2ac085
JR		 1694static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1695{
1696 unsigned port;
1697 u8 val, bit;
1698 u64 gpa;
34f80cfa 1699
ce2ac085
JR		 1700 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1701 return NESTED_EXIT_HOST;
34f80cfa 1702
ce2ac085
JR		 1703 port = svm->vmcb->control.exit_info_1 >> 16;
1704 gpa = svm->nested.vmcb_iopm + (port / 8);
1705 bit = port % 8;
1706 val = 0;
1707
1708 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1709 val &= (1 << bit);
1710
1711 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1712}
1713
d2477826 1714static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1715{
0d6b3537
JR		 1716 u32 offset, msr, value;
1717 int write, mask;
4c2161ae 1718
3d62d9aa 1719 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1720 return NESTED_EXIT_HOST;
3d62d9aa 1721
0d6b3537
JR		 1722 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1723 offset = svm_msrpm_offset(msr);
1724 write = svm->vmcb->control.exit_info_1 & 1;
1725 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1726
0d6b3537
JR		 1727 if (offset == MSR_INVALID)
1728 return NESTED_EXIT_DONE;
4c2161ae 1729
0d6b3537
JR		 1730 /* Offset is in 32 bit units but need in 8 bit units */
1731 offset *= 4;
4c2161ae 1732
0d6b3537
JR		 1733 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1734 return NESTED_EXIT_DONE;
3d62d9aa 1735
0d6b3537 1736 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1737}
1738
410e4d57 1739static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1740{
cf74a78b 1741 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1742
410e4d57
JR		 1743 switch (exit_code) {
1744 case SVM_EXIT_INTR:
1745 case SVM_EXIT_NMI:
ff47a49b 1746 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1747 return NESTED_EXIT_HOST;
410e4d57 1748 case SVM_EXIT_NPF:
e0231715 1749 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1750 if (npt_enabled)
1751 return NESTED_EXIT_HOST;
1752 break;
410e4d57 1753 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1754 /* When we're shadowing, trap PFs */
410e4d57
JR		 1755 if (!npt_enabled)
1756 return NESTED_EXIT_HOST;
1757 break;
66a562f7
JR		 1758 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1759 nm_interception(svm);
1760 break;
410e4d57
JR		 1761 default:
1762 break;
cf74a78b
AG		 1763 }
1764
410e4d57
JR		 1765 return NESTED_EXIT_CONTINUE;
1766}
1767
1768/*
1769 * If this function returns true, this #vmexit was already handled
1770 */
b8e88bc8 1771static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1772{
1773 u32 exit_code = svm->vmcb->control.exit_code;
1774 int vmexit = NESTED_EXIT_HOST;
1775
cf74a78b 1776 switch (exit_code) {
9c4e40b9 1777 case SVM_EXIT_MSR:
3d62d9aa 1778 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1779 break;
ce2ac085
JR		 1780 case SVM_EXIT_IOIO:
1781 vmexit = nested_svm_intercept_ioio(svm);
1782 break;
cf74a78b
AG		 1783 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1784 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1785 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1786 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1787 break;
1788 }
1789 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1790 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1791 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1792 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1793 break;
1794 }
1795 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1796 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1797 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1798 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1799 break;
1800 }
1801 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1802 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1803 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1804 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1805 break;
1806 }
1807 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1808 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1809 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1810 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1811 break;
1812 }
228070b1
JR		 1813 case SVM_EXIT_ERR: {
1814 vmexit = NESTED_EXIT_DONE;
1815 break;
1816 }
cf74a78b
AG		 1817 default: {
1818 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1819 if (svm->nested.intercept & exit_bits)
410e4d57 1820 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1821 }
1822 }
1823
b8e88bc8
JR		 1824 return vmexit;
1825}
1826
1827static int nested_svm_exit_handled(struct vcpu_svm *svm)
1828{
1829 int vmexit;
1830
1831 vmexit = nested_svm_intercept(svm);
1832
1833 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1834 nested_svm_vmexit(svm);
9c4e40b9
JR		 1835
1836 return vmexit;
cf74a78b
AG		 1837}
1838
0460a979
JR		 1839static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1840{
1841 struct vmcb_control_area *dst = &dst_vmcb->control;
1842 struct vmcb_control_area *from = &from_vmcb->control;
1843
1844 dst->intercept_cr_read = from->intercept_cr_read;
1845 dst->intercept_cr_write = from->intercept_cr_write;
1846 dst->intercept_dr_read = from->intercept_dr_read;
1847 dst->intercept_dr_write = from->intercept_dr_write;
1848 dst->intercept_exceptions = from->intercept_exceptions;
1849 dst->intercept = from->intercept;
1850 dst->iopm_base_pa = from->iopm_base_pa;
1851 dst->msrpm_base_pa = from->msrpm_base_pa;
1852 dst->tsc_offset = from->tsc_offset;
1853 dst->asid = from->asid;
1854 dst->tlb_ctl = from->tlb_ctl;
1855 dst->int_ctl = from->int_ctl;
1856 dst->int_vector = from->int_vector;
1857 dst->int_state = from->int_state;
1858 dst->exit_code = from->exit_code;
1859 dst->exit_code_hi = from->exit_code_hi;
1860 dst->exit_info_1 = from->exit_info_1;
1861 dst->exit_info_2 = from->exit_info_2;
1862 dst->exit_int_info = from->exit_int_info;
1863 dst->exit_int_info_err = from->exit_int_info_err;
1864 dst->nested_ctl = from->nested_ctl;
1865 dst->event_inj = from->event_inj;
1866 dst->event_inj_err = from->event_inj_err;
1867 dst->nested_cr3 = from->nested_cr3;
1868 dst->lbr_ctl = from->lbr_ctl;
1869}
1870
34f80cfa 1871static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1872{
34f80cfa 1873 struct vmcb *nested_vmcb;
e6aa9abd 1874 struct vmcb *hsave = svm->nested.hsave;
33740e40 1875 struct vmcb *vmcb = svm->vmcb;
7597f129 1876 struct page *page;
cf74a78b 1877
17897f36
JR		 1878 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1879 vmcb->control.exit_info_1,
1880 vmcb->control.exit_info_2,
1881 vmcb->control.exit_int_info,
1882 vmcb->control.exit_int_info_err);
1883
7597f129 1884 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1885 if (!nested_vmcb)
1886 return 1;
1887
06fc7772
JR		 1888 /* Exit nested SVM mode */
1889 svm->nested.vmcb = 0;
1890
cf74a78b 1891 /* Give the current vmcb to the guest */
33740e40
JR		 1892 disable_gif(svm);
1893
1894 nested_vmcb->save.es = vmcb->save.es;
1895 nested_vmcb->save.cs = vmcb->save.cs;
1896 nested_vmcb->save.ss = vmcb->save.ss;
1897 nested_vmcb->save.ds = vmcb->save.ds;
1898 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1899 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1900 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 1901 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1902 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1903 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1904 nested_vmcb->save.rflags = vmcb->save.rflags;
1905 nested_vmcb->save.rip = vmcb->save.rip;
1906 nested_vmcb->save.rsp = vmcb->save.rsp;
1907 nested_vmcb->save.rax = vmcb->save.rax;
1908 nested_vmcb->save.dr7 = vmcb->save.dr7;
1909 nested_vmcb->save.dr6 = vmcb->save.dr6;
1910 nested_vmcb->save.cpl = vmcb->save.cpl;
1911
1912 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1913 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1914 nested_vmcb->control.int_state = vmcb->control.int_state;
1915 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1916 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1917 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1918 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1919 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1920 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1921
1922 /*
1923 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1924 * to make sure that we do not lose injected events. So check event_inj
1925 * here and copy it to exit_int_info if it is valid.
1926 * Exit_int_info and event_inj can't be both valid because the case
1927 * below only happens on a VMRUN instruction intercept which has
1928 * no valid exit_int_info set.
1929 */
1930 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1931 struct vmcb_control_area *nc = &nested_vmcb->control;
1932
1933 nc->exit_int_info = vmcb->control.event_inj;
1934 nc->exit_int_info_err = vmcb->control.event_inj_err;
1935 }
1936
33740e40
JR		 1937 nested_vmcb->control.tlb_ctl = 0;
1938 nested_vmcb->control.event_inj = 0;
1939 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1940
1941 /* We always set V_INTR_MASKING and remember the old value in hflags */
1942 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1943 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1944
cf74a78b 1945 /* Restore the original control entries */
0460a979 1946 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1947
219b65dc
AG		 1948 kvm_clear_exception_queue(&svm->vcpu);
1949 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1950
1951 /* Restore selected save entries */
1952 svm->vmcb->save.es = hsave->save.es;
1953 svm->vmcb->save.cs = hsave->save.cs;
1954 svm->vmcb->save.ss = hsave->save.ss;
1955 svm->vmcb->save.ds = hsave->save.ds;
1956 svm->vmcb->save.gdtr = hsave->save.gdtr;
1957 svm->vmcb->save.idtr = hsave->save.idtr;
1958 svm->vmcb->save.rflags = hsave->save.rflags;
1959 svm_set_efer(&svm->vcpu, hsave->save.efer);
1960 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1961 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1962 if (npt_enabled) {
1963 svm->vmcb->save.cr3 = hsave->save.cr3;
1964 svm->vcpu.arch.cr3 = hsave->save.cr3;
1965 } else {
2390218b 1966 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 1967 }
1968 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1969 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1970 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1971 svm->vmcb->save.dr7 = 0;
1972 svm->vmcb->save.cpl = 0;
1973 svm->vmcb->control.exit_int_info = 0;
1974
7597f129 1975 nested_svm_unmap(page);
cf74a78b
AG		 1976
1977 kvm_mmu_reset_context(&svm->vcpu);
1978 kvm_mmu_load(&svm->vcpu);
1979
1980 return 0;
1981}
3d6368ef 1982
9738b2c9 1983static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1984{
323c3d80
JR		 1985 /*
1986 * This function merges the msr permission bitmaps of kvm and the
1987 * nested vmcb. It is omptimized in that it only merges the parts where
1988 * the kvm msr permission bitmap may contain zero bits
1989 */
3d6368ef 1990 int i;
9738b2c9 1991
323c3d80
JR		 1992 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1993 return true;
9738b2c9 1994
323c3d80
JR		 1995 for (i = 0; i < MSRPM_OFFSETS; i++) {
1996 u32 value, p;
1997 u64 offset;
9738b2c9 1998
323c3d80
JR		 1999 if (msrpm_offsets[i] == 0xffffffff)
2000 break;
3d6368ef 2001
0d6b3537
JR		 2002 p = msrpm_offsets[i];
2003 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2004
2005 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2006 return false;
2007
2008 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2009 }
3d6368ef 2010
323c3d80 2011 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2012
2013 return true;
3d6368ef
AG		 2014}
2015
9738b2c9 2016static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2017{
9738b2c9 2018 struct vmcb *nested_vmcb;
e6aa9abd 2019 struct vmcb *hsave = svm->nested.hsave;
defbba56 2020 struct vmcb *vmcb = svm->vmcb;
7597f129 2021 struct page *page;
06fc7772 2022 u64 vmcb_gpa;
3d6368ef 2023
06fc7772 2024 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2025
7597f129 2026 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2027 if (!nested_vmcb)
2028 return false;
2029
ecf1405d 2030 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 2031 nested_vmcb->save.rip,
2032 nested_vmcb->control.int_ctl,
2033 nested_vmcb->control.event_inj,
2034 nested_vmcb->control.nested_ctl);
2035
2e554e8d
JR		 2036 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2037 nested_vmcb->control.intercept_cr_write,
2038 nested_vmcb->control.intercept_exceptions,
2039 nested_vmcb->control.intercept);
2040
3d6368ef 2041 /* Clear internal status */
219b65dc
AG		 2042 kvm_clear_exception_queue(&svm->vcpu);
2043 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2044
e0231715
JR		 2045 /*
2046 * Save the old vmcb, so we don't need to pick what we save, but can
2047 * restore everything when a VMEXIT occurs
2048 */
defbba56
JR		 2049 hsave->save.es = vmcb->save.es;
2050 hsave->save.cs = vmcb->save.cs;
2051 hsave->save.ss = vmcb->save.ss;
2052 hsave->save.ds = vmcb->save.ds;
2053 hsave->save.gdtr = vmcb->save.gdtr;
2054 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2055 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2056 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2057 hsave->save.cr4 = svm->vcpu.arch.cr4;
2058 hsave->save.rflags = vmcb->save.rflags;
2059 hsave->save.rip = svm->next_rip;
2060 hsave->save.rsp = vmcb->save.rsp;
2061 hsave->save.rax = vmcb->save.rax;
2062 if (npt_enabled)
2063 hsave->save.cr3 = vmcb->save.cr3;
2064 else
2065 hsave->save.cr3 = svm->vcpu.arch.cr3;
2066
0460a979 2067 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2068
2069 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2070 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2071 else
2072 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2073
2074 /* Load the nested guest state */
2075 svm->vmcb->save.es = nested_vmcb->save.es;
2076 svm->vmcb->save.cs = nested_vmcb->save.cs;
2077 svm->vmcb->save.ss = nested_vmcb->save.ss;
2078 svm->vmcb->save.ds = nested_vmcb->save.ds;
2079 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2080 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2081 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2082 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2083 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2084 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2085 if (npt_enabled) {
2086 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2087 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2088 } else
2390218b 2089 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2090
2091 /* Guest paging mode is active - reset mmu */
2092 kvm_mmu_reset_context(&svm->vcpu);
2093
defbba56 2094 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2095 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2096 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2097 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2098
3d6368ef
AG		 2099 /* In case we don't even reach vcpu_run, the fields are not updated */
2100 svm->vmcb->save.rax = nested_vmcb->save.rax;
2101 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2102 svm->vmcb->save.rip = nested_vmcb->save.rip;
2103 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2104 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2105 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2106
f7138538 2107 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2108 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2109
aad42c64
JR		 2110 /* cache intercepts */
2111 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2112 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2113 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2114 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2115 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2116 svm->nested.intercept = nested_vmcb->control.intercept;
2117
3d6368ef 2118 force_new_asid(&svm->vcpu);
3d6368ef 2119 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2120 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2121 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2122 else
2123 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2124
88ab24ad
JR		 2125 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2126 /* We only want the cr8 intercept bits of the guest */
2127 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2128 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2129 }
2130
0d945bd9
JR		 2131 /* We don't want to see VMMCALLs from a nested guest */
2132 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2133
e0231715
JR		 2134 /*
2135 * We don't want a nested guest to be more powerful than the guest, so
2136 * all intercepts are ORed
2137 */
88ab24ad
JR		 2138 svm->vmcb->control.intercept_cr_read |=
2139 nested_vmcb->control.intercept_cr_read;
2140 svm->vmcb->control.intercept_cr_write |=
2141 nested_vmcb->control.intercept_cr_write;
2142 svm->vmcb->control.intercept_dr_read |=
2143 nested_vmcb->control.intercept_dr_read;
2144 svm->vmcb->control.intercept_dr_write |=
2145 nested_vmcb->control.intercept_dr_write;
2146 svm->vmcb->control.intercept_exceptions |=
2147 nested_vmcb->control.intercept_exceptions;
2148
2149 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2150
2151 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2152 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2153 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2154 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2155 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2156 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2157
7597f129 2158 nested_svm_unmap(page);
9738b2c9 2159
06fc7772
JR		 2160 /* nested_vmcb is our indicator if nested SVM is activated */
2161 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2162
2af9194d 2163 enable_gif(svm);
3d6368ef 2164
9738b2c9 2165 return true;
3d6368ef
AG		 2166}
2167
9966bf68 2168static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2169{
2170 to_vmcb->save.fs = from_vmcb->save.fs;
2171 to_vmcb->save.gs = from_vmcb->save.gs;
2172 to_vmcb->save.tr = from_vmcb->save.tr;
2173 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2174 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2175 to_vmcb->save.star = from_vmcb->save.star;
2176 to_vmcb->save.lstar = from_vmcb->save.lstar;
2177 to_vmcb->save.cstar = from_vmcb->save.cstar;
2178 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2179 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2180 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2181 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2182}
2183
851ba692 2184static int vmload_interception(struct vcpu_svm *svm)
5542675b 2185{
9966bf68 2186 struct vmcb *nested_vmcb;
7597f129 2187 struct page *page;
9966bf68 2188
5542675b
AG		 2189 if (nested_svm_check_permissions(svm))
2190 return 1;
2191
2192 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2193 skip_emulated_instruction(&svm->vcpu);
2194
7597f129 2195 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2196 if (!nested_vmcb)
2197 return 1;
2198
2199 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2200 nested_svm_unmap(page);
5542675b
AG		 2201
2202 return 1;
2203}
2204
851ba692 2205static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2206{
9966bf68 2207 struct vmcb *nested_vmcb;
7597f129 2208 struct page *page;
9966bf68 2209
5542675b
AG		 2210 if (nested_svm_check_permissions(svm))
2211 return 1;
2212
2213 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2214 skip_emulated_instruction(&svm->vcpu);
2215
7597f129 2216 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2217 if (!nested_vmcb)
2218 return 1;
2219
2220 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2221 nested_svm_unmap(page);
5542675b
AG		 2222
2223 return 1;
2224}
2225
851ba692 2226static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2227{
3d6368ef
AG		 2228 if (nested_svm_check_permissions(svm))
2229 return 1;
2230
2231 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2232 skip_emulated_instruction(&svm->vcpu);
2233
9738b2c9 2234 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2235 return 1;
2236
9738b2c9 2237 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2238 goto failed;
2239
2240 return 1;
2241
2242failed:
2243
2244 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2245 svm->vmcb->control.exit_code_hi = 0;
2246 svm->vmcb->control.exit_info_1 = 0;
2247 svm->vmcb->control.exit_info_2 = 0;
2248
2249 nested_svm_vmexit(svm);
3d6368ef
AG		 2250
2251 return 1;
2252}
2253
851ba692 2254static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2255{
2256 if (nested_svm_check_permissions(svm))
2257 return 1;
2258
2259 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2260 skip_emulated_instruction(&svm->vcpu);
2261
2af9194d 2262 enable_gif(svm);
1371d904
AG		 2263
2264 return 1;
2265}
2266
851ba692 2267static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2268{
2269 if (nested_svm_check_permissions(svm))
2270 return 1;
2271
2272 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2273 skip_emulated_instruction(&svm->vcpu);
2274
2af9194d 2275 disable_gif(svm);
1371d904
AG		 2276
2277 /* After a CLGI no interrupts should come */
2278 svm_clear_vintr(svm);
2279 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2280
2281 return 1;
2282}
2283
851ba692 2284static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2285{
2286 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2287
ec1ff790
JR		 2288 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2289 vcpu->arch.regs[VCPU_REGS_RAX]);
2290
ff092385
AG		 2291 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2292 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2293
2294 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2295 skip_emulated_instruction(&svm->vcpu);
2296 return 1;
2297}
2298
532a46b9
JR		 2299static int skinit_interception(struct vcpu_svm *svm)
2300{
2301 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2302
2303 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2304 return 1;
2305}
2306
851ba692 2307static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2308{
7ee5d940 2309 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2310 return 1;
2311}
2312
851ba692 2313static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2314{
37817f29 2315 u16 tss_selector;
64a7ec06
GN		 2316 int reason;
2317 int int_type = svm->vmcb->control.exit_int_info &
2318 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2319 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2320 uint32_t type =
2321 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2322 uint32_t idt_v =
2323 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2324 bool has_error_code = false;
2325 u32 error_code = 0;
37817f29
IE		 2326
2327 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2328
37817f29
IE		 2329 if (svm->vmcb->control.exit_info_2 &
2330 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2331 reason = TASK_SWITCH_IRET;
2332 else if (svm->vmcb->control.exit_info_2 &
2333 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2334 reason = TASK_SWITCH_JMP;
fe8e7f83 2335 else if (idt_v)
64a7ec06
GN		 2336 reason = TASK_SWITCH_GATE;
2337 else
2338 reason = TASK_SWITCH_CALL;
2339
fe8e7f83
GN		 2340 if (reason == TASK_SWITCH_GATE) {
2341 switch (type) {
2342 case SVM_EXITINTINFO_TYPE_NMI:
2343 svm->vcpu.arch.nmi_injected = false;
2344 break;
2345 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2346 if (svm->vmcb->control.exit_info_2 &
2347 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2348 has_error_code = true;
2349 error_code =
2350 (u32)svm->vmcb->control.exit_info_2;
2351 }
fe8e7f83
GN		 2352 kvm_clear_exception_queue(&svm->vcpu);
2353 break;
2354 case SVM_EXITINTINFO_TYPE_INTR:
2355 kvm_clear_interrupt_queue(&svm->vcpu);
2356 break;
2357 default:
2358 break;
2359 }
2360 }
64a7ec06 2361
8317c298
GN		 2362 if (reason != TASK_SWITCH_GATE ||
2363 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2364 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2365 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2366 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2367
acb54517
GN		 2368 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2369 has_error_code, error_code) == EMULATE_FAIL) {
2370 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2371 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2372 svm->vcpu.run->internal.ndata = 0;
2373 return 0;
2374 }
2375 return 1;
6aa8b732
AK		 2376}
2377
851ba692 2378static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2379{
5fdbf976 2380 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2381 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2382 return 1;
6aa8b732
AK		 2383}
2384
851ba692 2385static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2386{
2387 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2388 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2389 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2390 return 1;
2391}
2392
851ba692 2393static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2394{
6d77dbfc 2395 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2396}
2397
851ba692 2398static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2399{
6d77dbfc 2400 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2401}
2402
851ba692 2403static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2404{
851ba692
AK		 2405 struct kvm_run *kvm_run = svm->vcpu.run;
2406
0a5fff19
GN		 2407 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2408 /* instruction emulation calls kvm_set_cr8() */
851ba692 2409 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2410 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2411 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2412 return 1;
95ba8273 2413 }
0a5fff19
GN		 2414 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2415 return 1;
1d075434
JR		 2416 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2417 return 0;
2418}
2419
6aa8b732
AK		 2420static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2421{
a2fa3e9f
GH		 2422 struct vcpu_svm *svm = to_svm(vcpu);
2423
6aa8b732 2424 switch (ecx) {
af24a4e4 2425 case MSR_IA32_TSC: {
20824f30 2426 u64 tsc_offset;
6aa8b732 2427
20824f30
JR		 2428 if (is_nested(svm))
2429 tsc_offset = svm->nested.hsave->control.tsc_offset;
2430 else
2431 tsc_offset = svm->vmcb->control.tsc_offset;
2432
2433 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2434 break;
2435 }
0e859cac 2436 case MSR_K6_STAR:
a2fa3e9f 2437 *data = svm->vmcb->save.star;
6aa8b732 2438 break;
0e859cac 2439#ifdef CONFIG_X86_64
6aa8b732 2440 case MSR_LSTAR:
a2fa3e9f 2441 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2442 break;
2443 case MSR_CSTAR:
a2fa3e9f 2444 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2445 break;
2446 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2447 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2448 break;
2449 case MSR_SYSCALL_MASK:
a2fa3e9f 2450 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2451 break;
2452#endif
2453 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2454 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2455 break;
2456 case MSR_IA32_SYSENTER_EIP:
017cb99e 2457 *data = svm->sysenter_eip;
6aa8b732
AK		 2458 break;
2459 case MSR_IA32_SYSENTER_ESP:
017cb99e 2460 *data = svm->sysenter_esp;
6aa8b732 2461 break;
e0231715
JR		 2462 /*
2463 * Nobody will change the following 5 values in the VMCB so we can
2464 * safely return them on rdmsr. They will always be 0 until LBRV is
2465 * implemented.
2466 */
a2938c80
JR		 2467 case MSR_IA32_DEBUGCTLMSR:
2468 *data = svm->vmcb->save.dbgctl;
2469 break;
2470 case MSR_IA32_LASTBRANCHFROMIP:
2471 *data = svm->vmcb->save.br_from;
2472 break;
2473 case MSR_IA32_LASTBRANCHTOIP:
2474 *data = svm->vmcb->save.br_to;
2475 break;
2476 case MSR_IA32_LASTINTFROMIP:
2477 *data = svm->vmcb->save.last_excp_from;
2478 break;
2479 case MSR_IA32_LASTINTTOIP:
2480 *data = svm->vmcb->save.last_excp_to;
2481 break;
b286d5d8 2482 case MSR_VM_HSAVE_PA:
e6aa9abd 2483 *data = svm->nested.hsave_msr;
b286d5d8 2484 break;
eb6f302e 2485 case MSR_VM_CR:
4a810181 2486 *data = svm->nested.vm_cr_msr;
eb6f302e 2487 break;
c8a73f18
AG		 2488 case MSR_IA32_UCODE_REV:
2489 *data = 0x01000065;
2490 break;
6aa8b732 2491 default:
3bab1f5d 2492 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2493 }
2494 return 0;
2495}
2496
851ba692 2497static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2498{
ad312c7c 2499 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2500 u64 data;
2501
59200273
AK		 2502 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2503 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2504 kvm_inject_gp(&svm->vcpu, 0);
59200273 2505 } else {
229456fc 2506 trace_kvm_msr_read(ecx, data);
af9ca2d7 2507
5fdbf976 2508 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2509 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2510 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2511 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2512 }
2513 return 1;
2514}
2515
4a810181
JR		 2516static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2517{
2518 struct vcpu_svm *svm = to_svm(vcpu);
2519 int svm_dis, chg_mask;
2520
2521 if (data & ~SVM_VM_CR_VALID_MASK)
2522 return 1;
2523
2524 chg_mask = SVM_VM_CR_VALID_MASK;
2525
2526 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2527 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2528
2529 svm->nested.vm_cr_msr &= ~chg_mask;
2530 svm->nested.vm_cr_msr |= (data & chg_mask);
2531
2532 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2533
2534 /* check for svm_disable while efer.svme is set */
2535 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2536 return 1;
2537
2538 return 0;
2539}
2540
6aa8b732
AK		 2541static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2542{
a2fa3e9f
GH		 2543 struct vcpu_svm *svm = to_svm(vcpu);
2544
6aa8b732 2545 switch (ecx) {
af24a4e4 2546 case MSR_IA32_TSC: {
20824f30
JR		 2547 u64 tsc_offset = data - native_read_tsc();
2548 u64 g_tsc_offset = 0;
2549
2550 if (is_nested(svm)) {
2551 g_tsc_offset = svm->vmcb->control.tsc_offset -
2552 svm->nested.hsave->control.tsc_offset;
2553 svm->nested.hsave->control.tsc_offset = tsc_offset;
2554 }
2555
2556 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2557
6aa8b732
AK		 2558 break;
2559 }
0e859cac 2560 case MSR_K6_STAR:
a2fa3e9f 2561 svm->vmcb->save.star = data;
6aa8b732 2562 break;
49b14f24 2563#ifdef CONFIG_X86_64
6aa8b732 2564 case MSR_LSTAR:
a2fa3e9f 2565 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2566 break;
2567 case MSR_CSTAR:
a2fa3e9f 2568 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2569 break;
2570 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2571 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2572 break;
2573 case MSR_SYSCALL_MASK:
a2fa3e9f 2574 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2575 break;
2576#endif
2577 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2578 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2579 break;
2580 case MSR_IA32_SYSENTER_EIP:
017cb99e 2581 svm->sysenter_eip = data;
a2fa3e9f 2582 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2583 break;
2584 case MSR_IA32_SYSENTER_ESP:
017cb99e 2585 svm->sysenter_esp = data;
a2fa3e9f 2586 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2587 break;
a2938c80 2588 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2589 if (!svm_has(SVM_FEATURE_LBRV)) {
2590 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2591 __func__, data);
24e09cbf
JR		 2592 break;
2593 }
2594 if (data & DEBUGCTL_RESERVED_BITS)
2595 return 1;
2596
2597 svm->vmcb->save.dbgctl = data;
2598 if (data & (1ULL<<0))
2599 svm_enable_lbrv(svm);
2600 else
2601 svm_disable_lbrv(svm);
a2938c80 2602 break;
b286d5d8 2603 case MSR_VM_HSAVE_PA:
e6aa9abd 2604 svm->nested.hsave_msr = data;
62b9abaa 2605 break;
3c5d0a44 2606 case MSR_VM_CR:
4a810181 2607 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2608 case MSR_VM_IGNNE:
3c5d0a44
AG		 2609 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2610 break;
6aa8b732 2611 default:
3bab1f5d 2612 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2613 }
2614 return 0;
2615}
2616
851ba692 2617static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2618{
ad312c7c 2619 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2620 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2621 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2622
af9ca2d7 2623
5fdbf976 2624 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2625 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2626 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2627 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2628 } else {
2629 trace_kvm_msr_write(ecx, data);
e756fc62 2630 skip_emulated_instruction(&svm->vcpu);
59200273 2631 }
6aa8b732
AK		 2632 return 1;
2633}
2634
851ba692 2635static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2636{
e756fc62 2637 if (svm->vmcb->control.exit_info_1)
851ba692 2638 return wrmsr_interception(svm);
6aa8b732 2639 else
851ba692 2640 return rdmsr_interception(svm);
6aa8b732
AK		 2641}
2642
851ba692 2643static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2644{
851ba692
AK		 2645 struct kvm_run *kvm_run = svm->vcpu.run;
2646
f0b85051 2647 svm_clear_vintr(svm);
85f455f7 2648 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2649 /*
2650 * If the user space waits to inject interrupts, exit as soon as
2651 * possible
2652 */
8061823a
GN		 2653 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2654 kvm_run->request_interrupt_window &&
2655 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2656 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2657 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2658 return 0;
2659 }
2660
2661 return 1;
2662}
2663
565d0998
ML		 2664static int pause_interception(struct vcpu_svm *svm)
2665{
2666 kvm_vcpu_on_spin(&(svm->vcpu));
2667 return 1;
2668}
2669
851ba692 2670static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2671 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2672 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2673 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2674 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2675 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2676 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2677 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2678 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2679 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2680 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2681 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2682 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2683 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2684 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2685 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2686 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2687 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2688 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2689 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2690 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2691 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2692 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2693 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2694 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2695 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2696 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2697 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2698 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2699 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2700 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2701 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2702 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2703 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2704 [SVM_EXIT_SMI] = nop_on_interception,
2705 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2706 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2707 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2708 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2709 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2710 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2711 [SVM_EXIT_HLT] = halt_interception,
a7052897 2712 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2713 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2714 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2715 [SVM_EXIT_MSR] = msr_interception,
2716 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2717 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2718 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2719 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2720 [SVM_EXIT_VMLOAD] = vmload_interception,
2721 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2722 [SVM_EXIT_STGI] = stgi_interception,
2723 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2724 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2725 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2726 [SVM_EXIT_MONITOR] = invalid_op_interception,
2727 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2728 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2729};
2730
3f10c846
JR		 2731void dump_vmcb(struct kvm_vcpu *vcpu)
2732{
2733 struct vcpu_svm *svm = to_svm(vcpu);
2734 struct vmcb_control_area *control = &svm->vmcb->control;
2735 struct vmcb_save_area *save = &svm->vmcb->save;
2736
2737 pr_err("VMCB Control Area:\n");
2738 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2739 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2740 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2741 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2742 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2743 pr_err("intercepts: %016llx\n", control->intercept);
2744 pr_err("pause filter count: %d\n", control->pause_filter_count);
2745 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2746 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2747 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2748 pr_err("asid: %d\n", control->asid);
2749 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2750 pr_err("int_ctl: %08x\n", control->int_ctl);
2751 pr_err("int_vector: %08x\n", control->int_vector);
2752 pr_err("int_state: %08x\n", control->int_state);
2753 pr_err("exit_code: %08x\n", control->exit_code);
2754 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2755 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2756 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2757 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2758 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2759 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2760 pr_err("event_inj: %08x\n", control->event_inj);
2761 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2762 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2763 pr_err("next_rip: %016llx\n", control->next_rip);
2764 pr_err("VMCB State Save Area:\n");
2765 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2766 save->es.selector, save->es.attrib,
2767 save->es.limit, save->es.base);
2768 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2769 save->cs.selector, save->cs.attrib,
2770 save->cs.limit, save->cs.base);
2771 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2772 save->ss.selector, save->ss.attrib,
2773 save->ss.limit, save->ss.base);
2774 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2775 save->ds.selector, save->ds.attrib,
2776 save->ds.limit, save->ds.base);
2777 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2778 save->fs.selector, save->fs.attrib,
2779 save->fs.limit, save->fs.base);
2780 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2781 save->gs.selector, save->gs.attrib,
2782 save->gs.limit, save->gs.base);
2783 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2784 save->gdtr.selector, save->gdtr.attrib,
2785 save->gdtr.limit, save->gdtr.base);
2786 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2787 save->ldtr.selector, save->ldtr.attrib,
2788 save->ldtr.limit, save->ldtr.base);
2789 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2790 save->idtr.selector, save->idtr.attrib,
2791 save->idtr.limit, save->idtr.base);
2792 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2793 save->tr.selector, save->tr.attrib,
2794 save->tr.limit, save->tr.base);
2795 pr_err("cpl: %d efer: %016llx\n",
2796 save->cpl, save->efer);
2797 pr_err("cr0: %016llx cr2: %016llx\n",
2798 save->cr0, save->cr2);
2799 pr_err("cr3: %016llx cr4: %016llx\n",
2800 save->cr3, save->cr4);
2801 pr_err("dr6: %016llx dr7: %016llx\n",
2802 save->dr6, save->dr7);
2803 pr_err("rip: %016llx rflags: %016llx\n",
2804 save->rip, save->rflags);
2805 pr_err("rsp: %016llx rax: %016llx\n",
2806 save->rsp, save->rax);
2807 pr_err("star: %016llx lstar: %016llx\n",
2808 save->star, save->lstar);
2809 pr_err("cstar: %016llx sfmask: %016llx\n",
2810 save->cstar, save->sfmask);
2811 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2812 save->kernel_gs_base, save->sysenter_cs);
2813 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2814 save->sysenter_esp, save->sysenter_eip);
2815 pr_err("gpat: %016llx dbgctl: %016llx\n",
2816 save->g_pat, save->dbgctl);
2817 pr_err("br_from: %016llx br_to: %016llx\n",
2818 save->br_from, save->br_to);
2819 pr_err("excp_from: %016llx excp_to: %016llx\n",
2820 save->last_excp_from, save->last_excp_to);
2821
2822}
2823
851ba692 2824static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2825{
04d2cc77 2826 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2827 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2828 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2829
5bfd8b54 2830 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2831
2be4fc7a
JR		 2832 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2833 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2834 if (npt_enabled)
2835 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2836
cd3ff653
JR		 2837 if (unlikely(svm->nested.exit_required)) {
2838 nested_svm_vmexit(svm);
2839 svm->nested.exit_required = false;
2840
2841 return 1;
2842 }
2843
cf74a78b 2844 if (is_nested(svm)) {
410e4d57
JR		 2845 int vmexit;
2846
d8cabddf
JR		 2847 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2848 svm->vmcb->control.exit_info_1,
2849 svm->vmcb->control.exit_info_2,
2850 svm->vmcb->control.exit_int_info,
2851 svm->vmcb->control.exit_int_info_err);
2852
410e4d57
JR		 2853 vmexit = nested_svm_exit_special(svm);
2854
2855 if (vmexit == NESTED_EXIT_CONTINUE)
2856 vmexit = nested_svm_exit_handled(svm);
2857
2858 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2859 return 1;
cf74a78b
AG		 2860 }
2861
a5c3832d
JR		 2862 svm_complete_interrupts(svm);
2863
04d2cc77
AK		 2864 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2865 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2866 kvm_run->fail_entry.hardware_entry_failure_reason
2867 = svm->vmcb->control.exit_code;
3f10c846
JR		 2868 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2869 dump_vmcb(vcpu);
04d2cc77
AK		 2870 return 0;
2871 }
2872
a2fa3e9f 2873 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2874 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2875 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2876 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2877 "exit_code 0x%x\n",
b8688d51 2878 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2879 exit_code);
2880
9d8f549d 2881 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2882 || !svm_exit_handlers[exit_code]) {
6aa8b732 2883 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2884 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2885 return 0;
2886 }
2887
851ba692 2888 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2889}
2890
2891static void reload_tss(struct kvm_vcpu *vcpu)
2892{
2893 int cpu = raw_smp_processor_id();
2894
0fe1e009
TH		 2895 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2896 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2897 load_TR_desc();
2898}
2899
e756fc62 2900static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2901{
2902 int cpu = raw_smp_processor_id();
2903
0fe1e009 2904 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2905
a2fa3e9f 2906 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2907 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2908 if (svm->asid_generation != sd->asid_generation)
2909 new_asid(svm, sd);
6aa8b732
AK		 2910}
2911
95ba8273
GN		 2912static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2913{
2914 struct vcpu_svm *svm = to_svm(vcpu);
2915
2916 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2917 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 2918 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 2919 ++vcpu->stat.nmi_injections;
2920}
6aa8b732 2921
85f455f7 2922static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2923{
2924 struct vmcb_control_area *control;
2925
e756fc62 2926 control = &svm->vmcb->control;
85f455f7 2927 control->int_vector = irq;
6aa8b732
AK		 2928 control->int_ctl &= ~V_INTR_PRIO_MASK;
2929 control->int_ctl |= V_IRQ_MASK |
2930 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2931}
2932
66fd3f7f 2933static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2934{
2935 struct vcpu_svm *svm = to_svm(vcpu);
2936
2af9194d 2937 BUG_ON(!(gif_set(svm)));
cf74a78b 2938
9fb2d2b4
GN		 2939 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
2940 ++vcpu->stat.irq_injections;
2941
219b65dc
AG		 2942 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2943 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2944}
2945
95ba8273 2946static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2947{
2948 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2949
88ab24ad
JR		 2950 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2951 return;
2952
95ba8273 2953 if (irr == -1)
aaacfc9a
JR		 2954 return;
2955
95ba8273
GN		 2956 if (tpr >= irr)
2957 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2958}
aaacfc9a 2959
95ba8273
GN		 2960static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2961{
2962 struct vcpu_svm *svm = to_svm(vcpu);
2963 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 2964 int ret;
2965 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2966 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2967 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2968
2969 return ret;
aaacfc9a
JR		 2970}
2971
3cfc3092
JK		 2972static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2973{
2974 struct vcpu_svm *svm = to_svm(vcpu);
2975
2976 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2977}
2978
2979static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2980{
2981 struct vcpu_svm *svm = to_svm(vcpu);
2982
2983 if (masked) {
2984 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 2985 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 2986 } else {
2987 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 2988 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 2989 }
2990}
2991
78646121
GN		 2992static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2993{
2994 struct vcpu_svm *svm = to_svm(vcpu);
2995 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2996 int ret;
2997
2998 if (!gif_set(svm) ||
2999 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3000 return 0;
3001
3002 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3003
3004 if (is_nested(svm))
3005 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3006
3007 return ret;
78646121
GN		 3008}
3009
9222be18 3010static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3011{
219b65dc 3012 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3013
e0231715
JR		 3014 /*
3015 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3016 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3017 * get that intercept, this function will be called again though and
3018 * we'll get the vintr intercept.
3019 */
8fe54654 3020 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3021 svm_set_vintr(svm);
3022 svm_inject_irq(svm, 0x0);
3023 }
85f455f7
ED		 3024}
3025
95ba8273 3026static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3027{
04d2cc77 3028 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3029
44c11430
GN		 3030 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3031 == HF_NMI_MASK)
3032 return; /* IRET will cause a vm exit */
3033
e0231715
JR		 3034 /*
3035 * Something prevents NMI from been injected. Single step over possible
3036 * problem (IRET or exception injection or interrupt shadow)
3037 */
6be7d306 3038 svm->nmi_singlestep = true;
44c11430
GN		 3039 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3040 update_db_intercept(vcpu);
c1150d8c
DL		 3041}
3042
cbc94022
IE		 3043static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3044{
3045 return 0;
3046}
3047
d9e368d6
AK		 3048static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3049{
3050 force_new_asid(vcpu);
3051}
3052
04d2cc77
AK		 3053static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3054{
3055}
3056
d7bf8221
JR		 3057static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3058{
3059 struct vcpu_svm *svm = to_svm(vcpu);
3060
88ab24ad
JR		 3061 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3062 return;
3063
d7bf8221
JR		 3064 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3065 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3066 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3067 }
3068}
3069
649d6864
JR		 3070static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3071{
3072 struct vcpu_svm *svm = to_svm(vcpu);
3073 u64 cr8;
3074
88ab24ad
JR		 3075 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3076 return;
3077
649d6864
JR		 3078 cr8 = kvm_get_cr8(vcpu);
3079 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3080 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3081}
3082
9222be18
GN		 3083static void svm_complete_interrupts(struct vcpu_svm *svm)
3084{
3085 u8 vector;
3086 int type;
3087 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3088 unsigned int3_injected = svm->int3_injected;
3089
3090 svm->int3_injected = 0;
9222be18 3091
44c11430
GN		 3092 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3093 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3094
9222be18
GN		 3095 svm->vcpu.arch.nmi_injected = false;
3096 kvm_clear_exception_queue(&svm->vcpu);
3097 kvm_clear_interrupt_queue(&svm->vcpu);
3098
3099 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3100 return;
3101
3102 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3103 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3104
3105 switch (type) {
3106 case SVM_EXITINTINFO_TYPE_NMI:
3107 svm->vcpu.arch.nmi_injected = true;
3108 break;
3109 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3110 /*
3111 * In case of software exceptions, do not reinject the vector,
3112 * but re-execute the instruction instead. Rewind RIP first
3113 * if we emulated INT3 before.
3114 */
3115 if (kvm_exception_is_soft(vector)) {
3116 if (vector == BP_VECTOR && int3_injected &&
3117 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3118 kvm_rip_write(&svm->vcpu,
3119 kvm_rip_read(&svm->vcpu) -
3120 int3_injected);
9222be18 3121 break;
66b7138f 3122 }
9222be18
GN		 3123 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3124 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3125 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3126
3127 } else
ce7ddec4 3128 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3129 break;
3130 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3131 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3132 break;
3133 default:
3134 break;
3135 }
3136}
3137
80e31d4f
AK		 3138#ifdef CONFIG_X86_64
3139#define R "r"
3140#else
3141#define R "e"
3142#endif
3143
851ba692 3144static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3145{
a2fa3e9f 3146 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 3147 u16 fs_selector;
3148 u16 gs_selector;
3149 u16 ldt_selector;
d9e368d6 3150
2041a06a
JR		 3151 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3152 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3153 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3154
cd3ff653
JR		 3155 /*
3156 * A vmexit emulation is required before the vcpu can be executed
3157 * again.
3158 */
3159 if (unlikely(svm->nested.exit_required))
3160 return;
3161
e756fc62 3162 pre_svm_run(svm);
6aa8b732 3163
649d6864
JR		 3164 sync_lapic_to_cr8(vcpu);
3165
6aa8b732 3166 save_host_msrs(vcpu);
d6e88aec
AK		 3167 fs_selector = kvm_read_fs();
3168 gs_selector = kvm_read_gs();
3169 ldt_selector = kvm_read_ldt();
cda0ffdd 3170 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 3171 /* required for live migration with NPT */
3172 if (npt_enabled)
3173 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 3174
04d2cc77
AK		 3175 clgi();
3176
3177 local_irq_enable();
36241b8c 3178
6aa8b732 3179 asm volatile (
80e31d4f
AK		 3180 "push %%"R"bp; \n\t"
3181 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3182 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3183 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3184 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3185 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3186 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3187#ifdef CONFIG_X86_64
fb3f0f51
RR		 3188 "mov %c[r8](%[svm]), %%r8 \n\t"
3189 "mov %c[r9](%[svm]), %%r9 \n\t"
3190 "mov %c[r10](%[svm]), %%r10 \n\t"
3191 "mov %c[r11](%[svm]), %%r11 \n\t"
3192 "mov %c[r12](%[svm]), %%r12 \n\t"
3193 "mov %c[r13](%[svm]), %%r13 \n\t"
3194 "mov %c[r14](%[svm]), %%r14 \n\t"
3195 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3196#endif
3197
6aa8b732 3198 /* Enter guest mode */
80e31d4f
AK		 3199 "push %%"R"ax \n\t"
3200 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3201 __ex(SVM_VMLOAD) "\n\t"
3202 __ex(SVM_VMRUN) "\n\t"
3203 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3204 "pop %%"R"ax \n\t"
6aa8b732
AK		 3205
3206 /* Save guest registers, load host registers */
80e31d4f
AK		 3207 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3208 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3209 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3210 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3211 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3212 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3213#ifdef CONFIG_X86_64
fb3f0f51
RR		 3214 "mov %%r8, %c[r8](%[svm]) \n\t"
3215 "mov %%r9, %c[r9](%[svm]) \n\t"
3216 "mov %%r10, %c[r10](%[svm]) \n\t"
3217 "mov %%r11, %c[r11](%[svm]) \n\t"
3218 "mov %%r12, %c[r12](%[svm]) \n\t"
3219 "mov %%r13, %c[r13](%[svm]) \n\t"
3220 "mov %%r14, %c[r14](%[svm]) \n\t"
3221 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3222#endif
80e31d4f 3223 "pop %%"R"bp"
6aa8b732 3224 :
fb3f0f51 3225 : [svm]"a"(svm),
6aa8b732 3226 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3227 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3228 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3229 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3230 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3231 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3232 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3233#ifdef CONFIG_X86_64
ad312c7c
ZX		 3234 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3235 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3236 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3237 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3238 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3239 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3240 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3241 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3242#endif
54a08c04 3243 : "cc", "memory"
80e31d4f 3244 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3245#ifdef CONFIG_X86_64
54a08c04
LV		 3246 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3247#endif
3248 );
6aa8b732 3249
ad312c7c 3250 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3251 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3252 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3253 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3254
d6e88aec
AK		 3255 kvm_load_fs(fs_selector);
3256 kvm_load_gs(gs_selector);
3257 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3258 load_host_msrs(vcpu);
3259
3260 reload_tss(vcpu);
3261
56ba47dd
AK		 3262 local_irq_disable();
3263
3264 stgi();
3265
d7bf8221
JR		 3266 sync_cr8_to_lapic(vcpu);
3267
a2fa3e9f 3268 svm->next_rip = 0;
9222be18 3269
6de4f3ad
AK		 3270 if (npt_enabled) {
3271 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3272 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3273 }
fe5913e4
JR		 3274
3275 /*
3276 * We need to handle MC intercepts here before the vcpu has a chance to
3277 * change the physical cpu
3278 */
3279 if (unlikely(svm->vmcb->control.exit_code ==
3280 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3281 svm_handle_mce(svm);
6aa8b732
AK		 3282}
3283
80e31d4f
AK		 3284#undef R
3285
6aa8b732
AK		 3286static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3287{
a2fa3e9f
GH		 3288 struct vcpu_svm *svm = to_svm(vcpu);
3289
709ddebf
JR		 3290 if (npt_enabled) {
3291 svm->vmcb->control.nested_cr3 = root;
3292 force_new_asid(vcpu);
3293 return;
3294 }
3295
a2fa3e9f 3296 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3297 force_new_asid(vcpu);
3298}
3299
6aa8b732
AK		 3300static int is_disabled(void)
3301{
6031a61c
JR		 3302 u64 vm_cr;
3303
3304 rdmsrl(MSR_VM_CR, vm_cr);
3305 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3306 return 1;
3307
6aa8b732
AK		 3308 return 0;
3309}
3310
102d8325
IM		 3311static void
3312svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3313{
3314 /*
3315 * Patch in the VMMCALL instruction:
3316 */
3317 hypercall[0] = 0x0f;
3318 hypercall[1] = 0x01;
3319 hypercall[2] = 0xd9;
102d8325
IM		 3320}
3321
002c7f7c
YS		 3322static void svm_check_processor_compat(void *rtn)
3323{
3324 *(int *)rtn = 0;
3325}
3326
774ead3a
AK		 3327static bool svm_cpu_has_accelerated_tpr(void)
3328{
3329 return false;
3330}
3331
67253af5
SY		 3332static int get_npt_level(void)
3333{
3334#ifdef CONFIG_X86_64
3335 return PT64_ROOT_LEVEL;
3336#else
3337 return PT32E_ROOT_LEVEL;
3338#endif
3339}
3340
4b12f0de 3341static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3342{
3343 return 0;
3344}
3345
0e851880
SY		 3346static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3347{
3348}
3349
d4330ef2
JR		 3350static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3351{
c2c63a49
JR		 3352 switch (func) {
3353 case 0x8000000A:
3354 entry->eax = 1; /* SVM revision 1 */
3355 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3356 ASID emulation to nested SVM */
3357 entry->ecx = 0; /* Reserved */
3358 entry->edx = 0; /* Do not support any additional features */
3359
3360 break;
3361 }
d4330ef2
JR		 3362}
3363
229456fc 3364static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3365 { SVM_EXIT_READ_CR0, "read_cr0" },
3366 { SVM_EXIT_READ_CR3, "read_cr3" },
3367 { SVM_EXIT_READ_CR4, "read_cr4" },
3368 { SVM_EXIT_READ_CR8, "read_cr8" },
3369 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3370 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3371 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3372 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3373 { SVM_EXIT_READ_DR0, "read_dr0" },
3374 { SVM_EXIT_READ_DR1, "read_dr1" },
3375 { SVM_EXIT_READ_DR2, "read_dr2" },
3376 { SVM_EXIT_READ_DR3, "read_dr3" },
3377 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3378 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3379 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3380 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3381 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3382 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3383 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3384 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3385 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3386 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3387 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3388 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3389 { SVM_EXIT_INTR, "interrupt" },
3390 { SVM_EXIT_NMI, "nmi" },
3391 { SVM_EXIT_SMI, "smi" },
3392 { SVM_EXIT_INIT, "init" },
3393 { SVM_EXIT_VINTR, "vintr" },
3394 { SVM_EXIT_CPUID, "cpuid" },
3395 { SVM_EXIT_INVD, "invd" },
3396 { SVM_EXIT_HLT, "hlt" },
3397 { SVM_EXIT_INVLPG, "invlpg" },
3398 { SVM_EXIT_INVLPGA, "invlpga" },
3399 { SVM_EXIT_IOIO, "io" },
3400 { SVM_EXIT_MSR, "msr" },
3401 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3402 { SVM_EXIT_SHUTDOWN, "shutdown" },
3403 { SVM_EXIT_VMRUN, "vmrun" },
3404 { SVM_EXIT_VMMCALL, "hypercall" },
3405 { SVM_EXIT_VMLOAD, "vmload" },
3406 { SVM_EXIT_VMSAVE, "vmsave" },
3407 { SVM_EXIT_STGI, "stgi" },
3408 { SVM_EXIT_CLGI, "clgi" },
3409 { SVM_EXIT_SKINIT, "skinit" },
3410 { SVM_EXIT_WBINVD, "wbinvd" },
3411 { SVM_EXIT_MONITOR, "monitor" },
3412 { SVM_EXIT_MWAIT, "mwait" },
3413 { SVM_EXIT_NPF, "npf" },
3414 { -1, NULL }
3415};
3416
17cc3935 3417static int svm_get_lpage_level(void)
344f414f 3418{
17cc3935 3419 return PT_PDPE_LEVEL;
344f414f
JR		 3420}
3421
4e47c7a6
SY		 3422static bool svm_rdtscp_supported(void)
3423{
3424 return false;
3425}
3426
02daab21
AK		 3427static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3428{
3429 struct vcpu_svm *svm = to_svm(vcpu);
3430
02daab21 3431 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3432 if (is_nested(svm))
3433 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3434 update_cr0_intercept(svm);
02daab21
AK		 3435}
3436
cbdd1bea 3437static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3438 .cpu_has_kvm_support = has_svm,
3439 .disabled_by_bios = is_disabled,
3440 .hardware_setup = svm_hardware_setup,
3441 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3442 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3443 .hardware_enable = svm_hardware_enable,
3444 .hardware_disable = svm_hardware_disable,
774ead3a 3445 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3446
3447 .vcpu_create = svm_create_vcpu,
3448 .vcpu_free = svm_free_vcpu,
04d2cc77 3449 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3450
04d2cc77 3451 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3452 .vcpu_load = svm_vcpu_load,
3453 .vcpu_put = svm_vcpu_put,
3454
3455 .set_guest_debug = svm_guest_debug,
3456 .get_msr = svm_get_msr,
3457 .set_msr = svm_set_msr,
3458 .get_segment_base = svm_get_segment_base,
3459 .get_segment = svm_get_segment,
3460 .set_segment = svm_set_segment,
2e4d2653 3461 .get_cpl = svm_get_cpl,
1747fb71 3462 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3463 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3464 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3465 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3466 .set_cr3 = svm_set_cr3,
3467 .set_cr4 = svm_set_cr4,
3468 .set_efer = svm_set_efer,
3469 .get_idt = svm_get_idt,
3470 .set_idt = svm_set_idt,
3471 .get_gdt = svm_get_gdt,
3472 .set_gdt = svm_set_gdt,
020df079 3473 .set_dr7 = svm_set_dr7,
6de4f3ad 3474 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3475 .get_rflags = svm_get_rflags,
3476 .set_rflags = svm_set_rflags,
6b52d186 3477 .fpu_activate = svm_fpu_activate,
02daab21 3478 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3479
6aa8b732 3480 .tlb_flush = svm_flush_tlb,
6aa8b732 3481
6aa8b732 3482 .run = svm_vcpu_run,
04d2cc77 3483 .handle_exit = handle_exit,
6aa8b732 3484 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3485 .set_interrupt_shadow = svm_set_interrupt_shadow,
3486 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3487 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3488 .set_irq = svm_set_irq,
95ba8273 3489 .set_nmi = svm_inject_nmi,
298101da 3490 .queue_exception = svm_queue_exception,
78646121 3491 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3492 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3493 .get_nmi_mask = svm_get_nmi_mask,
3494 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3495 .enable_nmi_window = enable_nmi_window,
3496 .enable_irq_window = enable_irq_window,
3497 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3498
3499 .set_tss_addr = svm_set_tss_addr,
67253af5 3500 .get_tdp_level = get_npt_level,
4b12f0de 3501 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3502
3503 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3504 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3505
3506 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3507
3508 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3509
3510 .set_supported_cpuid = svm_set_supported_cpuid,
6aa8b732
AK		 3511};
3512
3513static int __init svm_init(void)
3514{
cb498ea2 3515 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3516 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3517}
3518
3519static void __exit svm_exit(void)
3520{
cb498ea2 3521 kvm_exit();
6aa8b732
AK		 3522}
3523
3524module_init(svm_init)
3525module_exit(svm_exit)
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