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7c38cf02 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap1/devices.c | |
3 | * | |
4 | * OMAP1 platform device setup/initialization | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
7c38cf02 TL |
12 | #include <linux/module.h> |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
d052d1be | 15 | #include <linux/platform_device.h> |
fced80c7 | 16 | #include <linux/io.h> |
7c38cf02 | 17 | |
a09e64fb | 18 | #include <mach/hardware.h> |
7c38cf02 TL |
19 | #include <asm/mach/map.h> |
20 | ||
ce491cf8 TL |
21 | #include <plat/tc.h> |
22 | #include <plat/board.h> | |
23 | #include <plat/mux.h> | |
a09e64fb | 24 | #include <mach/gpio.h> |
ce491cf8 | 25 | #include <plat/mmc.h> |
7c38cf02 | 26 | |
7c38cf02 TL |
27 | /*-------------------------------------------------------------------------*/ |
28 | ||
db68b189 | 29 | #if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE) |
7c38cf02 TL |
30 | |
31 | #define OMAP_RTC_BASE 0xfffb4800 | |
32 | ||
33 | static struct resource rtc_resources[] = { | |
34 | { | |
35 | .start = OMAP_RTC_BASE, | |
36 | .end = OMAP_RTC_BASE + 0x5f, | |
37 | .flags = IORESOURCE_MEM, | |
38 | }, | |
39 | { | |
40 | .start = INT_RTC_TIMER, | |
41 | .flags = IORESOURCE_IRQ, | |
42 | }, | |
43 | { | |
44 | .start = INT_RTC_ALARM, | |
45 | .flags = IORESOURCE_IRQ, | |
46 | }, | |
47 | }; | |
48 | ||
49 | static struct platform_device omap_rtc_device = { | |
50 | .name = "omap_rtc", | |
51 | .id = -1, | |
7c38cf02 TL |
52 | .num_resources = ARRAY_SIZE(rtc_resources), |
53 | .resource = rtc_resources, | |
54 | }; | |
55 | ||
56 | static void omap_init_rtc(void) | |
57 | { | |
58 | (void) platform_device_register(&omap_rtc_device); | |
59 | } | |
60 | #else | |
61 | static inline void omap_init_rtc(void) {} | |
62 | #endif | |
63 | ||
c40fae95 TL |
64 | #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) |
65 | ||
66 | #if defined(CONFIG_ARCH_OMAP15XX) | |
67 | # define OMAP1_MBOX_SIZE 0x23 | |
68 | # define INT_DSP_MAILBOX1 INT_1510_DSP_MAILBOX1 | |
69 | #elif defined(CONFIG_ARCH_OMAP16XX) | |
70 | # define OMAP1_MBOX_SIZE 0x2f | |
71 | # define INT_DSP_MAILBOX1 INT_1610_DSP_MAILBOX1 | |
72 | #endif | |
73 | ||
94113260 | 74 | #define OMAP1_MBOX_BASE OMAP1_IO_ADDRESS(OMAP16XX_MAILBOX_BASE) |
c40fae95 TL |
75 | |
76 | static struct resource mbox_resources[] = { | |
77 | { | |
78 | .start = OMAP1_MBOX_BASE, | |
79 | .end = OMAP1_MBOX_BASE + OMAP1_MBOX_SIZE, | |
80 | .flags = IORESOURCE_MEM, | |
81 | }, | |
82 | { | |
83 | .start = INT_DSP_MAILBOX1, | |
84 | .flags = IORESOURCE_IRQ, | |
85 | }, | |
86 | }; | |
87 | ||
88 | static struct platform_device mbox_device = { | |
f98d67a0 | 89 | .name = "omap1-mailbox", |
c40fae95 TL |
90 | .id = -1, |
91 | .num_resources = ARRAY_SIZE(mbox_resources), | |
92 | .resource = mbox_resources, | |
93 | }; | |
94 | ||
95 | static inline void omap_init_mbox(void) | |
96 | { | |
97 | platform_device_register(&mbox_device); | |
98 | } | |
99 | #else | |
100 | static inline void omap_init_mbox(void) { } | |
101 | #endif | |
102 | ||
d8874665 TL |
103 | /*-------------------------------------------------------------------------*/ |
104 | ||
105 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) | |
106 | ||
107 | static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller, | |
108 | int controller_nr) | |
109 | { | |
110 | if (controller_nr == 0) { | |
490a5665 CM |
111 | if (cpu_is_omap7xx()) { |
112 | omap_cfg_reg(MMC_7XX_CMD); | |
113 | omap_cfg_reg(MMC_7XX_CLK); | |
114 | omap_cfg_reg(MMC_7XX_DAT0); | |
115 | } else { | |
116 | omap_cfg_reg(MMC_CMD); | |
117 | omap_cfg_reg(MMC_CLK); | |
118 | omap_cfg_reg(MMC_DAT0); | |
119 | } | |
120 | ||
d8874665 TL |
121 | if (cpu_is_omap1710()) { |
122 | omap_cfg_reg(M15_1710_MMC_CLKI); | |
123 | omap_cfg_reg(P19_1710_MMC_CMDDIR); | |
124 | omap_cfg_reg(P20_1710_MMC_DATDIR0); | |
125 | } | |
490a5665 | 126 | if (mmc_controller->slots[0].wires == 4 && !cpu_is_omap7xx()) { |
d8874665 TL |
127 | omap_cfg_reg(MMC_DAT1); |
128 | /* NOTE: DAT2 can be on W10 (here) or M15 */ | |
129 | if (!mmc_controller->slots[0].nomux) | |
130 | omap_cfg_reg(MMC_DAT2); | |
131 | omap_cfg_reg(MMC_DAT3); | |
132 | } | |
133 | } | |
134 | ||
135 | /* Block 2 is on newer chips, and has many pinout options */ | |
136 | if (cpu_is_omap16xx() && controller_nr == 1) { | |
137 | if (!mmc_controller->slots[1].nomux) { | |
138 | omap_cfg_reg(Y8_1610_MMC2_CMD); | |
139 | omap_cfg_reg(Y10_1610_MMC2_CLK); | |
140 | omap_cfg_reg(R18_1610_MMC2_CLKIN); | |
141 | omap_cfg_reg(W8_1610_MMC2_DAT0); | |
90c62bf0 | 142 | if (mmc_controller->slots[1].wires == 4) { |
d8874665 TL |
143 | omap_cfg_reg(V8_1610_MMC2_DAT1); |
144 | omap_cfg_reg(W15_1610_MMC2_DAT2); | |
145 | omap_cfg_reg(R10_1610_MMC2_DAT3); | |
146 | } | |
147 | ||
148 | /* These are needed for the level shifter */ | |
149 | omap_cfg_reg(V9_1610_MMC2_CMDDIR); | |
150 | omap_cfg_reg(V5_1610_MMC2_DATDIR0); | |
151 | omap_cfg_reg(W19_1610_MMC2_DATDIR1); | |
152 | } | |
153 | ||
154 | /* Feedback clock must be set on OMAP-1710 MMC2 */ | |
155 | if (cpu_is_omap1710()) | |
156 | omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24), | |
157 | MOD_CONF_CTRL_1); | |
158 | } | |
159 | } | |
160 | ||
161 | void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, | |
162 | int nr_controllers) | |
163 | { | |
164 | int i; | |
165 | ||
166 | for (i = 0; i < nr_controllers; i++) { | |
167 | unsigned long base, size; | |
168 | unsigned int irq = 0; | |
169 | ||
170 | if (!mmc_data[i]) | |
171 | continue; | |
172 | ||
173 | omap1_mmc_mux(mmc_data[i], i); | |
174 | ||
175 | switch (i) { | |
176 | case 0: | |
177 | base = OMAP1_MMC1_BASE; | |
178 | irq = INT_MMC; | |
179 | break; | |
180 | case 1: | |
181 | if (!cpu_is_omap16xx()) | |
182 | return; | |
183 | base = OMAP1_MMC2_BASE; | |
184 | irq = INT_1610_MMC2; | |
185 | break; | |
186 | default: | |
187 | continue; | |
188 | } | |
189 | size = OMAP1_MMC_SIZE; | |
190 | ||
0dffb5c5 | 191 | omap_mmc_add("mmci-omap", i, base, size, irq, mmc_data[i]); |
d8874665 TL |
192 | }; |
193 | } | |
194 | ||
195 | #endif | |
196 | ||
197 | /*-------------------------------------------------------------------------*/ | |
198 | ||
9b6553cd TL |
199 | #if defined(CONFIG_OMAP_STI) |
200 | ||
646e3ed1 | 201 | #define OMAP1_STI_BASE 0xfffea000 |
9b6553cd TL |
202 | #define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400) |
203 | ||
204 | static struct resource sti_resources[] = { | |
205 | { | |
206 | .start = OMAP1_STI_BASE, | |
207 | .end = OMAP1_STI_BASE + SZ_1K - 1, | |
208 | .flags = IORESOURCE_MEM, | |
209 | }, | |
210 | { | |
211 | .start = OMAP1_STI_CHANNEL_BASE, | |
212 | .end = OMAP1_STI_CHANNEL_BASE + SZ_1K - 1, | |
213 | .flags = IORESOURCE_MEM, | |
214 | }, | |
215 | { | |
216 | .start = INT_1610_STI, | |
217 | .flags = IORESOURCE_IRQ, | |
218 | } | |
219 | }; | |
220 | ||
221 | static struct platform_device sti_device = { | |
222 | .name = "sti", | |
223 | .id = -1, | |
9b6553cd TL |
224 | .num_resources = ARRAY_SIZE(sti_resources), |
225 | .resource = sti_resources, | |
226 | }; | |
227 | ||
228 | static inline void omap_init_sti(void) | |
229 | { | |
230 | platform_device_register(&sti_device); | |
231 | } | |
232 | #else | |
233 | static inline void omap_init_sti(void) {} | |
234 | #endif | |
7c38cf02 TL |
235 | |
236 | /*-------------------------------------------------------------------------*/ | |
237 | ||
238 | /* | |
239 | * This gets called after board-specific INIT_MACHINE, and initializes most | |
240 | * on-chip peripherals accessible on this board (except for few like USB): | |
241 | * | |
242 | * (a) Does any "standard config" pin muxing needed. Board-specific | |
243 | * code will have muxed GPIO pins and done "nonstandard" setup; | |
244 | * that code could live in the boot loader. | |
245 | * (b) Populating board-specific platform_data with the data drivers | |
246 | * rely on to handle wiring variations. | |
247 | * (c) Creating platform devices as meaningful on this board and | |
248 | * with this kernel configuration. | |
249 | * | |
250 | * Claiming GPIOs, and setting their direction and initial values, is the | |
251 | * responsibility of the device drivers. So is responding to probe(). | |
252 | * | |
253 | * Board-specific knowlege like creating devices or pin setup is to be | |
254 | * kept out of drivers as much as possible. In particular, pin setup | |
255 | * may be handled by the boot loader, and drivers should expect it will | |
256 | * normally have been done by the time they're probed. | |
257 | */ | |
3179a019 | 258 | static int __init omap1_init_devices(void) |
7c38cf02 TL |
259 | { |
260 | /* please keep these calls, and their implementations above, | |
261 | * in alphabetical order so they're easier to sort through. | |
262 | */ | |
c40fae95 TL |
263 | |
264 | omap_init_mbox(); | |
7c38cf02 | 265 | omap_init_rtc(); |
9b6553cd | 266 | omap_init_sti(); |
7c38cf02 TL |
267 | |
268 | return 0; | |
269 | } | |
3179a019 | 270 | arch_initcall(omap1_init_devices); |
7c38cf02 | 271 |