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davinci: cleanup mdio arch code and switch to phy_id
[net-next-2.6.git] / arch / arm / mach-davinci / board-da850-evm.c
CommitLineData
0fbc5592
SR		 1/*
2 * TI DA850/OMAP-L138 EVM board
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/board-da830-evm.c
7 * Original Copyrights follow:
8 *
9 * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#include <linux/kernel.h>
0fbc5592
SR		 15#include <linux/init.h>
16#include <linux/console.h>
17#include <linux/i2c.h>
18#include <linux/i2c/at24.h>
75e2ea64 19#include <linux/i2c/pca953x.h>
0bc20bba 20#include <linux/mfd/tps6507x.h>
5cbdf276 21#include <linux/gpio.h>
38beb929
SR		 22#include <linux/platform_device.h>
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/nand.h>
25#include <linux/mtd/partitions.h>
7c5ec609 26#include <linux/mtd/physmap.h>
a9eb1f67 27#include <linux/regulator/machine.h>
8b24599e 28#include <linux/regulator/tps6507x.h>
da1e3680
TF		 29#include <linux/mfd/tps6507x.h>
30#include <linux/input/tps6507x-ts.h>
0fbc5592
SR		 31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34
0fbc5592
SR		 35#include <mach/cp_intc.h>
36#include <mach/da8xx.h>
38beb929 37#include <mach/nand.h>
7761ef67 38#include <mach/mux.h>
18a8505c 39#include <mach/aemif.h>
0fbc5592 40
782f2d78 41#define DA850_EVM_PHY_ID "0:00"
7761ef67 42#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
5cbdf276 43#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
5cbdf276 44
700691f2
SR		 45#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
46#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
47
2206771c
C		 48#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
49
7c5ec609
SR		 50static struct mtd_partition da850_evm_norflash_partition[] = {
51 {
e2abd5a2 52 .name = "bootloaders + env",
7c5ec609 53 .offset = 0,
e2abd5a2
SR		 54 .size = SZ_512K,
55 .mask_flags = MTD_WRITEABLE,
56 },
57 {
58 .name = "kernel",
59 .offset = MTDPART_OFS_APPEND,
60 .size = SZ_2M,
61 .mask_flags = 0,
62 },
63 {
64 .name = "filesystem",
65 .offset = MTDPART_OFS_APPEND,
7c5ec609
SR		 66 .size = MTDPART_SIZ_FULL,
67 .mask_flags = 0,
68 },
69};
70
71static struct physmap_flash_data da850_evm_norflash_data = {
72 .width = 2,
73 .parts = da850_evm_norflash_partition,
74 .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition),
75};
76
77static struct resource da850_evm_norflash_resource[] = {
78 {
79 .start = DA8XX_AEMIF_CS2_BASE,
80 .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1,
81 .flags = IORESOURCE_MEM,
82 },
83};
84
85static struct platform_device da850_evm_norflash_device = {
86 .name = "physmap-flash",
87 .id = 0,
88 .dev = {
89 .platform_data = &da850_evm_norflash_data,
90 },
91 .num_resources = 1,
92 .resource = da850_evm_norflash_resource,
93};
94
63534443
SN		 95static struct davinci_pm_config da850_pm_pdata = {
96 .sleepcount = 128,
97};
98
99static struct platform_device da850_pm_device = {
100 .name = "pm-davinci",
101 .dev = {
102 .platform_data = &da850_pm_pdata,
103 },
104 .id = -1,
105};
106
38beb929
SR		 107/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
108 * (128K blocks). It may be used instead of the (default) SPI flash
109 * to boot, using TI's tools to install the secondary boot loader
110 * (UBL) and U-Boot.
111 */
db549d22 112static struct mtd_partition da850_evm_nandflash_partition[] = {
38beb929
SR		 113 {
114 .name = "u-boot env",
115 .offset = 0,
116 .size = SZ_128K,
117 .mask_flags = MTD_WRITEABLE,
118 },
119 {
120 .name = "UBL",
121 .offset = MTDPART_OFS_APPEND,
122 .size = SZ_128K,
123 .mask_flags = MTD_WRITEABLE,
124 },
125 {
126 .name = "u-boot",
127 .offset = MTDPART_OFS_APPEND,
128 .size = 4 * SZ_128K,
129 .mask_flags = MTD_WRITEABLE,
130 },
131 {
132 .name = "kernel",
133 .offset = 0x200000,
134 .size = SZ_2M,
135 .mask_flags = 0,
136 },
137 {
138 .name = "filesystem",
139 .offset = MTDPART_OFS_APPEND,
140 .size = MTDPART_SIZ_FULL,
141 .mask_flags = 0,
142 },
143};
144
18a8505c
SN		 145static struct davinci_aemif_timing da850_evm_nandflash_timing = {
146 .wsetup = 24,
147 .wstrobe = 21,
148 .whold = 14,
149 .rsetup = 19,
150 .rstrobe = 50,
151 .rhold = 0,
152 .ta = 20,
153};
154
38beb929
SR		 155static struct davinci_nand_pdata da850_evm_nandflash_data = {
156 .parts = da850_evm_nandflash_partition,
157 .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
158 .ecc_mode = NAND_ECC_HW,
fc42e335 159 .ecc_bits = 4,
38beb929 160 .options = NAND_USE_FLASH_BBT,
18a8505c 161 .timing = &da850_evm_nandflash_timing,
38beb929
SR		 162};
163
164static struct resource da850_evm_nandflash_resource[] = {
165 {
166 .start = DA8XX_AEMIF_CS3_BASE,
167 .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
168 .flags = IORESOURCE_MEM,
169 },
170 {
171 .start = DA8XX_AEMIF_CTL_BASE,
172 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
173 .flags = IORESOURCE_MEM,
174 },
175};
176
177static struct platform_device da850_evm_nandflash_device = {
178 .name = "davinci_nand",
179 .id = 1,
180 .dev = {
181 .platform_data = &da850_evm_nandflash_data,
182 },
183 .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource),
184 .resource = da850_evm_nandflash_resource,
185};
186
039c5ee3
SR		 187static struct platform_device *da850_evm_devices[] __initdata = {
188 &da850_evm_nandflash_device,
189 &da850_evm_norflash_device,
190};
191
192#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10
193#define DA8XX_AEMIF_ASIZE_16BIT 0x1
194
195static void __init da850_evm_init_nor(void)
196{
197 void __iomem *aemif_addr;
198
199 aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K);
200
201 /* Configure data bus width of CS2 to 16 bit */
202 writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) |
203 DA8XX_AEMIF_ASIZE_16BIT,
204 aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET);
205
206 iounmap(aemif_addr);
207}
208
f48ecc2f
SS		 209static const short da850_evm_nand_pins[] = {
210 DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
211 DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
212 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
213 DA850_NEMA_WE, DA850_NEMA_OE,
214 -1
215};
216
217static const short da850_evm_nor_pins[] = {
218 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
219 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
220 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
221 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
222 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
223 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
224 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
225 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
226 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
227 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
228 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
229 DA850_EMA_A_22, DA850_EMA_A_23,
230 -1
231};
232
75e2ea64 233static u32 ui_card_detected;
039c5ee3
SR		 234
235#if defined(CONFIG_MMC_DAVINCI) || \
236 defined(CONFIG_MMC_DAVINCI_MODULE)
237#define HAS_MMC 1
238#else
239#define HAS_MMC 0
240#endif
241
f48ecc2f 242static inline void da850_evm_setup_nor_nand(void)
039c5ee3
SR		 243{
244 int ret = 0;
245
246 if (ui_card_detected & !HAS_MMC) {
f48ecc2f 247 ret = davinci_cfg_reg_list(da850_evm_nand_pins);
039c5ee3
SR		 248 if (ret)
249 pr_warning("da850_evm_init: nand mux setup failed: "
250 "%d\n", ret);
251
f48ecc2f 252 ret = davinci_cfg_reg_list(da850_evm_nor_pins);
039c5ee3
SR		 253 if (ret)
254 pr_warning("da850_evm_init: nor mux setup failed: %d\n",
255 ret);
256
257 da850_evm_init_nor();
258
259 platform_add_devices(da850_evm_devices,
260 ARRAY_SIZE(da850_evm_devices));
261 }
262}
75e2ea64 263
bae10587
SN		 264#ifdef CONFIG_DA850_UI_RMII
265static inline void da850_evm_setup_emac_rmii(int rmii_sel)
266{
267 struct davinci_soc_info *soc_info = &davinci_soc_info;
268
269 soc_info->emac_pdata->rmii_en = 1;
270 gpio_set_value(rmii_sel, 0);
271}
272#else
273static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
274#endif
275
75e2ea64
C		 276static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
277 unsigned ngpio, void *c)
278{
279 int sel_a, sel_b, sel_c, ret;
280
281 sel_a = gpio + 7;
282 sel_b = gpio + 6;
283 sel_c = gpio + 5;
284
285 ret = gpio_request(sel_a, "sel_a");
286 if (ret) {
287 pr_warning("Cannot open UI expander pin %d\n", sel_a);
288 goto exp_setup_sela_fail;
289 }
290
291 ret = gpio_request(sel_b, "sel_b");
292 if (ret) {
293 pr_warning("Cannot open UI expander pin %d\n", sel_b);
294 goto exp_setup_selb_fail;
295 }
296
297 ret = gpio_request(sel_c, "sel_c");
298 if (ret) {
299 pr_warning("Cannot open UI expander pin %d\n", sel_c);
300 goto exp_setup_selc_fail;
301 }
302
303 /* deselect all functionalities */
304 gpio_direction_output(sel_a, 1);
305 gpio_direction_output(sel_b, 1);
306 gpio_direction_output(sel_c, 1);
307
308 ui_card_detected = 1;
309 pr_info("DA850/OMAP-L138 EVM UI card detected\n");
310
311 da850_evm_setup_nor_nand();
312
bae10587 313 da850_evm_setup_emac_rmii(sel_a);
2206771c 314
75e2ea64
C		 315 return 0;
316
317exp_setup_selc_fail:
318 gpio_free(sel_b);
319exp_setup_selb_fail:
320 gpio_free(sel_a);
321exp_setup_sela_fail:
322 return ret;
323}
324
325static int da850_evm_ui_expander_teardown(struct i2c_client *client,
326 unsigned gpio, unsigned ngpio, void *c)
327{
328 /* deselect all functionalities */
329 gpio_set_value(gpio + 5, 1);
330 gpio_set_value(gpio + 6, 1);
331 gpio_set_value(gpio + 7, 1);
332
333 gpio_free(gpio + 5);
334 gpio_free(gpio + 6);
335 gpio_free(gpio + 7);
336
337 return 0;
338}
339
340static struct pca953x_platform_data da850_evm_ui_expander_info = {
341 .gpio_base = DAVINCI_N_GPIO,
342 .setup = da850_evm_ui_expander_setup,
343 .teardown = da850_evm_ui_expander_teardown,
344};
345
1a7ff8ff
C		 346static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
347 {
348 I2C_BOARD_INFO("tlv320aic3x", 0x18),
75e2ea64
C		 349 },
350 {
351 I2C_BOARD_INFO("tca6416", 0x20),
352 .platform_data = &da850_evm_ui_expander_info,
353 },
1a7ff8ff
C		 354};
355
0fbc5592
SR		 356static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
357 .bus_freq = 100, /* kHz */
358 .bus_delay = 0, /* usec */
359};
360
361static struct davinci_uart_config da850_evm_uart_config __initdata = {
362 .enabled_uarts = 0x7,
363};
364
491214e1
C		 365/* davinci da850 evm audio machine driver */
366static u8 da850_iis_serializer_direction[] = {
367 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
368 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
369 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE,
370 RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
371};
372
373static struct snd_platform_data da850_evm_snd_data = {
374 .tx_dma_offset = 0x2000,
375 .rx_dma_offset = 0x2000,
376 .op_mode = DAVINCI_MCASP_IIS_MODE,
377 .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction),
378 .tdm_slots = 2,
379 .serial_dir = da850_iis_serializer_direction,
48519f0a 380 .asp_chan_q = EVENTQ_1,
491214e1
C		 381 .version = MCASP_VERSION_2,
382 .txnumevt = 1,
383 .rxnumevt = 1,
384};
385
700691f2
SR		 386static int da850_evm_mmc_get_ro(int index)
387{
388 return gpio_get_value(DA850_MMCSD_WP_PIN);
389}
390
391static int da850_evm_mmc_get_cd(int index)
392{
393 return !gpio_get_value(DA850_MMCSD_CD_PIN);
394}
395
396static struct davinci_mmc_config da850_mmc_config = {
397 .get_ro = da850_evm_mmc_get_ro,
398 .get_cd = da850_evm_mmc_get_cd,
399 .wires = 4,
0046d0bf
C		 400 .max_freq = 50000000,
401 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
700691f2
SR		 402 .version = MMC_CTLR_VERSION_2,
403};
404
d52f235f
C		 405static void da850_panel_power_ctrl(int val)
406{
407 /* lcd backlight */
408 gpio_set_value(DA850_LCD_BL_PIN, val);
409
410 /* lcd power */
411 gpio_set_value(DA850_LCD_PWR_PIN, val);
412}
413
5cbdf276
SR		 414static int da850_lcd_hw_init(void)
415{
416 int status;
417
418 status = gpio_request(DA850_LCD_BL_PIN, "lcd bl\n");
419 if (status < 0)
420 return status;
421
422 status = gpio_request(DA850_LCD_PWR_PIN, "lcd pwr\n");
423 if (status < 0) {
424 gpio_free(DA850_LCD_BL_PIN);
425 return status;
426 }
427
428 gpio_direction_output(DA850_LCD_BL_PIN, 0);
429 gpio_direction_output(DA850_LCD_PWR_PIN, 0);
430
d52f235f
C		 431 /* Switch off panel power and backlight */
432 da850_panel_power_ctrl(0);
5cbdf276 433
d52f235f
C		 434 /* Switch on panel power and backlight */
435 da850_panel_power_ctrl(1);
5cbdf276
SR		 436
437 return 0;
438}
491214e1 439
a9eb1f67
SN		 440/* TPS65070 voltage regulator support */
441
442/* 3.3V */
db549d22 443static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
a9eb1f67
SN		 444 {
445 .supply = "usb0_vdda33",
446 },
447 {
448 .supply = "usb1_vdda33",
449 },
450};
451
452/* 3.3V or 1.8V */
db549d22 453static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
a9eb1f67
SN		 454 {
455 .supply = "dvdd3318_a",
456 },
457 {
458 .supply = "dvdd3318_b",
459 },
460 {
461 .supply = "dvdd3318_c",
462 },
463};
464
465/* 1.2V */
db549d22 466static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
a9eb1f67
SN		 467 {
468 .supply = "cvdd",
469 },
470};
471
472/* 1.8V LDO */
db549d22 473static struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
a9eb1f67
SN		 474 {
475 .supply = "sata_vddr",
476 },
477 {
478 .supply = "usb0_vdda18",
479 },
480 {
481 .supply = "usb1_vdda18",
482 },
483 {
484 .supply = "ddr_dvdd18",
485 },
486};
487
488/* 1.2V LDO */
db549d22 489static struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
a9eb1f67
SN		 490 {
491 .supply = "sata_vdd",
492 },
493 {
494 .supply = "pll0_vdda",
495 },
496 {
497 .supply = "pll1_vdda",
498 },
499 {
500 .supply = "usbs_cvdd",
501 },
502 {
503 .supply = "vddarnwa1",
504 },
505};
506
8b24599e
SN		 507/* We take advantage of the fact that both defdcdc{2,3} are tied high */
508static struct tps6507x_reg_platform_data tps6507x_platform_data = {
509 .defdcdc_default = true,
510};
511
db549d22 512static struct regulator_init_data tps65070_regulator_data[] = {
a9eb1f67
SN		 513 /* dcdc1 */
514 {
515 .constraints = {
516 .min_uV = 3150000,
517 .max_uV = 3450000,
518 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
519 REGULATOR_CHANGE_STATUS),
520 .boot_on = 1,
521 },
522 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers),
523 .consumer_supplies = tps65070_dcdc1_consumers,
524 },
525
526 /* dcdc2 */
527 {
528 .constraints = {
529 .min_uV = 1710000,
530 .max_uV = 3450000,
531 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
532 REGULATOR_CHANGE_STATUS),
533 .boot_on = 1,
534 },
535 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
536 .consumer_supplies = tps65070_dcdc2_consumers,
8b24599e 537 .driver_data = &tps6507x_platform_data,
a9eb1f67
SN		 538 },
539
540 /* dcdc3 */
541 {
542 .constraints = {
543 .min_uV = 950000,
544 .max_uV = 1320000,
545 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
546 REGULATOR_CHANGE_STATUS),
547 .boot_on = 1,
548 },
549 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
550 .consumer_supplies = tps65070_dcdc3_consumers,
8b24599e 551 .driver_data = &tps6507x_platform_data,
a9eb1f67
SN		 552 },
553
554 /* ldo1 */
555 {
556 .constraints = {
557 .min_uV = 1710000,
558 .max_uV = 1890000,
559 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
560 REGULATOR_CHANGE_STATUS),
561 .boot_on = 1,
562 },
563 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers),
564 .consumer_supplies = tps65070_ldo1_consumers,
565 },
566
567 /* ldo2 */
568 {
569 .constraints = {
570 .min_uV = 1140000,
571 .max_uV = 1320000,
572 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
573 REGULATOR_CHANGE_STATUS),
574 .boot_on = 1,
575 },
576 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers),
577 .consumer_supplies = tps65070_ldo2_consumers,
578 },
579};
580
da1e3680
TF		 581static struct touchscreen_init_data tps6507x_touchscreen_data = {
582 .poll_period = 30, /* ms between touch samples */
583 .min_pressure = 0x30, /* minimum pressure to trigger touch */
584 .vref = 0, /* turn off vref when not using A/D */
585 .vendor = 0, /* /sys/class/input/input?/id/vendor */
586 .product = 65070, /* /sys/class/input/input?/id/product */
587 .version = 0x100, /* /sys/class/input/input?/id/version */
588};
589
0bc20bba
TF		 590static struct tps6507x_board tps_board = {
591 .tps6507x_pmic_init_data = &tps65070_regulator_data[0],
da1e3680 592 .tps6507x_ts_init_data = &tps6507x_touchscreen_data,
0bc20bba
TF		 593};
594
a9eb1f67
SN		 595static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
596 {
597 I2C_BOARD_INFO("tps6507x", 0x48),
0bc20bba 598 .platform_data = &tps_board,
a9eb1f67
SN		 599 },
600};
601
602static int __init pmic_tps65070_init(void)
603{
604 return i2c_register_board_info(1, da850evm_tps65070_info,
605 ARRAY_SIZE(da850evm_tps65070_info));
606}
607
7761ef67
SR		 608static const short da850_evm_lcdc_pins[] = {
609 DA850_GPIO2_8, DA850_GPIO2_15,
610 -1
611};
612
85b8307f
SS		 613static const short da850_evm_mii_pins[] = {
614 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
615 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
616 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
617 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
618 DA850_MDIO_D,
619 -1
620};
621
622static const short da850_evm_rmii_pins[] = {
623 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
624 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
625 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
626 DA850_MDIO_D,
627 -1
628};
629
bae10587 630static int __init da850_evm_config_emac(void)
2206771c
C		 631{
632 void __iomem *cfg_chip3_base;
633 int ret;
634 u32 val;
bae10587
SN		 635 struct davinci_soc_info *soc_info = &davinci_soc_info;
636 u8 rmii_en = soc_info->emac_pdata->rmii_en;
637
638 if (!machine_is_davinci_da850_evm())
639 return 0;
2206771c 640
d2de0582 641 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
2206771c 642
2206771c 643 val = __raw_readl(cfg_chip3_base);
17fadd9a
SN		 644
645 if (rmii_en) {
2206771c 646 val |= BIT(8);
85b8307f 647 ret = davinci_cfg_reg_list(da850_evm_rmii_pins);
17fadd9a
SN		 648 pr_info("EMAC: RMII PHY configured, MII PHY will not be"
649 " functional\n");
650 } else {
2206771c 651 val &= ~BIT(8);
85b8307f 652 ret = davinci_cfg_reg_list(da850_evm_mii_pins);
17fadd9a
SN		 653 pr_info("EMAC: MII PHY configured, RMII PHY will not be"
654 " functional\n");
655 }
656
2206771c
C		 657 if (ret)
658 pr_warning("da850_evm_init: cpgmac/rmii mux setup failed: %d\n",
659 ret);
660
17fadd9a
SN		 661 /* configure the CFGCHIP3 register for RMII or MII */
662 __raw_writel(val, cfg_chip3_base);
663
2206771c
C		 664 ret = davinci_cfg_reg(DA850_GPIO2_6);
665 if (ret)
666 pr_warning("da850_evm_init:GPIO(2,6) mux setup "
667 "failed\n");
668
669 ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en");
670 if (ret) {
671 pr_warning("Cannot open GPIO %d\n",
672 DA850_MII_MDIO_CLKEN_PIN);
673 return ret;
674 }
675
17fadd9a
SN		 676 /* Enable/Disable MII MDIO clock */
677 gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
2206771c 678
782f2d78 679 soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID;
bae10587
SN		 680
681 ret = da8xx_register_emac();
682 if (ret)
683 pr_warning("da850_evm_init: emac registration failed: %d\n",
684 ret);
685
2206771c
C		 686 return 0;
687}
bae10587 688device_initcall(da850_evm_config_emac);
2206771c 689
a941c503
RS		 690/*
691 * The following EDMA channels/slots are not being used by drivers (for
692 * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence
693 * they are being reserved for codecs on the DSP side.
694 */
695static const s16 da850_dma0_rsv_chans[][2] = {
696 /* (offset, number) */
697 { 8, 6},
698 {24, 4},
699 {30, 2},
700 {-1, -1}
701};
702
703static const s16 da850_dma0_rsv_slots[][2] = {
704 /* (offset, number) */
705 { 8, 6},
706 {24, 4},
707 {30, 50},
708 {-1, -1}
709};
710
711static const s16 da850_dma1_rsv_chans[][2] = {
712 /* (offset, number) */
713 { 0, 28},
714 {30, 2},
715 {-1, -1}
716};
717
718static const s16 da850_dma1_rsv_slots[][2] = {
719 /* (offset, number) */
720 { 0, 28},
721 {30, 90},
722 {-1, -1}
723};
724
725static struct edma_rsv_info da850_edma_cc0_rsv = {
726 .rsv_chans = da850_dma0_rsv_chans,
727 .rsv_slots = da850_dma0_rsv_slots,
728};
729
730static struct edma_rsv_info da850_edma_cc1_rsv = {
731 .rsv_chans = da850_dma1_rsv_chans,
732 .rsv_slots = da850_dma1_rsv_slots,
733};
734
735static struct edma_rsv_info *da850_edma_rsv[2] = {
736 &da850_edma_cc0_rsv,
737 &da850_edma_cc1_rsv,
738};
739
0fbc5592
SR		 740static __init void da850_evm_init(void)
741{
742 int ret;
743
a9eb1f67
SN		 744 ret = pmic_tps65070_init();
745 if (ret)
746 pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n",
747 ret);
748
a941c503 749 ret = da850_register_edma(da850_edma_rsv);
0fbc5592
SR		 750 if (ret)
751 pr_warning("da850_evm_init: edma registration failed: %d\n",
752 ret);
753
3821d10a 754 ret = davinci_cfg_reg_list(da850_i2c0_pins);
0fbc5592
SR		 755 if (ret)
756 pr_warning("da850_evm_init: i2c0 mux setup failed: %d\n",
757 ret);
758
759 ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata);
760 if (ret)
761 pr_warning("da850_evm_init: i2c0 registration failed: %d\n",
762 ret);
763
5a4b1315 764
0fbc5592
SR		 765 ret = da8xx_register_watchdog();
766 if (ret)
767 pr_warning("da830_evm_init: watchdog registration failed: %d\n",
768 ret);
769
820c4fe3 770 if (HAS_MMC) {
3821d10a 771 ret = davinci_cfg_reg_list(da850_mmcsd0_pins);
820c4fe3
SR		 772 if (ret)
773 pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
774 " %d\n", ret);
775
776 ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n");
777 if (ret)
778 pr_warning("da850_evm_init: can not open GPIO %d\n",
779 DA850_MMCSD_CD_PIN);
780 gpio_direction_input(DA850_MMCSD_CD_PIN);
781
782 ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n");
783 if (ret)
784 pr_warning("da850_evm_init: can not open GPIO %d\n",
785 DA850_MMCSD_WP_PIN);
786 gpio_direction_input(DA850_MMCSD_WP_PIN);
787
788 ret = da8xx_register_mmcsd0(&da850_mmc_config);
789 if (ret)
790 pr_warning("da850_evm_init: mmcsd0 registration failed:"
791 " %d\n", ret);
792 }
700691f2 793
0fbc5592
SR		 794 davinci_serial_init(&da850_evm_uart_config);
795
1a7ff8ff
C		 796 i2c_register_board_info(1, da850_evm_i2c_devices,
797 ARRAY_SIZE(da850_evm_i2c_devices));
798
0fbc5592
SR		 799 /*
800 * shut down uart 0 and 1; they are not used on the board and
801 * accessing them causes endless "too much work in irq53" messages
802 * with arago fs
803 */
804 __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30);
805 __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
491214e1 806
3821d10a 807 ret = davinci_cfg_reg_list(da850_mcasp_pins);
491214e1
C		 808 if (ret)
809 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
810 ret);
811
b8864aa4 812 da8xx_register_mcasp(0, &da850_evm_snd_data);
5cbdf276 813
3821d10a 814 ret = davinci_cfg_reg_list(da850_lcdcntl_pins);
5cbdf276
SR		 815 if (ret)
816 pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
817 ret);
818
7761ef67 819 /* Handle board specific muxing for LCD here */
3821d10a 820 ret = davinci_cfg_reg_list(da850_evm_lcdc_pins);
7761ef67
SR		 821 if (ret)
822 pr_warning("da850_evm_init: evm specific lcd mux setup "
823 "failed: %d\n", ret);
824
5cbdf276
SR		 825 ret = da850_lcd_hw_init();
826 if (ret)
827 pr_warning("da850_evm_init: lcd initialization failed: %d\n",
828 ret);
829
d52f235f 830 sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl,
b9e6342b 831 ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
5cbdf276
SR		 832 if (ret)
833 pr_warning("da850_evm_init: lcdc registration failed: %d\n",
834 ret);
c51df70b
MG		 835
836 ret = da8xx_register_rtc();
837 if (ret)
838 pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
09dc2d45 839
b987c4b2 840 ret = da850_register_cpufreq("pll0_sysclk3");
09dc2d45
SN		 841 if (ret)
842 pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
843 ret);
5aeb15aa
SN		 844
845 ret = da8xx_register_cpuidle();
846 if (ret)
847 pr_warning("da850_evm_init: cpuidle registration failed: %d\n",
848 ret);
63534443
SN		 849
850 ret = da850_register_pm(&da850_pm_device);
851 if (ret)
852 pr_warning("da850_evm_init: suspend registration failed: %d\n",
853 ret);
0fbc5592
SR		 854}
855
856#ifdef CONFIG_SERIAL_8250_CONSOLE
857static int __init da850_evm_console_init(void)
858{
1aa5f2a9
MW		 859 if (!machine_is_davinci_da850_evm())
860 return 0;
861
0fbc5592
SR		 862 return add_preferred_console("ttyS", 2, "115200");
863}
864console_initcall(da850_evm_console_init);
865#endif
866
0fbc5592
SR		 867static void __init da850_evm_map_io(void)
868{
869 da850_init();
870}
871
48ea89ea 872MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
0fbc5592
SR		 873 .phys_io = IO_PHYS,
874 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
875 .boot_params = (DA8XX_DDR_BASE + 0x100),
876 .map_io = da850_evm_map_io,
bd808947 877 .init_irq = cp_intc_init,
0fbc5592
SR		 878 .timer = &davinci_timer,
879 .init_machine = da850_evm_init,
880MACHINE_END
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