tg3: 5719: Prevent tx data corruption

[net-next-2.6.git] / drivers / net / tg3.c

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index e7a2ba8b20a22833a184b4ac903e2381c6d7772a..b6388be1cd1e8d3da7d87cab51ae81431fd59407 100644 (file)
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -752,42 +752,6 @@ static void tg3_int_reenable(struct tg3_napi *tnapi)
                     HOSTCC_MODE_ENABLE | tnapi->coal_now);
 }
 
-static void tg3_napi_disable(struct tg3 *tp)
-{
-       int i;
-
-       for (i = tp->irq_cnt - 1; i >= 0; i--)
-               napi_disable(&tp->napi[i].napi);
-}
-
-static void tg3_napi_enable(struct tg3 *tp)
-{
-       int i;
-
-       for (i = 0; i < tp->irq_cnt; i++)
-               napi_enable(&tp->napi[i].napi);
-}
-
-static inline void tg3_netif_stop(struct tg3 *tp)
-{
-       tp->dev->trans_start = jiffies; /* prevent tx timeout */
-       tg3_napi_disable(tp);
-       netif_tx_disable(tp->dev);
-}
-
-static inline void tg3_netif_start(struct tg3 *tp)
-{
-       /* NOTE: unconditional netif_tx_wake_all_queues is only
-        * appropriate so long as all callers are assured to
-        * have free tx slots (such as after tg3_init_hw)
-        */
-       netif_tx_wake_all_queues(tp->dev);
-
-       tg3_napi_enable(tp);
-       tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
-       tg3_enable_ints(tp);
-}
-
 static void tg3_switch_clocks(struct tg3 *tp)
 {
        u32 clock_ctrl;
@@ -4338,6 +4302,11 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
        return err;
 }
 
+static inline int tg3_irq_sync(struct tg3 *tp)
+{
+       return tp->irq_sync;
+}
+
 /* This is called whenever we suspect that the system chipset is re-
  * ordering the sequence of MMIO to the tx send mailbox. The symptom
  * is bogus tx completions. We try to recover by setting the
@@ -5083,6 +5052,59 @@ tx_recovery:
        return work_done;
 }
 
+static void tg3_napi_disable(struct tg3 *tp)
+{
+       int i;
+
+       for (i = tp->irq_cnt - 1; i >= 0; i--)
+               napi_disable(&tp->napi[i].napi);
+}
+
+static void tg3_napi_enable(struct tg3 *tp)
+{
+       int i;
+
+       for (i = 0; i < tp->irq_cnt; i++)
+               napi_enable(&tp->napi[i].napi);
+}
+
+static void tg3_napi_init(struct tg3 *tp)
+{
+       int i;
+
+       netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
+       for (i = 1; i < tp->irq_cnt; i++)
+               netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
+}
+
+static void tg3_napi_fini(struct tg3 *tp)
+{
+       int i;
+
+       for (i = 0; i < tp->irq_cnt; i++)
+               netif_napi_del(&tp->napi[i].napi);
+}
+
+static inline void tg3_netif_stop(struct tg3 *tp)
+{
+       tp->dev->trans_start = jiffies; /* prevent tx timeout */
+       tg3_napi_disable(tp);
+       netif_tx_disable(tp->dev);
+}
+
+static inline void tg3_netif_start(struct tg3 *tp)
+{
+       /* NOTE: unconditional netif_tx_wake_all_queues is only
+        * appropriate so long as all callers are assured to
+        * have free tx slots (such as after tg3_init_hw)
+        */
+       netif_tx_wake_all_queues(tp->dev);
+
+       tg3_napi_enable(tp);
+       tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
+       tg3_enable_ints(tp);
+}
+
 static void tg3_irq_quiesce(struct tg3 *tp)
 {
        int i;
@@ -5096,11 +5118,6 @@ static void tg3_irq_quiesce(struct tg3 *tp)
                synchronize_irq(tp->napi[i].irq_vec);
 }
 
-static inline int tg3_irq_sync(struct tg3 *tp)
-{
-       return tp->irq_sync;
-}
-
 /* Fully shutdown all tg3 driver activity elsewhere in the system.
  * If irq_sync is non-zero, then the IRQ handler must be synchronized
  * with as well.  Most of the time, this is not necessary except when
@@ -5389,8 +5406,7 @@ static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
 {
        u32 base = (u32) mapping & 0xffffffff;
 
-       return ((base > 0xffffdcc0) &&
-               (base + len + 8 < base));
+       return (base > 0xffffdcc0) && (base + len + 8 < base);
 }
 
 /* Test for DMA addresses > 40-bit */
@@ -5399,7 +5415,7 @@ static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
 {
 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
        if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
-               return (((u64) mapping + len) > DMA_BIT_MASK(40));
+               return ((u64) mapping + len) > DMA_BIT_MASK(40);
        return 0;
 #else
        return 0;
@@ -7841,7 +7857,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        tw32(BUFMGR_DMA_HIGH_WATER,
             tp->bufmgr_config.dma_high_water);
 
-       tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
+       val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+               val |= BUFMGR_MODE_NO_TX_UNDERRUN;
+       tw32(BUFMGR_MODE, val);
        for (i = 0; i < 2000; i++) {
                if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
                        break;
@@ -8021,6 +8040,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                     val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
        }
 
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+               val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
+               tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
+                    TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
+                    TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
+       }
+
        /* Receive/send statistics. */
        if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
                val = tr32(RCVLPC_STATS_ENABLE);
@@ -8822,7 +8848,12 @@ static bool tg3_enable_msix(struct tg3 *tp)
        for (i = 0; i < tp->irq_max; i++)
                tp->napi[i].irq_vec = msix_ent[i].vector;
 
-       tp->dev->real_num_tx_queues = 1;
+       netif_set_real_num_tx_queues(tp->dev, 1);
+       rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
+       if (netif_set_real_num_rx_queues(tp->dev, rc)) {
+               pci_disable_msix(tp->pdev);
+               return false;
+       }
        if (tp->irq_cnt > 1)
                tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
 
@@ -8857,7 +8888,7 @@ defcfg:
        if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
                tp->irq_cnt = 1;
                tp->napi[0].irq_vec = tp->pdev->irq;
-               tp->dev->real_num_tx_queues = 1;
+               netif_set_real_num_tx_queues(tp->dev, 1);
        }
 }
 
@@ -8916,6 +8947,8 @@ static int tg3_open(struct net_device *dev)
        if (err)
                goto err_out1;
 
+       tg3_napi_init(tp);
+
        tg3_napi_enable(tp);
 
        for (i = 0; i < tp->irq_cnt; i++) {
@@ -9003,6 +9036,7 @@ err_out3:
 
 err_out2:
        tg3_napi_disable(tp);
+       tg3_napi_fini(tp);
        tg3_free_consistent(tp);
 
 err_out1:
@@ -9050,6 +9084,8 @@ static int tg3_close(struct net_device *dev)
        memcpy(&tp->estats_prev, tg3_get_estats(tp),
               sizeof(tp->estats_prev));
 
+       tg3_napi_fini(tp);
+
        tg3_free_consistent(tp);
 
        tg3_set_power_state(tp, PCI_D3hot);
@@ -14600,13 +14636,10 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
                tnapi->consmbox = rcvmbx;
                tnapi->prodmbox = sndmbx;
 
-               if (i) {
+               if (i)
                        tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
-                       netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
-               } else {
+               else
                        tnapi->coal_now = HOSTCC_MODE_NOW;
-                       netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
-               }
 
                if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
                        break;