tg3: Clarify semantics of TG3_IRQ_MAX_VECS

[net-next-2.6.git] / drivers / net / tg3.c

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 4e92b81bccfa7572f3969f71500c85120c5a97e6..7468479902ae6c7c5969d7ae7e3736c270ce21b8 100644 (file)
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7564,7 +7564,7 @@ static void tg3_rings_reset(struct tg3 *tp)
 
        /* Zero mailbox registers. */
        if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
-               for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
+               for (i = 1; i < tp->irq_max; i++) {
                        tp->napi[i].tx_prod = 0;
                        tp->napi[i].tx_cons = 0;
                        if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
@@ -9886,7 +9886,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
                tp->rx_pending = 63;
        tp->rx_jumbo_pending = ering->rx_jumbo_pending;
 
-       for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
+       for (i = 0; i < tp->irq_max; i++)
                tp->napi[i].tx_pending = ering->tx_pending;
 
        if (netif_running(dev)) {
@@ -14598,7 +14598,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
        intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
        rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
        sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
-       for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
+       for (i = 0; i < tp->irq_max; i++) {
                struct tg3_napi *tnapi = &tp->napi[i];
 
                tnapi->tp = tp;