drm/i915: enable low power render writes on GEN3 hardware.

[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 074385882ccfe721ff5630b9e825950c6479af7e..43ce3809ef6419bdefa31e8731dae359e30836ca 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4741,6 +4741,16 @@ i915_gem_load(struct drm_device *dev)
        list_add(&dev_priv->mm.shrink_list, &shrink_list);
        spin_unlock(&shrink_list_lock);
 
+       /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
+       if (IS_GEN3(dev)) {
+               u32 tmp = I915_READ(MI_ARB_STATE);
+               if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
+                       /* arb state is a masked write, so set bit + bit in mask */
+                       tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
+                       I915_WRITE(MI_ARB_STATE, tmp);
+               }
+       }
+
        /* Old X drivers will take 0-2 for front, back, depth buffers */
        if (!drm_core_check_feature(dev, DRIVER_MODESET))
                dev_priv->fence_reg_start = 3;