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Merge branch 'fix/asoc' into for-linus
[net-next-2.6.git] / sound / soc / omap / omap-mcbsp.c
CommitLineData
2e74796a
JN		 1/*
2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 *
b08f7a62
JN		 6 * Contact: Jarkko Nikula <jhnikula@gmail.com>
7 * Peter Ujfalusi <peter.ujfalusi@nokia.com>
2e74796a
JN		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/initval.h>
32#include <sound/soc.h>
33
ce491cf8
TL		 34#include <plat/dma.h>
35#include <plat/mcbsp.h>
2e74796a
JN		 36#include "omap-mcbsp.h"
37#include "omap-pcm.h"
38
0b604856 39#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
2e74796a 40
83905c13
IK		 41#define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
42 xhandler_get, xhandler_put) \
43{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
44 .info = omap_mcbsp_st_info_volsw, \
45 .get = xhandler_get, .put = xhandler_put, \
46 .private_value = (unsigned long) &(struct soc_mixer_control) \
47 {.min = xmin, .max = xmax} }
48
2e74796a
JN		 49struct omap_mcbsp_data {
50 unsigned int bus_id;
51 struct omap_mcbsp_reg_cfg regs;
ba9d0fd0 52 unsigned int fmt;
2e74796a
JN		 53 /*
54 * Flags indicating is the bus already activated and configured by
55 * another substream
56 */
57 int active;
58 int configured;
5f63ef99
GG		 59 unsigned int in_freq;
60 int clk_div;
3f024039 61 int wlen;
2e74796a
JN		 62};
63
2e74796a
JN		 64static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
65
66/*
67 * Stream DMA parameters. DMA request line and port address are set runtime
68 * since they are different between OMAP1 and later OMAPs
69 */
2e89713a 70static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
2e74796a
JN		 71
72#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
73static const int omap1_dma_reqs[][2] = {
74 { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
75 { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
76 { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
77};
78static const unsigned long omap1_mcbsp_port[][2] = {
79 { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
80 OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
81 { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
82 OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
83 { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
84 OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
85};
86#else
87static const int omap1_dma_reqs[][2] = {};
88static const unsigned long omap1_mcbsp_port[][2] = {};
89#endif
406e2c48 90
a8eb7ca0 91#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
406e2c48 92static const int omap24xx_dma_reqs[][2] = {
2e74796a
JN		 93 { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
94 { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
a8eb7ca0 95#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
406e2c48
JN		 96 { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
97 { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
98 { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
99#endif
2e74796a 100};
406e2c48
JN		 101#else
102static const int omap24xx_dma_reqs[][2] = {};
103#endif
104
105#if defined(CONFIG_ARCH_OMAP2420)
2e74796a
JN		 106static const unsigned long omap2420_mcbsp_port[][2] = {
107 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
108 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
109 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
110 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
111};
112#else
2e74796a
JN		 113static const unsigned long omap2420_mcbsp_port[][2] = {};
114#endif
115
406e2c48
JN		 116#if defined(CONFIG_ARCH_OMAP2430)
117static const unsigned long omap2430_mcbsp_port[][2] = {
118 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
119 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
120 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
121 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
122 { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
123 OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
124 { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
125 OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
126 { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
127 OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
128};
129#else
130static const unsigned long omap2430_mcbsp_port[][2] = {};
131#endif
132
a8eb7ca0 133#if defined(CONFIG_ARCH_OMAP3)
406e2c48
JN		 134static const unsigned long omap34xx_mcbsp_port[][2] = {
135 { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
136 OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
137 { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
138 OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
139 { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
140 OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
141 { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
142 OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
143 { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
144 OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
145};
146#else
147static const unsigned long omap34xx_mcbsp_port[][2] = {};
148#endif
149
caebc0cb
EV		 150static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
151{
152 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad
LG		 153 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
154 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
cf80e158 155 struct omap_pcm_dma_data *dma_data;
a0a499c5 156 int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
3f024039 157 int words;
a0a499c5 158
f0fba2ad 159 dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
cf80e158 160
a0a499c5
EV		 161 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
162 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
cf80e158
PU		 163 /*
164 * Configure McBSP threshold based on either:
165 * packet_size, when the sDMA is in packet mode, or
166 * based on the period size.
167 */
168 if (dma_data->packet_size)
169 words = dma_data->packet_size;
170 else
171 words = snd_pcm_lib_period_bytes(substream) /
3f024039 172 (mcbsp_data->wlen / 8);
a0a499c5 173 else
3f024039 174 words = 1;
caebc0cb
EV		 175
176 /* Configure McBSP internal buffer usage */
177 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3f024039 178 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words);
caebc0cb 179 else
3f024039 180 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words);
caebc0cb
EV		 181}
182
ddc29b01
PU		 183static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
184 struct snd_pcm_hw_rule *rule)
185{
186 struct snd_interval *buffer_size = hw_param_interval(params,
187 SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
188 struct snd_interval *channels = hw_param_interval(params,
189 SNDRV_PCM_HW_PARAM_CHANNELS);
190 struct omap_mcbsp_data *mcbsp_data = rule->private;
191 struct snd_interval frames;
192 int size;
193
194 snd_interval_any(&frames);
195 size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id);
196
197 frames.min = size / channels->min;
198 frames.integer = 1;
199 return snd_interval_refine(buffer_size, &frames);
200}
201
dee89c4d 202static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
f0fba2ad 203 struct snd_soc_dai *cpu_dai)
2e74796a 204{
f0fba2ad 205 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
caebc0cb 206 int bus_id = mcbsp_data->bus_id;
2e74796a
JN		 207 int err = 0;
208
caebc0cb
EV		 209 if (!cpu_dai->active)
210 err = omap_mcbsp_request(bus_id);
211
ddc29b01
PU		 212 /*
213 * OMAP3 McBSP FIFO is word structured.
214 * McBSP2 has 1024 + 256 = 1280 word long buffer,
215 * McBSP1,3,4,5 has 128 word long buffer
216 * This means that the size of the FIFO depends on the sample format.
217 * For example on McBSP3:
218 * 16bit samples: size is 128 * 2 = 256 bytes
219 * 32bit samples: size is 128 * 4 = 512 bytes
220 * It is simpler to place constraint for buffer and period based on
221 * channels.
222 * McBSP3 as example again (16 or 32 bit samples):
223 * 1 channel (mono): size is 128 frames (128 words)
224 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
225 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
226 */
caebc0cb 227 if (cpu_is_omap343x()) {
6984992b 228 /*
998a8a69 229 * Rule for the buffer size. We should not allow
ddc29b01
PU		 230 * smaller buffer than the FIFO size to avoid underruns
231 */
232 snd_pcm_hw_rule_add(substream->runtime, 0,
233 SNDRV_PCM_HW_PARAM_CHANNELS,
234 omap_mcbsp_hwrule_min_buffersize,
235 mcbsp_data,
236 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1);
caebc0cb 237
998a8a69
PU		 238 /* Make sure, that the period size is always even */
239 snd_pcm_hw_constraint_step(substream->runtime, 0,
240 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
6984992b
JN		 241 }
242
2e74796a
JN		 243 return err;
244}
245
dee89c4d 246static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
f0fba2ad 247 struct snd_soc_dai *cpu_dai)
2e74796a 248{
f0fba2ad 249 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
2e74796a
JN		 250
251 if (!cpu_dai->active) {
252 omap_mcbsp_free(mcbsp_data->bus_id);
253 mcbsp_data->configured = 0;
254 }
255}
256
dee89c4d 257static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
f0fba2ad 258 struct snd_soc_dai *cpu_dai)
2e74796a 259{
f0fba2ad 260 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
c12abc01 261 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
2e74796a
JN		 262
263 switch (cmd) {
264 case SNDRV_PCM_TRIGGER_START:
265 case SNDRV_PCM_TRIGGER_RESUME:
266 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
c12abc01
JN		 267 mcbsp_data->active++;
268 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
2e74796a
JN		 269 break;
270
271 case SNDRV_PCM_TRIGGER_STOP:
272 case SNDRV_PCM_TRIGGER_SUSPEND:
273 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
c12abc01
JN		 274 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
275 mcbsp_data->active--;
2e74796a
JN		 276 break;
277 default:
278 err = -EINVAL;
279 }
280
281 return err;
282}
283
75581d24
PU		 284static snd_pcm_sframes_t omap_mcbsp_dai_delay(
285 struct snd_pcm_substream *substream,
286 struct snd_soc_dai *dai)
287{
288 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad
LG		 289 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
290 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
75581d24
PU		 291 u16 fifo_use;
292 snd_pcm_sframes_t delay;
293
294 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
295 fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
296 else
297 fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
298
299 /*
300 * Divide the used locations with the channel count to get the
301 * FIFO usage in samples (don't care about partial samples in the
302 * buffer).
303 */
304 delay = fifo_use / substream->runtime->channels;
305
306 return delay;
307}
308
2e74796a 309static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
dee89c4d 310 struct snd_pcm_hw_params *params,
f0fba2ad 311 struct snd_soc_dai *cpu_dai)
2e74796a 312{
f0fba2ad 313 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
2e74796a 314 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
81ec027e
PU		 315 struct omap_pcm_dma_data *dma_data;
316 int dma, bus_id = mcbsp_data->bus_id;
caebc0cb 317 int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
cf80e158 318 int pkt_size = 0;
2e74796a 319 unsigned long port;
5f63ef99 320 unsigned int format, div, framesize, master;
2e74796a 321
81ec027e 322 dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream];
2e74796a
JN		 323 if (cpu_class_is_omap1()) {
324 dma = omap1_dma_reqs[bus_id][substream->stream];
325 port = omap1_mcbsp_port[bus_id][substream->stream];
326 } else if (cpu_is_omap2420()) {
406e2c48 327 dma = omap24xx_dma_reqs[bus_id][substream->stream];
2e74796a 328 port = omap2420_mcbsp_port[bus_id][substream->stream];
406e2c48
JN		 329 } else if (cpu_is_omap2430()) {
330 dma = omap24xx_dma_reqs[bus_id][substream->stream];
331 port = omap2430_mcbsp_port[bus_id][substream->stream];
332 } else if (cpu_is_omap343x()) {
333 dma = omap24xx_dma_reqs[bus_id][substream->stream];
334 port = omap34xx_mcbsp_port[bus_id][substream->stream];
2e74796a 335 } else {
2e74796a
JN		 336 return -ENODEV;
337 }
d98508a1
SL		 338 switch (params_format(params)) {
339 case SNDRV_PCM_FORMAT_S16_LE:
81ec027e 340 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
cf80e158 341 wlen = 16;
d98508a1
SL		 342 break;
343 case SNDRV_PCM_FORMAT_S32_LE:
81ec027e 344 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
cf80e158 345 wlen = 32;
d98508a1
SL		 346 break;
347 default:
348 return -EINVAL;
349 }
15d01430
PU		 350 if (cpu_is_omap343x()) {
351 dma_data->set_threshold = omap_mcbsp_set_threshold;
352 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
353 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
cf80e158
PU		 354 MCBSP_DMA_MODE_THRESHOLD) {
355 int period_words, max_thrsh;
356
357 period_words = params_period_bytes(params) / (wlen / 8);
358 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
359 max_thrsh = omap_mcbsp_get_max_tx_threshold(
360 mcbsp_data->bus_id);
361 else
362 max_thrsh = omap_mcbsp_get_max_rx_threshold(
363 mcbsp_data->bus_id);
364 /*
365 * If the period contains less or equal number of words,
366 * we are using the original threshold mode setup:
367 * McBSP threshold = sDMA frame size = period_size
368 * Otherwise we switch to sDMA packet mode:
369 * McBSP threshold = sDMA packet size
370 * sDMA frame size = period size
371 */
372 if (period_words > max_thrsh) {
373 int divider = 0;
374
375 /*
376 * Look for the biggest threshold value, which
377 * divides the period size evenly.
378 */
379 divider = period_words / max_thrsh;
380 if (period_words % max_thrsh)
381 divider++;
382 while (period_words % divider &&
383 divider < period_words)
384 divider++;
385 if (divider == period_words)
386 return -EINVAL;
387
388 pkt_size = period_words / divider;
389 sync_mode = OMAP_DMA_SYNC_PACKET;
390 } else {
391 sync_mode = OMAP_DMA_SYNC_FRAME;
392 }
393 }
15d01430
PU		 394 }
395
396 dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback";
397 dma_data->dma_req = dma;
398 dma_data->port_addr = port;
399 dma_data->sync_mode = sync_mode;
cf80e158 400 dma_data->packet_size = pkt_size;
fd23b7de 401
81ec027e 402 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
2e74796a
JN		 403
404 if (mcbsp_data->configured) {
405 /* McBSP already configured by another stream */
406 return 0;
407 }
408
c29b206f
PU		 409 format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
410 wpf = channels = params_channels(params);
299a151f
PU		 411 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
412 format == SND_SOC_DAIFMT_LEFT_J)) {
5f63ef99
GG		 413 /* Use dual-phase frames */
414 regs->rcr2 |= RPHASE;
415 regs->xcr2 |= XPHASE;
416 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
417 wpf--;
418 regs->rcr2 |= RFRLEN2(wpf - 1);
419 regs->xcr2 |= XFRLEN2(wpf - 1);
2e74796a
JN		 420 }
421
5f63ef99
GG		 422 regs->rcr1 |= RFRLEN1(wpf - 1);
423 regs->xcr1 |= XFRLEN1(wpf - 1);
424
2e74796a
JN		 425 switch (params_format(params)) {
426 case SNDRV_PCM_FORMAT_S16_LE:
427 /* Set word lengths */
428 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
429 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
430 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
431 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
2e74796a 432 break;
d98508a1
SL		 433 case SNDRV_PCM_FORMAT_S32_LE:
434 /* Set word lengths */
d98508a1
SL		 435 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
436 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
437 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
438 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
439 break;
2e74796a
JN		 440 default:
441 /* Unsupported PCM format */
442 return -EINVAL;
443 }
444
5f63ef99
GG		 445 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
446 * by _counting_ BCLKs. Calculate frame size in BCLKs */
447 master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
448 if (master == SND_SOC_DAIFMT_CBS_CFS) {
449 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
450 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
451
452 if (framesize < wlen * channels) {
453 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
454 "channels\n", __func__);
455 return -EINVAL;
456 }
457 } else
458 framesize = wlen * channels;
459
ba9d0fd0 460 /* Set FS period and length in terms of bit clock periods */
c29b206f 461 switch (format) {
ba9d0fd0 462 case SND_SOC_DAIFMT_I2S:
299a151f 463 case SND_SOC_DAIFMT_LEFT_J:
5f63ef99
GG		 464 regs->srgr2 |= FPER(framesize - 1);
465 regs->srgr1 |= FWID((framesize >> 1) - 1);
ba9d0fd0 466 break;
3ba191ce 467 case SND_SOC_DAIFMT_DSP_A:
bd25867a 468 case SND_SOC_DAIFMT_DSP_B:
5f63ef99 469 regs->srgr2 |= FPER(framesize - 1);
36ce8582 470 regs->srgr1 |= FWID(0);
ba9d0fd0
JN		 471 break;
472 }
473
2e74796a 474 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
3f024039 475 mcbsp_data->wlen = wlen;
2e74796a
JN		 476 mcbsp_data->configured = 1;
477
478 return 0;
479}
480
481/*
482 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
483 * cache is initialized here
484 */
8687eb8b 485static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 486 unsigned int fmt)
487{
f0fba2ad 488 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
2e74796a 489 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
36ce8582 490 unsigned int temp_fmt = fmt;
2e74796a
JN		 491
492 if (mcbsp_data->configured)
493 return 0;
494
ba9d0fd0 495 mcbsp_data->fmt = fmt;
2e74796a
JN		 496 memset(regs, 0, sizeof(*regs));
497 /* Generic McBSP register settings */
498 regs->spcr2 |= XINTM(3) | FREE;
499 regs->spcr1 |= RINTM(3);
c721bbda
EN		 500 /* RFIG and XFIG are not defined in 34xx */
501 if (!cpu_is_omap34xx()) {
502 regs->rcr2 |= RFIG;
503 regs->xcr2 |= XFIG;
504 }
ef390c0b 505 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
32080af7
JN		 506 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
507 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
ef390c0b 508 }
2e74796a
JN		 509
510 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
511 case SND_SOC_DAIFMT_I2S:
512 /* 1-bit data delay */
513 regs->rcr2 |= RDATDLY(1);
514 regs->xcr2 |= XDATDLY(1);
515 break;
299a151f
PU		 516 case SND_SOC_DAIFMT_LEFT_J:
517 /* 0-bit data delay */
518 regs->rcr2 |= RDATDLY(0);
519 regs->xcr2 |= XDATDLY(0);
520 regs->spcr1 |= RJUST(2);
521 /* Invert FS polarity configuration */
522 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
523 break;
3ba191ce
PU		 524 case SND_SOC_DAIFMT_DSP_A:
525 /* 1-bit data delay */
526 regs->rcr2 |= RDATDLY(1);
527 regs->xcr2 |= XDATDLY(1);
528 /* Invert FS polarity configuration */
529 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
530 break;
bd25867a 531 case SND_SOC_DAIFMT_DSP_B:
3336c5b5
AK		 532 /* 0-bit data delay */
533 regs->rcr2 |= RDATDLY(0);
534 regs->xcr2 |= XDATDLY(0);
36ce8582
JN		 535 /* Invert FS polarity configuration */
536 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
3336c5b5 537 break;
2e74796a
JN		 538 default:
539 /* Unsupported data format */
540 return -EINVAL;
541 }
542
543 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
544 case SND_SOC_DAIFMT_CBS_CFS:
545 /* McBSP master. Set FS and bit clocks as outputs */
546 regs->pcr0 |= FSXM | FSRM |
547 CLKXM | CLKRM;
548 /* Sample rate generator drives the FS */
549 regs->srgr2 |= FSGM;
550 break;
551 case SND_SOC_DAIFMT_CBM_CFM:
552 /* McBSP slave */
553 break;
554 default:
555 /* Unsupported master/slave configuration */
556 return -EINVAL;
557 }
558
559 /* Set bit clock (CLKX/CLKR) and FS polarities */
36ce8582 560 switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
2e74796a
JN		 561 case SND_SOC_DAIFMT_NB_NF:
562 /*
563 * Normal BCLK + FS.
564 * FS active low. TX data driven on falling edge of bit clock
565 * and RX data sampled on rising edge of bit clock.
566 */
567 regs->pcr0 |= FSXP | FSRP |
568 CLKXP | CLKRP;
569 break;
570 case SND_SOC_DAIFMT_NB_IF:
571 regs->pcr0 |= CLKXP | CLKRP;
572 break;
573 case SND_SOC_DAIFMT_IB_NF:
574 regs->pcr0 |= FSXP | FSRP;
575 break;
576 case SND_SOC_DAIFMT_IB_IF:
577 break;
578 default:
579 return -EINVAL;
580 }
581
582 return 0;
583}
584
8687eb8b 585static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 586 int div_id, int div)
587{
f0fba2ad 588 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
2e74796a
JN		 589 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
590
591 if (div_id != OMAP_MCBSP_CLKGDV)
592 return -ENODEV;
593
5f63ef99 594 mcbsp_data->clk_div = div;
2e74796a
JN		 595 regs->srgr1 |= CLKGDV(div - 1);
596
597 return 0;
598}
599
8687eb8b 600static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
2e74796a
JN		 601 int clk_id, unsigned int freq,
602 int dir)
603{
f0fba2ad 604 struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
2e74796a
JN		 605 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
606 int err = 0;
607
cf4c87ab
PW		 608 /* The McBSP signal muxing functions are only available on McBSP1 */
609 if (clk_id == OMAP_MCBSP_CLKR_SRC_CLKR ||
610 clk_id == OMAP_MCBSP_CLKR_SRC_CLKX ||
611 clk_id == OMAP_MCBSP_FSR_SRC_FSR ||
612 clk_id == OMAP_MCBSP_FSR_SRC_FSX)
613 if (cpu_class_is_omap1() || mcbsp_data->bus_id != 0)
614 return -EINVAL;
615
5f63ef99
GG		 616 mcbsp_data->in_freq = freq;
617
2e74796a
JN		 618 switch (clk_id) {
619 case OMAP_MCBSP_SYSCLK_CLK:
620 regs->srgr2 |= CLKSM;
621 break;
622 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
d1358657
PW		 623 if (cpu_class_is_omap1()) {
624 err = -EINVAL;
625 break;
626 }
627 err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id,
628 MCBSP_CLKS_PRCM_SRC);
629 break;
2e74796a 630 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
d1358657
PW		 631 if (cpu_class_is_omap1()) {
632 err = 0;
633 break;
634 }
635 err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id,
636 MCBSP_CLKS_PAD_SRC);
2e74796a
JN		 637 break;
638
639 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
640 regs->srgr2 |= CLKSM;
641 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
642 regs->pcr0 |= SCLKME;
643 break;
d2c0bdaa 644
cf4c87ab 645
d2c0bdaa 646 case OMAP_MCBSP_CLKR_SRC_CLKR:
cf4c87ab
PW		 647 omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKR);
648 break;
d2c0bdaa 649 case OMAP_MCBSP_CLKR_SRC_CLKX:
cf4c87ab
PW		 650 omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKX);
651 break;
d2c0bdaa 652 case OMAP_MCBSP_FSR_SRC_FSR:
cf4c87ab
PW		 653 omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSR);
654 break;
d2c0bdaa 655 case OMAP_MCBSP_FSR_SRC_FSX:
cf4c87ab 656 omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSX);
d2c0bdaa 657 break;
2e74796a
JN		 658 default:
659 err = -ENODEV;
660 }
661
662 return err;
663}
664
f0fba2ad 665static struct snd_soc_dai_ops mcbsp_dai_ops = {
6335d055
EM		 666 .startup = omap_mcbsp_dai_startup,
667 .shutdown = omap_mcbsp_dai_shutdown,
668 .trigger = omap_mcbsp_dai_trigger,
75581d24 669 .delay = omap_mcbsp_dai_delay,
6335d055
EM		 670 .hw_params = omap_mcbsp_dai_hw_params,
671 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
672 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
673 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
674};
675
f0fba2ad
LG		 676static int mcbsp_dai_probe(struct snd_soc_dai *dai)
677{
678 mcbsp_data[dai->id].bus_id = dai->id;
679 snd_soc_dai_set_drvdata(dai, &mcbsp_data[dai->id].bus_id);
680 return 0;
8def464d
JN		 681}
682
f0fba2ad
LG		 683static struct snd_soc_dai_driver omap_mcbsp_dai =
684{
685 .probe = mcbsp_dai_probe,
686 .playback = {
687 .channels_min = 1,
688 .channels_max = 16,
689 .rates = OMAP_MCBSP_RATES,
690 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
691 },
692 .capture = {
693 .channels_min = 1,
694 .channels_max = 16,
695 .rates = OMAP_MCBSP_RATES,
696 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
697 },
698 .ops = &mcbsp_dai_ops,
2e74796a 699};
8def464d 700
3484457f 701static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
83905c13
IK		 702 struct snd_ctl_elem_info *uinfo)
703{
704 struct soc_mixer_control *mc =
705 (struct soc_mixer_control *)kcontrol->private_value;
706 int max = mc->max;
707 int min = mc->min;
708
709 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
710 uinfo->count = 1;
711 uinfo->value.integer.min = min;
712 uinfo->value.integer.max = max;
713 return 0;
714}
715
716#define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \
717static int \
718omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
719 struct snd_ctl_elem_value *uc) \
720{ \
721 struct soc_mixer_control *mc = \
722 (struct soc_mixer_control *)kc->private_value; \
723 int max = mc->max; \
724 int min = mc->min; \
725 int val = uc->value.integer.value[0]; \
726 \
727 if (val < min || val > max) \
728 return -EINVAL; \
729 \
730 /* OMAP McBSP implementation uses index values 0..4 */ \
731 return omap_st_set_chgain((id)-1, channel, val); \
732}
733
734#define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \
735static int \
736omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
737 struct snd_ctl_elem_value *uc) \
738{ \
739 s16 chgain; \
740 \
741 if (omap_st_get_chgain((id)-1, channel, &chgain)) \
742 return -EAGAIN; \
743 \
744 uc->value.integer.value[0] = chgain; \
745 return 0; \
746}
747
748OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
749OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
750OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
751OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
752OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
753OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
754OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
755OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
756
757static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
758 struct snd_ctl_elem_value *ucontrol)
759{
760 struct soc_mixer_control *mc =
761 (struct soc_mixer_control *)kcontrol->private_value;
762 u8 value = ucontrol->value.integer.value[0];
763
764 if (value == omap_st_is_enabled(mc->reg))
765 return 0;
766
767 if (value)
768 omap_st_enable(mc->reg);
769 else
770 omap_st_disable(mc->reg);
771
772 return 1;
773}
774
775static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
776 struct snd_ctl_elem_value *ucontrol)
777{
778 struct soc_mixer_control *mc =
779 (struct soc_mixer_control *)kcontrol->private_value;
780
781 ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
782 return 0;
783}
784
785static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
786 SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
787 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
788 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
789 -32768, 32767,
790 omap_mcbsp2_get_st_ch0_volume,
791 omap_mcbsp2_set_st_ch0_volume),
792 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
793 -32768, 32767,
794 omap_mcbsp2_get_st_ch1_volume,
795 omap_mcbsp2_set_st_ch1_volume),
796};
797
798static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
799 SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
800 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
801 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
802 -32768, 32767,
803 omap_mcbsp3_get_st_ch0_volume,
804 omap_mcbsp3_set_st_ch0_volume),
805 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
806 -32768, 32767,
807 omap_mcbsp3_get_st_ch1_volume,
808 omap_mcbsp3_set_st_ch1_volume),
809};
810
811int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
812{
813 if (!cpu_is_omap34xx())
814 return -ENODEV;
815
816 switch (mcbsp_id) {
817 case 1: /* McBSP 2 */
818 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
819 ARRAY_SIZE(omap_mcbsp2_st_controls));
820 case 2: /* McBSP 3 */
821 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
822 ARRAY_SIZE(omap_mcbsp3_st_controls));
823 default:
824 break;
825 }
826
827 return -EINVAL;
828}
829EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
830
f0fba2ad
LG		 831static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
832{
833 return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
834}
835
836static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
837{
838 snd_soc_unregister_dai(&pdev->dev);
839 return 0;
840}
841
842static struct platform_driver asoc_mcbsp_driver = {
843 .driver = {
844 .name = "omap-mcbsp-dai",
845 .owner = THIS_MODULE,
846 },
847
848 .probe = asoc_mcbsp_probe,
849 .remove = __devexit_p(asoc_mcbsp_remove),
850};
851
f73f2a6a 852static int __init snd_omap_mcbsp_init(void)
3f4b783c 853{
f0fba2ad 854 return platform_driver_register(&asoc_mcbsp_driver);
3f4b783c 855}
f73f2a6a 856module_init(snd_omap_mcbsp_init);
3f4b783c 857
f73f2a6a 858static void __exit snd_omap_mcbsp_exit(void)
3f4b783c 859{
f0fba2ad 860 platform_driver_unregister(&asoc_mcbsp_driver);
3f4b783c 861}
f73f2a6a 862module_exit(snd_omap_mcbsp_exit);
3f4b783c 863
b08f7a62 864MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
2e74796a
JN		 865MODULE_DESCRIPTION("OMAP I2S SoC Interface");
866MODULE_LICENSE("GPL");
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