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ASoC: Remove volatility from WM8900 POWER1 register
[net-next-2.6.git] / sound / soc / codecs / wm8900.c
CommitLineData
0e0e16a8
MB		 1/*
2 * wm8900.c -- WM8900 ALSA Soc Audio driver
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - Tristating.
14 * - TDM.
15 * - Jack detect.
16 * - FLL source configuration, currently only MCLK is supported.
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
0e0e16a8
MB		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/pm.h>
25#include <linux/i2c.h>
f0fba2ad 26#include <linux/spi/spi.h>
0e0e16a8 27#include <linux/platform_device.h>
5a0e3ad6 28#include <linux/slab.h>
0e0e16a8
MB		 29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
33#include <sound/soc-dapm.h>
34#include <sound/initval.h>
35#include <sound/tlv.h>
36
37#include "wm8900.h"
38
39/* WM8900 register space */
40#define WM8900_REG_RESET 0x0
41#define WM8900_REG_ID 0x0
42#define WM8900_REG_POWER1 0x1
43#define WM8900_REG_POWER2 0x2
44#define WM8900_REG_POWER3 0x3
45#define WM8900_REG_AUDIO1 0x4
46#define WM8900_REG_AUDIO2 0x5
47#define WM8900_REG_CLOCKING1 0x6
48#define WM8900_REG_CLOCKING2 0x7
49#define WM8900_REG_AUDIO3 0x8
50#define WM8900_REG_AUDIO4 0x9
51#define WM8900_REG_DACCTRL 0xa
52#define WM8900_REG_LDAC_DV 0xb
53#define WM8900_REG_RDAC_DV 0xc
54#define WM8900_REG_SIDETONE 0xd
55#define WM8900_REG_ADCCTRL 0xe
56#define WM8900_REG_LADC_DV 0xf
57#define WM8900_REG_RADC_DV 0x10
58#define WM8900_REG_GPIO 0x12
59#define WM8900_REG_INCTL 0x15
60#define WM8900_REG_LINVOL 0x16
61#define WM8900_REG_RINVOL 0x17
62#define WM8900_REG_INBOOSTMIX1 0x18
63#define WM8900_REG_INBOOSTMIX2 0x19
64#define WM8900_REG_ADCPATH 0x1a
65#define WM8900_REG_AUXBOOST 0x1b
66#define WM8900_REG_ADDCTL 0x1e
67#define WM8900_REG_FLLCTL1 0x24
68#define WM8900_REG_FLLCTL2 0x25
69#define WM8900_REG_FLLCTL3 0x26
70#define WM8900_REG_FLLCTL4 0x27
71#define WM8900_REG_FLLCTL5 0x28
72#define WM8900_REG_FLLCTL6 0x29
73#define WM8900_REG_LOUTMIXCTL1 0x2c
74#define WM8900_REG_ROUTMIXCTL1 0x2d
75#define WM8900_REG_BYPASS1 0x2e
76#define WM8900_REG_BYPASS2 0x2f
77#define WM8900_REG_AUXOUT_CTL 0x30
78#define WM8900_REG_LOUT1CTL 0x33
79#define WM8900_REG_ROUT1CTL 0x34
80#define WM8900_REG_LOUT2CTL 0x35
81#define WM8900_REG_ROUT2CTL 0x36
82#define WM8900_REG_HPCTL1 0x3a
83#define WM8900_REG_OUTBIASCTL 0x73
84
85#define WM8900_MAXREG 0x80
86
87#define WM8900_REG_ADDCTL_OUT1_DIS 0x80
88#define WM8900_REG_ADDCTL_OUT2_DIS 0x40
89#define WM8900_REG_ADDCTL_VMID_DIS 0x20
90#define WM8900_REG_ADDCTL_BIAS_SRC 0x10
91#define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
92#define WM8900_REG_ADDCTL_TEMP_SD 0x02
93
94#define WM8900_REG_GPIO_TEMP_ENA 0x2
95
96#define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
97#define WM8900_REG_POWER1_BIAS_ENA 0x0008
98#define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
99#define WM8900_REG_POWER1_FLL_ENA 0x0040
100
101#define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
102#define WM8900_REG_POWER2_ADCL_ENA 0x0002
103#define WM8900_REG_POWER2_ADCR_ENA 0x0001
104
105#define WM8900_REG_POWER3_DACL_ENA 0x0002
106#define WM8900_REG_POWER3_DACR_ENA 0x0001
107
108#define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
109#define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
110#define WM8900_REG_AUDIO1_BCLK_INV 0x0100
111
112#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
113#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
114#define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
115#define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
116
117#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
118#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
119
120#define WM8900_REG_DACCTRL_MUTE 0x004
21002e20 121#define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
0e0e16a8
MB		 122#define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
123
124#define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
125
126#define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
127
128#define WM8900_REG_FLLCTL1_OSC_ENA 0x100
129
130#define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
131
132#define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
133#define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
134#define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
135#define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
136#define WM8900_REG_HPCTL1_HP_SHORT 0x08
137#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
138
139#define WM8900_LRC_MASK 0xfc00
140
0e0e16a8 141struct wm8900_priv {
f0fba2ad 142 enum snd_soc_control_type control_type;
78e19a39
MB		 143 u16 reg_cache[WM8900_MAXREG];
144
0e0e16a8
MB		 145 u32 fll_in; /* FLL input frequency */
146 u32 fll_out; /* FLL output frequency */
147};
148
149/*
150 * wm8900 register cache. We can't read the entire register space and we
151 * have slow control buses so we cache the registers.
152 */
153static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
154 0x8900, 0x0000,
155 0xc000, 0x0000,
156 0x4050, 0x4000,
157 0x0008, 0x0000,
158 0x0040, 0x0040,
159 0x1004, 0x00c0,
160 0x00c0, 0x0000,
161 0x0100, 0x00c0,
162 0x00c0, 0x0000,
163 0xb001, 0x0000,
164 0x0000, 0x0044,
165 0x004c, 0x004c,
166 0x0044, 0x0044,
167 0x0000, 0x0044,
168 0x0000, 0x0000,
169 0x0002, 0x0000,
170 0x0000, 0x0000,
171 0x0000, 0x0000,
172 0x0008, 0x0000,
173 0x0000, 0x0008,
174 0x0097, 0x0100,
175 0x0000, 0x0000,
176 0x0050, 0x0050,
177 0x0055, 0x0055,
178 0x0055, 0x0000,
179 0x0000, 0x0079,
180 0x0079, 0x0079,
181 0x0079, 0x0000,
182 /* Remaining registers all zero */
183};
184
8d50e447 185static int wm8900_volatile_register(unsigned int reg)
0e0e16a8
MB		 186{
187 switch (reg) {
188 case WM8900_REG_ID:
8d50e447 189 return 1;
0e0e16a8 190 default:
8d50e447 191 return 0;
0e0e16a8
MB		 192 }
193}
194
195static void wm8900_reset(struct snd_soc_codec *codec)
196{
8d50e447 197 snd_soc_write(codec, WM8900_REG_RESET, 0);
0e0e16a8
MB		 198
199 memcpy(codec->reg_cache, wm8900_reg_defaults,
bc258006 200 sizeof(wm8900_reg_defaults));
0e0e16a8
MB		 201}
202
203static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
204 struct snd_kcontrol *kcontrol, int event)
205{
206 struct snd_soc_codec *codec = w->codec;
8d50e447 207 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
0e0e16a8
MB		 208
209 switch (event) {
210 case SND_SOC_DAPM_PRE_PMU:
211 /* Clamp headphone outputs */
212 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
213 WM8900_REG_HPCTL1_HP_CLAMP_OP;
8d50e447 214 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 215 break;
216
217 case SND_SOC_DAPM_POST_PMU:
218 /* Enable the input stage */
219 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
220 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
221 WM8900_REG_HPCTL1_HP_SHORT2 |
222 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 223 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 224
225 msleep(400);
226
227 /* Enable the output stage */
228 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
229 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 230 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 231
232 /* Remove the shorts */
233 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
8d50e447 234 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8 235 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 236 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 237 break;
238
239 case SND_SOC_DAPM_PRE_PMD:
240 /* Short the output */
241 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 242 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 243
244 /* Disable the output stage */
245 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 246 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 247
248 /* Clamp the outputs and power down input */
249 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
250 WM8900_REG_HPCTL1_HP_CLAMP_OP;
251 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 252 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 253 break;
254
255 case SND_SOC_DAPM_POST_PMD:
256 /* Disable everything */
8d50e447 257 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 258 break;
259
260 default:
261 BUG();
262 }
263
264 return 0;
265}
266
267static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
268
269static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
270
271static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
272
273static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
274
275static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
276
277static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
278
279static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
280
281static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
282
283static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
284
285static const struct soc_enum mic_bias_level =
286SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
287
288static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
289
290static const struct soc_enum dac_mute_rate =
291SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
292
293static const char *dac_deemphasis_txt[] = {
294 "Disabled", "32kHz", "44.1kHz", "48kHz"
295};
296
297static const struct soc_enum dac_deemphasis =
298SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
299
300static const char *adc_hpf_cut_txt[] = {
301 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
302};
303
304static const struct soc_enum adc_hpf_cut =
305SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
306
307static const char *lr_txt[] = {
308 "Left", "Right"
309};
310
311static const struct soc_enum aifl_src =
312SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
313
314static const struct soc_enum aifr_src =
315SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
316
317static const struct soc_enum dacl_src =
318SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
319
320static const struct soc_enum dacr_src =
321SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
322
323static const char *sidetone_txt[] = {
324 "Disabled", "Left ADC", "Right ADC"
325};
326
327static const struct soc_enum dacl_sidetone =
328SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
329
330static const struct soc_enum dacr_sidetone =
331SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
332
333static const struct snd_kcontrol_new wm8900_snd_controls[] = {
334SOC_ENUM("Mic Bias Level", mic_bias_level),
335
336SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
337 in_pga_tlv),
338SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
339SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
340
341SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
342 in_pga_tlv),
343SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
344SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
345
346SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
347SOC_ENUM("DAC Mute Rate", dac_mute_rate),
348SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
349SOC_ENUM("DAC Deemphasis", dac_deemphasis),
0e0e16a8
MB		 350SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
351 12, 1, 0),
352
353SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
354SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
355SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
356SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
357 adc_svol_tlv),
358SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
359 adc_svol_tlv),
360SOC_ENUM("Left Digital Audio Source", aifl_src),
361SOC_ENUM("Right Digital Audio Source", aifr_src),
362
363SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
364 dac_boost_tlv),
365SOC_ENUM("Left DAC Source", dacl_src),
366SOC_ENUM("Right DAC Source", dacr_src),
367SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
368SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
369SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
370
371SOC_DOUBLE_R_TLV("Digital Playback Volume",
372 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
373 1, 96, 0, dac_tlv),
374SOC_DOUBLE_R_TLV("Digital Capture Volume",
375 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
376
377SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
378 out_mix_tlv),
379SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
380 out_mix_tlv),
381SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
382 out_mix_tlv),
383SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
384 out_mix_tlv),
385
386SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
387 out_mix_tlv),
388SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
389 out_mix_tlv),
390SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
391 out_mix_tlv),
392SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
393 out_mix_tlv),
394
395SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
396 in_boost_tlv),
397SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
398 in_boost_tlv),
399SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
400 in_boost_tlv),
401SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
402 in_boost_tlv),
403SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
404 in_boost_tlv),
405SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
406 in_boost_tlv),
407
408SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
409 0, 63, 0, out_pga_tlv),
410SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
411 6, 1, 1),
412SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
413 7, 1, 0),
414
415SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
416 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
417 0, 63, 0, out_pga_tlv),
418SOC_DOUBLE_R("LINEOUT2 Switch",
419 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
420SOC_DOUBLE_R("LINEOUT2 ZC Switch",
421 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
422SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
423 0, 1, 1),
424
425};
426
0e0e16a8
MB		 427static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
428SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
429
430static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
431SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
432
433static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
434SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
435SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
436SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
437SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
438SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
439};
440
441static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
442SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
443SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
444SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
445SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
446SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
447};
448
449static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
450SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
451SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
452SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
453SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
454};
455
456static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
457SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
458SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
459SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
460SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
461};
462
463static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
464SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
465SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
466SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
467};
468
469static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
470SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
471SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
472SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
473};
474
475static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
476
477static const struct soc_enum wm8900_lineout2_lp_mux =
478SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
479
480static const struct snd_kcontrol_new wm8900_lineout2_lp =
481SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
482
483static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
484
485/* Externally visible pins */
486SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
487SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
488SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
489SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
490SND_SOC_DAPM_OUTPUT("HP_L"),
491SND_SOC_DAPM_OUTPUT("HP_R"),
492
493SND_SOC_DAPM_INPUT("RINPUT1"),
494SND_SOC_DAPM_INPUT("LINPUT1"),
495SND_SOC_DAPM_INPUT("RINPUT2"),
496SND_SOC_DAPM_INPUT("LINPUT2"),
497SND_SOC_DAPM_INPUT("RINPUT3"),
498SND_SOC_DAPM_INPUT("LINPUT3"),
499SND_SOC_DAPM_INPUT("AUX"),
500
501SND_SOC_DAPM_VMID("VMID"),
502
503/* Input */
504SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
505 wm8900_linpga_controls,
506 ARRAY_SIZE(wm8900_linpga_controls)),
507SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
508 wm8900_rinpga_controls,
509 ARRAY_SIZE(wm8900_rinpga_controls)),
510
511SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
512 wm8900_linmix_controls,
513 ARRAY_SIZE(wm8900_linmix_controls)),
514SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
515 wm8900_rinmix_controls,
516 ARRAY_SIZE(wm8900_rinmix_controls)),
517
518SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0),
519
520SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
521SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
522
523/* Output */
524SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
525SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
526
527SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
528 wm8900_hp_event,
529 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
530 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
531
532SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
533SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
534
535SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
536SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
537SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
538
539SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
540 wm8900_loutmix_controls,
541 ARRAY_SIZE(wm8900_loutmix_controls)),
542SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
543 wm8900_routmix_controls,
544 ARRAY_SIZE(wm8900_routmix_controls)),
545};
546
547/* Target, Path, Source */
548static const struct snd_soc_dapm_route audio_map[] = {
549/* Inputs */
550{"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
551{"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
552{"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
553
554{"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
555{"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
556{"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
557
558{"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
559{"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
560{"Left Input Mixer", "AUX Switch", "AUX"},
561{"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
562
563{"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
564{"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
565{"Right Input Mixer", "AUX Switch", "AUX"},
566{"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
567
568{"ADCL", NULL, "Left Input Mixer"},
569{"ADCR", NULL, "Right Input Mixer"},
570
571/* Outputs */
572{"LINEOUT1L", NULL, "LINEOUT1L PGA"},
573{"LINEOUT1L PGA", NULL, "Left Output Mixer"},
574{"LINEOUT1R", NULL, "LINEOUT1R PGA"},
575{"LINEOUT1R PGA", NULL, "Right Output Mixer"},
576
577{"LINEOUT2L PGA", NULL, "Left Output Mixer"},
578{"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
579{"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
580{"LINEOUT2L", NULL, "LINEOUT2 LP"},
581
582{"LINEOUT2R PGA", NULL, "Right Output Mixer"},
583{"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
584{"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
585{"LINEOUT2R", NULL, "LINEOUT2 LP"},
586
587{"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
588{"Left Output Mixer", "AUX Bypass Switch", "AUX"},
589{"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
590{"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
591{"Left Output Mixer", "DACL Switch", "DACL"},
592
593{"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
594{"Right Output Mixer", "AUX Bypass Switch", "AUX"},
595{"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
596{"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
597{"Right Output Mixer", "DACR Switch", "DACR"},
598
599/* Note that the headphone output stage needs to be connected
600 * externally to LINEOUT2 via DC blocking capacitors. Other
601 * configurations are not supported.
602 *
603 * Note also that left and right headphone paths are treated as a
604 * mono path.
605 */
606{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
607{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
608{"HP_L", NULL, "Headphone Amplifier"},
609{"HP_R", NULL, "Headphone Amplifier"},
610};
611
612static int wm8900_add_widgets(struct snd_soc_codec *codec)
613{
614 snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets,
615 ARRAY_SIZE(wm8900_dapm_widgets));
616
617 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
618
0e0e16a8
MB		 619 return 0;
620}
621
622static int wm8900_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 623 struct snd_pcm_hw_params *params,
624 struct snd_soc_dai *dai)
0e0e16a8
MB		 625{
626 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 627 struct snd_soc_codec *codec = rtd->codec;
0e0e16a8
MB		 628 u16 reg;
629
8d50e447 630 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
0e0e16a8
MB		 631
632 switch (params_format(params)) {
633 case SNDRV_PCM_FORMAT_S16_LE:
634 break;
635 case SNDRV_PCM_FORMAT_S20_3LE:
636 reg |= 0x20;
637 break;
638 case SNDRV_PCM_FORMAT_S24_LE:
639 reg |= 0x40;
640 break;
641 case SNDRV_PCM_FORMAT_S32_LE:
642 reg |= 0x60;
643 break;
644 default:
645 return -EINVAL;
646 }
647
8d50e447 648 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
0e0e16a8 649
21002e20 650 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
8d50e447 651 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
21002e20
MB		 652
653 if (params_rate(params) <= 24000)
654 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
655 else
656 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
657
8d50e447 658 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
21002e20
MB		 659 }
660
0e0e16a8
MB		 661 return 0;
662}
663
664/* FLL divisors */
665struct _fll_div {
666 u16 fll_ratio;
667 u16 fllclk_div;
668 u16 fll_slow_lock_ref;
669 u16 n;
670 u16 k;
671};
672
673/* The size in bits of the FLL divide multiplied by 10
674 * to allow rounding later */
675#define FIXED_FLL_SIZE ((1 << 16) * 10)
676
677static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
678 unsigned int Fout)
679{
680 u64 Kpart;
681 unsigned int K, Ndiv, Nmod, target;
682 unsigned int div;
683
684 BUG_ON(!Fout);
685
686 /* The FLL must run at 90-100MHz which is then scaled down to
687 * the output value by FLLCLK_DIV. */
688 target = Fout;
689 div = 1;
690 while (target < 90000000) {
691 div *= 2;
692 target *= 2;
693 }
694
695 if (target > 100000000)
449bd54d
RK		 696 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
697 " Fout=%u\n", target, Fref, Fout);
0e0e16a8
MB		 698 if (div > 32) {
699 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
449bd54d 700 "Fref=%u, Fout=%u, target=%u\n",
0e0e16a8
MB		 701 div, Fref, Fout, target);
702 return -EINVAL;
703 }
704
705 fll_div->fllclk_div = div >> 2;
706
707 if (Fref < 48000)
708 fll_div->fll_slow_lock_ref = 1;
709 else
710 fll_div->fll_slow_lock_ref = 0;
711
712 Ndiv = target / Fref;
713
714 if (Fref < 1000000)
715 fll_div->fll_ratio = 8;
716 else
717 fll_div->fll_ratio = 1;
718
719 fll_div->n = Ndiv / fll_div->fll_ratio;
720 Nmod = (target / fll_div->fll_ratio) % Fref;
721
722 /* Calculate fractional part - scale up so we can round. */
723 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
724
725 do_div(Kpart, Fref);
726
727 K = Kpart & 0xFFFFFFFF;
728
729 if ((K % 10) >= 5)
730 K += 5;
731
732 /* Move down to proper range now rounding is done */
733 fll_div->k = K / 10;
734
735 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
736 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
737
738 return 0;
739}
740
741static int wm8900_set_fll(struct snd_soc_codec *codec,
742 int fll_id, unsigned int freq_in, unsigned int freq_out)
743{
b2c812e2 744 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 745 struct _fll_div fll_div;
746 unsigned int reg;
747
748 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
749 return 0;
750
751 /* The digital side should be disabled during any change. */
8d50e447
MB		 752 reg = snd_soc_read(codec, WM8900_REG_POWER1);
753 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 754 reg & (~WM8900_REG_POWER1_FLL_ENA));
755
756 /* Disable the FLL? */
757 if (!freq_in || !freq_out) {
8d50e447
MB		 758 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
759 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 760 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
761
8d50e447
MB		 762 reg = snd_soc_read(codec, WM8900_REG_FLLCTL1);
763 snd_soc_write(codec, WM8900_REG_FLLCTL1,
0e0e16a8
MB		 764 reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
765
766 wm8900->fll_in = freq_in;
767 wm8900->fll_out = freq_out;
768
769 return 0;
770 }
771
772 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
773 goto reenable;
774
775 wm8900->fll_in = freq_in;
776 wm8900->fll_out = freq_out;
777
778 /* The osclilator *MUST* be enabled before we enable the
779 * digital circuit. */
8d50e447 780 snd_soc_write(codec, WM8900_REG_FLLCTL1,
0e0e16a8
MB		 781 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
782
8d50e447
MB		 783 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
784 snd_soc_write(codec, WM8900_REG_FLLCTL5,
0e0e16a8
MB		 785 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
786
787 if (fll_div.k) {
8d50e447 788 snd_soc_write(codec, WM8900_REG_FLLCTL2,
0e0e16a8 789 (fll_div.k >> 8) | 0x100);
8d50e447 790 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
0e0e16a8 791 } else
8d50e447 792 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
0e0e16a8
MB		 793
794 if (fll_div.fll_slow_lock_ref)
8d50e447 795 snd_soc_write(codec, WM8900_REG_FLLCTL6,
0e0e16a8
MB		 796 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
797 else
8d50e447 798 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
0e0e16a8 799
8d50e447
MB		 800 reg = snd_soc_read(codec, WM8900_REG_POWER1);
801 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 802 reg | WM8900_REG_POWER1_FLL_ENA);
803
804reenable:
8d50e447
MB		 805 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
806 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 807 reg | WM8900_REG_CLOCKING1_MCLK_SRC);
808
809 return 0;
810}
811
85488037
MB		 812static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
813 int source, unsigned int freq_in, unsigned int freq_out)
0e0e16a8
MB		 814{
815 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
816}
817
818static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
819 int div_id, int div)
820{
821 struct snd_soc_codec *codec = codec_dai->codec;
822 unsigned int reg;
823
824 switch (div_id) {
825 case WM8900_BCLK_DIV:
8d50e447
MB		 826 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
827 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 828 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
829 break;
830 case WM8900_OPCLK_DIV:
8d50e447
MB		 831 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
832 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 833 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
834 break;
835 case WM8900_DAC_LRCLK:
8d50e447
MB		 836 reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
837 snd_soc_write(codec, WM8900_REG_AUDIO4,
0e0e16a8
MB		 838 div | (reg & WM8900_LRC_MASK));
839 break;
840 case WM8900_ADC_LRCLK:
8d50e447
MB		 841 reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
842 snd_soc_write(codec, WM8900_REG_AUDIO3,
0e0e16a8
MB		 843 div | (reg & WM8900_LRC_MASK));
844 break;
845 case WM8900_DAC_CLKDIV:
8d50e447
MB		 846 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
847 snd_soc_write(codec, WM8900_REG_CLOCKING2,
0e0e16a8
MB		 848 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
849 break;
850 case WM8900_ADC_CLKDIV:
8d50e447
MB		 851 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
852 snd_soc_write(codec, WM8900_REG_CLOCKING2,
0e0e16a8
MB		 853 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
854 break;
855 case WM8900_LRCLK_MODE:
8d50e447
MB		 856 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
857 snd_soc_write(codec, WM8900_REG_DACCTRL,
0e0e16a8
MB		 858 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
859 break;
860 default:
861 return -EINVAL;
862 }
863
864 return 0;
865}
866
867
868static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
869 unsigned int fmt)
870{
871 struct snd_soc_codec *codec = codec_dai->codec;
872 unsigned int clocking1, aif1, aif3, aif4;
873
8d50e447
MB		 874 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
875 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
876 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
877 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
0e0e16a8
MB		 878
879 /* set master/slave audio interface */
880 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
881 case SND_SOC_DAIFMT_CBS_CFS:
882 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
883 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
884 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
885 break;
886 case SND_SOC_DAIFMT_CBS_CFM:
887 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
888 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
889 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
890 break;
891 case SND_SOC_DAIFMT_CBM_CFM:
892 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
893 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
894 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
895 break;
896 case SND_SOC_DAIFMT_CBM_CFS:
897 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
898 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
899 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
900 break;
901 default:
902 return -EINVAL;
903 }
904
905 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
906 case SND_SOC_DAIFMT_DSP_A:
907 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
908 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
909 break;
910 case SND_SOC_DAIFMT_DSP_B:
911 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
912 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
913 break;
914 case SND_SOC_DAIFMT_I2S:
915 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
916 aif1 |= 0x10;
917 break;
918 case SND_SOC_DAIFMT_RIGHT_J:
919 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
920 break;
921 case SND_SOC_DAIFMT_LEFT_J:
922 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
923 aif1 |= 0x8;
924 break;
925 default:
926 return -EINVAL;
927 }
928
929 /* Clock inversion */
930 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
931 case SND_SOC_DAIFMT_DSP_A:
932 case SND_SOC_DAIFMT_DSP_B:
933 /* frame inversion not valid for DSP modes */
934 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
935 case SND_SOC_DAIFMT_NB_NF:
936 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
937 break;
938 case SND_SOC_DAIFMT_IB_NF:
939 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
940 break;
941 default:
942 return -EINVAL;
943 }
944 break;
945 case SND_SOC_DAIFMT_I2S:
946 case SND_SOC_DAIFMT_RIGHT_J:
947 case SND_SOC_DAIFMT_LEFT_J:
948 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
949 case SND_SOC_DAIFMT_NB_NF:
950 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
951 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
952 break;
953 case SND_SOC_DAIFMT_IB_IF:
954 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
955 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
956 break;
957 case SND_SOC_DAIFMT_IB_NF:
958 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
959 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
960 break;
961 case SND_SOC_DAIFMT_NB_IF:
962 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
963 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
964 break;
965 default:
966 return -EINVAL;
967 }
968 break;
969 default:
970 return -EINVAL;
971 }
972
8d50e447
MB		 973 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
974 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
975 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
976 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
0e0e16a8
MB		 977
978 return 0;
979}
980
981static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
982{
983 struct snd_soc_codec *codec = codec_dai->codec;
984 u16 reg;
985
8d50e447 986 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
0e0e16a8
MB		 987
988 if (mute)
989 reg |= WM8900_REG_DACCTRL_MUTE;
990 else
991 reg &= ~WM8900_REG_DACCTRL_MUTE;
992
8d50e447 993 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
0e0e16a8
MB		 994
995 return 0;
996}
997
998#define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
999 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1000 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1001
1002#define WM8900_PCM_FORMATS \
1003 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1004 SNDRV_PCM_FORMAT_S24_LE)
1005
6335d055
EM		 1006static struct snd_soc_dai_ops wm8900_dai_ops = {
1007 .hw_params = wm8900_hw_params,
1008 .set_clkdiv = wm8900_set_dai_clkdiv,
1009 .set_pll = wm8900_set_dai_pll,
1010 .set_fmt = wm8900_set_dai_fmt,
1011 .digital_mute = wm8900_digital_mute,
1012};
1013
f0fba2ad
LG		 1014static struct snd_soc_dai_driver wm8900_dai = {
1015 .name = "wm8900-hifi",
0e0e16a8
MB		 1016 .playback = {
1017 .stream_name = "HiFi Playback",
1018 .channels_min = 1,
1019 .channels_max = 2,
1020 .rates = WM8900_RATES,
1021 .formats = WM8900_PCM_FORMATS,
1022 },
1023 .capture = {
1024 .stream_name = "HiFi Capture",
1025 .channels_min = 1,
1026 .channels_max = 2,
1027 .rates = WM8900_RATES,
1028 .formats = WM8900_PCM_FORMATS,
1029 },
6335d055 1030 .ops = &wm8900_dai_ops,
0e0e16a8 1031};
0e0e16a8
MB		 1032
1033static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1034 enum snd_soc_bias_level level)
1035{
1036 u16 reg;
1037
1038 switch (level) {
1039 case SND_SOC_BIAS_ON:
1040 /* Enable thermal shutdown */
8d50e447
MB		 1041 reg = snd_soc_read(codec, WM8900_REG_GPIO);
1042 snd_soc_write(codec, WM8900_REG_GPIO,
0e0e16a8 1043 reg | WM8900_REG_GPIO_TEMP_ENA);
8d50e447
MB		 1044 reg = snd_soc_read(codec, WM8900_REG_ADDCTL);
1045 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1046 reg | WM8900_REG_ADDCTL_TEMP_SD);
1047 break;
1048
1049 case SND_SOC_BIAS_PREPARE:
1050 break;
1051
1052 case SND_SOC_BIAS_STANDBY:
1053 /* Charge capacitors if initial power up */
1054 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1055 /* STARTUP_BIAS_ENA on */
8d50e447 1056 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1057 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1058
1059 /* Startup bias mode */
8d50e447 1060 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1061 WM8900_REG_ADDCTL_BIAS_SRC |
1062 WM8900_REG_ADDCTL_VMID_SOFTST);
1063
1064 /* VMID 2x50k */
8d50e447 1065 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1066 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1067
1068 /* Allow capacitors to charge */
1069 schedule_timeout_interruptible(msecs_to_jiffies(400));
1070
1071 /* Enable bias */
8d50e447 1072 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1073 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1074 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1075
8d50e447 1076 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
0e0e16a8 1077
8d50e447 1078 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1079 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1080 }
1081
8d50e447
MB		 1082 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1083 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1084 (reg & WM8900_REG_POWER1_FLL_ENA) |
1085 WM8900_REG_POWER1_BIAS_ENA | 0x1);
8d50e447 1086 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8 1087 WM8900_REG_POWER2_SYSCLK_ENA);
8d50e447 1088 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1089 break;
1090
1091 case SND_SOC_BIAS_OFF:
1092 /* Startup bias enable */
8d50e447
MB		 1093 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1094 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8 1095 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
8d50e447 1096 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1097 WM8900_REG_ADDCTL_BIAS_SRC |
1098 WM8900_REG_ADDCTL_VMID_SOFTST);
1099
1100 /* Discharge caps */
8d50e447 1101 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1102 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1103 schedule_timeout_interruptible(msecs_to_jiffies(500));
1104
1105 /* Remove clamp */
8d50e447 1106 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 1107
1108 /* Power down */
8d50e447
MB		 1109 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1110 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1111 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1112 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1113
1114 /* Need to let things settle before stopping the clock
1115 * to ensure that restart works, see "Stopping the
1116 * master clock" in the datasheet. */
1117 schedule_timeout_interruptible(msecs_to_jiffies(1));
8d50e447 1118 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8
MB		 1119 WM8900_REG_POWER2_SYSCLK_ENA);
1120 break;
1121 }
1122 codec->bias_level = level;
1123 return 0;
1124}
1125
f0fba2ad 1126static int wm8900_suspend(struct snd_soc_codec *codec, pm_message_t state)
0e0e16a8 1127{
b2c812e2 1128 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 1129 int fll_out = wm8900->fll_out;
1130 int fll_in = wm8900->fll_in;
1131 int ret;
1132
1133 /* Stop the FLL in an orderly fashion */
1134 ret = wm8900_set_fll(codec, 0, 0, 0);
1135 if (ret != 0) {
f0fba2ad 1136 dev_err(codec->dev, "Failed to stop FLL\n");
0e0e16a8
MB		 1137 return ret;
1138 }
1139
1140 wm8900->fll_out = fll_out;
1141 wm8900->fll_in = fll_in;
1142
1143 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1144
1145 return 0;
1146}
1147
f0fba2ad 1148static int wm8900_resume(struct snd_soc_codec *codec)
0e0e16a8 1149{
b2c812e2 1150 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 1151 u16 *cache;
1152 int i, ret;
1153
1154 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1155 GFP_KERNEL);
1156
1157 wm8900_reset(codec);
1158 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1159
1160 /* Restart the FLL? */
1161 if (wm8900->fll_out) {
1162 int fll_out = wm8900->fll_out;
1163 int fll_in = wm8900->fll_in;
1164
1165 wm8900->fll_in = 0;
1166 wm8900->fll_out = 0;
1167
1168 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1169 if (ret != 0) {
f0fba2ad 1170 dev_err(codec->dev, "Failed to restart FLL\n");
0e0e16a8
MB		 1171 return ret;
1172 }
1173 }
1174
1175 if (cache) {
1176 for (i = 0; i < WM8900_MAXREG; i++)
8d50e447 1177 snd_soc_write(codec, i, cache[i]);
0e0e16a8
MB		 1178 kfree(cache);
1179 } else
f0fba2ad 1180 dev_err(codec->dev, "Unable to allocate register cache\n");
0e0e16a8
MB		 1181
1182 return 0;
1183}
1184
f0fba2ad 1185static int wm8900_probe(struct snd_soc_codec *codec)
0e0e16a8 1186{
f0fba2ad
LG		 1187 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1188 int ret = 0, reg;
78e19a39 1189
f0fba2ad 1190 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8900->control_type);
8d50e447 1191 if (ret != 0) {
f0fba2ad
LG		 1192 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1193 return ret;
8d50e447
MB		 1194 }
1195
1196 reg = snd_soc_read(codec, WM8900_REG_ID);
0e0e16a8 1197 if (reg != 0x8900) {
f0fba2ad
LG		 1198 dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
1199 return -ENODEV;
0e0e16a8
MB		 1200 }
1201
0e0e16a8
MB		 1202 wm8900_reset(codec);
1203
78e19a39
MB		 1204 /* Turn the chip on */
1205 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1206
0e0e16a8 1207 /* Latch the volume update bits */
8d50e447
MB		 1208 snd_soc_write(codec, WM8900_REG_LINVOL,
1209 snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100);
1210 snd_soc_write(codec, WM8900_REG_RINVOL,
1211 snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100);
1212 snd_soc_write(codec, WM8900_REG_LOUT1CTL,
1213 snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1214 snd_soc_write(codec, WM8900_REG_ROUT1CTL,
1215 snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1216 snd_soc_write(codec, WM8900_REG_LOUT2CTL,
1217 snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1218 snd_soc_write(codec, WM8900_REG_ROUT2CTL,
1219 snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1220 snd_soc_write(codec, WM8900_REG_LDAC_DV,
1221 snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1222 snd_soc_write(codec, WM8900_REG_RDAC_DV,
1223 snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1224 snd_soc_write(codec, WM8900_REG_LADC_DV,
1225 snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100);
1226 snd_soc_write(codec, WM8900_REG_RADC_DV,
1227 snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100);
0e0e16a8
MB		 1228
1229 /* Set the DAC and mixer output bias */
8d50e447 1230 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
0e0e16a8 1231
f0fba2ad
LG		 1232 snd_soc_add_controls(codec, wm8900_snd_controls,
1233 ARRAY_SIZE(wm8900_snd_controls));
1234 wm8900_add_widgets(codec);
0e0e16a8 1235
f0fba2ad
LG		 1236 return 0;
1237}
0e0e16a8 1238
f0fba2ad
LG		 1239/* power down chip */
1240static int wm8900_remove(struct snd_soc_codec *codec)
1241{
1242 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1243 return 0;
1244}
0e0e16a8 1245
f0fba2ad
LG		 1246static struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
1247 .probe = wm8900_probe,
1248 .remove = wm8900_remove,
1249 .suspend = wm8900_suspend,
1250 .resume = wm8900_resume,
1251 .set_bias_level = wm8900_set_bias_level,
1252 .volatile_register = wm8900_volatile_register,
e5eec34c 1253 .reg_cache_size = ARRAY_SIZE(wm8900_reg_defaults),
f0fba2ad
LG		 1254 .reg_word_size = sizeof(u16),
1255 .reg_cache_default = wm8900_reg_defaults,
1256};
0e0e16a8 1257
f0fba2ad
LG		 1258#if defined(CONFIG_SPI_MASTER)
1259static int __devinit wm8900_spi_probe(struct spi_device *spi)
1260{
1261 struct wm8900_priv *wm8900;
1262 int ret;
1263
1264 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1265 if (wm8900 == NULL)
1266 return -ENOMEM;
0e0e16a8 1267
f0fba2ad
LG		 1268 wm8900->control_type = SND_SOC_SPI;
1269 spi_set_drvdata(spi, wm8900);
1270
1271 ret = snd_soc_register_codec(&spi->dev,
1272 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1273 if (ret < 0)
1274 kfree(wm8900);
78e19a39 1275 return ret;
0e0e16a8
MB		 1276}
1277
f0fba2ad 1278static int __devexit wm8900_spi_remove(struct spi_device *spi)
0e0e16a8 1279{
f0fba2ad
LG		 1280 snd_soc_unregister_codec(&spi->dev);
1281 kfree(spi_get_drvdata(spi));
1282 return 0;
1283}
78e19a39 1284
f0fba2ad
LG		 1285static struct spi_driver wm8900_spi_driver = {
1286 .driver = {
1287 .name = "wm8900-codec",
f0fba2ad
LG		 1288 .owner = THIS_MODULE,
1289 },
1290 .probe = wm8900_spi_probe,
1291 .remove = __devexit_p(wm8900_spi_remove),
1292};
1293#endif /* CONFIG_SPI_MASTER */
1294
1295#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1296static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1297 const struct i2c_device_id *id)
1298{
1299 struct wm8900_priv *wm8900;
1300 int ret;
1301
1302 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1303 if (wm8900 == NULL)
1304 return -ENOMEM;
1305
1306 i2c_set_clientdata(i2c, wm8900);
f0fba2ad 1307 wm8900->control_type = SND_SOC_I2C;
78e19a39 1308
f0fba2ad
LG		 1309 ret = snd_soc_register_codec(&i2c->dev,
1310 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1311 if (ret < 0)
1312 kfree(wm8900);
1313 return ret;
1314}
78e19a39 1315
f0fba2ad
LG		 1316static __devexit int wm8900_i2c_remove(struct i2c_client *client)
1317{
1318 snd_soc_unregister_codec(&client->dev);
1319 kfree(i2c_get_clientdata(client));
0e0e16a8
MB		 1320 return 0;
1321}
1322
8ae6a552
JD		 1323static const struct i2c_device_id wm8900_i2c_id[] = {
1324 { "wm8900", 0 },
1325 { }
1326};
1327MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
0e0e16a8 1328
0e0e16a8
MB		 1329static struct i2c_driver wm8900_i2c_driver = {
1330 .driver = {
f0fba2ad 1331 .name = "wm8900-codec",
0e0e16a8
MB		 1332 .owner = THIS_MODULE,
1333 },
f0fba2ad
LG		 1334 .probe = wm8900_i2c_probe,
1335 .remove = __devexit_p(wm8900_i2c_remove),
8ae6a552 1336 .id_table = wm8900_i2c_id,
0e0e16a8 1337};
f0fba2ad 1338#endif
0e0e16a8 1339
f0fba2ad 1340static int __init wm8900_modinit(void)
0e0e16a8 1341{
0e0e16a8 1342 int ret = 0;
f0fba2ad
LG		 1343#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1344 ret = i2c_add_driver(&wm8900_i2c_driver);
1345 if (ret != 0) {
1346 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1347 ret);
f0752331 1348 }
f0fba2ad
LG		 1349#endif
1350#if defined(CONFIG_SPI_MASTER)
1351 ret = spi_register_driver(&wm8900_spi_driver);
1352 if (ret != 0) {
1353 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1354 ret);
78e19a39 1355 }
f0fba2ad 1356#endif
0e0e16a8
MB		 1357 return ret;
1358}
64089b84
MB		 1359module_init(wm8900_modinit);
1360
1361static void __exit wm8900_exit(void)
1362{
f0fba2ad 1363#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
f0752331 1364 i2c_del_driver(&wm8900_i2c_driver);
f0fba2ad
LG		 1365#endif
1366#if defined(CONFIG_SPI_MASTER)
1367 spi_unregister_driver(&wm8900_spi_driver);
1368#endif
64089b84
MB		 1369}
1370module_exit(wm8900_exit);
1371
0e0e16a8
MB		 1372MODULE_DESCRIPTION("ASoC WM8900 driver");
1373MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1374MODULE_LICENSE("GPL");
Clone of davem's net-next-2.6 tree