[net-next-2.6.git] / net / dsa / mv88e6060.c

/*
 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
 * Copyright (c) 2008-2009 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/list.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include "dsa_priv.h"

#define REG_PORT(p)		(8 + (p))
#define REG_GLOBAL		0x0f

static int reg_read(struct dsa_switch *ds, int addr, int reg)
{
	return mdiobus_read(ds->master_mii_bus, addr, reg);
}

#define REG_READ(addr, reg)					\
	({							\
		int __ret;					\
								\
		__ret = reg_read(ds, addr, reg);		\
		if (__ret < 0)					\
			return __ret;				\
		__ret;						\
	})


static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
{
	return mdiobus_write(ds->master_mii_bus, addr, reg, val);
}

#define REG_WRITE(addr, reg, val)				\
	({							\
		int __ret;					\
								\
		__ret = reg_write(ds, addr, reg, val);		\
		if (__ret < 0)					\
			return __ret;				\
	})

static char *mv88e6060_probe(struct mii_bus *bus, int sw_addr)
{
	int ret;

	ret = mdiobus_read(bus, REG_PORT(0), 0x03);
	if (ret >= 0) {
		ret &= 0xfff0;
		if (ret == 0x0600)
			return "Marvell 88E6060";
	}

	return NULL;
}

static int mv88e6060_switch_reset(struct dsa_switch *ds)
{
	int i;
	int ret;

	/*
	 * Set all ports to the disabled state.
	 */
	for (i = 0; i < 6; i++) {
		ret = REG_READ(REG_PORT(i), 0x04);
		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	}

	/*
	 * Wait for transmit queues to drain.
	 */
	msleep(2);

	/*
	 * Reset the switch.
	 */
	REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);

	/*
	 * Wait up to one second for reset to complete.
	 */
	for (i = 0; i < 1000; i++) {
		ret = REG_READ(REG_GLOBAL, 0x00);
		if ((ret & 0x8000) == 0x0000)
			break;

		msleep(1);
	}
	if (i == 1000)
		return -ETIMEDOUT;

	return 0;
}

static int mv88e6060_setup_global(struct dsa_switch *ds)
{
	/*
	 * Disable discarding of frames with excessive collisions,
	 * set the maximum frame size to 1536 bytes, and mask all
	 * interrupt sources.
	 */
	REG_WRITE(REG_GLOBAL, 0x04, 0x0800);

	/*
	 * Enable automatic address learning, set the address
	 * database size to 1024 entries, and set the default aging
	 * time to 5 minutes.
	 */
	REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);

	return 0;
}

static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
{
	int addr = REG_PORT(p);

	/*
	 * Do not force flow control, disable Ingress and Egress
	 * Header tagging, disable VLAN tunneling, and set the port
	 * state to Forwarding.  Additionally, if this is the CPU
	 * port, enable Ingress and Egress Trailer tagging mode.
	 */
	REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ?  0x4103 : 0x0003);

	/*
	 * Port based VLAN map: give each port its own address
	 * database, allow the CPU port to talk to each of the 'real'
	 * ports, and allow each of the 'real' ports to only talk to
	 * the CPU port.
	 */
	REG_WRITE(addr, 0x06,
			((p & 0xf) << 12) |
			 (dsa_is_cpu_port(ds, p) ?
				ds->phys_port_mask :
				(1 << ds->dst->cpu_port)));

	/*
	 * Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
	REG_WRITE(addr, 0x0b, 1 << p);

	return 0;
}

static int mv88e6060_setup(struct dsa_switch *ds)
{
	int i;
	int ret;

	ret = mv88e6060_switch_reset(ds);
	if (ret < 0)
		return ret;

	/* @@@ initialise atu */

	ret = mv88e6060_setup_global(ds);
	if (ret < 0)
		return ret;

	for (i = 0; i < 6; i++) {
		ret = mv88e6060_setup_port(ds, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
{
	REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
	REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
	REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);

	return 0;
}

static int mv88e6060_port_to_phy_addr(int port)
{
	if (port >= 0 && port <= 5)
		return port;
	return -1;
}

static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
{
	int addr;

	addr = mv88e6060_port_to_phy_addr(port);
	if (addr == -1)
		return 0xffff;

	return reg_read(ds, addr, regnum);
}

static int
mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
{
	int addr;

	addr = mv88e6060_port_to_phy_addr(port);
	if (addr == -1)
		return 0xffff;

	return reg_write(ds, addr, regnum, val);
}

static void mv88e6060_poll_link(struct dsa_switch *ds)
{
	int i;

	for (i = 0; i < DSA_MAX_PORTS; i++) {
		struct net_device *dev;
		int uninitialized_var(port_status);
		int link;
		int speed;
		int duplex;
		int fc;

		dev = ds->ports[i];
		if (dev == NULL)
			continue;

		link = 0;
		if (dev->flags & IFF_UP) {
			port_status = reg_read(ds, REG_PORT(i), 0x00);
			if (port_status < 0)
				continue;

			link = !!(port_status & 0x1000);
		}

		if (!link) {
			if (netif_carrier_ok(dev)) {
				printk(KERN_INFO "%s: link down\n", dev->name);
				netif_carrier_off(dev);
			}
			continue;
		}

		speed = (port_status & 0x0100) ? 100 : 10;
		duplex = (port_status & 0x0200) ? 1 : 0;
		fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;

		if (!netif_carrier_ok(dev)) {
			printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
					 "flow control %sabled\n", dev->name,
					 speed, duplex ? "full" : "half",
					 fc ? "en" : "dis");
			netif_carrier_on(dev);
		}
	}
}

static struct dsa_switch_driver mv88e6060_switch_driver = {
	.tag_protocol	= htons(ETH_P_TRAILER),
	.probe		= mv88e6060_probe,
	.setup		= mv88e6060_setup,
	.set_addr	= mv88e6060_set_addr,
	.phy_read	= mv88e6060_phy_read,
	.phy_write	= mv88e6060_phy_write,
	.poll_link	= mv88e6060_poll_link,
};

static int __init mv88e6060_init(void)
{
	register_switch_driver(&mv88e6060_switch_driver);
	return 0;
}
module_init(mv88e6060_init);

static void __exit mv88e6060_cleanup(void)
{
	unregister_switch_driver(&mv88e6060_switch_driver);
}
module_exit(mv88e6060_cleanup);
Commit	Line	Data
2e16a77e LB	1	/*
2e16a77e LB	2	* net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
e84665c9	3	* Copyright (c) 2008-2009 Marvell Semiconductor
2e16a77e LB	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
	11	#include <linux/list.h>
	12	#include <linux/netdevice.h>
	13	#include <linux/phy.h>
	14	#include "dsa_priv.h"
	15
	16	#define REG_PORT(p) (8 + (p))
	17	#define REG_GLOBAL 0x0f
	18
	19	static int reg_read(struct dsa_switch *ds, int addr, int reg)
	20	{
	21	return mdiobus_read(ds->master_mii_bus, addr, reg);
	22	}
	23
	24	#define REG_READ(addr, reg) \
	25	({ \
	26	int __ret; \
	27	\
	28	__ret = reg_read(ds, addr, reg); \
	29	if (__ret < 0) \
	30	return __ret; \
	31	__ret; \
	32	})
	33
	34
	35	static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
	36	{
	37	return mdiobus_write(ds->master_mii_bus, addr, reg, val);
	38	}
	39
	40	#define REG_WRITE(addr, reg, val) \
	41	({ \
	42	int __ret; \
	43	\
	44	__ret = reg_write(ds, addr, reg, val); \
	45	if (__ret < 0) \
	46	return __ret; \
	47	})
	48
	49	static char mv88e6060_probe(struct mii_bus bus, int sw_addr)
	50	{
	51	int ret;
	52
	53	ret = mdiobus_read(bus, REG_PORT(0), 0x03);
	54	if (ret >= 0) {
	55	ret &= 0xfff0;
	56	if (ret == 0x0600)
	57	return "Marvell 88E6060";
	58	}
	59
	60	return NULL;
	61	}
	62
	63	static int mv88e6060_switch_reset(struct dsa_switch *ds)
	64	{
	65	int i;
	66	int ret;
	67
68	/*
69	* Set all ports to the disabled state.
70	*/
71	for (i = 0; i < 6; i++) {
72	ret = REG_READ(REG_PORT(i), 0x04);
73	REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
74	}
75
76	/*
77	* Wait for transmit queues to drain.
78	*/
79	msleep(2);
80
81	/*
82	* Reset the switch.
83	*/
e84665c9	84	REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
2e16a77e LB	85
	86	/*
	87	* Wait up to one second for reset to complete.
	88	*/
	89	for (i = 0; i < 1000; i++) {
	90	ret = REG_READ(REG_GLOBAL, 0x00);
	91	if ((ret & 0x8000) == 0x0000)
	92	break;
	93
	94	msleep(1);
	95	}
	96	if (i == 1000)
	97	return -ETIMEDOUT;
	98
	99	return 0;
	100	}
	101
	102	static int mv88e6060_setup_global(struct dsa_switch *ds)
	103	{
	104	/*
	105	* Disable discarding of frames with excessive collisions,
	106	* set the maximum frame size to 1536 bytes, and mask all
	107	* interrupt sources.
	108	*/
	109	REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
	110
	111	/*
	112	* Enable automatic address learning, set the address
	113	* database size to 1024 entries, and set the default aging
	114	* time to 5 minutes.
	115	*/
	116	REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
	117
	118	return 0;
	119	}
	120
	121	static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
	122	{
	123	int addr = REG_PORT(p);
	124
	125	/*
	126	* Do not force flow control, disable Ingress and Egress
	127	* Header tagging, disable VLAN tunneling, and set the port
	128	* state to Forwarding. Additionally, if this is the CPU
	129	* port, enable Ingress and Egress Trailer tagging mode.
	130	*/
e84665c9	131	REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
2e16a77e LB	132
	133	/*
	134	* Port based VLAN map: give each port its own address
	135	* database, allow the CPU port to talk to each of the 'real'
	136	* ports, and allow each of the 'real' ports to only talk to
	137	* the CPU port.
	138	*/
	139	REG_WRITE(addr, 0x06,
	140	((p & 0xf) << 12) \|
e84665c9 LB	141	(dsa_is_cpu_port(ds, p) ?
	142	ds->phys_port_mask :
	143	(1 << ds->dst->cpu_port)));
2e16a77e LB	144
	145	/*
	146	* Port Association Vector: when learning source addresses
	147	* of packets, add the address to the address database using
	148	* a port bitmap that has only the bit for this port set and
	149	* the other bits clear.
	150	*/
	151	REG_WRITE(addr, 0x0b, 1 << p);
	152
	153	return 0;
	154	}
	155
	156	static int mv88e6060_setup(struct dsa_switch *ds)
	157	{
	158	int i;
	159	int ret;
	160
	161	ret = mv88e6060_switch_reset(ds);
	162	if (ret < 0)
	163	return ret;
	164
	165	/* @@@ initialise atu */
	166
	167	ret = mv88e6060_setup_global(ds);
	168	if (ret < 0)
	169	return ret;
	170
	171	for (i = 0; i < 6; i++) {
	172	ret = mv88e6060_setup_port(ds, i);
	173	if (ret < 0)
	174	return ret;
	175	}
	176
	177	return 0;
	178	}
	179
	180	static int mv88e6060_set_addr(struct dsa_switch ds, u8 addr)
	181	{
	182	REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) \| addr[1]);
	183	REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) \| addr[3]);
	184	REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) \| addr[5]);
	185
	186	return 0;
	187	}
	188
	189	static int mv88e6060_port_to_phy_addr(int port)
	190	{
	191	if (port >= 0 && port <= 5)
	192	return port;
	193	return -1;
	194	}
	195
	196	static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
	197	{
	198	int addr;
	199
	200	addr = mv88e6060_port_to_phy_addr(port);
	201	if (addr == -1)
	202	return 0xffff;
	203
	204	return reg_read(ds, addr, regnum);
	205	}
	206
	207	static int
208	mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
209	{
210	int addr;
211
212	addr = mv88e6060_port_to_phy_addr(port);
213	if (addr == -1)
214	return 0xffff;
215
216	return reg_write(ds, addr, regnum, val);
217	}
218
219	static void mv88e6060_poll_link(struct dsa_switch *ds)
220	{
221	int i;
222
223	for (i = 0; i < DSA_MAX_PORTS; i++) {
224	struct net_device *dev;
d3f644da	225	int uninitialized_var(port_status);
2e16a77e LB	226	int link;
	227	int speed;
	228	int duplex;
	229	int fc;
	230
	231	dev = ds->ports[i];
	232	if (dev == NULL)
	233	continue;
	234
	235	link = 0;
	236	if (dev->flags & IFF_UP) {
	237	port_status = reg_read(ds, REG_PORT(i), 0x00);
	238	if (port_status < 0)
	239	continue;
	240
	241	link = !!(port_status & 0x1000);
	242	}
	243
	244	if (!link) {
	245	if (netif_carrier_ok(dev)) {
	246	printk(KERN_INFO "%s: link down\n", dev->name);
	247	netif_carrier_off(dev);
	248	}
	249	continue;
	250	}
	251
	252	speed = (port_status & 0x0100) ? 100 : 10;
	253	duplex = (port_status & 0x0200) ? 1 : 0;
	254	fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
	255
	256	if (!netif_carrier_ok(dev)) {
	257	printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
	258	"flow control %sabled\n", dev->name,
	259	speed, duplex ? "full" : "half",
	260	fc ? "en" : "dis");
	261	netif_carrier_on(dev);
	262	}
	263	}
	264	}
	265
	266	static struct dsa_switch_driver mv88e6060_switch_driver = {
	267	.tag_protocol = htons(ETH_P_TRAILER),
	268	.probe = mv88e6060_probe,
	269	.setup = mv88e6060_setup,
	270	.set_addr = mv88e6060_set_addr,
	271	.phy_read = mv88e6060_phy_read,
	272	.phy_write = mv88e6060_phy_write,
	273	.poll_link = mv88e6060_poll_link,
	274	};
	275
5eaa65b2	276	static int __init mv88e6060_init(void)
2e16a77e LB	277	{
	278	register_switch_driver(&mv88e6060_switch_driver);
	279	return 0;
	280	}
	281	module_init(mv88e6060_init);
	282
5eaa65b2	283	static void __exit mv88e6060_cleanup(void)
2e16a77e LB	284	{
	285	unregister_switch_driver(&mv88e6060_switch_driver);
	286	}
	287	module_exit(mv88e6060_cleanup);