[net-next-2.6.git] / drivers / usb / host / ehci-pci.c

/*
 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
 *
 * Copyright (c) 2000-2004 by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef CONFIG_PCI
#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
#endif

/*-------------------------------------------------------------------------*/

/* called after powerup, by probe or system-pm "wakeup" */
static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
{
	int			retval;

	/* we expect static quirk code to handle the "extended capabilities"
	 * (currently just BIOS handoff) allowed starting with EHCI 0.96
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	retval = pci_set_mwi(pdev);
	if (!retval)
		ehci_dbg(ehci, "MWI active\n");

	return 0;
}

/* called during probe() after chip reset completes */
static int ehci_pci_setup(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	struct pci_dev		*p_smbus;
	u8			rev;
	u32			temp;
	int			retval;

	switch (pdev->vendor) {
	case PCI_VENDOR_ID_TOSHIBA_2:
		/* celleb's companion chip */
		if (pdev->device == 0x01b5) {
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
			ehci->big_endian_mmio = 1;
#else
			ehci_warn(ehci,
				  "unsupported big endian Toshiba quirk\n");
#endif
		}
		break;
	}

	ehci->caps = hcd->regs;
	ehci->regs = hcd->regs +
		HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));

	dbg_hcs_params(ehci, "reset");
	dbg_hcc_params(ehci, "reset");

        /* ehci_init() causes memory for DMA transfers to be
         * allocated.  Thus, any vendor-specific workarounds based on
         * limiting the type of memory used for DMA transfers must
         * happen before ehci_init() is called. */
	switch (pdev->vendor) {
	case PCI_VENDOR_ID_NVIDIA:
		/* NVidia reports that certain chips don't handle
		 * QH, ITD, or SITD addresses above 2GB.  (But TD,
		 * data buffer, and periodic schedule are normal.)
		 */
		switch (pdev->device) {
		case 0x003c:	/* MCP04 */
		case 0x005b:	/* CK804 */
		case 0x00d8:	/* CK8 */
		case 0x00e8:	/* CK8S */
			if (pci_set_consistent_dma_mask(pdev,
						DMA_BIT_MASK(31)) < 0)
				ehci_warn(ehci, "can't enable NVidia "
					"workaround for >2GB RAM\n");
			break;
		}
		break;
	}

	/* cache this readonly data; minimize chip reads */
	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);

	retval = ehci_halt(ehci);
	if (retval)
		return retval;

	/* data structure init */
	retval = ehci_init(hcd);
	if (retval)
		return retval;

	switch (pdev->vendor) {
	case PCI_VENDOR_ID_NEC:
		ehci->need_io_watchdog = 0;
		break;
	case PCI_VENDOR_ID_INTEL:
		ehci->need_io_watchdog = 0;
		ehci->fs_i_thresh = 1;
		if (pdev->device == 0x27cc) {
			ehci->broken_periodic = 1;
			ehci_info(ehci, "using broken periodic workaround\n");
		}
		if (pdev->device == 0x0806 || pdev->device == 0x0811
				|| pdev->device == 0x0829) {
			ehci_info(ehci, "disable lpm for langwell/penwell\n");
			ehci->has_lpm = 0;
		}
		break;
	case PCI_VENDOR_ID_TDI:
		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
			hcd->has_tt = 1;
			tdi_reset(ehci);
		}
		break;
	case PCI_VENDOR_ID_AMD:
		/* AMD8111 EHCI doesn't work, according to AMD errata */
		if (pdev->device == 0x7463) {
			ehci_info(ehci, "ignoring AMD8111 (errata)\n");
			retval = -EIO;
			goto done;
		}
		break;
	case PCI_VENDOR_ID_NVIDIA:
		switch (pdev->device) {
		/* Some NForce2 chips have problems with selective suspend;
		 * fixed in newer silicon.
		 */
		case 0x0068:
			if (pdev->revision < 0xa4)
				ehci->no_selective_suspend = 1;
			break;
		}
		break;
	case PCI_VENDOR_ID_VIA:
		if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
			u8 tmp;

			/* The VT6212 defaults to a 1 usec EHCI sleep time which
			 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
			 * that sleep time use the conventional 10 usec.
			 */
			pci_read_config_byte(pdev, 0x4b, &tmp);
			if (tmp & 0x20)
				break;
			pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
		}
		break;
	case PCI_VENDOR_ID_ATI:
		/* SB600 and old version of SB700 have a bug in EHCI controller,
		 * which causes usb devices lose response in some cases.
		 */
		if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
			p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
						 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
						 NULL);
			if (!p_smbus)
				break;
			rev = p_smbus->revision;
			if ((pdev->device == 0x4386) || (rev == 0x3a)
			    || (rev == 0x3b)) {
				u8 tmp;
				ehci_info(ehci, "applying AMD SB600/SB700 USB "
					"freeze workaround\n");
				pci_read_config_byte(pdev, 0x53, &tmp);
				pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
			}
			pci_dev_put(p_smbus);
		}
		break;
	}

	/* optional debug port, normally in the first BAR */
	temp = pci_find_capability(pdev, 0x0a);
	if (temp) {
		pci_read_config_dword(pdev, temp, &temp);
		temp >>= 16;
		if ((temp & (3 << 13)) == (1 << 13)) {
			temp &= 0x1fff;
			ehci->debug = ehci_to_hcd(ehci)->regs + temp;
			temp = ehci_readl(ehci, &ehci->debug->control);
			ehci_info(ehci, "debug port %d%s\n",
				HCS_DEBUG_PORT(ehci->hcs_params),
				(temp & DBGP_ENABLED)
					? " IN USE"
					: "");
			if (!(temp & DBGP_ENABLED))
				ehci->debug = NULL;
		}
	}

	ehci_reset(ehci);

	/* at least the Genesys GL880S needs fixup here */
	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	temp &= 0x0f;
	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
		ehci_dbg(ehci, "bogus port configuration: "
			"cc=%d x pcc=%d < ports=%d\n",
			HCS_N_CC(ehci->hcs_params),
			HCS_N_PCC(ehci->hcs_params),
			HCS_N_PORTS(ehci->hcs_params));

		switch (pdev->vendor) {
		case 0x17a0:		/* GENESYS */
			/* GL880S: should be PORTS=2 */
			temp |= (ehci->hcs_params & ~0xf);
			ehci->hcs_params = temp;
			break;
		case PCI_VENDOR_ID_NVIDIA:
			/* NF4: should be PCC=10 */
			break;
		}
	}

	/* Serial Bus Release Number is at PCI 0x60 offset */
	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);

	/* Keep this around for a while just in case some EHCI
	 * implementation uses legacy PCI PM support.  This test
	 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
	 * been triggered by then.
	 */
	if (!device_can_wakeup(&pdev->dev)) {
		u16	port_wake;

		pci_read_config_word(pdev, 0x62, &port_wake);
		if (port_wake & 0x0001) {
			dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
			device_set_wakeup_capable(&pdev->dev, 1);
		}
	}

#ifdef	CONFIG_USB_SUSPEND
	/* REVISIT: the controller works fine for wakeup iff the root hub
	 * itself is "globally" suspended, but usbcore currently doesn't
	 * understand such things.
	 *
	 * System suspend currently expects to be able to suspend the entire
	 * device tree, device-at-a-time.  If we failed selective suspend
	 * reports, system suspend would fail; so the root hub code must claim
	 * success.  That's lying to usbcore, and it matters for runtime
	 * PM scenarios with selective suspend and remote wakeup...
	 */
	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
		ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
#endif

	ehci_port_power(ehci, 1);
	retval = ehci_pci_reinit(ehci, pdev);
done:
	return retval;
}

/*-------------------------------------------------------------------------*/

#ifdef	CONFIG_PM

/* suspend/resume, section 4.3 */

/* These routines rely on the PCI bus glue
 * to handle powerdown and wakeup, and currently also on
 * transceivers that don't need any software attention to set up
 * the right sort of wakeup.
 * Also they depend on separate root hub suspend/resume.
 */

static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	unsigned long		flags;
	int			rc = 0;

	if (time_before(jiffies, ehci->next_statechange))
		msleep(10);

	/* Root hub was already suspended. Disable irq emission and
	 * mark HW unaccessible.  The PM and USB cores make sure that
	 * the root hub is either suspended or stopped.
	 */
	spin_lock_irqsave (&ehci->lock, flags);
	ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
	(void)ehci_readl(ehci, &ehci->regs->intr_enable);

	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
	spin_unlock_irqrestore (&ehci->lock, flags);

	// could save FLADJ in case of Vaux power loss
	// ... we'd only use it to handle clock skew

	return rc;
}

static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	// maybe restore FLADJ

	if (time_before(jiffies, ehci->next_statechange))
		msleep(100);

	/* Mark hardware accessible again as we are out of D3 state by now */
	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);

	/* If CF is still set and we aren't resuming from hibernation
	 * then we maintained PCI Vaux power.
	 * Just undo the effect of ehci_pci_suspend().
	 */
	if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
				!hibernated) {
		int	mask = INTR_MASK;

		ehci_prepare_ports_for_controller_resume(ehci);
		if (!hcd->self.root_hub->do_remote_wakeup)
			mask &= ~STS_PCD;
		ehci_writel(ehci, mask, &ehci->regs->intr_enable);
		ehci_readl(ehci, &ehci->regs->intr_enable);
		return 0;
	}

	usb_root_hub_lost_power(hcd->self.root_hub);

	/* Else reset, to cope with power loss or flush-to-storage
	 * style "resume" having let BIOS kick in during reboot.
	 */
	(void) ehci_halt(ehci);
	(void) ehci_reset(ehci);
	(void) ehci_pci_reinit(ehci, pdev);

	/* emptying the schedule aborts any urbs */
	spin_lock_irq(&ehci->lock);
	if (ehci->reclaim)
		end_unlink_async(ehci);
	ehci_work(ehci);
	spin_unlock_irq(&ehci->lock);

	ehci_writel(ehci, ehci->command, &ehci->regs->command);
	ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
	ehci_readl(ehci, &ehci->regs->command);	/* unblock posted writes */

	/* here we "know" root ports should always stay powered */
	ehci_port_power(ehci, 1);

	hcd->state = HC_STATE_SUSPENDED;
	return 0;
}
#endif

static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
{
	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
	int rc = 0;

	if (!udev->parent) /* udev is root hub itself, impossible */
		rc = -1;
	/* we only support lpm device connected to root hub yet */
	if (ehci->has_lpm && !udev->parent->parent) {
		rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
		if (!rc)
			rc = ehci_lpm_check(ehci, udev->portnum);
	}
	return rc;
}

static const struct hc_driver ehci_pci_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"EHCI Host Controller",
	.hcd_priv_size =	sizeof(struct ehci_hcd),

	/*
	 * generic hardware linkage
	 */
	.irq =			ehci_irq,
	.flags =		HCD_MEMORY | HCD_USB2,

	/*
	 * basic lifecycle operations
	 */
	.reset =		ehci_pci_setup,
	.start =		ehci_run,
#ifdef	CONFIG_PM
	.pci_suspend =		ehci_pci_suspend,
	.pci_resume =		ehci_pci_resume,
#endif
	.stop =			ehci_stop,
	.shutdown =		ehci_shutdown,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ehci_urb_enqueue,
	.urb_dequeue =		ehci_urb_dequeue,
	.endpoint_disable =	ehci_endpoint_disable,
	.endpoint_reset =	ehci_endpoint_reset,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ehci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ehci_hub_status_data,
	.hub_control =		ehci_hub_control,
	.bus_suspend =		ehci_bus_suspend,
	.bus_resume =		ehci_bus_resume,
	.relinquish_port =	ehci_relinquish_port,
	.port_handed_over =	ehci_port_handed_over,

	/*
	 * call back when device connected and addressed
	 */
	.update_device =	ehci_update_device,

	.clear_tt_buffer_complete	= ehci_clear_tt_buffer_complete,
};

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids [] = { {
	/* handle any USB 2.0 EHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
	.driver_data =	(unsigned long) &ehci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver ehci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	usb_hcd_pci_probe,
	.remove =	usb_hcd_pci_remove,
	.shutdown = 	usb_hcd_pci_shutdown,

#ifdef CONFIG_PM_SLEEP
	.driver =	{
		.pm =	&usb_hcd_pci_pm_ops
	},
#endif
};
Commit	Line	Data
7ff71d6a MP	1	/*
	2	* EHCI HCD (Host Controller Driver) PCI Bus Glue.
	3	*
	4	* Copyright (c) 2000-2004 by David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software Foundation,
	18	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#ifndef CONFIG_PCI
	22	#error "This file is PCI bus glue. CONFIG_PCI must be defined."
	23	#endif
	24
	25	/-------------------------------------------------------------------------/
	26
18807521 DB	27	/* called after powerup, by probe or system-pm "wakeup" */
	28	static int ehci_pci_reinit(struct ehci_hcd ehci, struct pci_dev pdev)
	29	{
18807521	30	int retval;
18807521	31
401feafa DB	32	/* we expect static quirk code to handle the "extended capabilities"
	33	* (currently just BIOS handoff) allowed starting with EHCI 0.96
	34	*/
18807521 DB	35
	36	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	37	retval = pci_set_mwi(pdev);
	38	if (!retval)
	39	ehci_dbg(ehci, "MWI active\n");
	40
18807521 DB	41	return 0;
	42	}
	43
8926bfa7 DB	44	/* called during probe() after chip reset completes */
8926bfa7 DB	45	static int ehci_pci_setup(struct usb_hcd *hcd)
7ff71d6a	46	{
abcc9448 DB	47	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
abcc9448 DB	48	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
b09bc6cb AX	49	struct pci_dev *p_smbus;
b09bc6cb AX	50	u8 rev;
7ff71d6a	51	u32 temp;
18807521	52	int retval;
7ff71d6a	53
083522d7 BH	54	switch (pdev->vendor) {
	55	case PCI_VENDOR_ID_TOSHIBA_2:
	56	/* celleb's companion chip */
	57	if (pdev->device == 0x01b5) {
	58	#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
	59	ehci->big_endian_mmio = 1;
	60	#else
	61	ehci_warn(ehci,
	62	"unsupported big endian Toshiba quirk\n");
	63	#endif
	64	}
	65	break;
	66	}
	67
7ff71d6a	68	ehci->caps = hcd->regs;
083522d7 BH	69	ehci->regs = hcd->regs +
	70	HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
	71
abcc9448 DB	72	dbg_hcs_params(ehci, "reset");
abcc9448 DB	73	dbg_hcc_params(ehci, "reset");
7ff71d6a	74
c32ba30f PS	75	/* ehci_init() causes memory for DMA transfers to be
	76	* allocated. Thus, any vendor-specific workarounds based on
	77	* limiting the type of memory used for DMA transfers must
	78	* happen before ehci_init() is called. */
	79	switch (pdev->vendor) {
	80	case PCI_VENDOR_ID_NVIDIA:
	81	/* NVidia reports that certain chips don't handle
	82	* QH, ITD, or SITD addresses above 2GB. (But TD,
	83	* data buffer, and periodic schedule are normal.)
	84	*/
	85	switch (pdev->device) {
	86	case 0x003c: /* MCP04 */
	87	case 0x005b: /* CK804 */
	88	case 0x00d8: /* CK8 */
	89	case 0x00e8: /* CK8S */
	90	if (pci_set_consistent_dma_mask(pdev,
929a22a5	91	DMA_BIT_MASK(31)) < 0)
c32ba30f PS	92	ehci_warn(ehci, "can't enable NVidia "
	93	"workaround for >2GB RAM\n");
	94	break;
	95	}
	96	break;
	97	}
	98
7ff71d6a	99	/* cache this readonly data; minimize chip reads */
083522d7	100	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
7ff71d6a	101
18807521 DB	102	retval = ehci_halt(ehci);
	103	if (retval)
	104	return retval;
	105
8926bfa7 DB	106	/* data structure init */
	107	retval = ehci_init(hcd);
	108	if (retval)
	109	return retval;
	110
abcc9448	111	switch (pdev->vendor) {
3681d8f3 DM	112	case PCI_VENDOR_ID_NEC:
	113	ehci->need_io_watchdog = 0;
	114	break;
403dbd36 AD	115	case PCI_VENDOR_ID_INTEL:
403dbd36 AD	116	ehci->need_io_watchdog = 0;
ae68a83b	117	ehci->fs_i_thresh = 1;
ee4ecb8a ON	118	if (pdev->device == 0x27cc) {
	119	ehci->broken_periodic = 1;
	120	ehci_info(ehci, "using broken periodic workaround\n");
	121	}
fc928250 AD	122	if (pdev->device == 0x0806 \|\| pdev->device == 0x0811
	123	\|\| pdev->device == 0x0829) {
	124	ehci_info(ehci, "disable lpm for langwell/penwell\n");
	125	ehci->has_lpm = 0;
	126	}
403dbd36	127	break;
abcc9448 DB	128	case PCI_VENDOR_ID_TDI:
abcc9448 DB	129	if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
7329e211	130	hcd->has_tt = 1;
abcc9448 DB	131	tdi_reset(ehci);
	132	}
	133	break;
	134	case PCI_VENDOR_ID_AMD:
	135	/* AMD8111 EHCI doesn't work, according to AMD errata */
	136	if (pdev->device == 0x7463) {
	137	ehci_info(ehci, "ignoring AMD8111 (errata)\n");
8926bfa7 DB	138	retval = -EIO;
8926bfa7 DB	139	goto done;
abcc9448 DB	140	}
	141	break;
	142	case PCI_VENDOR_ID_NVIDIA:
f8aeb3bb	143	switch (pdev->device) {
f8aeb3bb DB	144	/* Some NForce2 chips have problems with selective suspend;
	145	* fixed in newer silicon.
	146	*/
	147	case 0x0068:
44c10138	148	if (pdev->revision < 0xa4)
f8aeb3bb DB	149	ehci->no_selective_suspend = 1;
f8aeb3bb DB	150	break;
7ff71d6a	151	}
abcc9448	152	break;
055b93c9 RH	153	case PCI_VENDOR_ID_VIA:
	154	if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
	155	u8 tmp;
	156
	157	/* The VT6212 defaults to a 1 usec EHCI sleep time which
	158	* hogs the PCI bus badly. Setting bit 5 of 0x4B makes
	159	* that sleep time use the conventional 10 usec.
	160	*/
	161	pci_read_config_byte(pdev, 0x4b, &tmp);
	162	if (tmp & 0x20)
	163	break;
	164	pci_write_config_byte(pdev, 0x4b, tmp \| 0x20);
	165	}
	166	break;
b09bc6cb	167	case PCI_VENDOR_ID_ATI:
0a99e8ac	168	/* SB600 and old version of SB700 have a bug in EHCI controller,
b09bc6cb AX	169	* which causes usb devices lose response in some cases.
b09bc6cb AX	170	*/
0a99e8ac	171	if ((pdev->device == 0x4386) \|\| (pdev->device == 0x4396)) {
b09bc6cb AX	172	p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
	173	PCI_DEVICE_ID_ATI_SBX00_SMBUS,
	174	NULL);
	175	if (!p_smbus)
	176	break;
	177	rev = p_smbus->revision;
0a99e8ac SH	178	if ((pdev->device == 0x4386) \|\| (rev == 0x3a)
0a99e8ac SH	179	\|\| (rev == 0x3b)) {
b09bc6cb	180	u8 tmp;
0a99e8ac SH	181	ehci_info(ehci, "applying AMD SB600/SB700 USB "
0a99e8ac SH	182	"freeze workaround\n");
b09bc6cb AX	183	pci_read_config_byte(pdev, 0x53, &tmp);
	184	pci_write_config_byte(pdev, 0x53, tmp \| (1<<3));
	185	}
	186	pci_dev_put(p_smbus);
	187	}
	188	break;
abcc9448	189	}
7ff71d6a	190
8d053c79 JW	191	/* optional debug port, normally in the first BAR */
	192	temp = pci_find_capability(pdev, 0x0a);
	193	if (temp) {
	194	pci_read_config_dword(pdev, temp, &temp);
	195	temp >>= 16;
	196	if ((temp & (3 << 13)) == (1 << 13)) {
	197	temp &= 0x1fff;
	198	ehci->debug = ehci_to_hcd(ehci)->regs + temp;
	199	temp = ehci_readl(ehci, &ehci->debug->control);
	200	ehci_info(ehci, "debug port %d%s\n",
	201	HCS_DEBUG_PORT(ehci->hcs_params),
	202	(temp & DBGP_ENABLED)
	203	? " IN USE"
	204	: "");
	205	if (!(temp & DBGP_ENABLED))
	206	ehci->debug = NULL;
	207	}
	208	}
	209
af1c51fc	210	ehci_reset(ehci);
7ff71d6a	211
7ff71d6a MP	212	/* at least the Genesys GL880S needs fixup here */
	213	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	214	temp &= 0x0f;
	215	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
abcc9448	216	ehci_dbg(ehci, "bogus port configuration: "
7ff71d6a MP	217	"cc=%d x pcc=%d < ports=%d\n",
	218	HCS_N_CC(ehci->hcs_params),
	219	HCS_N_PCC(ehci->hcs_params),
	220	HCS_N_PORTS(ehci->hcs_params));
	221
abcc9448 DB	222	switch (pdev->vendor) {
	223	case 0x17a0: /* GENESYS */
	224	/* GL880S: should be PORTS=2 */
	225	temp \|= (ehci->hcs_params & ~0xf);
	226	ehci->hcs_params = temp;
	227	break;
	228	case PCI_VENDOR_ID_NVIDIA:
	229	/* NF4: should be PCC=10 */
	230	break;
7ff71d6a MP	231	}
	232	}
	233
abcc9448 DB	234	/* Serial Bus Release Number is at PCI 0x60 offset */
abcc9448 DB	235	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
7ff71d6a	236
6fd9086a AS	237	/* Keep this around for a while just in case some EHCI
	238	* implementation uses legacy PCI PM support. This test
	239	* can be removed on 17 Dec 2009 if the dev_warn() hasn't
	240	* been triggered by then.
2c1c3c4c DB	241	*/
	242	if (!device_can_wakeup(&pdev->dev)) {
	243	u16 port_wake;
	244
	245	pci_read_config_word(pdev, 0x62, &port_wake);
6fd9086a AS	246	if (port_wake & 0x0001) {
6fd9086a AS	247	dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
bcca06ef	248	device_set_wakeup_capable(&pdev->dev, 1);
6fd9086a	249	}
2c1c3c4c	250	}
7ff71d6a	251
f8aeb3bb DB	252	#ifdef CONFIG_USB_SUSPEND
	253	/* REVISIT: the controller works fine for wakeup iff the root hub
	254	* itself is "globally" suspended, but usbcore currently doesn't
	255	* understand such things.
	256	*
	257	* System suspend currently expects to be able to suspend the entire
	258	* device tree, device-at-a-time. If we failed selective suspend
	259	* reports, system suspend would fail; so the root hub code must claim
411c9403	260	* success. That's lying to usbcore, and it matters for runtime
f8aeb3bb DB	261	* PM scenarios with selective suspend and remote wakeup...
	262	*/
	263	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
	264	ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
	265	#endif
	266
aff6d18f	267	ehci_port_power(ehci, 1);
18807521	268	retval = ehci_pci_reinit(ehci, pdev);
8926bfa7 DB	269	done:
8926bfa7 DB	270	return retval;
7ff71d6a MP	271	}
	272
	273	/-------------------------------------------------------------------------/
	274
	275	#ifdef CONFIG_PM
	276
	277	/* suspend/resume, section 4.3 */
	278
f03c17fc	279	/* These routines rely on the PCI bus glue
7ff71d6a MP	280	* to handle powerdown and wakeup, and currently also on
	281	* transceivers that don't need any software attention to set up
	282	* the right sort of wakeup.
f03c17fc	283	* Also they depend on separate root hub suspend/resume.
7ff71d6a MP	284	*/
7ff71d6a MP	285
4147200d	286	static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
7ff71d6a	287	{
abcc9448	288	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
8de98402 BH	289	unsigned long flags;
8de98402 BH	290	int rc = 0;
7ff71d6a	291
abcc9448 DB	292	if (time_before(jiffies, ehci->next_statechange))
abcc9448 DB	293	msleep(10);
7ff71d6a	294
8de98402	295	/* Root hub was already suspended. Disable irq emission and
16032c4f AS	296	* mark HW unaccessible. The PM and USB cores make sure that
16032c4f AS	297	* the root hub is either suspended or stopped.
8de98402 BH	298	*/
8de98402 BH	299	spin_lock_irqsave (&ehci->lock, flags);
4147200d	300	ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
083522d7 BH	301	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
083522d7 BH	302	(void)ehci_readl(ehci, &ehci->regs->intr_enable);
8de98402 BH	303
8de98402 BH	304	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
8de98402 BH	305	spin_unlock_irqrestore (&ehci->lock, flags);
8de98402 BH	306
f03c17fc	307	// could save FLADJ in case of Vaux power loss
7ff71d6a MP	308	// ... we'd only use it to handle clock skew
7ff71d6a MP	309
8de98402	310	return rc;
7ff71d6a MP	311	}
7ff71d6a MP	312
6ec4beb5	313	static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
7ff71d6a	314	{
abcc9448	315	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
18807521	316	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	317
f03c17fc	318	// maybe restore FLADJ
7ff71d6a	319
abcc9448 DB	320	if (time_before(jiffies, ehci->next_statechange))
abcc9448 DB	321	msleep(100);
7ff71d6a	322
8de98402 BH	323	/* Mark hardware accessible again as we are out of D3 state by now */
	324	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
	325
6ec4beb5 AS	326	/* If CF is still set and we aren't resuming from hibernation
6ec4beb5 AS	327	* then we maintained PCI Vaux power.
8c03356a	328	* Just undo the effect of ehci_pci_suspend().
7ff71d6a	329	*/
6ec4beb5 AS	330	if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
6ec4beb5 AS	331	!hibernated) {
8c03356a AS	332	int mask = INTR_MASK;
8c03356a AS	333
16032c4f	334	ehci_prepare_ports_for_controller_resume(ehci);
58a97ffe	335	if (!hcd->self.root_hub->do_remote_wakeup)
8c03356a	336	mask &= ~STS_PCD;
083522d7 BH	337	ehci_writel(ehci, mask, &ehci->regs->intr_enable);
083522d7 BH	338	ehci_readl(ehci, &ehci->regs->intr_enable);
8c03356a	339	return 0;
f03c17fc DB	340	}
f03c17fc DB	341
1c50c317	342	usb_root_hub_lost_power(hcd->self.root_hub);
7ff71d6a MP	343
7ff71d6a MP	344	/* Else reset, to cope with power loss or flush-to-storage
f03c17fc	345	* style "resume" having let BIOS kick in during reboot.
7ff71d6a	346	*/
abcc9448 DB	347	(void) ehci_halt(ehci);
abcc9448 DB	348	(void) ehci_reset(ehci);
18807521	349	(void) ehci_pci_reinit(ehci, pdev);
f03c17fc DB	350
f03c17fc DB	351	/* emptying the schedule aborts any urbs */
abcc9448	352	spin_lock_irq(&ehci->lock);
f03c17fc	353	if (ehci->reclaim)
07d29b63	354	end_unlink_async(ehci);
7d12e780	355	ehci_work(ehci);
abcc9448	356	spin_unlock_irq(&ehci->lock);
f03c17fc	357
083522d7 BH	358	ehci_writel(ehci, ehci->command, &ehci->regs->command);
	359	ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
	360	ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
8c03356a	361
383975d7 AS	362	/* here we "know" root ports should always stay powered */
383975d7 AS	363	ehci_port_power(ehci, 1);
383975d7	364
8c03356a AS	365	hcd->state = HC_STATE_SUSPENDED;
8c03356a AS	366	return 0;
7ff71d6a MP	367	}
	368	#endif
	369
48f24970 AD	370	static int ehci_update_device(struct usb_hcd hcd, struct usb_device udev)
	371	{
	372	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
	373	int rc = 0;
	374
	375	if (!udev->parent) /* udev is root hub itself, impossible */
	376	rc = -1;
	377	/* we only support lpm device connected to root hub yet */
	378	if (ehci->has_lpm && !udev->parent->parent) {
	379	rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
	380	if (!rc)
	381	rc = ehci_lpm_check(ehci, udev->portnum);
	382	}
	383	return rc;
	384	}
	385
7ff71d6a MP	386	static const struct hc_driver ehci_pci_hc_driver = {
	387	.description = hcd_name,
	388	.product_desc = "EHCI Host Controller",
	389	.hcd_priv_size = sizeof(struct ehci_hcd),
	390
	391	/*
	392	* generic hardware linkage
	393	*/
	394	.irq = ehci_irq,
	395	.flags = HCD_MEMORY \| HCD_USB2,
	396
	397	/*
	398	* basic lifecycle operations
	399	*/
8926bfa7	400	.reset = ehci_pci_setup,
18807521	401	.start = ehci_run,
7ff71d6a	402	#ifdef CONFIG_PM
7be7d741 AS	403	.pci_suspend = ehci_pci_suspend,
7be7d741 AS	404	.pci_resume = ehci_pci_resume,
7ff71d6a	405	#endif
18807521	406	.stop = ehci_stop,
64a21d02	407	.shutdown = ehci_shutdown,
7ff71d6a MP	408
	409	/*
	410	* managing i/o requests and associated device resources
	411	*/
	412	.urb_enqueue = ehci_urb_enqueue,
	413	.urb_dequeue = ehci_urb_dequeue,
	414	.endpoint_disable = ehci_endpoint_disable,
b18ffd49	415	.endpoint_reset = ehci_endpoint_reset,
7ff71d6a MP	416
	417	/*
	418	* scheduling support
	419	*/
	420	.get_frame_number = ehci_get_frame,
	421
	422	/*
	423	* root hub support
	424	*/
	425	.hub_status_data = ehci_hub_status_data,
	426	.hub_control = ehci_hub_control,
0c0382e3 AS	427	.bus_suspend = ehci_bus_suspend,
0c0382e3 AS	428	.bus_resume = ehci_bus_resume,
a8e51775	429	.relinquish_port = ehci_relinquish_port,
3a31155c	430	.port_handed_over = ehci_port_handed_over,
914b7012	431
48f24970 AD	432	/*
	433	* call back when device connected and addressed
	434	*/
	435	.update_device = ehci_update_device,
	436
914b7012	437	.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
7ff71d6a MP	438	};
	439
	440	/-------------------------------------------------------------------------/
	441
	442	/* PCI driver selection metadata; PCI hotplugging uses this */
	443	static const struct pci_device_id pci_ids [] = { {
	444	/* handle any USB 2.0 EHCI controller */
c67808ee	445	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
7ff71d6a MP	446	.driver_data = (unsigned long) &ehci_pci_hc_driver,
	447	},
	448	{ /* end: all zeroes */ }
	449	};
abcc9448	450	MODULE_DEVICE_TABLE(pci, pci_ids);
7ff71d6a MP	451
	452	/* pci driver glue; this is a "new style" PCI driver module */
	453	static struct pci_driver ehci_pci_driver = {
	454	.name = (char *) hcd_name,
	455	.id_table = pci_ids,
	456
	457	.probe = usb_hcd_pci_probe,
	458	.remove = usb_hcd_pci_remove,
abb30641	459	.shutdown = usb_hcd_pci_shutdown,
7ff71d6a	460
abb30641 AS	461	#ifdef CONFIG_PM_SLEEP
	462	.driver = {
	463	.pm = &usb_hcd_pci_pm_ops
	464	},
7ff71d6a MP	465	#endif
7ff71d6a MP	466	};