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Staging: rtl8187se: fixed space style issues in r8180_core.c
[net-next-2.6.git] / drivers / staging / rtl8187se / r8180_core.c
CommitLineData
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1/*
2 This is part of rtl818x pci OpenSource driver - v 0.1
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public License)
5
6 Parts of this driver are based on the GPL part of the official
7 Realtek driver.
8
9 Parts of this driver are based on the rtl8180 driver skeleton
10 from Patric Schenke & Andres Salomon.
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
13
14 Parts of BB/RF code are derived from David Young rtl8180 netbsd driver.
15
16 RSSI calc function from 'The Deuce'
17
18 Some ideas borrowed from the 8139too.c driver included in linux kernel.
19
20 We (I?) want to thanks the Authors of those projecs and also the
21 Ndiswrapper's project Authors.
22
23 A big big thanks goes also to Realtek corp. for their help in my attempt to
24 add RTL8185 and RTL8225 support, and to David Young also.
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25
26 Power management interface routines.
27 Written by Mariusz Matuszek.
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28*/
29
c8d86be3 30#undef RX_DONT_PASS_UL
c8d86be3 31#undef DUMMY_RX
c8d86be3 32
5a0e3ad6 33#include <linux/slab.h>
c8d86be3 34#include <linux/syscalls.h>
742821ce 35#include <linux/eeprom_93cx6.h>
fd882783 36
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37#include "r8180_hw.h"
38#include "r8180.h"
c8d86be3 39#include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
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40#include "r8180_93cx6.h" /* Card EEPROM */
41#include "r8180_wx.h"
42#include "r8180_dm.h"
43
fd9b8d6e 44#include "ieee80211/dot11d.h"
c8d86be3 45
c8d86be3 46static struct pci_device_id rtl8180_pci_id_tbl[] __devinitdata = {
cb73da25
JC
47 {
48 .vendor = PCI_VENDOR_ID_REALTEK,
49 .device = 0x8199,
50 .subvendor = PCI_ANY_ID,
51 .subdevice = PCI_ANY_ID,
52 .driver_data = 0,
53 },
54 {
55 .vendor = 0,
56 .device = 0,
57 .subvendor = 0,
58 .subdevice = 0,
59 .driver_data = 0,
60 }
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61};
62
63
cb73da25 64static char *ifname = "wlan%d";
c8d86be3 65static int hwseqnum = 0;
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66static int hwwep = 0;
67static int channels = 0x3fff;
68
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69#define eqMacAddr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
70#define cpMacAddr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
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71MODULE_LICENSE("GPL");
72MODULE_DEVICE_TABLE(pci, rtl8180_pci_id_tbl);
73MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
74MODULE_DESCRIPTION("Linux driver for Realtek RTL8180 / RTL8185 WiFi cards");
75
76
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77module_param(ifname, charp, S_IRUGO|S_IWUSR);
78module_param(hwseqnum, int, S_IRUGO|S_IWUSR);
79module_param(hwwep, int, S_IRUGO|S_IWUSR);
80module_param(channels, int, S_IRUGO|S_IWUSR);
c8d86be3 81
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82MODULE_PARM_DESC(devname, " Net interface name, wlan%d=default");
83MODULE_PARM_DESC(hwseqnum, " Try to use hardware 802.11 header sequence numbers. Zero=default");
84MODULE_PARM_DESC(hwwep, " Try to use hardware WEP support. Still broken and not available on all cards");
85MODULE_PARM_DESC(channels, " Channel bitmask for specific locales. NYI");
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86
87
88static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
89 const struct pci_device_id *id);
90
91static void __devexit rtl8180_pci_remove(struct pci_dev *pdev);
92
bbfb5652 93static void rtl8180_shutdown(struct pci_dev *pdev)
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94{
95 struct net_device *dev = pci_get_drvdata(pdev);
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96 if (dev->netdev_ops->ndo_stop)
97 dev->netdev_ops->ndo_stop(dev);
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98 pci_disable_device(pdev);
99}
100
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101static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
102{
103 struct net_device *dev = pci_get_drvdata(pdev);
104
105 if (!netif_running(dev))
106 goto out_pci_suspend;
107
108 if (dev->netdev_ops->ndo_stop)
109 dev->netdev_ops->ndo_stop(dev);
110
111 netif_device_detach(dev);
112
113out_pci_suspend:
114 pci_save_state(pdev);
115 pci_disable_device(pdev);
116 pci_set_power_state(pdev, pci_choose_state(pdev, state));
117 return 0;
118}
119
120static int rtl8180_resume(struct pci_dev *pdev)
121{
122 struct net_device *dev = pci_get_drvdata(pdev);
123 int err;
124 u32 val;
125
126 pci_set_power_state(pdev, PCI_D0);
127
128 err = pci_enable_device(pdev);
129 if (err) {
130 printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
131 dev->name);
132
133 return err;
134 }
135
136 pci_restore_state(pdev);
137
138 /*
139 * Suspend/Resume resets the PCI configuration space, so we have to
140 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
141 * from interfering with C3 CPU state. pci_restore_state won't help
142 * here since it only restores the first 64 bytes pci config header.
143 */
144 pci_read_config_dword(pdev, 0x40, &val);
145 if ((val & 0x0000ff00) != 0)
146 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
147
148 if (!netif_running(dev))
149 goto out;
150
151 if (dev->netdev_ops->ndo_open)
152 dev->netdev_ops->ndo_open(dev);
153
154 netif_device_attach(dev);
155out:
156 return 0;
157}
158
c8d86be3 159static struct pci_driver rtl8180_pci_driver = {
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160 .name = RTL8180_MODULE_NAME,
161 .id_table = rtl8180_pci_id_tbl,
162 .probe = rtl8180_pci_probe,
163 .remove = __devexit_p(rtl8180_pci_remove),
164 .suspend = rtl8180_suspend,
165 .resume = rtl8180_resume,
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166 .shutdown = rtl8180_shutdown,
167};
168
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169u8 read_nic_byte(struct net_device *dev, int x)
170{
cb73da25 171 return 0xff&readb((u8 *)dev->mem_start + x);
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172}
173
174u32 read_nic_dword(struct net_device *dev, int x)
175{
cb73da25 176 return readl((u8 *)dev->mem_start + x);
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177}
178
179u16 read_nic_word(struct net_device *dev, int x)
180{
cb73da25 181 return readw((u8 *)dev->mem_start + x);
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182}
183
bbfb5652 184void write_nic_byte(struct net_device *dev, int x, u8 y)
c8d86be3 185{
cb73da25 186 writeb(y, (u8 *)dev->mem_start + x);
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187 udelay(20);
188}
189
bbfb5652 190void write_nic_dword(struct net_device *dev, int x, u32 y)
c8d86be3 191{
cb73da25 192 writel(y, (u8 *)dev->mem_start + x);
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193 udelay(20);
194}
195
bbfb5652 196void write_nic_word(struct net_device *dev, int x, u16 y)
c8d86be3 197{
cb73da25 198 writew(y, (u8 *)dev->mem_start + x);
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199 udelay(20);
200}
201
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202inline void force_pci_posting(struct net_device *dev)
203{
bbfb5652 204 read_nic_byte(dev, EPROM_CMD);
c8d86be3 205 mb();
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206}
207
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208irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs);
209void set_nic_rxring(struct net_device *dev);
210void set_nic_txring(struct net_device *dev);
211static struct net_device_stats *rtl8180_stats(struct net_device *dev);
212void rtl8180_commit(struct net_device *dev);
213void rtl8180_start_tx_beacon(struct net_device *dev);
214
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215static struct proc_dir_entry *rtl8180_proc = NULL;
216
217static int proc_get_registers(char *page, char **start,
218 off_t offset, int count,
219 int *eof, void *data)
220{
221 struct net_device *dev = data;
c8d86be3 222 int len = 0;
bbfb5652 223 int i, n;
fd882783 224 int max = 0xff;
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225
226 /* This dump the current register page */
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227 for (n = 0; n <= max;) {
228 len += snprintf(page + len, count - len, "\nD: %2x > ", n);
c8d86be3 229
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230 for (i = 0; i < 16 && n <= max; i++, n++)
231 len += snprintf(page + len, count - len, "%2x ",
232 read_nic_byte(dev, n));
c8d86be3 233 }
bbfb5652 234 len += snprintf(page + len, count - len, "\n");
c8d86be3 235
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236 *eof = 1;
237 return len;
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238}
239
240int get_curr_tx_free_desc(struct net_device *dev, int priority);
241
242static int proc_get_stats_hw(char *page, char **start,
243 off_t offset, int count,
244 int *eof, void *data)
245{
c8d86be3 246 int len = 0;
c8d86be3 247
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248 *eof = 1;
249 return len;
250}
251
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252static int proc_get_stats_rx(char *page, char **start,
253 off_t offset, int count,
254 int *eof, void *data)
255{
256 struct net_device *dev = data;
257 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
258
259 int len = 0;
260
261 len += snprintf(page + len, count - len,
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262 "RX OK: %lu\n"
263 "RX Retry: %lu\n"
264 "RX CRC Error(0-500): %lu\n"
265 "RX CRC Error(500-1000): %lu\n"
266 "RX CRC Error(>1000): %lu\n"
267 "RX ICV Error: %lu\n",
268 priv->stats.rxint,
269 priv->stats.rxerr,
270 priv->stats.rxcrcerrmin,
271 priv->stats.rxcrcerrmid,
272 priv->stats.rxcrcerrmax,
273 priv->stats.rxicverr
274 );
275
276 *eof = 1;
277 return len;
278}
279
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280static int proc_get_stats_tx(char *page, char **start,
281 off_t offset, int count,
282 int *eof, void *data)
283{
284 struct net_device *dev = data;
285 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
286
287 int len = 0;
288 unsigned long totalOK;
289
bbfb5652 290 totalOK = priv->stats.txnpokint+priv->stats.txhpokint+priv->stats.txlpokint;
c8d86be3 291 len += snprintf(page + len, count - len,
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292 "TX OK: %lu\n"
293 "TX Error: %lu\n"
294 "TX Retry: %lu\n"
295 "TX beacon OK: %lu\n"
296 "TX beacon error: %lu\n",
297 totalOK,
298 priv->stats.txnperr+priv->stats.txhperr+priv->stats.txlperr,
299 priv->stats.txretry,
300 priv->stats.txbeacon,
301 priv->stats.txbeaconerr
302 );
303
304 *eof = 1;
305 return len;
306}
307
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308void rtl8180_proc_module_init(void)
309{
310 DMESG("Initializing proc filesystem");
bbfb5652 311 rtl8180_proc = create_proc_entry(RTL8180_MODULE_NAME, S_IFDIR, init_net.proc_net);
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312}
313
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314void rtl8180_proc_module_remove(void)
315{
cb73da25 316 remove_proc_entry(RTL8180_MODULE_NAME, init_net.proc_net);
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317}
318
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319void rtl8180_proc_remove_one(struct net_device *dev)
320{
321 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
322 if (priv->dir_dev) {
323 remove_proc_entry("stats-hw", priv->dir_dev);
324 remove_proc_entry("stats-tx", priv->dir_dev);
325 remove_proc_entry("stats-rx", priv->dir_dev);
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326 remove_proc_entry("registers", priv->dir_dev);
327 remove_proc_entry(dev->name, rtl8180_proc);
328 priv->dir_dev = NULL;
329 }
330}
331
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332void rtl8180_proc_init_one(struct net_device *dev)
333{
334 struct proc_dir_entry *e;
335 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
fd882783 336
be286fd2 337 priv->dir_dev = rtl8180_proc;
c8d86be3 338 if (!priv->dir_dev) {
be286fd2 339 DMESGE("Unable to initialize /proc/net/r8180/%s\n",
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340 dev->name);
341 return;
342 }
343
344 e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO,
345 priv->dir_dev, proc_get_stats_hw, dev);
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346 if (!e) {
347 DMESGE("Unable to initialize "
be286fd2 348 "/proc/net/r8180/%s/stats-hw\n",
c8d86be3
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349 dev->name);
350 }
351
352 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO,
353 priv->dir_dev, proc_get_stats_rx, dev);
c8d86be3
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354 if (!e) {
355 DMESGE("Unable to initialize "
be286fd2 356 "/proc/net/r8180/%s/stats-rx\n",
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357 dev->name);
358 }
359
360
361 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO,
362 priv->dir_dev, proc_get_stats_tx, dev);
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363 if (!e) {
364 DMESGE("Unable to initialize "
be286fd2 365 "/proc/net/r8180/%s/stats-tx\n",
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366 dev->name);
367 }
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368
369 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO,
370 priv->dir_dev, proc_get_registers, dev);
c8d86be3
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371 if (!e) {
372 DMESGE("Unable to initialize "
be286fd2 373 "/proc/net/r8180/%s/registers\n",
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374 dev->name);
375 }
376}
fd882783 377
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378/*
379 FIXME: check if we can use some standard already-existent
380 data type+functions in kernel
381*/
382
383short buffer_add(struct buffer **buffer, u32 *buf, dma_addr_t dma,
384 struct buffer **bufferhead)
385{
cb73da25 386 struct buffer *tmp;
c8d86be3 387
bbfb5652 388 if (!*buffer) {
c8d86be3 389
bbfb5652 390 *buffer = kmalloc(sizeof(struct buffer), GFP_KERNEL);
c8d86be3
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391
392 if (*buffer == NULL) {
393 DMESGE("Failed to kmalloc head of TX/RX struct");
394 return -1;
395 }
bbfb5652
PS
396 (*buffer)->next = *buffer;
397 (*buffer)->buf = buf;
398 (*buffer)->dma = dma;
399 if (bufferhead != NULL)
c8d86be3
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400 (*bufferhead) = (*buffer);
401 return 0;
402 }
bbfb5652 403 tmp = *buffer;
c8d86be3 404
bbfb5652
PS
405 while (tmp->next != (*buffer))
406 tmp = tmp->next;
407 tmp->next = kmalloc(sizeof(struct buffer), GFP_KERNEL);
53756de3 408 if (tmp->next == NULL) {
c8d86be3
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409 DMESGE("Failed to kmalloc TX/RX struct");
410 return -1;
411 }
bbfb5652
PS
412 tmp->next->buf = buf;
413 tmp->next->dma = dma;
414 tmp->next->next = *buffer;
c8d86be3
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415
416 return 0;
417}
418
bbfb5652 419void buffer_free(struct net_device *dev, struct buffer **buffer, int len, short consistent)
c8d86be3
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420{
421
bbfb5652 422 struct buffer *tmp, *next;
c8d86be3 423 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
bbfb5652 424 struct pci_dev *pdev = priv->pdev;
c8d86be3 425
fd882783
BZ
426 if (!*buffer)
427 return;
c8d86be3 428
fd882783 429 tmp = *buffer;
c8d86be3 430
bbfb5652
PS
431 do {
432 next = tmp->next;
433 if (consistent) {
434 pci_free_consistent(pdev, len,
435 tmp->buf, tmp->dma);
436 } else {
c8d86be3 437 pci_unmap_single(pdev, tmp->dma,
bbfb5652 438 len, PCI_DMA_FROMDEVICE);
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439 kfree(tmp->buf);
440 }
441 kfree(tmp);
442 tmp = next;
443 }
bbfb5652 444 while (next != *buffer);
c8d86be3 445
bbfb5652 446 *buffer = NULL;
c8d86be3
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447}
448
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449void print_buffer(u32 *buffer, int len)
450{
451 int i;
bbfb5652 452 u8 *buf = (u8 *)buffer;
c8d86be3 453
bbfb5652 454 printk("ASCII BUFFER DUMP (len: %x):\n", len);
c8d86be3 455
bbfb5652
PS
456 for (i = 0; i < len; i++)
457 printk("%c", buf[i]);
c8d86be3 458
bbfb5652 459 printk("\nBINARY BUFFER DUMP (len: %x):\n", len);
c8d86be3 460
bbfb5652
PS
461 for (i = 0; i < len; i++)
462 printk("%02x", buf[i]);
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463
464 printk("\n");
465}
466
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467int get_curr_tx_free_desc(struct net_device *dev, int priority)
468{
469 struct r8180_priv *priv = ieee80211_priv(dev);
bbfb5652
PS
470 u32 *tail;
471 u32 *head;
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472 int ret;
473
bbfb5652
PS
474 switch (priority) {
475 case MANAGE_PRIORITY:
476 head = priv->txmapringhead;
477 tail = priv->txmapringtail;
478 break;
479 case BK_PRIORITY:
480 head = priv->txbkpringhead;
481 tail = priv->txbkpringtail;
482 break;
483 case BE_PRIORITY:
484 head = priv->txbepringhead;
485 tail = priv->txbepringtail;
486 break;
487 case VI_PRIORITY:
488 head = priv->txvipringhead;
489 tail = priv->txvipringtail;
490 break;
491 case VO_PRIORITY:
492 head = priv->txvopringhead;
493 tail = priv->txvopringtail;
494 break;
495 case HI_PRIORITY:
496 head = priv->txhpringhead;
497 tail = priv->txhpringtail;
498 break;
499 default:
500 return -1;
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501 }
502
fd882783 503 if (head <= tail)
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504 ret = priv->txringcount - (tail - head)/8;
505 else
506 ret = (head - tail)/8;
507
fd882783
BZ
508 if (ret > priv->txringcount)
509 DMESG("BUG");
510
c8d86be3 511 return ret;
c8d86be3
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512}
513
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514short check_nic_enought_desc(struct net_device *dev, int priority)
515{
516 struct r8180_priv *priv = ieee80211_priv(dev);
517 struct ieee80211_device *ieee = netdev_priv(dev);
c8d86be3 518 int requiredbyte, required;
fd882783 519
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520 requiredbyte = priv->ieee80211->fts + sizeof(struct ieee80211_header_data);
521
fd882783 522 if (ieee->current_network.QoS_Enable)
c8d86be3 523 requiredbyte += 2;
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524
525 required = requiredbyte / (priv->txbuffsize-4);
fd882783
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526
527 if (requiredbyte % priv->txbuffsize)
528 required++;
529
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530 /* for now we keep two free descriptor as a safety boundary
531 * between the tail and the head
532 */
533
bbfb5652 534 return (required+2 < get_curr_tx_free_desc(dev, priority));
c8d86be3
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535}
536
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537void fix_tx_fifo(struct net_device *dev)
538{
539 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
540 u32 *tmp;
541 int i;
ff954853 542
bbfb5652 543 for (tmp = priv->txmapring, i = 0;
c8d86be3 544 i < priv->txringcount;
bbfb5652
PS
545 tmp += 8, i++) {
546 *tmp = *tmp & ~(1<<31);
c8d86be3
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547 }
548
bbfb5652 549 for (tmp = priv->txbkpring, i = 0;
c8d86be3 550 i < priv->txringcount;
bbfb5652
PS
551 tmp += 8, i++) {
552 *tmp = *tmp & ~(1<<31);
c8d86be3
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553 }
554
bbfb5652 555 for (tmp = priv->txbepring, i = 0;
c8d86be3 556 i < priv->txringcount;
bbfb5652
PS
557 tmp += 8, i++) {
558 *tmp = *tmp & ~(1<<31);
c8d86be3 559 }
bbfb5652 560 for (tmp = priv->txvipring, i = 0;
c8d86be3 561 i < priv->txringcount;
bbfb5652
PS
562 tmp += 8, i++) {
563 *tmp = *tmp & ~(1<<31);
c8d86be3
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564 }
565
bbfb5652 566 for (tmp = priv->txvopring, i = 0;
c8d86be3 567 i < priv->txringcount;
bbfb5652
PS
568 tmp += 8, i++) {
569 *tmp = *tmp & ~(1<<31);
c8d86be3
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570 }
571
bbfb5652 572 for (tmp = priv->txhpring, i = 0;
c8d86be3 573 i < priv->txringcount;
bbfb5652
PS
574 tmp += 8, i++) {
575 *tmp = *tmp & ~(1<<31);
c8d86be3
GKH
576 }
577
bbfb5652 578 for (tmp = priv->txbeaconring, i = 0;
c8d86be3 579 i < priv->txbeaconcount;
bbfb5652
PS
580 tmp += 8, i++) {
581 *tmp = *tmp & ~(1<<31);
c8d86be3 582 }
ff954853 583
c8d86be3
GKH
584 priv->txmapringtail = priv->txmapring;
585 priv->txmapringhead = priv->txmapring;
586 priv->txmapbufstail = priv->txmapbufs;
587
588 priv->txbkpringtail = priv->txbkpring;
589 priv->txbkpringhead = priv->txbkpring;
590 priv->txbkpbufstail = priv->txbkpbufs;
591
592 priv->txbepringtail = priv->txbepring;
593 priv->txbepringhead = priv->txbepring;
594 priv->txbepbufstail = priv->txbepbufs;
595
596 priv->txvipringtail = priv->txvipring;
597 priv->txvipringhead = priv->txvipring;
598 priv->txvipbufstail = priv->txvipbufs;
599
600 priv->txvopringtail = priv->txvopring;
601 priv->txvopringhead = priv->txvopring;
602 priv->txvopbufstail = priv->txvopbufs;
603
604 priv->txhpringtail = priv->txhpring;
605 priv->txhpringhead = priv->txhpring;
606 priv->txhpbufstail = priv->txhpbufs;
607
608 priv->txbeaconringtail = priv->txbeaconring;
609 priv->txbeaconbufstail = priv->txbeaconbufs;
610 set_nic_txring(dev);
611
612 ieee80211_reset_queue(priv->ieee80211);
613 priv->ack_tx_to_ieee = 0;
614}
615
c8d86be3
GKH
616void fix_rx_fifo(struct net_device *dev)
617{
618 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
619 u32 *tmp;
620 struct buffer *rxbuf;
621 u8 rx_desc_size;
622
c8d86be3 623 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3 624
bbfb5652 625 for (tmp = priv->rxring, rxbuf = priv->rxbufferhead;
c8d86be3 626 (tmp < (priv->rxring)+(priv->rxringcount)*rx_desc_size);
bbfb5652 627 tmp += rx_desc_size, rxbuf = rxbuf->next) {
c8d86be3 628 *(tmp+2) = rxbuf->dma;
bbfb5652
PS
629 *tmp = *tmp & ~0xfff;
630 *tmp = *tmp | priv->rxbuffersize;
c8d86be3
GKH
631 *tmp |= (1<<31);
632 }
633
bbfb5652
PS
634 priv->rxringtail = priv->rxring;
635 priv->rxbuffer = priv->rxbufferhead;
636 priv->rx_skb_complete = 1;
c8d86be3
GKH
637 set_nic_rxring(dev);
638}
639
c8d86be3 640unsigned char QUALITY_MAP[] = {
fd882783
BZ
641 0x64, 0x64, 0x64, 0x63, 0x63, 0x62, 0x62, 0x61,
642 0x61, 0x60, 0x60, 0x5f, 0x5f, 0x5e, 0x5d, 0x5c,
643 0x5b, 0x5a, 0x59, 0x57, 0x56, 0x54, 0x52, 0x4f,
644 0x4c, 0x49, 0x45, 0x41, 0x3c, 0x37, 0x31, 0x29,
645 0x24, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
646 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x20,
647 0x20, 0x20, 0x20, 0x1f, 0x1f, 0x1e, 0x1e, 0x1e,
648 0x1d, 0x1d, 0x1c, 0x1c, 0x1b, 0x1a, 0x19, 0x19,
649 0x18, 0x17, 0x16, 0x15, 0x14, 0x12, 0x11, 0x0f,
650 0x0e, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x01, 0x00
c8d86be3
GKH
651};
652
653unsigned char STRENGTH_MAP[] = {
fd882783
BZ
654 0x64, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e,
655 0x5d, 0x5c, 0x5b, 0x5a, 0x57, 0x54, 0x52, 0x50,
656 0x4e, 0x4c, 0x4a, 0x48, 0x46, 0x44, 0x41, 0x3f,
657 0x3c, 0x3a, 0x37, 0x36, 0x36, 0x1c, 0x1c, 0x1b,
658 0x1b, 0x1a, 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17,
659 0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13,
660 0x13, 0x12, 0x12, 0x11, 0x11, 0x10, 0x10, 0x0f,
661 0x0f, 0x0e, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b,
662 0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07,
663 0x07, 0x06, 0x06, 0x05, 0x04, 0x03, 0x02, 0x00
c8d86be3
GKH
664};
665
fd882783
BZ
666void rtl8180_RSSI_calc(struct net_device *dev, u8 *rssi, u8 *qual)
667{
c8d86be3
GKH
668 u32 temp;
669 u32 temp2;
c8d86be3
GKH
670 u32 q;
671 u32 orig_qual;
672 u8 _rssi;
673
674 q = *qual;
675 orig_qual = *qual;
676 _rssi = 0; // avoid gcc complains..
677
678 if (q <= 0x4e) {
679 temp = QUALITY_MAP[q];
680 } else {
bbfb5652 681 if (q & 0x80)
c8d86be3 682 temp = 0x32;
bbfb5652 683 else
c8d86be3 684 temp = 1;
c8d86be3
GKH
685 }
686
687 *qual = temp;
688 temp2 = *rssi;
689
bbfb5652
PS
690 if (_rssi < 0x64) {
691 if (_rssi == 0)
c8d86be3 692 *rssi = 1;
c8d86be3
GKH
693 } else {
694 *rssi = 0x64;
695 }
696
697 return;
698}
699
c8d86be3
GKH
700void rtl8180_irq_enable(struct net_device *dev)
701{
702 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
fd882783 703
c8d86be3 704 priv->irq_enabled = 1;
bbfb5652 705 write_nic_word(dev, INTA_MASK, priv->irq_mask);
c8d86be3
GKH
706}
707
c8d86be3
GKH
708void rtl8180_irq_disable(struct net_device *dev)
709{
710 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
711
bbfb5652 712 write_nic_dword(dev, IMR, 0);
c8d86be3
GKH
713 force_pci_posting(dev);
714 priv->irq_enabled = 0;
715}
716
bbfb5652 717void rtl8180_set_mode(struct net_device *dev, int mode)
c8d86be3
GKH
718{
719 u8 ecmd;
fd882783 720
bbfb5652
PS
721 ecmd = read_nic_byte(dev, EPROM_CMD);
722 ecmd = ecmd & ~EPROM_CMD_OPERATING_MODE_MASK;
723 ecmd = ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
724 ecmd = ecmd & ~(1<<EPROM_CS_SHIFT);
725 ecmd = ecmd & ~(1<<EPROM_CK_SHIFT);
c8d86be3
GKH
726 write_nic_byte(dev, EPROM_CMD, ecmd);
727}
728
729void rtl8180_adapter_start(struct net_device *dev);
730void rtl8180_beacon_tx_enable(struct net_device *dev);
731
732void rtl8180_update_msr(struct net_device *dev)
733{
734 struct r8180_priv *priv = ieee80211_priv(dev);
735 u8 msr;
736 u32 rxconf;
737
738 msr = read_nic_byte(dev, MSR);
bbfb5652 739 msr &= ~MSR_LINK_MASK;
c8d86be3 740
bbfb5652 741 rxconf = read_nic_dword(dev, RX_CONF);
c8d86be3 742
bbfb5652
PS
743 if (priv->ieee80211->state == IEEE80211_LINKED) {
744 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
c8d86be3
GKH
745 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
746 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
747 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
748 else if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
749 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
750 else
751 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
752 rxconf |= (1<<RX_CHECK_BSSID_SHIFT);
753
bbfb5652 754 } else {
c8d86be3
GKH
755 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
756 rxconf &= ~(1<<RX_CHECK_BSSID_SHIFT);
757 }
758
759 write_nic_byte(dev, MSR, msr);
760 write_nic_dword(dev, RX_CONF, rxconf);
c8d86be3
GKH
761}
762
bbfb5652 763void rtl8180_set_chan(struct net_device *dev, short ch)
c8d86be3
GKH
764{
765 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
766
fd882783 767 if ((ch > 14) || (ch < 1)) {
d599edca 768 printk("In %s: Invalid chnanel %d\n", __func__, ch);
c8d86be3
GKH
769 return;
770 }
771
bbfb5652
PS
772 priv->chan = ch;
773 priv->rf_set_chan(dev, priv->chan);
c8d86be3
GKH
774}
775
c8d86be3
GKH
776void rtl8180_rx_enable(struct net_device *dev)
777{
778 u8 cmd;
779 u32 rxconf;
780 /* for now we accept data, management & ctl frame*/
781 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
782
bbfb5652
PS
783 rxconf = read_nic_dword(dev, RX_CONF);
784 rxconf = rxconf & ~MAC_FILTER_MASK;
c8d86be3
GKH
785 rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
786 rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
787 rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
788 rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
fd882783
BZ
789 if (dev->flags & IFF_PROMISC)
790 DMESG("NIC in promisc mode");
c8d86be3 791
bbfb5652
PS
792 if (priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
793 dev->flags & IFF_PROMISC) {
c8d86be3 794 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
bbfb5652 795 } else {
c8d86be3 796 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
c8d86be3
GKH
797 }
798
bbfb5652 799 if (priv->ieee80211->iw_mode == IW_MODE_MONITOR) {
c8d86be3
GKH
800 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
801 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
802 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
803 }
804
bbfb5652 805 if (priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
c8d86be3
GKH
806 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
807
fd882783
BZ
808 rxconf = rxconf & ~RX_FIFO_THRESHOLD_MASK;
809 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE << RX_FIFO_THRESHOLD_SHIFT);
c8d86be3
GKH
810
811 rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
bbfb5652 812 rxconf = rxconf & ~MAX_RX_DMA_MASK;
c8d86be3
GKH
813 rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
814
fd882783 815 rxconf = rxconf | RCR_ONLYERLPKT;
c8d86be3 816
bbfb5652 817 rxconf = rxconf & ~RCR_CS_MASK;
fd882783 818
c8d86be3
GKH
819 write_nic_dword(dev, RX_CONF, rxconf);
820
821 fix_rx_fifo(dev);
822
bbfb5652
PS
823 cmd = read_nic_byte(dev, CMD);
824 write_nic_byte(dev, CMD, cmd | (1<<CMD_RX_ENABLE_SHIFT));
c8d86be3
GKH
825}
826
c8d86be3
GKH
827void set_nic_txring(struct net_device *dev)
828{
829 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH
830
831 write_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR, priv->txmapringdma);
c8d86be3 832 write_nic_dword(dev, TX_BKPRIORITY_RING_ADDR, priv->txbkpringdma);
c8d86be3 833 write_nic_dword(dev, TX_BEPRIORITY_RING_ADDR, priv->txbepringdma);
c8d86be3 834 write_nic_dword(dev, TX_VIPRIORITY_RING_ADDR, priv->txvipringdma);
c8d86be3 835 write_nic_dword(dev, TX_VOPRIORITY_RING_ADDR, priv->txvopringdma);
c8d86be3 836 write_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR, priv->txhpringdma);
c8d86be3
GKH
837 write_nic_dword(dev, TX_BEACON_RING_ADDR, priv->txbeaconringdma);
838}
839
c8d86be3
GKH
840void rtl8180_conttx_enable(struct net_device *dev)
841{
842 u32 txconf;
fd882783 843
bbfb5652
PS
844 txconf = read_nic_dword(dev, TX_CONF);
845 txconf = txconf & ~TX_LOOPBACK_MASK;
846 txconf = txconf | (TX_LOOPBACK_CONTINUE<<TX_LOOPBACK_SHIFT);
847 write_nic_dword(dev, TX_CONF, txconf);
c8d86be3
GKH
848}
849
c8d86be3
GKH
850void rtl8180_conttx_disable(struct net_device *dev)
851{
852 u32 txconf;
fd882783 853
bbfb5652
PS
854 txconf = read_nic_dword(dev, TX_CONF);
855 txconf = txconf & ~TX_LOOPBACK_MASK;
856 txconf = txconf | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT);
857 write_nic_dword(dev, TX_CONF, txconf);
c8d86be3
GKH
858}
859
c8d86be3
GKH
860void rtl8180_tx_enable(struct net_device *dev)
861{
862 u8 cmd;
863 u8 tx_agc_ctl;
864 u8 byte;
865 u32 txconf;
866 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3 867
fd882783 868 txconf = read_nic_dword(dev, TX_CONF);
c8d86be3 869
d44eb889
LF
870 byte = read_nic_byte(dev, CW_CONF);
871 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
872 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
873 write_nic_byte(dev, CW_CONF, byte);
c8d86be3 874
d44eb889
LF
875 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
876 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
877 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
878 tx_agc_ctl |= (1<<TX_AGC_CTL_FEEDBACK_ANT);
879 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
880 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
881
882 txconf = txconf & ~(1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
c8d86be3 883
bbfb5652
PS
884 txconf = txconf & ~TX_LOOPBACK_MASK;
885 txconf = txconf | (TX_LOOPBACK_NONE<<TX_LOOPBACK_SHIFT);
886 txconf = txconf & ~TCR_DPRETRY_MASK;
887 txconf = txconf & ~TCR_RTSRETRY_MASK;
c8d86be3
GKH
888 txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
889 txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
bbfb5652 890 txconf = txconf & ~(1<<TX_NOCRC_SHIFT);
c8d86be3 891
d44eb889
LF
892 if (priv->hw_plcp_len)
893 txconf = txconf & ~TCR_PLCP_LEN;
894 else
895 txconf = txconf | TCR_PLCP_LEN;
fd882783 896
bbfb5652 897 txconf = txconf & ~TCR_MXDMA_MASK;
c8d86be3
GKH
898 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
899 txconf = txconf | TCR_CWMIN;
900 txconf = txconf | TCR_DISCW;
901
fd882783 902 txconf = txconf | (1 << TX_NOICV_SHIFT);
c8d86be3 903
bbfb5652 904 write_nic_dword(dev, TX_CONF, txconf);
c8d86be3 905
c8d86be3
GKH
906 fix_tx_fifo(dev);
907
bbfb5652
PS
908 cmd = read_nic_byte(dev, CMD);
909 write_nic_byte(dev, CMD, cmd | (1<<CMD_TX_ENABLE_SHIFT));
c8d86be3 910
bbfb5652 911 write_nic_dword(dev, TX_CONF, txconf);
c8d86be3
GKH
912}
913
c8d86be3
GKH
914void rtl8180_beacon_tx_enable(struct net_device *dev)
915{
916 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
917
bbfb5652 918 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
c8d86be3 919 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_BQ);
bbfb5652
PS
920 write_nic_byte(dev, TPPollStop, priv->dma_poll_mask);
921 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH
922}
923
c8d86be3
GKH
924void rtl8180_beacon_tx_disable(struct net_device *dev)
925{
926 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
927
bbfb5652 928 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
c8d86be3 929 priv->dma_poll_stop_mask |= TPPOLLSTOP_BQ;
bbfb5652
PS
930 write_nic_byte(dev, TPPollStop, priv->dma_poll_stop_mask);
931 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH
932
933}
934
c8d86be3
GKH
935void rtl8180_rtx_disable(struct net_device *dev)
936{
937 u8 cmd;
938 struct r8180_priv *priv = ieee80211_priv(dev);
939
bbfb5652
PS
940 cmd = read_nic_byte(dev, CMD);
941 write_nic_byte(dev, CMD, cmd & ~\
c8d86be3
GKH
942 ((1<<CMD_RX_ENABLE_SHIFT)|(1<<CMD_TX_ENABLE_SHIFT)));
943 force_pci_posting(dev);
944 mdelay(10);
c8d86be3 945
bbfb5652 946 if (!priv->rx_skb_complete)
c8d86be3
GKH
947 dev_kfree_skb_any(priv->rx_skb);
948}
949
c8d86be3
GKH
950short alloc_tx_desc_ring(struct net_device *dev, int bufsize, int count,
951 int addr)
952{
953 int i;
954 u32 *desc;
955 u32 *tmp;
956 dma_addr_t dma_desc, dma_tmp;
957 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
958 struct pci_dev *pdev = priv->pdev;
959 void *buf;
960
bbfb5652
PS
961 if ((bufsize & 0xfff) != bufsize) {
962 DMESGE("TX buffer allocation too large");
c8d86be3
GKH
963 return 0;
964 }
bbfb5652 965 desc = (u32 *)pci_alloc_consistent(pdev,
c8d86be3 966 sizeof(u32)*8*count+256, &dma_desc);
fd882783
BZ
967 if (desc == NULL)
968 return -1;
c8d86be3 969
fd882783 970 if (dma_desc & 0xff)
c8d86be3
GKH
971 /*
972 * descriptor's buffer must be 256 byte aligned
973 * we shouldn't be here, since we set DMA mask !
974 */
be286fd2 975 WARN(1, "DMA buffer is not aligned\n");
fd882783
BZ
976
977 tmp = desc;
978
979 for (i = 0; i < count; i++) {
980 buf = (void *)pci_alloc_consistent(pdev, bufsize, &dma_tmp);
981 if (buf == NULL)
982 return -ENOMEM;
c8d86be3 983
bbfb5652 984 switch (addr) {
c8d86be3 985 case TX_MANAGEPRIORITY_RING_ADDR:
bbfb5652 986 if (-1 == buffer_add(&(priv->txmapbufs), buf, dma_tmp, NULL)) {
c8d86be3
GKH
987 DMESGE("Unable to allocate mem for buffer NP");
988 return -ENOMEM;
989 }
990 break;
c8d86be3 991 case TX_BKPRIORITY_RING_ADDR:
bbfb5652 992 if (-1 == buffer_add(&(priv->txbkpbufs), buf, dma_tmp, NULL)) {
c8d86be3
GKH
993 DMESGE("Unable to allocate mem for buffer LP");
994 return -ENOMEM;
995 }
996 break;
997 case TX_BEPRIORITY_RING_ADDR:
bbfb5652 998 if (-1 == buffer_add(&(priv->txbepbufs), buf, dma_tmp, NULL)) {
c8d86be3
GKH
999 DMESGE("Unable to allocate mem for buffer NP");
1000 return -ENOMEM;
1001 }
1002 break;
c8d86be3 1003 case TX_VIPRIORITY_RING_ADDR:
bbfb5652 1004 if (-1 == buffer_add(&(priv->txvipbufs), buf, dma_tmp, NULL)) {
c8d86be3
GKH
1005 DMESGE("Unable to allocate mem for buffer LP");
1006 return -ENOMEM;
1007 }
1008 break;
1009 case TX_VOPRIORITY_RING_ADDR:
bbfb5652 1010 if (-1 == buffer_add(&(priv->txvopbufs), buf, dma_tmp, NULL)) {
c8d86be3
GKH
1011 DMESGE("Unable to allocate mem for buffer NP");
1012 return -ENOMEM;
1013 }
1014 break;
c8d86be3 1015 case TX_HIGHPRIORITY_RING_ADDR:
bbfb5652 1016 if (-1 == buffer_add(&(priv->txhpbufs), buf, dma_tmp, NULL)) {
c8d86be3
GKH
1017 DMESGE("Unable to allocate mem for buffer HP");
1018 return -ENOMEM;
1019 }
1020 break;
1021 case TX_BEACON_RING_ADDR:
bbfb5652
PS
1022 if (-1 == buffer_add(&(priv->txbeaconbufs), buf, dma_tmp, NULL)) {
1023 DMESGE("Unable to allocate mem for buffer BP");
c8d86be3
GKH
1024 return -ENOMEM;
1025 }
1026 break;
1027 }
bbfb5652 1028 *tmp = *tmp & ~(1<<31); // descriptor empty, owned by the drv
c8d86be3
GKH
1029 *(tmp+2) = (u32)dma_tmp;
1030 *(tmp+3) = bufsize;
1031
bbfb5652 1032 if (i+1 < count)
c8d86be3
GKH
1033 *(tmp+4) = (u32)dma_desc+((i+1)*8*4);
1034 else
1035 *(tmp+4) = (u32)dma_desc;
1036
bbfb5652 1037 tmp = tmp+8;
c8d86be3
GKH
1038 }
1039
bbfb5652 1040 switch (addr) {
c8d86be3 1041 case TX_MANAGEPRIORITY_RING_ADDR:
bbfb5652
PS
1042 priv->txmapringdma = dma_desc;
1043 priv->txmapring = desc;
c8d86be3 1044 break;
c8d86be3 1045 case TX_BKPRIORITY_RING_ADDR:
bbfb5652
PS
1046 priv->txbkpringdma = dma_desc;
1047 priv->txbkpring = desc;
c8d86be3 1048 break;
c8d86be3 1049 case TX_BEPRIORITY_RING_ADDR:
bbfb5652
PS
1050 priv->txbepringdma = dma_desc;
1051 priv->txbepring = desc;
c8d86be3 1052 break;
c8d86be3 1053 case TX_VIPRIORITY_RING_ADDR:
bbfb5652
PS
1054 priv->txvipringdma = dma_desc;
1055 priv->txvipring = desc;
c8d86be3 1056 break;
c8d86be3 1057 case TX_VOPRIORITY_RING_ADDR:
bbfb5652
PS
1058 priv->txvopringdma = dma_desc;
1059 priv->txvopring = desc;
c8d86be3 1060 break;
c8d86be3 1061 case TX_HIGHPRIORITY_RING_ADDR:
bbfb5652
PS
1062 priv->txhpringdma = dma_desc;
1063 priv->txhpring = desc;
c8d86be3 1064 break;
c8d86be3 1065 case TX_BEACON_RING_ADDR:
bbfb5652
PS
1066 priv->txbeaconringdma = dma_desc;
1067 priv->txbeaconring = desc;
c8d86be3
GKH
1068 break;
1069
1070 }
1071
c8d86be3
GKH
1072 return 0;
1073}
1074
c8d86be3
GKH
1075void free_tx_desc_rings(struct net_device *dev)
1076{
c8d86be3 1077 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
bbfb5652 1078 struct pci_dev *pdev = priv->pdev;
c8d86be3
GKH
1079 int count = priv->txringcount;
1080
1081 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1082 priv->txmapring, priv->txmapringdma);
bbfb5652 1083 buffer_free(dev, &(priv->txmapbufs), priv->txbuffsize, 1);
c8d86be3
GKH
1084
1085 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1086 priv->txbkpring, priv->txbkpringdma);
bbfb5652 1087 buffer_free(dev, &(priv->txbkpbufs), priv->txbuffsize, 1);
c8d86be3
GKH
1088
1089 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1090 priv->txbepring, priv->txbepringdma);
bbfb5652 1091 buffer_free(dev, &(priv->txbepbufs), priv->txbuffsize, 1);
c8d86be3
GKH
1092
1093 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1094 priv->txvipring, priv->txvipringdma);
bbfb5652 1095 buffer_free(dev, &(priv->txvipbufs), priv->txbuffsize, 1);
c8d86be3
GKH
1096
1097 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1098 priv->txvopring, priv->txvopringdma);
bbfb5652 1099 buffer_free(dev, &(priv->txvopbufs), priv->txbuffsize, 1);
c8d86be3
GKH
1100
1101 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1102 priv->txhpring, priv->txhpringdma);
bbfb5652 1103 buffer_free(dev, &(priv->txhpbufs), priv->txbuffsize, 1);
c8d86be3
GKH
1104
1105 count = priv->txbeaconcount;
1106 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1107 priv->txbeaconring, priv->txbeaconringdma);
bbfb5652 1108 buffer_free(dev, &(priv->txbeaconbufs), priv->txbuffsize, 1);
c8d86be3
GKH
1109}
1110
c8d86be3
GKH
1111void free_rx_desc_ring(struct net_device *dev)
1112{
1113 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1114 struct pci_dev *pdev = priv->pdev;
c8d86be3
GKH
1115 int count = priv->rxringcount;
1116
c8d86be3
GKH
1117 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1118 priv->rxring, priv->rxringdma);
c8d86be3 1119
bbfb5652 1120 buffer_free(dev, &(priv->rxbuffer), priv->rxbuffersize, 0);
c8d86be3
GKH
1121}
1122
c8d86be3
GKH
1123short alloc_rx_desc_ring(struct net_device *dev, u16 bufsize, int count)
1124{
1125 int i;
1126 u32 *desc;
1127 u32 *tmp;
bbfb5652 1128 dma_addr_t dma_desc, dma_tmp;
c8d86be3 1129 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
bbfb5652 1130 struct pci_dev *pdev = priv->pdev;
c8d86be3
GKH
1131 void *buf;
1132 u8 rx_desc_size;
1133
c8d86be3 1134 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3 1135
bbfb5652
PS
1136 if ((bufsize & 0xfff) != bufsize) {
1137 DMESGE("RX buffer allocation too large");
c8d86be3
GKH
1138 return -1;
1139 }
1140
bbfb5652 1141 desc = (u32 *)pci_alloc_consistent(pdev, sizeof(u32)*rx_desc_size*count+256,
c8d86be3
GKH
1142 &dma_desc);
1143
fd882783 1144 if (dma_desc & 0xff)
c8d86be3
GKH
1145 /*
1146 * descriptor's buffer must be 256 byte aligned
1147 * should never happen since we specify the DMA mask
1148 */
be286fd2 1149 WARN(1, "DMA buffer is not aligned\n");
c8d86be3 1150
bbfb5652
PS
1151 priv->rxring = desc;
1152 priv->rxringdma = dma_desc;
1153 tmp = desc;
c8d86be3 1154
fd882783 1155 for (i = 0; i < count; i++) {
bbfb5652 1156 buf = kmalloc(bufsize * sizeof(u8), GFP_ATOMIC);
53756de3 1157 if (buf == NULL) {
c8d86be3
GKH
1158 DMESGE("Failed to kmalloc RX buffer");
1159 return -1;
1160 }
1161
bbfb5652 1162 dma_tmp = pci_map_single(pdev, buf, bufsize * sizeof(u8),
c8d86be3
GKH
1163 PCI_DMA_FROMDEVICE);
1164
bbfb5652
PS
1165 if (-1 == buffer_add(&(priv->rxbuffer), buf, dma_tmp,
1166 &(priv->rxbufferhead))) {
1167 DMESGE("Unable to allocate mem RX buf");
1168 return -1;
c8d86be3 1169 }
bbfb5652
PS
1170 *tmp = 0; // zero pads the header of the descriptor
1171 *tmp = *tmp | (bufsize&0xfff);
c8d86be3 1172 *(tmp+2) = (u32)dma_tmp;
bbfb5652 1173 *tmp = *tmp | (1<<31); // descriptor void, owned by the NIC
c8d86be3 1174
bbfb5652 1175 tmp = tmp+rx_desc_size;
c8d86be3
GKH
1176 }
1177
1178 *(tmp-rx_desc_size) = *(tmp-rx_desc_size) | (1<<30); // this is the last descriptor
1179
c8d86be3
GKH
1180 return 0;
1181}
1182
1183
1184void set_nic_rxring(struct net_device *dev)
1185{
1186 u8 pgreg;
1187 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1188
bbfb5652
PS
1189 pgreg = read_nic_byte(dev, PGSELECT);
1190 write_nic_byte(dev, PGSELECT, pgreg & ~(1<<PGSELECT_PG_SHIFT));
c8d86be3 1191
bbfb5652 1192 write_nic_dword(dev, RXRING_ADDR, priv->rxringdma);
c8d86be3
GKH
1193}
1194
c8d86be3
GKH
1195void rtl8180_reset(struct net_device *dev)
1196{
c8d86be3
GKH
1197 u8 cr;
1198
c8d86be3
GKH
1199 rtl8180_irq_disable(dev);
1200
bbfb5652 1201 cr = read_nic_byte(dev, CMD);
c8d86be3
GKH
1202 cr = cr & 2;
1203 cr = cr | (1<<CMD_RST_SHIFT);
bbfb5652 1204 write_nic_byte(dev, CMD, cr);
c8d86be3
GKH
1205
1206 force_pci_posting(dev);
1207
1208 mdelay(200);
1209
bbfb5652 1210 if (read_nic_byte(dev, CMD) & (1<<CMD_RST_SHIFT))
c8d86be3
GKH
1211 DMESGW("Card reset timeout!");
1212 else
1213 DMESG("Card successfully reset");
1214
bbfb5652 1215 rtl8180_set_mode(dev, EPROM_CMD_LOAD);
c8d86be3
GKH
1216 force_pci_posting(dev);
1217 mdelay(200);
c8d86be3
GKH
1218}
1219
1220inline u16 ieeerate2rtlrate(int rate)
1221{
bbfb5652 1222 switch (rate) {
c8d86be3 1223 case 10:
fd882783 1224 return 0;
c8d86be3 1225 case 20:
fd882783 1226 return 1;
c8d86be3 1227 case 55:
fd882783 1228 return 2;
c8d86be3 1229 case 110:
fd882783 1230 return 3;
c8d86be3 1231 case 60:
fd882783 1232 return 4;
c8d86be3 1233 case 90:
fd882783 1234 return 5;
c8d86be3 1235 case 120:
fd882783 1236 return 6;
c8d86be3 1237 case 180:
fd882783 1238 return 7;
c8d86be3 1239 case 240:
fd882783 1240 return 8;
c8d86be3 1241 case 360:
fd882783 1242 return 9;
c8d86be3 1243 case 480:
fd882783 1244 return 10;
c8d86be3 1245 case 540:
fd882783 1246 return 11;
c8d86be3 1247 default:
fd882783 1248 return 3;
c8d86be3
GKH
1249 }
1250}
1251
bbfb5652 1252static u16 rtl_rate[] = {10, 20, 55, 110, 60, 90, 120, 180, 240, 360, 480, 540, 720};
fd882783 1253
c8d86be3
GKH
1254inline u16 rtl8180_rate2rate(short rate)
1255{
fd882783
BZ
1256 if (rate > 12)
1257 return 10;
c8d86be3
GKH
1258 return rtl_rate[rate];
1259}
fd882783 1260
c8d86be3
GKH
1261inline u8 rtl8180_IsWirelessBMode(u16 rate)
1262{
bbfb5652 1263 if (((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220))
c8d86be3 1264 return 1;
fd882783
BZ
1265 else
1266 return 0;
c8d86be3 1267}
fd882783 1268
c8d86be3 1269u16 N_DBPSOfRate(u16 DataRate);
fd882783
BZ
1270
1271u16 ComputeTxTime(u16 FrameLength, u16 DataRate, u8 bManagementFrame,
1272 u8 bShortPreamble)
c8d86be3
GKH
1273{
1274 u16 FrameTime;
1275 u16 N_DBPS;
1276 u16 Ceiling;
1277
fd882783
BZ
1278 if (rtl8180_IsWirelessBMode(DataRate)) {
1279 if (bManagementFrame || !bShortPreamble || DataRate == 10)
1280 /* long preamble */
c8d86be3 1281 FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10)));
c8d86be3 1282 else
fd882783 1283 /* short preamble */
c8d86be3 1284 FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10)));
fd882783
BZ
1285
1286 if ((FrameLength*8 % (DataRate/10)) != 0) /* get the ceilling */
1287 FrameTime++;
1288 } else { /* 802.11g DSSS-OFDM PLCP length field calculation. */
c8d86be3
GKH
1289 N_DBPS = N_DBPSOfRate(DataRate);
1290 Ceiling = (16 + 8*FrameLength + 6) / N_DBPS
1291 + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0);
1292 FrameTime = (u16)(16 + 4 + 4*Ceiling + 6);
1293 }
1294 return FrameTime;
1295}
fd882783 1296
c8d86be3
GKH
1297u16 N_DBPSOfRate(u16 DataRate)
1298{
1299 u16 N_DBPS = 24;
1300
fd882783
BZ
1301 switch (DataRate) {
1302 case 60:
1303 N_DBPS = 24;
1304 break;
1305 case 90:
1306 N_DBPS = 36;
1307 break;
1308 case 120:
1309 N_DBPS = 48;
1310 break;
1311 case 180:
1312 N_DBPS = 72;
1313 break;
1314 case 240:
1315 N_DBPS = 96;
1316 break;
1317 case 360:
1318 N_DBPS = 144;
1319 break;
1320 case 480:
1321 N_DBPS = 192;
1322 break;
1323 case 540:
1324 N_DBPS = 216;
1325 break;
1326 default:
1327 break;
1328 }
c8d86be3 1329
fd882783 1330 return N_DBPS;
c8d86be3
GKH
1331}
1332
c8d86be3
GKH
1333//
1334// Description:
bbfb5652 1335// For Netgear case, they want good-looking singal strength.
c8d86be3 1336//
fd882783 1337long NetgearSignalStrengthTranslate(long LastSS, long CurrSS)
c8d86be3
GKH
1338{
1339 long RetSS;
1340
1341 // Step 1. Scale mapping.
fd882783 1342 if (CurrSS >= 71 && CurrSS <= 100)
c8d86be3 1343 RetSS = 90 + ((CurrSS - 70) / 3);
fd882783 1344 else if (CurrSS >= 41 && CurrSS <= 70)
c8d86be3 1345 RetSS = 78 + ((CurrSS - 40) / 3);
fd882783 1346 else if (CurrSS >= 31 && CurrSS <= 40)
c8d86be3 1347 RetSS = 66 + (CurrSS - 30);
fd882783 1348 else if (CurrSS >= 21 && CurrSS <= 30)
c8d86be3 1349 RetSS = 54 + (CurrSS - 20);
fd882783 1350 else if (CurrSS >= 5 && CurrSS <= 20)
c8d86be3 1351 RetSS = 42 + (((CurrSS - 5) * 2) / 3);
fd882783 1352 else if (CurrSS == 4)
c8d86be3 1353 RetSS = 36;
fd882783 1354 else if (CurrSS == 3)
c8d86be3 1355 RetSS = 27;
fd882783 1356 else if (CurrSS == 2)
c8d86be3 1357 RetSS = 18;
fd882783 1358 else if (CurrSS == 1)
c8d86be3 1359 RetSS = 9;
c8d86be3 1360 else
c8d86be3 1361 RetSS = CurrSS;
c8d86be3
GKH
1362
1363 // Step 2. Smoothing.
bbfb5652
PS
1364 if (LastSS > 0)
1365 RetSS = ((LastSS * 5) + (RetSS) + 5) / 6;
c8d86be3
GKH
1366
1367 return RetSS;
1368}
fd882783 1369
c8d86be3
GKH
1370//
1371// Description:
1372// Translate 0-100 signal strength index into dBm.
1373//
fd882783 1374long TranslateToDbm8185(u8 SignalStrengthIndex)
c8d86be3 1375{
fd882783 1376 long SignalPower;
c8d86be3
GKH
1377
1378 // Translate to dBm (x=0.5y-95).
1379 SignalPower = (long)((SignalStrengthIndex + 1) >> 1);
1380 SignalPower -= 95;
1381
1382 return SignalPower;
1383}
fd882783 1384
c8d86be3
GKH
1385//
1386// Description:
1387// Perform signal smoothing for dynamic mechanism.
1388// This is different with PerformSignalSmoothing8185 in smoothing fomula.
1389// No dramatic adjustion is apply because dynamic mechanism need some degree
1390// of correctness. Ported from 8187B.
c8d86be3 1391//
fd882783
BZ
1392void PerformUndecoratedSignalSmoothing8185(struct r8180_priv *priv,
1393 bool bCckRate)
c8d86be3 1394{
c8d86be3
GKH
1395 // Determin the current packet is CCK rate.
1396 priv->bCurCCKPkt = bCckRate;
1397
fd882783 1398 if (priv->UndecoratedSmoothedSS >= 0)
bbfb5652 1399 priv->UndecoratedSmoothedSS = ((priv->UndecoratedSmoothedSS * 5) + (priv->SignalStrength * 10)) / 6;
c8d86be3 1400 else
c8d86be3 1401 priv->UndecoratedSmoothedSS = priv->SignalStrength * 10;
c8d86be3 1402
bbfb5652 1403 priv->UndercorateSmoothedRxPower = ((priv->UndercorateSmoothedRxPower * 50) + (priv->RxPower * 11)) / 60;
c8d86be3 1404
fd882783 1405 if (bCckRate)
c8d86be3 1406 priv->CurCCKRSSI = priv->RSSI;
c8d86be3 1407 else
c8d86be3 1408 priv->CurCCKRSSI = 0;
c8d86be3
GKH
1409}
1410
c8d86be3
GKH
1411
1412/* This is rough RX isr handling routine*/
1413void rtl8180_rx(struct net_device *dev)
1414{
1415 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1416 struct sk_buff *tmp_skb;
bbfb5652 1417 short first, last;
c8d86be3
GKH
1418 u32 len;
1419 int lastlen;
1420 unsigned char quality, signal;
1421 u8 rate;
bbfb5652 1422 u32 *tmp, *tmp2;
c8d86be3
GKH
1423 u8 rx_desc_size;
1424 u8 padding;
c8d86be3
GKH
1425 char rxpower = 0;
1426 u32 RXAGC = 0;
1427 long RxAGC_dBm = 0;
bbfb5652 1428 u8 LNA = 0, BB = 0;
cb73da25 1429 u8 LNA_gain[4] = {02, 17, 29, 39};
c8d86be3 1430 u8 Antenna = 0;
0604384d 1431 struct ieee80211_hdr_4addr *hdr;
bbfb5652
PS
1432 u16 fc, type;
1433 u8 bHwError = 0, bCRC = 0, bICV = 0;
c8d86be3
GKH
1434 bool bCckRate = false;
1435 u8 RSSI = 0;
fd882783 1436 long SignalStrengthIndex = 0;
c8d86be3
GKH
1437 struct ieee80211_rx_stats stats = {
1438 .signal = 0,
1439 .noise = -98,
1440 .rate = 0,
c8d86be3
GKH
1441 .freq = IEEE80211_24GHZ_BAND,
1442 };
1443
c8d86be3
GKH
1444 stats.nic_type = NIC_8185B;
1445 rx_desc_size = 8;
1446
c8d86be3 1447 if ((*(priv->rxringtail)) & (1<<31)) {
c8d86be3
GKH
1448 /* we have got an RX int, but the descriptor
1449 * we are pointing is empty*/
1450
1451 priv->stats.rxnodata++;
1452 priv->ieee80211->stats.rx_errors++;
1453
c8d86be3
GKH
1454 tmp2 = NULL;
1455 tmp = priv->rxringtail;
bbfb5652
PS
1456 do {
1457 if (tmp == priv->rxring)
c8d86be3
GKH
1458 tmp = priv->rxring + (priv->rxringcount - 1)*rx_desc_size;
1459 else
1460 tmp -= rx_desc_size;
1461
bbfb5652 1462 if (!(*tmp & (1<<31)))
c8d86be3 1463 tmp2 = tmp;
bbfb5652 1464 } while (tmp != priv->rxring);
c8d86be3 1465
bbfb5652
PS
1466 if (tmp2)
1467 priv->rxringtail = tmp2;
c8d86be3
GKH
1468 }
1469
1470 /* while there are filled descriptors */
bbfb5652
PS
1471 while (!(*(priv->rxringtail) & (1<<31))) {
1472 if (*(priv->rxringtail) & (1<<26))
c8d86be3 1473 DMESGW("RX buffer overflow");
bbfb5652 1474 if (*(priv->rxringtail) & (1<<12))
c8d86be3
GKH
1475 priv->stats.rxicverr++;
1476
bbfb5652 1477 if (*(priv->rxringtail) & (1<<27)) {
c8d86be3
GKH
1478 priv->stats.rxdmafail++;
1479 //DMESG("EE: RX DMA FAILED at buffer pointed by descriptor %x",(u32)priv->rxringtail);
1480 goto drop;
1481 }
1482
1483 pci_dma_sync_single_for_cpu(priv->pdev,
1484 priv->rxbuffer->dma,
1485 priv->rxbuffersize * \
1486 sizeof(u8),
1487 PCI_DMA_FROMDEVICE);
1488
bbfb5652
PS
1489 first = *(priv->rxringtail) & (1<<29) ? 1 : 0;
1490 if (first)
1491 priv->rx_prevlen = 0;
c8d86be3 1492
bbfb5652
PS
1493 last = *(priv->rxringtail) & (1<<28) ? 1 : 0;
1494 if (last) {
1495 lastlen = ((*priv->rxringtail) & 0xfff);
c8d86be3
GKH
1496
1497 /* if the last descriptor (that should
1498 * tell us the total packet len) tell
1499 * us something less than the descriptors
1500 * len we had until now, then there is some
1501 * problem..
1502 * workaround to prevent kernel panic
1503 */
bbfb5652
PS
1504 if (lastlen < priv->rx_prevlen)
1505 len = 0;
c8d86be3 1506 else
bbfb5652 1507 len = lastlen-priv->rx_prevlen;
c8d86be3 1508
bbfb5652
PS
1509 if (*(priv->rxringtail) & (1<<13)) {
1510 if ((*(priv->rxringtail) & 0xfff) < 500)
c8d86be3 1511 priv->stats.rxcrcerrmin++;
bbfb5652 1512 else if ((*(priv->rxringtail) & 0x0fff) > 1000)
c8d86be3
GKH
1513 priv->stats.rxcrcerrmax++;
1514 else
1515 priv->stats.rxcrcerrmid++;
1516
1517 }
1518
bbfb5652 1519 } else {
c8d86be3
GKH
1520 len = priv->rxbuffersize;
1521 }
1522
bbfb5652 1523 if (first && last) {
c8d86be3 1524 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
bbfb5652 1525 } else if (first) {
c8d86be3 1526 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
bbfb5652 1527 if (padding)
c8d86be3 1528 len -= 2;
bbfb5652 1529 } else {
c8d86be3
GKH
1530 padding = 0;
1531 }
cb73da25 1532 padding = 0;
bbfb5652 1533 priv->rx_prevlen += len;
c8d86be3 1534
bbfb5652 1535 if (priv->rx_prevlen > MAX_FRAG_THRESHOLD + 100) {
c8d86be3
GKH
1536 /* HW is probably passing several buggy frames
1537 * without FD or LD flag set.
1538 * Throw this garbage away to prevent skb
1539 * memory exausting
1540 */
bbfb5652 1541 if (!priv->rx_skb_complete)
c8d86be3
GKH
1542 dev_kfree_skb_any(priv->rx_skb);
1543 priv->rx_skb_complete = 1;
1544 }
1545
bbfb5652 1546 signal = (unsigned char)(((*(priv->rxringtail+3)) & (0x00ff0000))>>16);
1994130e 1547 signal = (signal & 0xfe) >> 1;
c8d86be3 1548
bbfb5652 1549 quality = (unsigned char)((*(priv->rxringtail+3)) & (0xff));
c8d86be3
GKH
1550
1551 stats.mac_time[0] = *(priv->rxringtail+1);
1552 stats.mac_time[1] = *(priv->rxringtail+2);
bbfb5652
PS
1553 rxpower = ((char)(((*(priv->rxringtail+4)) & (0x00ff0000))>>16))/2 - 42;
1554 RSSI = ((u8)(((*(priv->rxringtail+3)) & (0x0000ff00))>>8)) & (0x7f);
c8d86be3 1555
bbfb5652 1556 rate = ((*(priv->rxringtail)) &
c8d86be3
GKH
1557 ((1<<23)|(1<<22)|(1<<21)|(1<<20)))>>20;
1558
1559 stats.rate = rtl8180_rate2rate(rate);
bbfb5652
PS
1560 Antenna = (((*(priv->rxringtail+3)) & (0x00008000)) == 0) ? 0 : 1;
1561 if (!rtl8180_IsWirelessBMode(stats.rate)) { // OFDM rate.
c8d86be3 1562 RxAGC_dBm = rxpower+1; //bias
bbfb5652
PS
1563 } else { // CCK rate.
1564 RxAGC_dBm = signal; //bit 0 discard
c8d86be3 1565
bbfb5652 1566 LNA = (u8) (RxAGC_dBm & 0x60) >> 5 ; //bit 6~ bit 5
c8d86be3
GKH
1567 BB = (u8) (RxAGC_dBm & 0x1F); // bit 4 ~ bit 0
1568
bbfb5652 1569 RxAGC_dBm = -(LNA_gain[LNA] + (BB*2)); //Pin_11b=-(LNA_gain+BB_gain) (dBm)
c8d86be3 1570
bbfb5652 1571 RxAGC_dBm += 4; //bias
c8d86be3
GKH
1572 }
1573
bbfb5652
PS
1574 if (RxAGC_dBm & 0x80) //absolute value
1575 RXAGC = ~(RxAGC_dBm)+1;
c8d86be3
GKH
1576 bCckRate = rtl8180_IsWirelessBMode(stats.rate);
1577 // Translate RXAGC into 1-100.
bbfb5652
PS
1578 if (!rtl8180_IsWirelessBMode(stats.rate)) { // OFDM rate.
1579 if (RXAGC > 90)
1580 RXAGC = 90;
1581 else if (RXAGC < 25)
1582 RXAGC = 25;
1583 RXAGC = (90-RXAGC)*100/65;
1584 } else { // CCK rate.
1585 if (RXAGC > 95)
1586 RXAGC = 95;
1587 else if (RXAGC < 30)
1588 RXAGC = 30;
1589 RXAGC = (95-RXAGC)*100/65;
c8d86be3
GKH
1590 }
1591 priv->SignalStrength = (u8)RXAGC;
1994130e 1592 priv->RecvSignalPower = RxAGC_dBm;
c8d86be3
GKH
1593 priv->RxPower = rxpower;
1594 priv->RSSI = RSSI;
1994130e 1595 /* SQ translation formula is provided by SD3 DZ. 2006.06.27 */
bbfb5652 1596 if (quality >= 127)
c8d86be3 1597 quality = 1;//0; //0 will cause epc to show signal zero , walk aroud now;
bbfb5652 1598 else if (quality < 27)
c8d86be3
GKH
1599 quality = 100;
1600 else
1601 quality = 127 - quality;
1602 priv->SignalQuality = quality;
c8d86be3
GKH
1603
1604 stats.signal = (u8)quality;//priv->wstats.qual.level = priv->SignalStrength;
1605 stats.signalstrength = RXAGC;
bbfb5652 1606 if (stats.signalstrength > 100)
c8d86be3
GKH
1607 stats.signalstrength = 100;
1608 stats.signalstrength = (stats.signalstrength * 70)/100 + 30;
1609 // printk("==========================>rx : RXAGC is %d,signalstrength is %d\n",RXAGC,stats.signalstrength);
1610 stats.rssi = priv->wstats.qual.qual = priv->SignalQuality;
bbfb5652
PS
1611 stats.noise = priv->wstats.qual.noise = 100 - priv->wstats.qual.qual;
1612 bHwError = (((*(priv->rxringtail)) & (0x00000fff)) == 4080) | (((*(priv->rxringtail)) & (0x04000000)) != 0)
1613 | (((*(priv->rxringtail)) & (0x08000000)) != 0) | (((~(*(priv->rxringtail))) & (0x10000000)) != 0) | (((~(*(priv->rxringtail))) & (0x20000000)) != 0);
c8d86be3
GKH
1614 bCRC = ((*(priv->rxringtail)) & (0x00002000)) >> 13;
1615 bICV = ((*(priv->rxringtail)) & (0x00001000)) >> 12;
0604384d 1616 hdr = (struct ieee80211_hdr_4addr *)priv->rxbuffer->buf;
c8d86be3 1617 fc = le16_to_cpu(hdr->frame_ctl);
cb73da25 1618 type = WLAN_FC_GET_TYPE(fc);
c8d86be3 1619
bbfb5652
PS
1620 if ((IEEE80211_FTYPE_CTL != type) &&
1621 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS) ? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : hdr->addr3))
1622 && (!bHwError) && (!bCRC) && (!bICV)) {
1994130e
LF
1623 /* Perform signal smoothing for dynamic
1624 * mechanism on demand. This is different
1625 * with PerformSignalSmoothing8185 in smoothing
1626 * fomula. No dramatic adjustion is apply
1627 * because dynamic mechanism need some degree
1628 * of correctness. */
bbfb5652 1629 PerformUndecoratedSignalSmoothing8185(priv, bCckRate);
c8d86be3
GKH
1630 //
1631 // For good-looking singal strength.
1632 //
1633 SignalStrengthIndex = NetgearSignalStrengthTranslate(
1634 priv->LastSignalStrengthInPercent,
1635 priv->SignalStrength);
1636
1637 priv->LastSignalStrengthInPercent = SignalStrengthIndex;
1638 priv->Stats_SignalStrength = TranslateToDbm8185((u8)SignalStrengthIndex);
1639 //
1640 // We need more correct power of received packets and the "SignalStrength" of RxStats is beautified,
1641 // so we record the correct power here.
1642 //
bbfb5652
PS
1643 priv->Stats_SignalQuality = (long)(priv->Stats_SignalQuality * 5 + (long)priv->SignalQuality + 5) / 6;
1644 priv->Stats_RecvSignalPower = (long)(priv->Stats_RecvSignalPower * 5 + priv->RecvSignalPower - 1) / 6;
c8d86be3
GKH
1645
1646 // Figure out which antenna that received the lasted packet.
1647 priv->LastRxPktAntenna = Antenna ? 1 : 0; // 0: aux, 1: main.
bbfb5652 1648 SwAntennaDiversityRxOk8185(dev, priv->SignalStrength);
c8d86be3
GKH
1649 }
1650
bbfb5652
PS
1651 if (first) {
1652 if (!priv->rx_skb_complete) {
c8d86be3
GKH
1653 /* seems that HW sometimes fails to reiceve and
1654 doesn't provide the last descriptor */
c8d86be3
GKH
1655 dev_kfree_skb_any(priv->rx_skb);
1656 priv->stats.rxnolast++;
c8d86be3
GKH
1657 }
1658 /* support for prism header has been originally added by Christian */
bbfb5652
PS
1659 if (priv->prism_hdr && priv->ieee80211->iw_mode == IW_MODE_MONITOR) {
1660
1661 } else {
c8d86be3 1662 priv->rx_skb = dev_alloc_skb(len+2);
bbfb5652
PS
1663 if (!priv->rx_skb)
1664 goto drop;
c8d86be3
GKH
1665 }
1666
bbfb5652
PS
1667 priv->rx_skb_complete = 0;
1668 priv->rx_skb->dev = dev;
1669 } else {
c8d86be3
GKH
1670 /* if we are here we should have already RXed
1671 * the first frame.
1672 * If we get here and the skb is not allocated then
1673 * we have just throw out garbage (skb not allocated)
1674 * and we are still rxing garbage....
1675 */
bbfb5652 1676 if (!priv->rx_skb_complete) {
c8d86be3 1677
bbfb5652 1678 tmp_skb = dev_alloc_skb(priv->rx_skb->len+len+2);
c8d86be3 1679
bbfb5652
PS
1680 if (!tmp_skb)
1681 goto drop;
c8d86be3 1682
bbfb5652 1683 tmp_skb->dev = dev;
c8d86be3 1684
bbfb5652 1685 memcpy(skb_put(tmp_skb, priv->rx_skb->len),
c8d86be3
GKH
1686 priv->rx_skb->data,
1687 priv->rx_skb->len);
c8d86be3
GKH
1688
1689 dev_kfree_skb_any(priv->rx_skb);
c8d86be3 1690
bbfb5652 1691 priv->rx_skb = tmp_skb;
c8d86be3
GKH
1692 }
1693 }
ff954853 1694
bbfb5652
PS
1695 if (!priv->rx_skb_complete) {
1696 if (padding) {
1697 memcpy(skb_put(priv->rx_skb, len),
1698 (((unsigned char *)priv->rxbuffer->buf) + 2), len);
c8d86be3 1699 } else {
bbfb5652
PS
1700 memcpy(skb_put(priv->rx_skb, len),
1701 priv->rxbuffer->buf, len);
c8d86be3 1702 }
c8d86be3 1703 }
c8d86be3 1704
bbfb5652
PS
1705 if (last && !priv->rx_skb_complete) {
1706 if (priv->rx_skb->len > 4)
1707 skb_trim(priv->rx_skb, priv->rx_skb->len-4);
1708 if (!ieee80211_rtl_rx(priv->ieee80211,
1994130e 1709 priv->rx_skb, &stats))
c8d86be3 1710 dev_kfree_skb_any(priv->rx_skb);
bbfb5652 1711 priv->rx_skb_complete = 1;
c8d86be3
GKH
1712 }
1713
c8d86be3
GKH
1714 pci_dma_sync_single_for_device(priv->pdev,
1715 priv->rxbuffer->dma,
1716 priv->rxbuffersize * \
1717 sizeof(u8),
1718 PCI_DMA_FROMDEVICE);
1719
bbc9a991 1720drop: // this is used when we have not enough mem
c8d86be3 1721 /* restore the descriptor */
bbfb5652
PS
1722 *(priv->rxringtail+2) = priv->rxbuffer->dma;
1723 *(priv->rxringtail) = *(priv->rxringtail) & ~0xfff;
1724 *(priv->rxringtail) =
c8d86be3
GKH
1725 *(priv->rxringtail) | priv->rxbuffersize;
1726
bbfb5652 1727 *(priv->rxringtail) =
c8d86be3 1728 *(priv->rxringtail) | (1<<31);
c8d86be3 1729
bbfb5652
PS
1730 priv->rxringtail += rx_desc_size;
1731 if (priv->rxringtail >=
1732 (priv->rxring)+(priv->rxringcount)*rx_desc_size)
1733 priv->rxringtail = priv->rxring;
c8d86be3 1734
bbfb5652 1735 priv->rxbuffer = (priv->rxbuffer->next);
c8d86be3 1736 }
c8d86be3
GKH
1737}
1738
1739
1740void rtl8180_dma_kick(struct net_device *dev, int priority)
1741{
1742 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1743
bbfb5652 1744 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
c8d86be3
GKH
1745 write_nic_byte(dev, TX_DMA_POLLING,
1746 (1 << (priority + 1)) | priv->dma_poll_mask);
bbfb5652 1747 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH
1748
1749 force_pci_posting(dev);
1750}
1751
c8d86be3
GKH
1752void rtl8180_data_hard_stop(struct net_device *dev)
1753{
1754 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1755
bbfb5652 1756 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
c8d86be3 1757 priv->dma_poll_stop_mask |= TPPOLLSTOP_AC_VIQ;
bbfb5652
PS
1758 write_nic_byte(dev, TPPollStop, priv->dma_poll_stop_mask);
1759 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH
1760}
1761
c8d86be3
GKH
1762void rtl8180_data_hard_resume(struct net_device *dev)
1763{
1764 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1765
bbfb5652 1766 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
c8d86be3 1767 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_AC_VIQ);
bbfb5652
PS
1768 write_nic_byte(dev, TPPollStop, priv->dma_poll_stop_mask);
1769 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH
1770}
1771
c8d86be3
GKH
1772/* this function TX data frames when the ieee80211 stack requires this.
1773 * It checks also if we need to stop the ieee tx queue, eventually do it
1774 */
bbfb5652
PS
1775void rtl8180_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, int
1776rate) {
c8d86be3
GKH
1777 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1778 int mode;
bbfb5652 1779 struct ieee80211_hdr_3addr *h = (struct ieee80211_hdr_3addr *) skb->data;
b6b1ac69 1780 short morefrag = (h->frame_control) & IEEE80211_FCTL_MOREFRAGS;
c8d86be3
GKH
1781 unsigned long flags;
1782 int priority;
c8d86be3
GKH
1783
1784 mode = priv->ieee80211->iw_mode;
1785
1786 rate = ieeerate2rtlrate(rate);
1787 /*
1788 * This function doesn't require lock because we make
1789 * sure it's called with the tx_lock already acquired.
bbc9a991
AGR
1790 * this come from the kernel's hard_xmit callback (through
1791 * the ieee stack, or from the try_wake_queue (again through
c8d86be3
GKH
1792 * the ieee stack.
1793 */
c8d86be3 1794 priority = AC2Q(skb->priority);
bbfb5652 1795 spin_lock_irqsave(&priv->tx_lock, flags);
c8d86be3 1796
bbfb5652
PS
1797 if (priv->ieee80211->bHwRadioOff) {
1798 spin_unlock_irqrestore(&priv->tx_lock, flags);
c8d86be3
GKH
1799
1800 return;
1801 }
1802
bbfb5652 1803 if (!check_nic_enought_desc(dev, priority)) {
c8d86be3
GKH
1804 DMESGW("Error: no descriptor left by previous TX (avail %d) ",
1805 get_curr_tx_free_desc(dev, priority));
df574b8e 1806 ieee80211_rtl_stop_queue(priv->ieee80211);
c8d86be3 1807 }
bbfb5652 1808 rtl8180_tx(dev, skb->data, skb->len, priority, morefrag, 0, rate);
c8d86be3 1809 if (!check_nic_enought_desc(dev, priority))
df574b8e 1810 ieee80211_rtl_stop_queue(priv->ieee80211);
c8d86be3 1811
bbfb5652 1812 spin_unlock_irqrestore(&priv->tx_lock, flags);
c8d86be3
GKH
1813}
1814
1815/* This is a rough attempt to TX a frame
1816 * This is called by the ieee 80211 stack to TX management frames.
1817 * If the ring is full packet are dropped (for data frame the queue
1818 * is stopped before this can happen). For this reason it is better
1819 * if the descriptors are larger than the largest management frame
1820 * we intend to TX: i'm unsure what the HW does if it will not found
1821 * the last fragment of a frame because it has been dropped...
1822 * Since queues for Management and Data frames are different we
1823 * might use a different lock than tx_lock (for example mgmt_tx_lock)
1824 */
1825/* these function may loops if invoked with 0 descriptors or 0 len buffer*/
bbfb5652 1826int rtl8180_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
c8d86be3
GKH
1827{
1828 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3 1829 unsigned long flags;
c8d86be3
GKH
1830 int priority;
1831
c8d86be3 1832 priority = MANAGE_PRIORITY;
c8d86be3 1833
bbfb5652 1834 spin_lock_irqsave(&priv->tx_lock, flags);
c8d86be3 1835
fd882783 1836 if (priv->ieee80211->bHwRadioOff) {
bbfb5652 1837 spin_unlock_irqrestore(&priv->tx_lock, flags);
c8d86be3 1838 dev_kfree_skb_any(skb);
ec634fe3 1839 return NETDEV_TX_OK;
c8d86be3
GKH
1840 }
1841
1842 rtl8180_tx(dev, skb->data, skb->len, priority,
bbfb5652 1843 0, 0, ieeerate2rtlrate(priv->ieee80211->basic_rate));
c8d86be3 1844
bbfb5652 1845 priv->ieee80211->stats.tx_bytes += skb->len;
c8d86be3 1846 priv->ieee80211->stats.tx_packets++;
bbfb5652 1847 spin_unlock_irqrestore(&priv->tx_lock, flags);
c8d86be3
GKH
1848
1849 dev_kfree_skb_any(skb);
ec634fe3 1850 return NETDEV_TX_OK;
c8d86be3
GKH
1851}
1852
1853// longpre 144+48 shortpre 72+24
bbfb5652 1854u16 rtl8180_len2duration(u32 len, short rate, short *ext)
c8d86be3
GKH
1855{
1856 u16 duration;
1857 u16 drift;
bbfb5652 1858 *ext = 0;
c8d86be3 1859
bbfb5652 1860 switch (rate) {
c8d86be3 1861 case 0://1mbps
bbfb5652
PS
1862 *ext = 0;
1863 duration = ((len+4)<<4) / 0x2;
c8d86be3 1864 drift = ((len+4)<<4) % 0x2;
bbfb5652
PS
1865 if (drift == 0)
1866 break;
c8d86be3
GKH
1867 duration++;
1868 break;
c8d86be3 1869 case 1://2mbps
bbfb5652
PS
1870 *ext = 0;
1871 duration = ((len+4)<<4) / 0x4;
c8d86be3 1872 drift = ((len+4)<<4) % 0x4;
bbfb5652
PS
1873 if (drift == 0)
1874 break;
c8d86be3
GKH
1875 duration++;
1876 break;
c8d86be3 1877 case 2: //5.5mbps
bbfb5652
PS
1878 *ext = 0;
1879 duration = ((len+4)<<4) / 0xb;
c8d86be3 1880 drift = ((len+4)<<4) % 0xb;
bbfb5652 1881 if (drift == 0)
c8d86be3
GKH
1882 break;
1883 duration++;
1884 break;
c8d86be3
GKH
1885 default:
1886 case 3://11mbps
bbfb5652
PS
1887 *ext = 0;
1888 duration = ((len+4)<<4) / 0x16;
c8d86be3 1889 drift = ((len+4)<<4) % 0x16;
bbfb5652 1890 if (drift == 0)
c8d86be3
GKH
1891 break;
1892 duration++;
bbfb5652 1893 if (drift > 6)
c8d86be3 1894 break;
bbfb5652 1895 *ext = 1;
c8d86be3
GKH
1896 break;
1897 }
1898
1899 return duration;
1900}
1901
c8d86be3
GKH
1902void rtl8180_prepare_beacon(struct net_device *dev)
1903{
c8d86be3 1904 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH
1905 struct sk_buff *skb;
1906
1907 u16 word = read_nic_word(dev, BcnItv);
1908 word &= ~BcnItv_BcnItv; // clear Bcn_Itv
bbfb5652 1909 word |= cpu_to_le16(priv->ieee80211->current_network.beacon_interval); //0x64;
c8d86be3
GKH
1910 write_nic_word(dev, BcnItv, word);
1911
c8d86be3 1912 skb = ieee80211_get_beacon(priv->ieee80211);
bbfb5652
PS
1913 if (skb) {
1914 rtl8180_tx(dev, skb->data, skb->len, BEACON_PRIORITY,
1915 0, 0, ieeerate2rtlrate(priv->ieee80211->basic_rate));
c8d86be3
GKH
1916 dev_kfree_skb_any(skb);
1917 }
c8d86be3
GKH
1918}
1919
1920/* This function do the real dirty work: it enqueues a TX command
1921 * descriptor in the ring buffer, copyes the frame in a TX buffer
1922 * and kicks the NIC to ensure it does the DMA transfer.
1923 */
1924short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority,
1925 short morefrag, short descfrag, int rate)
1926{
1927 struct r8180_priv *priv = ieee80211_priv(dev);
bbfb5652 1928 u32 *tail, *temp_tail;
c8d86be3
GKH
1929 u32 *begin;
1930 u32 *buf;
1931 int i;
1932 int remain;
1933 int buflen;
1934 int count;
c8d86be3
GKH
1935 u16 duration;
1936 short ext;
bbfb5652 1937 struct buffer *buflist;
c8d86be3
GKH
1938 struct ieee80211_hdr_3addr *frag_hdr = (struct ieee80211_hdr_3addr *)txbuf;
1939 u8 dest[ETH_ALEN];
1940 u8 bUseShortPreamble = 0;
1941 u8 bCTSEnable = 0;
1942 u8 bRTSEnable = 0;
cb73da25 1943 u16 Duration = 0;
c8d86be3
GKH
1944 u16 RtsDur = 0;
1945 u16 ThisFrameTime = 0;
1946 u16 TxDescDuration = 0;
cb73da25 1947 u8 ownbit_flag = false;
c8d86be3 1948
bbfb5652 1949 switch (priority) {
c8d86be3 1950 case MANAGE_PRIORITY:
bbfb5652
PS
1951 tail = priv->txmapringtail;
1952 begin = priv->txmapring;
c8d86be3
GKH
1953 buflist = priv->txmapbufstail;
1954 count = priv->txringcount;
1955 break;
c8d86be3 1956 case BK_PRIORITY:
bbfb5652
PS
1957 tail = priv->txbkpringtail;
1958 begin = priv->txbkpring;
c8d86be3
GKH
1959 buflist = priv->txbkpbufstail;
1960 count = priv->txringcount;
1961 break;
c8d86be3 1962 case BE_PRIORITY:
bbfb5652
PS
1963 tail = priv->txbepringtail;
1964 begin = priv->txbepring;
c8d86be3
GKH
1965 buflist = priv->txbepbufstail;
1966 count = priv->txringcount;
1967 break;
c8d86be3 1968 case VI_PRIORITY:
bbfb5652
PS
1969 tail = priv->txvipringtail;
1970 begin = priv->txvipring;
c8d86be3
GKH
1971 buflist = priv->txvipbufstail;
1972 count = priv->txringcount;
1973 break;
c8d86be3 1974 case VO_PRIORITY:
bbfb5652
PS
1975 tail = priv->txvopringtail;
1976 begin = priv->txvopring;
c8d86be3
GKH
1977 buflist = priv->txvopbufstail;
1978 count = priv->txringcount;
1979 break;
c8d86be3 1980 case HI_PRIORITY:
bbfb5652
PS
1981 tail = priv->txhpringtail;
1982 begin = priv->txhpring;
c8d86be3
GKH
1983 buflist = priv->txhpbufstail;
1984 count = priv->txringcount;
1985 break;
c8d86be3 1986 case BEACON_PRIORITY:
bbfb5652
PS
1987 tail = priv->txbeaconringtail;
1988 begin = priv->txbeaconring;
c8d86be3
GKH
1989 buflist = priv->txbeaconbufstail;
1990 count = priv->txbeaconcount;
1991 break;
c8d86be3
GKH
1992 default:
1993 return -1;
1994 break;
cb73da25 1995 }
c8d86be3 1996
c8d86be3
GKH
1997 memcpy(&dest, frag_hdr->addr1, ETH_ALEN);
1998 if (is_multicast_ether_addr(dest) ||
bbfb5652 1999 is_broadcast_ether_addr(dest)) {
c8d86be3
GKH
2000 Duration = 0;
2001 RtsDur = 0;
2002 bRTSEnable = 0;
2003 bCTSEnable = 0;
2004
2005 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2006 TxDescDuration = ThisFrameTime;
2007 } else {// Unicast packet
c8d86be3
GKH
2008 u16 AckTime;
2009
2010 //YJ,add,080828,for Keep alive
2011 priv->NumTxUnicast++;
2012
1994130e
LF
2013 /* Figure out ACK rate according to BSS basic rate
2014 * and Tx rate. */
bbfb5652 2015 AckTime = ComputeTxTime(14, 10, 0, 0); // AckCTSLng = 14 use 1M bps send
c8d86be3 2016
bbfb5652 2017 if (((len + sCrcLng) > priv->rts) && priv->rts) { // RTS/CTS.
c8d86be3
GKH
2018 u16 RtsTime, CtsTime;
2019 //u16 CtsRate;
2020 bRTSEnable = 1;
2021 bCTSEnable = 0;
2022
2023 // Rate and time required for RTS.
bbfb5652 2024 RtsTime = ComputeTxTime(sAckCtsLng/8, priv->ieee80211->basic_rate, 0, 0);
c8d86be3 2025 // Rate and time required for CTS.
bbfb5652 2026 CtsTime = ComputeTxTime(14, 10, 0, 0); // AckCTSLng = 14 use 1M bps send
c8d86be3
GKH
2027
2028 // Figure out time required to transmit this frame.
2029 ThisFrameTime = ComputeTxTime(len + sCrcLng,
2030 rtl8180_rate2rate(rate),
2031 0,
2032 bUseShortPreamble);
2033
2034 // RTS-CTS-ThisFrame-ACK.
2035 RtsDur = CtsTime + ThisFrameTime + AckTime + 3*aSifsTime;
2036
2037 TxDescDuration = RtsTime + RtsDur;
bbfb5652 2038 } else {// Normal case.
c8d86be3
GKH
2039 bCTSEnable = 0;
2040 bRTSEnable = 0;
2041 RtsDur = 0;
2042
2043 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2044 TxDescDuration = ThisFrameTime + aSifsTime + AckTime;
2045 }
2046
b6b1ac69 2047 if (!(frag_hdr->frame_control & IEEE80211_FCTL_MOREFRAGS)) {
c8d86be3
GKH
2048 // ThisFrame-ACK.
2049 Duration = aSifsTime + AckTime;
2050 } else { // One or more fragments remained.
2051 u16 NextFragTime;
bbfb5652 2052 NextFragTime = ComputeTxTime(len + sCrcLng, //pretend following packet length equal current packet
c8d86be3
GKH
2053 rtl8180_rate2rate(rate),
2054 0,
bbfb5652 2055 bUseShortPreamble);
c8d86be3
GKH
2056
2057 //ThisFrag-ACk-NextFrag-ACK.
2058 Duration = NextFragTime + 3*aSifsTime + 2*AckTime;
2059 }
2060
2061 } // End of Unicast packet
2062
2063 frag_hdr->duration_id = Duration;
c8d86be3 2064
bbfb5652
PS
2065 buflen = priv->txbuffsize;
2066 remain = len;
c8d86be3 2067 temp_tail = tail;
fd882783 2068
bbfb5652 2069 while (remain != 0) {
c8d86be3 2070 mb();
bbfb5652 2071 if (!buflist) {
c8d86be3 2072 DMESGE("TX buffer error, cannot TX frames. pri %d.", priority);
c8d86be3
GKH
2073 return -1;
2074 }
bbfb5652 2075 buf = buflist->buf;
c8d86be3 2076
fd882783
BZ
2077 if ((*tail & (1 << 31)) && (priority != BEACON_PRIORITY)) {
2078 DMESGW("No more TX desc, returning %x of %x",
2079 remain, len);
2080 priv->stats.txrdu++;
c8d86be3 2081 return remain;
c8d86be3
GKH
2082 }
2083
bbfb5652 2084 *tail = 0; // zeroes header
c8d86be3
GKH
2085 *(tail+1) = 0;
2086 *(tail+3) = 0;
2087 *(tail+5) = 0;
2088 *(tail+6) = 0;
2089 *(tail+7) = 0;
2090
d44eb889
LF
2091 /*FIXME: this should be triggered by HW encryption parameters.*/
2092 *tail |= (1<<15); /* no encrypt */
fd882783 2093
bbfb5652 2094 if (remain == len && !descfrag) {
1994130e 2095 ownbit_flag = false;
bbfb5652
PS
2096 *tail = *tail | (1<<29) ; //fist segment of the packet
2097 *tail = *tail | (len);
c8d86be3
GKH
2098 } else {
2099 ownbit_flag = true;
2100 }
2101
bbfb5652
PS
2102 for (i = 0; i < buflen && remain > 0; i++, remain--) {
2103 ((u8 *)buf)[i] = txbuf[i]; //copy data into descriptor pointed DMAble buffer
2104 if (remain == 4 && i+4 >= buflen)
2105 break;
c8d86be3
GKH
2106 /* ensure the last desc has at least 4 bytes payload */
2107
2108 }
2109 txbuf = txbuf + i;
bbfb5652
PS
2110 *(tail+3) = *(tail+3) & ~0xfff;
2111 *(tail+3) = *(tail+3) | i; // buffer lenght
c8d86be3
GKH
2112 // Use short preamble or not
2113 if (priv->ieee80211->current_network.capability&WLAN_CAPABILITY_SHORT_PREAMBLE)
bbfb5652 2114 if (priv->plcp_preamble_mode == 1 && rate != 0) // short mode now, not long!
b3184e1e 2115 ;// *tail |= (1<<16); // enable short preamble mode.
c8d86be3 2116
bbfb5652 2117 if (bCTSEnable)
c8d86be3 2118 *tail |= (1<<18);
c8d86be3 2119
bbfb5652 2120 if (bRTSEnable) { //rts enable
c8d86be3
GKH
2121 *tail |= ((ieeerate2rtlrate(priv->ieee80211->basic_rate))<<19);//RTS RATE
2122 *tail |= (1<<23);//rts enable
bbfb5652 2123 *(tail+1) |= (RtsDur&0xffff);//RTS Duration
c8d86be3
GKH
2124 }
2125 *(tail+3) |= ((TxDescDuration&0xffff)<<16); //DURATION
2126// *(tail+3) |= (0xe6<<16);
bbfb5652 2127 *(tail+5) |= (11<<8);//(priv->retry_data<<8); //retry lim ;
c8d86be3
GKH
2128
2129 *tail = *tail | ((rate&0xf) << 24);
c8d86be3
GKH
2130
2131 /* hw_plcp_len is not used for rtl8180 chip */
2132 /* FIXME */
d44eb889 2133 if (!priv->hw_plcp_len) {
fd882783 2134 duration = rtl8180_len2duration(len, rate, &ext);
c8d86be3 2135 *(tail+1) = *(tail+1) | ((duration & 0x7fff)<<16);
bbfb5652
PS
2136 if (ext)
2137 *(tail+1) = *(tail+1) | (1<<31); //plcp length extension
c8d86be3
GKH
2138 }
2139
bbfb5652
PS
2140 if (morefrag)
2141 *tail = (*tail) | (1<<17); // more fragment
2142 if (!remain)
2143 *tail = (*tail) | (1<<28); // last segment of frame
c8d86be3 2144
cb73da25
JC
2145 *(tail+5) = *(tail+5)|(2<<27);
2146 *(tail+7) = *(tail+7)|(1<<4);
c8d86be3
GKH
2147
2148 wmb();
bbfb5652 2149 if (ownbit_flag)
c8d86be3 2150 *tail = *tail | (1<<31); // descriptor ready to be txed
c8d86be3 2151
bbfb5652
PS
2152 if ((tail - begin)/8 == count-1)
2153 tail = begin;
c8d86be3 2154 else
bbfb5652 2155 tail = tail+8;
c8d86be3 2156
bbfb5652 2157 buflist = buflist->next;
c8d86be3
GKH
2158
2159 mb();
2160
bbfb5652
PS
2161 switch (priority) {
2162 case MANAGE_PRIORITY:
2163 priv->txmapringtail = tail;
2164 priv->txmapbufstail = buflist;
2165 break;
2166 case BK_PRIORITY:
2167 priv->txbkpringtail = tail;
2168 priv->txbkpbufstail = buflist;
2169 break;
2170 case BE_PRIORITY:
2171 priv->txbepringtail = tail;
2172 priv->txbepbufstail = buflist;
2173 break;
2174 case VI_PRIORITY:
2175 priv->txvipringtail = tail;
2176 priv->txvipbufstail = buflist;
2177 break;
2178 case VO_PRIORITY:
2179 priv->txvopringtail = tail;
2180 priv->txvopbufstail = buflist;
2181 break;
2182 case HI_PRIORITY:
2183 priv->txhpringtail = tail;
2184 priv->txhpbufstail = buflist;
2185 break;
2186 case BEACON_PRIORITY:
2187 /* the HW seems to be happy with the 1st
2188 * descriptor filled and the 2nd empty...
2189 * So always update descriptor 1 and never
2190 * touch 2nd
2191 */
2192 break;
c8d86be3 2193 }
c8d86be3
GKH
2194 }
2195 *temp_tail = *temp_tail | (1<<31); // descriptor ready to be txed
bbfb5652 2196 rtl8180_dma_kick(dev, priority);
c8d86be3
GKH
2197
2198 return 0;
c8d86be3
GKH
2199}
2200
bbfb5652 2201void rtl8180_irq_rx_tasklet(struct r8180_priv *priv);
c8d86be3 2202
c8d86be3
GKH
2203void rtl8180_link_change(struct net_device *dev)
2204{
2205 struct r8180_priv *priv = ieee80211_priv(dev);
2206 u16 beacon_interval;
c8d86be3 2207 struct ieee80211_network *net = &priv->ieee80211->current_network;
c8d86be3 2208
fd882783 2209 rtl8180_update_msr(dev);
c8d86be3 2210
bbfb5652 2211 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
c8d86be3 2212
bbfb5652
PS
2213 write_nic_dword(dev, BSSID, ((u32 *)net->bssid)[0]);
2214 write_nic_word(dev, BSSID+4, ((u16 *)net->bssid)[2]);
c8d86be3 2215
bbfb5652
PS
2216 beacon_interval = read_nic_dword(dev, BEACON_INTERVAL);
2217 beacon_interval &= ~BEACON_INTERVAL_MASK;
c8d86be3
GKH
2218 beacon_interval |= net->beacon_interval;
2219 write_nic_dword(dev, BEACON_INTERVAL, beacon_interval);
2220
2221 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
2222
d44eb889 2223 rtl8180_set_chan(dev, priv->chan);
c8d86be3
GKH
2224}
2225
bbfb5652
PS
2226void rtl8180_rq_tx_ack(struct net_device *dev)
2227{
c8d86be3
GKH
2228
2229 struct r8180_priv *priv = ieee80211_priv(dev);
fd882783 2230
bbfb5652 2231 write_nic_byte(dev, CONFIG4, read_nic_byte(dev, CONFIG4) | CONFIG4_PWRMGT);
c8d86be3
GKH
2232 priv->ack_tx_to_ieee = 1;
2233}
2234
bbfb5652
PS
2235short rtl8180_is_tx_queue_empty(struct net_device *dev)
2236{
c8d86be3
GKH
2237
2238 struct r8180_priv *priv = ieee80211_priv(dev);
bbfb5652 2239 u32 *d;
c8d86be3
GKH
2240
2241 for (d = priv->txmapring;
bbfb5652
PS
2242 d < priv->txmapring + priv->txringcount; d += 8)
2243 if (*d & (1<<31))
2244 return 0;
c8d86be3
GKH
2245
2246 for (d = priv->txbkpring;
bbfb5652
PS
2247 d < priv->txbkpring + priv->txringcount; d += 8)
2248 if (*d & (1<<31))
2249 return 0;
c8d86be3
GKH
2250
2251 for (d = priv->txbepring;
bbfb5652
PS
2252 d < priv->txbepring + priv->txringcount; d += 8)
2253 if (*d & (1<<31))
2254 return 0;
c8d86be3
GKH
2255
2256 for (d = priv->txvipring;
bbfb5652
PS
2257 d < priv->txvipring + priv->txringcount; d += 8)
2258 if (*d & (1<<31))
2259 return 0;
c8d86be3
GKH
2260
2261 for (d = priv->txvopring;
bbfb5652
PS
2262 d < priv->txvopring + priv->txringcount; d += 8)
2263 if (*d & (1<<31))
2264 return 0;
c8d86be3
GKH
2265
2266 for (d = priv->txhpring;
bbfb5652
PS
2267 d < priv->txhpring + priv->txringcount; d += 8)
2268 if (*d & (1<<31))
2269 return 0;
c8d86be3
GKH
2270 return 1;
2271}
2272/* FIXME FIXME 5msecs is random */
2273#define HW_WAKE_DELAY 5
2274
2275void rtl8180_hw_wakeup(struct net_device *dev)
2276{
2277 unsigned long flags;
c8d86be3
GKH
2278 struct r8180_priv *priv = ieee80211_priv(dev);
2279
bbfb5652
PS
2280 spin_lock_irqsave(&priv->ps_lock, flags);
2281 write_nic_byte(dev, CONFIG4, read_nic_byte(dev, CONFIG4) & ~CONFIG4_PWRMGT);
fd882783 2282 if (priv->rf_wakeup)
c8d86be3 2283 priv->rf_wakeup(dev);
bbfb5652 2284 spin_unlock_irqrestore(&priv->ps_lock, flags);
c8d86be3
GKH
2285}
2286
2287void rtl8180_hw_sleep_down(struct net_device *dev)
2288{
cb73da25
JC
2289 unsigned long flags;
2290 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3 2291
cb73da25
JC
2292 spin_lock_irqsave(&priv->ps_lock, flags);
2293 if (priv->rf_sleep)
2294 priv->rf_sleep(dev);
2295 spin_unlock_irqrestore(&priv->ps_lock, flags);
c8d86be3
GKH
2296}
2297
c8d86be3
GKH
2298void rtl8180_hw_sleep(struct net_device *dev, u32 th, u32 tl)
2299{
c8d86be3 2300 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH
2301 u32 rb = jiffies;
2302 unsigned long flags;
2303
bbfb5652 2304 spin_lock_irqsave(&priv->ps_lock, flags);
c8d86be3
GKH
2305
2306 /* Writing HW register with 0 equals to disable
2307 * the timer, that is not really what we want
2308 */
2309 tl -= MSECS(4+16+7);
2310
c8d86be3
GKH
2311 /* If the interval in witch we are requested to sleep is too
2312 * short then give up and remain awake
2313 */
bbfb5652
PS
2314 if (((tl >= rb) && (tl-rb) <= MSECS(MIN_SLEEP_TIME))
2315 || ((rb > tl) && (rb-tl) < MSECS(MIN_SLEEP_TIME))) {
2316 spin_unlock_irqrestore(&priv->ps_lock, flags);
c8d86be3
GKH
2317 printk("too short to sleep\n");
2318 return;
2319 }
2320
c8d86be3 2321 {
bbfb5652 2322 u32 tmp = (tl > rb) ? (tl-rb) : (rb-tl);
c8d86be3 2323
c8d86be3
GKH
2324 priv->DozePeriodInPast2Sec += jiffies_to_msecs(tmp);
2325
2326 queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb
2327 }
2328 /* if we suspect the TimerInt is gone beyond tl
2329 * while setting it, then give up
2330 */
fd882783 2331
bbfb5652 2332 if (((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME))) ||
c8d86be3 2333 ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) {
bbfb5652 2334 spin_unlock_irqrestore(&priv->ps_lock, flags);
c8d86be3
GKH
2335 return;
2336 }
c8d86be3
GKH
2337
2338 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq);
bbfb5652 2339 spin_unlock_irqrestore(&priv->ps_lock, flags);
c8d86be3
GKH
2340}
2341
bbfb5652 2342void rtl8180_wmm_param_update(struct work_struct *work)
c8d86be3 2343{
bbfb5652 2344 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, wmm_param_update_wq);
c8d86be3 2345 struct net_device *dev = ieee->dev;
c8d86be3
GKH
2346 u8 *ac_param = (u8 *)(ieee->current_network.wmm_param);
2347 u8 mode = ieee->current_network.mode;
2348 AC_CODING eACI;
2349 AC_PARAM AcParam;
2350 PAC_PARAM pAcParam;
2351 u8 i;
2352
bbfb5652 2353 if (!ieee->current_network.QoS_Enable) {
c8d86be3
GKH
2354 //legacy ac_xx_param update
2355 AcParam.longData = 0;
2356 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2357 AcParam.f.AciAifsn.f.ACM = 0;
2358 AcParam.f.Ecw.f.ECWmin = 3; // Follow 802.11 CWmin.
2359 AcParam.f.Ecw.f.ECWmax = 7; // Follow 802.11 CWmax.
2360 AcParam.f.TXOPLimit = 0;
bbfb5652 2361 for (eACI = 0; eACI < AC_MAX; eACI++) {
c8d86be3
GKH
2362 AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2363 {
2364 u8 u1bAIFS;
2365 u32 u4bAcParam;
2366 pAcParam = (PAC_PARAM)(&AcParam);
2367 // Retrive paramters to udpate.
bbfb5652 2368 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G) ? 9 : 20) + aSifsTime;
c8d86be3
GKH
2369 u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit))<<AC_PARAM_TXOP_LIMIT_OFFSET)|
2370 (((u32)(pAcParam->f.Ecw.f.ECWmax))<<AC_PARAM_ECW_MAX_OFFSET)|
2371 (((u32)(pAcParam->f.Ecw.f.ECWmin))<<AC_PARAM_ECW_MIN_OFFSET)|
2372 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
bbfb5652
PS
2373 switch (eACI) {
2374 case AC1_BK:
2375 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2376 break;
2377 case AC0_BE:
2378 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2379 break;
2380 case AC2_VI:
2381 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2382 break;
2383 case AC3_VO:
2384 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2385 break;
2386 default:
2387 printk(KERN_WARNING "SetHwReg8185():invalid ACI: %d!\n", eACI);
2388 break;
c8d86be3
GKH
2389 }
2390 }
2391 }
2392 return;
2393 }
2394
bbfb5652 2395 for (i = 0; i < AC_MAX; i++) {
c8d86be3 2396 //AcParam.longData = 0;
bbfb5652 2397 pAcParam = (AC_PARAM *)ac_param;
c8d86be3
GKH
2398 {
2399 AC_CODING eACI;
2400 u8 u1bAIFS;
2401 u32 u4bAcParam;
2402
2403 // Retrive paramters to udpate.
2404 eACI = pAcParam->f.AciAifsn.f.ACI;
2405 //Mode G/A: slotTimeTimer = 9; Mode B: 20
bbfb5652
PS
2406 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G) ? 9 : 20) + aSifsTime;
2407 u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) |
c8d86be3
GKH
2408 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) |
2409 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) |
2410 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2411
bbfb5652
PS
2412 switch (eACI) {
2413 case AC1_BK:
2414 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2415 break;
2416 case AC0_BE:
2417 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2418 break;
2419 case AC2_VI:
2420 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2421 break;
2422 case AC3_VO:
2423 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2424 break;
2425 default:
2426 printk(KERN_WARNING "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2427 break;
c8d86be3
GKH
2428 }
2429 }
2430 ac_param += (sizeof(AC_PARAM));
2431 }
c8d86be3
GKH
2432}
2433
c8d86be3 2434void rtl8180_tx_irq_wq(struct work_struct *work);
c8d86be3
GKH
2435void rtl8180_restart_wq(struct work_struct *work);
2436//void rtl8180_rq_tx_ack(struct work_struct *work);
c8d86be3 2437void rtl8180_watch_dog_wq(struct work_struct *work);
c8d86be3 2438void rtl8180_hw_wakeup_wq(struct work_struct *work);
c8d86be3 2439void rtl8180_hw_sleep_wq(struct work_struct *work);
c8d86be3 2440void rtl8180_sw_antenna_wq(struct work_struct *work);
0370453f
BZ
2441void rtl8180_watch_dog(struct net_device *dev);
2442
c8d86be3
GKH
2443void watch_dog_adaptive(unsigned long data)
2444{
fd882783
BZ
2445 struct r8180_priv* priv = ieee80211_priv((struct net_device *)data);
2446
2447 if (!priv->up) {
c8d86be3
GKH
2448 DMESG("<----watch_dog_adaptive():driver is not up!\n");
2449 return;
2450 }
2451
c8d86be3 2452 // Tx High Power Mechanism.
bbfb5652 2453 if (CheckHighPower((struct net_device *)data))
c8d86be3 2454 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->tx_pw_wq);
c8d86be3 2455
c8d86be3 2456 // Tx Power Tracking on 87SE.
cffd4e16 2457 if (CheckTxPwrTracking((struct net_device *)data))
c8d86be3 2458 TxPwrTracking87SE((struct net_device *)data);
c8d86be3
GKH
2459
2460 // Perform DIG immediately.
bbfb5652 2461 if (CheckDig((struct net_device *)data) == true)
c8d86be3 2462 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_dig_wq);
bbfb5652 2463 rtl8180_watch_dog((struct net_device *)data);
c8d86be3 2464
c8d86be3
GKH
2465 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->GPIOChangeRFWorkItem);
2466
bbfb5652 2467 priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME);
c8d86be3 2468 add_timer(&priv->watch_dog_timer);
c8d86be3
GKH
2469}
2470
c8d86be3 2471static CHANNEL_LIST ChannelPlan[] = {
bbfb5652
PS
2472 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, //FCC
2473 {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
2474 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
2475 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Spain. Change to ETSI.
2476 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //France. Change to ETSI.
2477 {{14,36,40,44,48,52,56,60,64},9}, //MKK
c8d86be3
GKH
2478 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14, 36,40,44,48,52,56,60,64},22},//MKK1
2479 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Israel.
bbfb5652 2480 {{1,2,3,4,5,6,7,8,9,10,11,12,13,34,38,42,46},17}, // For 11a , TELEC
c8d86be3
GKH
2481 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626
2482 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13} //world wide 13: ch1~ch11 active scan, ch12~13 passive //lzm add 080826
2483};
2484
2485static void rtl8180_set_channel_map(u8 channel_plan, struct ieee80211_device *ieee)
2486{
2487 int i;
2488
2489 //lzm add 080826
bbfb5652
PS
2490 ieee->MinPassiveChnlNum = MAX_CHANNEL_NUMBER+1;
2491 ieee->IbssStartChnl = 0;
2492
2493 switch (channel_plan) {
2494 case COUNTRY_CODE_FCC:
2495 case COUNTRY_CODE_IC:
2496 case COUNTRY_CODE_ETSI:
2497 case COUNTRY_CODE_SPAIN:
2498 case COUNTRY_CODE_FRANCE:
2499 case COUNTRY_CODE_MKK:
2500 case COUNTRY_CODE_MKK1:
2501 case COUNTRY_CODE_ISRAEL:
2502 case COUNTRY_CODE_TELEC:
c8d86be3
GKH
2503 {
2504 Dot11d_Init(ieee);
2505 ieee->bGlobalDomain = false;
bbfb5652 2506 if (ChannelPlan[channel_plan].Len != 0) {
c8d86be3
GKH
2507 // Clear old channel map
2508 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
2509 // Set new channel map
bbfb5652
PS
2510 for (i = 0; i < ChannelPlan[channel_plan].Len; i++) {
2511 if (ChannelPlan[channel_plan].Channel[i] <= 14)
c8d86be3
GKH
2512 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1;
2513 }
2514 }
2515 break;
2516 }
bbfb5652 2517 case COUNTRY_CODE_GLOBAL_DOMAIN:
c8d86be3
GKH
2518 {
2519 GET_DOT11D_INFO(ieee)->bEnabled = 0;
2520 Dot11d_Reset(ieee);
2521 ieee->bGlobalDomain = true;
2522 break;
2523 }
bbfb5652 2524 case COUNTRY_CODE_WORLD_WIDE_13_INDEX://lzm add 080826
c8d86be3 2525 {
bbfb5652
PS
2526 ieee->MinPassiveChnlNum = 12;
2527 ieee->IbssStartChnl = 10;
2528 break;
c8d86be3 2529 }
bbfb5652 2530 default:
c8d86be3
GKH
2531 {
2532 Dot11d_Init(ieee);
2533 ieee->bGlobalDomain = false;
2534 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
bbfb5652 2535 for (i = 1; i <= 14; i++)
c8d86be3 2536 GET_DOT11D_INFO(ieee)->channel_map[i] = 1;
c8d86be3
GKH
2537 break;
2538 }
2539 }
2540}
c8d86be3 2541
c8d86be3 2542void GPIOChangeRFWorkItemCallBack(struct work_struct *work);
c8d86be3
GKH
2543
2544//YJ,add,080828
2545static void rtl8180_statistics_init(struct Stats *pstats)
2546{
2547 memset(pstats, 0, sizeof(struct Stats));
2548}
fd882783 2549
c8d86be3
GKH
2550static void rtl8180_link_detect_init(plink_detect_t plink_detect)
2551{
2552 memset(plink_detect, 0, sizeof(link_detect_t));
2553 plink_detect->SlotNum = DEFAULT_SLOT_NUM;
2554}
2555//YJ,add,080828,end
2556
742821ce
LF
2557static void rtl8187se_eeprom_register_read(struct eeprom_93cx6 *eeprom)
2558{
2559 struct net_device *dev = eeprom->data;
2560 u8 reg = read_nic_byte(dev, EPROM_CMD);
2561
2562 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
2563 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
2564 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
2565 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
2566}
2567
2568static void rtl8187se_eeprom_register_write(struct eeprom_93cx6 *eeprom)
2569{
2570 struct net_device *dev = eeprom->data;
2571 u8 reg = 2 << 6;
2572
2573 if (eeprom->reg_data_in)
2574 reg |= RTL818X_EEPROM_CMD_WRITE;
2575 if (eeprom->reg_data_out)
2576 reg |= RTL818X_EEPROM_CMD_READ;
2577 if (eeprom->reg_data_clock)
2578 reg |= RTL818X_EEPROM_CMD_CK;
2579 if (eeprom->reg_chip_select)
2580 reg |= RTL818X_EEPROM_CMD_CS;
2581
2582 write_nic_byte(dev, EPROM_CMD, reg);
2583 read_nic_byte(dev, EPROM_CMD);
2584 udelay(10);
2585}
2586
c8d86be3
GKH
2587short rtl8180_init(struct net_device *dev)
2588{
2589 struct r8180_priv *priv = ieee80211_priv(dev);
2590 u16 word;
2591 u16 version;
c8d86be3
GKH
2592 u32 usValue;
2593 u16 tmpu16;
2594 int i, j;
742821ce
LF
2595 struct eeprom_93cx6 eeprom;
2596 u16 eeprom_val;
2597
2598 eeprom.data = dev;
2599 eeprom.register_read = rtl8187se_eeprom_register_read;
2600 eeprom.register_write = rtl8187se_eeprom_register_write;
2601 eeprom.width = PCI_EEPROM_WIDTH_93C46;
c8d86be3 2602
742821ce
LF
2603 eeprom_93cx6_read(&eeprom, EEPROM_COUNTRY_CODE>>1, &eeprom_val);
2604 priv->channel_plan = eeprom_val & 0xFF;
bbfb5652 2605 if (priv->channel_plan > COUNTRY_CODE_GLOBAL_DOMAIN) {
c8d86be3
GKH
2606 printk("rtl8180_init:Error channel plan! Set to default.\n");
2607 priv->channel_plan = 0;
2608 }
c8d86be3 2609
bbfb5652 2610 DMESG("Channel plan is %d\n", priv->channel_plan);
c8d86be3 2611 rtl8180_set_channel_map(priv->channel_plan, priv->ieee80211);
c8d86be3 2612
c8d86be3
GKH
2613 //FIXME: these constants are placed in a bad pleace.
2614 priv->txbuffsize = 2048;//1024;
2615 priv->txringcount = 32;//32;
2616 priv->rxbuffersize = 2048;//1024;
2617 priv->rxringcount = 64;//32;
2618 priv->txbeaconcount = 2;
2619 priv->rx_skb_complete = 1;
c8d86be3 2620
c8d86be3
GKH
2621 priv->RFChangeInProgress = false;
2622 priv->SetRFPowerStateInProgress = false;
2623 priv->RFProgType = 0;
2624 priv->bInHctTest = false;
2625
bbfb5652 2626 priv->irq_enabled = 0;
c8d86be3 2627
c8d86be3
GKH
2628 rtl8180_statistics_init(&priv->stats);
2629 rtl8180_link_detect_init(&priv->link_detect);
c8d86be3
GKH
2630
2631 priv->ack_tx_to_ieee = 0;
2632 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
2633 priv->ieee80211->iw_mode = IW_MODE_INFRA;
2634 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
2635 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2636 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2637 priv->ieee80211->active_scan = 1;
2638 priv->ieee80211->rate = 110; //11 mbps
2639 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION;
2640 priv->ieee80211->host_encrypt = 1;
2641 priv->ieee80211->host_decrypt = 1;
2642 priv->ieee80211->sta_wake_up = rtl8180_hw_wakeup;
2643 priv->ieee80211->ps_request_tx_ack = rtl8180_rq_tx_ack;
2644 priv->ieee80211->enter_sleep_state = rtl8180_hw_sleep;
2645 priv->ieee80211->ps_is_queue_empty = rtl8180_is_tx_queue_empty;
2646
2647 priv->hw_wep = hwwep;
bbfb5652
PS
2648 priv->prism_hdr = 0;
2649 priv->dev = dev;
c8d86be3
GKH
2650 priv->retry_rts = DEFAULT_RETRY_RTS;
2651 priv->retry_data = DEFAULT_RETRY_DATA;
2652 priv->RFChangeInProgress = false;
2653 priv->SetRFPowerStateInProgress = false;
2654 priv->RFProgType = 0;
2655 priv->bInHctTest = false;
2656 priv->bInactivePs = true;//false;
2657 priv->ieee80211->bInactivePs = priv->bInactivePs;
2658 priv->bSwRfProcessing = false;
2659 priv->eRFPowerState = eRfOff;
2660 priv->RfOffReason = 0;
2661 priv->LedStrategy = SW_LED_MODE0;
c8d86be3
GKH
2662 priv->TxPollingTimes = 0;//lzm add 080826
2663 priv->bLeisurePs = true;
2664 priv->dot11PowerSaveMode = eActive;
c8d86be3
GKH
2665 priv->AdMinCheckPeriod = 5;
2666 priv->AdMaxCheckPeriod = 10;
c8d86be3
GKH
2667 priv->AdMaxRxSsThreshold = 30;//60->30
2668 priv->AdRxSsThreshold = 20;//50->20
2669 priv->AdCheckPeriod = priv->AdMinCheckPeriod;
2670 priv->AdTickCount = 0;
2671 priv->AdRxSignalStrength = -1;
2672 priv->RegSwAntennaDiversityMechanism = 0;
2673 priv->RegDefaultAntenna = 0;
2674 priv->SignalStrength = 0;
2675 priv->AdRxOkCnt = 0;
2676 priv->CurrAntennaIndex = 0;
2677 priv->AdRxSsBeforeSwitched = 0;
2678 init_timer(&priv->SwAntennaDiversityTimer);
2679 priv->SwAntennaDiversityTimer.data = (unsigned long)dev;
2680 priv->SwAntennaDiversityTimer.function = (void *)SwAntennaDiversityTimerCallback;
c8d86be3
GKH
2681 priv->bDigMechanism = 1;
2682 priv->InitialGain = 6;
2683 priv->bXtalCalibration = false;
2684 priv->XtalCal_Xin = 0;
2685 priv->XtalCal_Xout = 0;
2686 priv->bTxPowerTrack = false;
2687 priv->ThermalMeter = 0;
2688 priv->FalseAlarmRegValue = 0;
2689 priv->RegDigOfdmFaUpTh = 0xc; // Upper threhold of OFDM false alarm, which is used in DIG.
2690 priv->DIG_NumberFallbackVote = 0;
2691 priv->DIG_NumberUpgradeVote = 0;
2692 priv->LastSignalStrengthInPercent = 0;
2693 priv->Stats_SignalStrength = 0;
2694 priv->LastRxPktAntenna = 0;
2695 priv->SignalQuality = 0; // in 0-100 index.
2696 priv->Stats_SignalQuality = 0;
2697 priv->RecvSignalPower = 0; // in dBm.
2698 priv->Stats_RecvSignalPower = 0;
2699 priv->AdMainAntennaRxOkCnt = 0;
2700 priv->AdAuxAntennaRxOkCnt = 0;
2701 priv->bHWAdSwitched = false;
2702 priv->bRegHighPowerMechanism = true;
2703 priv->RegHiPwrUpperTh = 77;
2704 priv->RegHiPwrLowerTh = 75;
2705 priv->RegRSSIHiPwrUpperTh = 70;
2706 priv->RegRSSIHiPwrLowerTh = 20;
2707 priv->bCurCCKPkt = false;
2708 priv->UndecoratedSmoothedSS = -1;
2709 priv->bToUpdateTxPwr = false;
2710 priv->CurCCKRSSI = 0;
2711 priv->RxPower = 0;
2712 priv->RSSI = 0;
c8d86be3
GKH
2713 priv->NumTxOkTotal = 0;
2714 priv->NumTxUnicast = 0;
2715 priv->keepAliveLevel = DEFAULT_KEEP_ALIVE_LEVEL;
2716 priv->PowerProfile = POWER_PROFILE_AC;
1994130e
LF
2717 priv->CurrRetryCnt = 0;
2718 priv->LastRetryCnt = 0;
2719 priv->LastTxokCnt = 0;
2720 priv->LastRxokCnt = 0;
2721 priv->LastRetryRate = 0;
2722 priv->bTryuping = 0;
2723 priv->CurrTxRate = 0;
2724 priv->CurrRetryRate = 0;
2725 priv->TryupingCount = 0;
2726 priv->TryupingCountNoData = 0;
2727 priv->TryDownCountLowData = 0;
2728 priv->LastTxOKBytes = 0;
2729 priv->LastFailTxRate = 0;
2730 priv->LastFailTxRateSS = 0;
2731 priv->FailTxRateCount = 0;
2732 priv->LastTxThroughput = 0;
2733 priv->NumTxOkBytesTotal = 0;
c8d86be3
GKH
2734 priv->ForcedDataRate = 0;
2735 priv->RegBModeGainStage = 1;
2736
1994130e 2737 priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
c8d86be3
GKH
2738 spin_lock_init(&priv->irq_lock);
2739 spin_lock_init(&priv->irq_th_lock);
2740 spin_lock_init(&priv->tx_lock);
2741 spin_lock_init(&priv->ps_lock);
2742 spin_lock_init(&priv->rf_ps_lock);
1994130e
LF
2743 sema_init(&priv->wx_sem, 1);
2744 sema_init(&priv->rf_state, 1);
2745 INIT_WORK(&priv->reset_wq, (void *)rtl8180_restart_wq);
2746 INIT_WORK(&priv->tx_irq_wq, (void *)rtl8180_tx_irq_wq);
2747 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,
2748 (void *)rtl8180_hw_wakeup_wq);
2749 INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,
2750 (void *)rtl8180_hw_sleep_wq);
2751 INIT_WORK(&priv->ieee80211->wmm_param_update_wq,
2752 (void *)rtl8180_wmm_param_update);
2753 INIT_DELAYED_WORK(&priv->ieee80211->rate_adapter_wq,
2754 (void *)rtl8180_rate_adapter);
2755 INIT_DELAYED_WORK(&priv->ieee80211->hw_dig_wq,
2756 (void *)rtl8180_hw_dig_wq);
2757 INIT_DELAYED_WORK(&priv->ieee80211->tx_pw_wq,
2758 (void *)rtl8180_tx_pw_wq);
2759 INIT_DELAYED_WORK(&priv->ieee80211->GPIOChangeRFWorkItem,
2760 (void *) GPIOChangeRFWorkItemCallBack);
c8d86be3
GKH
2761 tasklet_init(&priv->irq_rx_tasklet,
2762 (void(*)(unsigned long)) rtl8180_irq_rx_tasklet,
2763 (unsigned long)priv);
fd882783 2764
1994130e 2765 init_timer(&priv->watch_dog_timer);
c8d86be3
GKH
2766 priv->watch_dog_timer.data = (unsigned long)dev;
2767 priv->watch_dog_timer.function = watch_dog_adaptive;
c8d86be3 2768
1994130e
LF
2769 init_timer(&priv->rateadapter_timer);
2770 priv->rateadapter_timer.data = (unsigned long)dev;
2771 priv->rateadapter_timer.function = timer_rate_adaptive;
2772 priv->RateAdaptivePeriod = RATE_ADAPTIVE_TIMER_PERIOD;
2773 priv->bEnhanceTxPwr = false;
c8d86be3
GKH
2774
2775 priv->ieee80211->softmac_hard_start_xmit = rtl8180_hard_start_xmit;
2776 priv->ieee80211->set_chan = rtl8180_set_chan;
2777 priv->ieee80211->link_change = rtl8180_link_change;
2778 priv->ieee80211->softmac_data_hard_start_xmit = rtl8180_hard_data_xmit;
2779 priv->ieee80211->data_hard_stop = rtl8180_data_hard_stop;
2780 priv->ieee80211->data_hard_resume = rtl8180_data_hard_resume;
2781
cb73da25 2782 priv->ieee80211->init_wmmparam_flag = 0;
c8d86be3
GKH
2783
2784 priv->ieee80211->start_send_beacons = rtl8180_start_tx_beacon;
2785 priv->ieee80211->stop_send_beacons = rtl8180_beacon_tx_disable;
2786 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
2787
c8d86be3
GKH
2788 priv->MWIEnable = 0;
2789
2790 priv->ShortRetryLimit = 7;
2791 priv->LongRetryLimit = 7;
2792 priv->EarlyRxThreshold = 7;
2793
2794 priv->CSMethod = (0x01 << 29);
2795
1994130e
LF
2796 priv->TransmitConfig = TCR_DurProcMode_OFFSET |
2797 (7<<TCR_MXDMA_OFFSET) |
2798 (priv->ShortRetryLimit<<TCR_SRL_OFFSET) |
2799 (priv->LongRetryLimit<<TCR_LRL_OFFSET) |
2800 (0 ? TCR_SAT : 0);
2801
2802 priv->ReceiveConfig = RCR_AMF | RCR_ADF | RCR_ACF |
2803 RCR_AB | RCR_AM | RCR_APM |
2804 (7<<RCR_MXDMA_OFFSET) |
2805 (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) |
2806 (priv->EarlyRxThreshold == 7 ?
2807 RCR_ONLYERLPKT : 0);
c8d86be3
GKH
2808
2809 priv->IntrMask = IMR_TMGDOK | IMR_TBDER | IMR_THPDER |
1994130e
LF
2810 IMR_THPDER | IMR_THPDOK |
2811 IMR_TVODER | IMR_TVODOK |
2812 IMR_TVIDER | IMR_TVIDOK |
2813 IMR_TBEDER | IMR_TBEDOK |
2814 IMR_TBKDER | IMR_TBKDOK |
2815 IMR_RDU |
2816 IMR_RER | IMR_ROK |
2817 IMR_RQoSOK;
c8d86be3
GKH
2818
2819 priv->InitialGain = 6;
c8d86be3 2820
d44eb889
LF
2821 DMESG("MAC controller is a RTL8187SE b/g");
2822 priv->phy_ver = 2;
c8d86be3 2823
d44eb889
LF
2824 priv->ieee80211->modulation |= IEEE80211_OFDM_MODULATION;
2825 priv->ieee80211->short_slot = 1;
c8d86be3 2826
c8d86be3 2827 // just for sync 85
c8d86be3
GKH
2828 priv->enable_gpio0 = 0;
2829
742821ce
LF
2830 eeprom_93cx6_read(&eeprom, EEPROM_SW_REVD_OFFSET, &eeprom_val);
2831 usValue = eeprom_val;
bbfb5652 2832 DMESG("usValue is 0x%x\n", usValue);
c8d86be3 2833 //3Read AntennaDiversity
fd882783 2834
c8d86be3 2835 // SW Antenna Diversity.
fd882783 2836 if ((usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE)
c8d86be3 2837 priv->EEPROMSwAntennaDiversity = false;
c8d86be3 2838 else
c8d86be3 2839 priv->EEPROMSwAntennaDiversity = true;
fd882783 2840
c8d86be3 2841 // Default Antenna to use.
fd882783 2842 if ((usValue & EEPROM_DEF_ANT_MASK) != EEPROM_DEF_ANT_1)
c8d86be3 2843 priv->EEPROMDefaultAntenna1 = false;
c8d86be3 2844 else
c8d86be3 2845 priv->EEPROMDefaultAntenna1 = true;
c8d86be3 2846
bbfb5652 2847 if (priv->RegSwAntennaDiversityMechanism == 0) // Auto
fd882783 2848 /* 0: default from EEPROM. */
c8d86be3 2849 priv->bSwAntennaDiverity = priv->EEPROMSwAntennaDiversity;
c8d86be3 2850 else
fd882783 2851 /* 1:disable antenna diversity, 2: enable antenna diversity. */
bbfb5652 2852 priv->bSwAntennaDiverity = ((priv->RegSwAntennaDiversityMechanism == 1) ? false : true);
c8d86be3 2853
fd882783
BZ
2854 if (priv->RegDefaultAntenna == 0)
2855 /* 0: default from EEPROM. */
c8d86be3 2856 priv->bDefaultAntenna1 = priv->EEPROMDefaultAntenna1;
c8d86be3 2857 else
fd882783 2858 /* 1: main, 2: aux. */
bbfb5652 2859 priv->bDefaultAntenna1 = ((priv->RegDefaultAntenna == 2) ? true : false);
fd882783 2860
c8d86be3
GKH
2861 /* rtl8185 can calc plcp len in HW.*/
2862 priv->hw_plcp_len = 1;
2863
2864 priv->plcp_preamble_mode = 2;
2865 /*the eeprom type is stored in RCR register bit #6 */
fd882783 2866 if (RCR_9356SEL & read_nic_dword(dev, RCR))
bbfb5652 2867 priv->epromtype = EPROM_93c56;
fd882783 2868 else
bbfb5652 2869 priv->epromtype = EPROM_93c46;
c8d86be3 2870
742821ce
LF
2871 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)
2872 dev->dev_addr, 3);
c8d86be3 2873
bbfb5652 2874 for (i = 1, j = 0; i < 14; i += 2, j++) {
742821ce 2875 eeprom_93cx6_read(&eeprom, EPROM_TXPW_CH1_2 + j, &word);
bbfb5652
PS
2876 priv->chtxpwr[i] = word & 0xff;
2877 priv->chtxpwr[i+1] = (word & 0xff00)>>8;
c8d86be3 2878 }
d44eb889 2879 for (i = 1, j = 0; i < 14; i += 2, j++) {
742821ce 2880 eeprom_93cx6_read(&eeprom, EPROM_TXPW_OFDM_CH1_2 + j, &word);
d44eb889 2881 priv->chtxpwr_ofdm[i] = word & 0xff;
1994130e 2882 priv->chtxpwr_ofdm[i+1] = (word & 0xff00) >> 8;
c8d86be3 2883 }
fd882783 2884
1994130e 2885 /* 3Read crystal calibtration and thermal meter indication on 87SE. */
742821ce 2886 eeprom_93cx6_read(&eeprom, EEPROM_RSV>>1, &tmpu16);
c8d86be3 2887
1994130e
LF
2888 /* Crystal calibration for Xin and Xout resp. */
2889 priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK;
2890 priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK) >> 4;
2891 if ((tmpu16 & EEPROM_XTAL_CAL_ENABLE) >> 12)
2892 priv->bXtalCalibration = true;
c8d86be3 2893
1994130e
LF
2894 /* Thermal meter reference indication. */
2895 priv->ThermalMeter = (u8)((tmpu16 & EEPROM_THERMAL_METER_MASK) >> 8);
2896 if ((tmpu16 & EEPROM_THERMAL_METER_ENABLE) >> 13)
2897 priv->bTxPowerTrack = true;
c8d86be3 2898
742821ce 2899 eeprom_93cx6_read(&eeprom, EPROM_TXPW_BASE, &word);
c8d86be3
GKH
2900 priv->cck_txpwr_base = word & 0xf;
2901 priv->ofdm_txpwr_base = (word>>4) & 0xf;
c8d86be3 2902
742821ce 2903 eeprom_93cx6_read(&eeprom, EPROM_VERSION, &version);
bbfb5652 2904 DMESG("EEPROM version %x", version);
d44eb889 2905 priv->rcr_csense = 3;
c8d86be3 2906
742821ce
LF
2907 eeprom_93cx6_read(&eeprom, ENERGY_TRESHOLD, &eeprom_val);
2908 priv->cs_treshold = (eeprom_val & 0xff00) >> 8;
c8d86be3 2909
742821ce 2910 eeprom_93cx6_read(&eeprom, RFCHIPID, &eeprom_val);
c8d86be3
GKH
2911 priv->rf_sleep = rtl8225z4_rf_sleep;
2912 priv->rf_wakeup = rtl8225z4_rf_wakeup;
c8d86be3
GKH
2913 DMESGW("**PLEASE** REPORT SUCCESSFUL/UNSUCCESSFUL TO Realtek!");
2914
2915 priv->rf_close = rtl8225z2_rf_close;
2916 priv->rf_init = rtl8225z2_rf_init;
2917 priv->rf_set_chan = rtl8225z2_rf_set_chan;
2918 priv->rf_set_sens = NULL;
c8d86be3 2919
bbfb5652 2920 if (0 != alloc_rx_desc_ring(dev, priv->rxbuffersize, priv->rxringcount))
c8d86be3
GKH
2921 return -ENOMEM;
2922
bbfb5652 2923 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
c8d86be3
GKH
2924 TX_MANAGEPRIORITY_RING_ADDR))
2925 return -ENOMEM;
2926
bbfb5652 2927 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
c8d86be3
GKH
2928 TX_BKPRIORITY_RING_ADDR))
2929 return -ENOMEM;
2930
bbfb5652 2931 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
c8d86be3
GKH
2932 TX_BEPRIORITY_RING_ADDR))
2933 return -ENOMEM;
2934
bbfb5652 2935 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
c8d86be3
GKH
2936 TX_VIPRIORITY_RING_ADDR))
2937 return -ENOMEM;
2938
bbfb5652 2939 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
c8d86be3
GKH
2940 TX_VOPRIORITY_RING_ADDR))
2941 return -ENOMEM;
2942
bbfb5652 2943 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
c8d86be3
GKH
2944 TX_HIGHPRIORITY_RING_ADDR))
2945 return -ENOMEM;
2946
bbfb5652 2947 if (0 != alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txbeaconcount,
c8d86be3
GKH
2948 TX_BEACON_RING_ADDR))
2949 return -ENOMEM;
2950
bbfb5652 2951 if (request_irq(dev->irq, (void *)rtl8180_interrupt, IRQF_SHARED, dev->name, dev)) {
cb73da25
JC
2952 DMESGE("Error allocating IRQ %d", dev->irq);
2953 return -1;
bbfb5652
PS
2954 } else {
2955 priv->irq = dev->irq;
2956 DMESG("IRQ %d", dev->irq);
c8d86be3
GKH
2957 }
2958
c8d86be3 2959 return 0;
c8d86be3
GKH
2960}
2961
c8d86be3
GKH
2962void rtl8180_no_hw_wep(struct net_device *dev)
2963{
c8d86be3
GKH
2964}
2965
c8d86be3
GKH
2966void rtl8180_set_hw_wep(struct net_device *dev)
2967{
2968 struct r8180_priv *priv = ieee80211_priv(dev);
2969 u8 pgreg;
2970 u8 security;
2971 u32 key0_word4;
2972
bbfb5652
PS
2973 pgreg = read_nic_byte(dev, PGSELECT);
2974 write_nic_byte(dev, PGSELECT, pgreg & ~(1<<PGSELECT_PG_SHIFT));
c8d86be3
GKH
2975
2976 key0_word4 = read_nic_dword(dev, KEY0+4+4+4);
bbfb5652
PS
2977 key0_word4 &= ~0xff;
2978 key0_word4 |= priv->key0[3] & 0xff;
2979 write_nic_dword(dev, KEY0, (priv->key0[0]));
2980 write_nic_dword(dev, KEY0+4, (priv->key0[1]));
2981 write_nic_dword(dev, KEY0+4+4, (priv->key0[2]));
2982 write_nic_dword(dev, KEY0+4+4+4, (key0_word4));
2983
2984 security = read_nic_byte(dev, SECURITY);
c8d86be3
GKH
2985 security |= (1<<SECURITY_WEP_TX_ENABLE_SHIFT);
2986 security |= (1<<SECURITY_WEP_RX_ENABLE_SHIFT);
bbfb5652 2987 security &= ~SECURITY_ENCRYP_MASK;
c8d86be3
GKH
2988 security |= (SECURITY_ENCRYP_104<<SECURITY_ENCRYP_SHIFT);
2989
2990 write_nic_byte(dev, SECURITY, security);
2991
bbfb5652
PS
2992 DMESG("key %x %x %x %x", read_nic_dword(dev, KEY0+4+4+4),
2993 read_nic_dword(dev, KEY0+4+4), read_nic_dword(dev, KEY0+4),
2994 read_nic_dword(dev, KEY0));
c8d86be3
GKH
2995}
2996
2997
2998void rtl8185_rf_pins_enable(struct net_device *dev)
2999{
3000// u16 tmp;
3001// tmp = read_nic_word(dev, RFPinsEnable);
3002 write_nic_word(dev, RFPinsEnable, 0x1fff);// | tmp);
c8d86be3
GKH
3003}
3004
c8d86be3
GKH
3005void rtl8185_set_anaparam2(struct net_device *dev, u32 a)
3006{
3007 u8 conf3;
3008
3009 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3010
3011 conf3 = read_nic_byte(dev, CONFIG3);
3012 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3013 write_nic_dword(dev, ANAPARAM2, a);
3014
3015 conf3 = read_nic_byte(dev, CONFIG3);
bbfb5652 3016 write_nic_byte(dev, CONFIG3, conf3 & ~(1<<CONFIG3_ANAPARAM_W_SHIFT));
c8d86be3 3017 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH
3018}
3019
c8d86be3
GKH
3020void rtl8180_set_anaparam(struct net_device *dev, u32 a)
3021{
3022 u8 conf3;
3023
3024 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3025
3026 conf3 = read_nic_byte(dev, CONFIG3);
3027 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3028 write_nic_dword(dev, ANAPARAM, a);
3029
3030 conf3 = read_nic_byte(dev, CONFIG3);
bbfb5652 3031 write_nic_byte(dev, CONFIG3, conf3 & ~(1<<CONFIG3_ANAPARAM_W_SHIFT));
c8d86be3
GKH
3032 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3033}
3034
c8d86be3
GKH
3035void rtl8185_tx_antenna(struct net_device *dev, u8 ant)
3036{
3037 write_nic_byte(dev, TX_ANTENNA, ant);
3038 force_pci_posting(dev);
3039 mdelay(1);
3040}
3041
c8d86be3
GKH
3042void rtl8185_write_phy(struct net_device *dev, u8 adr, u32 data)
3043{
c8d86be3 3044 u32 phyw;
c8d86be3
GKH
3045
3046 adr |= 0x80;
3047
bbfb5652 3048 phyw = ((data<<8) | adr);
c8d86be3 3049
c8d86be3
GKH
3050 // Note that, we must write 0xff7c after 0x7d-0x7f to write BB register.
3051 write_nic_byte(dev, 0x7f, ((phyw & 0xff000000) >> 24));
3052 write_nic_byte(dev, 0x7e, ((phyw & 0x00ff0000) >> 16));
3053 write_nic_byte(dev, 0x7d, ((phyw & 0x0000ff00) >> 8));
bbfb5652 3054 write_nic_byte(dev, 0x7c, ((phyw & 0x000000ff)));
5521a513 3055
c8d86be3
GKH
3056 /* this is ok to fail when we write AGC table. check for AGC table might be
3057 * done by masking with 0x7f instead of 0xff
3058 */
3059 //if(phyr != (data&0xff)) DMESGW("Phy write timeout %x %x %x", phyr, data,adr);
3060}
3061
bbfb5652 3062inline void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data)
c8d86be3
GKH
3063{
3064 data = data & 0xff;
3065 rtl8185_write_phy(dev, adr, data);
3066}
3067
bbfb5652 3068void write_phy_cck(struct net_device *dev, u8 adr, u32 data)
c8d86be3
GKH
3069{
3070 data = data & 0xff;
3071 rtl8185_write_phy(dev, adr, data | 0x10000);
3072}
3073
c8d86be3
GKH
3074void rtl8185_set_rate(struct net_device *dev)
3075{
3076 int i;
3077 u16 word;
bbfb5652 3078 int basic_rate, min_rr_rate, max_rr_rate;
c8d86be3 3079
c8d86be3
GKH
3080 basic_rate = ieeerate2rtlrate(240);
3081 min_rr_rate = ieeerate2rtlrate(60);
3082 max_rr_rate = ieeerate2rtlrate(240);
3083
c8d86be3 3084 write_nic_byte(dev, RESP_RATE,
bbfb5652 3085 max_rr_rate<<MAX_RESP_RATE_SHIFT | min_rr_rate<<MIN_RESP_RATE_SHIFT);
c8d86be3
GKH
3086
3087 word = read_nic_word(dev, BRSR);
3088 word &= ~BRSR_MBR_8185;
3089
bbfb5652 3090 for (i = 0; i <= basic_rate; i++)
c8d86be3
GKH
3091 word |= (1<<i);
3092
3093 write_nic_word(dev, BRSR, word);
c8d86be3
GKH
3094}
3095
c8d86be3
GKH
3096void rtl8180_adapter_start(struct net_device *dev)
3097{
cb73da25 3098 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH
3099
3100 rtl8180_rtx_disable(dev);
3101 rtl8180_reset(dev);
3102
c8d86be3
GKH
3103 /* enable beacon timeout, beacon TX ok and err
3104 * LP tx ok and err, HP TX ok and err, NP TX ok and err,
3105 * RX ok and ERR, and GP timer */
3106 priv->irq_mask = 0x6fcf;
3107
3108 priv->dma_poll_mask = 0;
3109
3110 rtl8180_beacon_tx_disable(dev);
3111
c8d86be3 3112 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
bbfb5652
PS
3113 write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
3114 write_nic_word(dev, MAC4, ((u32 *)dev->dev_addr)[1] & 0xffff);
c8d86be3
GKH
3115 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3116
3117 rtl8180_update_msr(dev);
3118
c8d86be3
GKH
3119 /* These might be unnecessary since we do in rx_enable / tx_enable */
3120 fix_rx_fifo(dev);
3121 fix_tx_fifo(dev);
c8d86be3
GKH
3122
3123 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3124
3125 /*
3126 The following is very strange. seems to be that 1 means test mode,
3127 but we need to acknolwledges the nic when a packet is ready
bbc9a991 3128 although we set it to 0
c8d86be3
GKH
3129 */
3130
3131 write_nic_byte(dev,
bbfb5652 3132 CONFIG2, read_nic_byte(dev, CONFIG2) & ~\
c8d86be3
GKH
3133 (1<<CONFIG2_DMA_POLLING_MODE_SHIFT));
3134 //^the nic isn't in test mode
d44eb889 3135 write_nic_byte(dev,
bbfb5652 3136 CONFIG2, read_nic_byte(dev, CONFIG2)|(1<<4));
c8d86be3 3137
bbfb5652 3138 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3 3139
bbfb5652 3140 write_nic_dword(dev, INT_TIMEOUT, 0);
c8d86be3 3141
d44eb889 3142 write_nic_byte(dev, WPA_CONFIG, 0);
c8d86be3
GKH
3143
3144 rtl8180_no_hw_wep(dev);
3145
d44eb889
LF
3146 rtl8185_set_rate(dev);
3147 write_nic_byte(dev, RATE_FALLBACK, 0x81);
c8d86be3 3148
d44eb889 3149 write_nic_byte(dev, GP_ENABLE, read_nic_byte(dev, GP_ENABLE) & ~(1<<6));
c8d86be3 3150
d44eb889
LF
3151 /*FIXME cfg 3 ClkRun enable - isn't it ReadOnly ? */
3152 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3153 write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3)
3154 | (1 << CONFIG3_CLKRUN_SHIFT));
3155 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH
3156
3157 priv->rf_init(dev);
3158
bbfb5652
PS
3159 if (priv->rf_set_sens != NULL)
3160 priv->rf_set_sens(dev, priv->sens);
c8d86be3
GKH
3161 rtl8180_irq_enable(dev);
3162
3163 netif_start_queue(dev);
c8d86be3
GKH
3164}
3165
c8d86be3
GKH
3166/* this configures registers for beacon tx and enables it via
3167 * rtl8180_beacon_tx_enable(). rtl8180_beacon_tx_disable() might
3168 * be used to stop beacon transmission
3169 */
3170void rtl8180_start_tx_beacon(struct net_device *dev)
3171{
c8d86be3 3172 u16 word;
c8d86be3
GKH
3173
3174 DMESG("Enabling beacon TX");
c8d86be3
GKH
3175 rtl8180_prepare_beacon(dev);
3176 rtl8180_irq_disable(dev);
3177 rtl8180_beacon_tx_enable(dev);
c8d86be3 3178
bbfb5652
PS
3179 word = read_nic_word(dev, AtimWnd) & ~AtimWnd_AtimWnd;
3180 write_nic_word(dev, AtimWnd, word); // word |=
c8d86be3
GKH
3181
3182 word = read_nic_word(dev, BintrItv);
3183 word &= ~BintrItv_BintrItv;
3184 word |= 1000;/*priv->ieee80211->current_network.beacon_interval *
3185 ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1);
3186 // FIXME: check if correct ^^ worked with 0x3e8;
3187 */
3188 write_nic_word(dev, BintrItv, word);
3189
c8d86be3
GKH
3190 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3191
cb73da25 3192 rtl8185b_irq_enable(dev);
c8d86be3
GKH
3193}
3194
c8d86be3
GKH
3195static struct net_device_stats *rtl8180_stats(struct net_device *dev)
3196{
3197 struct r8180_priv *priv = ieee80211_priv(dev);
3198
3199 return &priv->ieee80211->stats;
3200}
3201//
3202// Change current and default preamble mode.
c8d86be3
GKH
3203//
3204bool
3205MgntActSet_802_11_PowerSaveMode(
3206 struct r8180_priv *priv,
3207 RT_PS_MODE rtPsMode
3208)
3209{
c8d86be3 3210 // Currently, we do not change power save mode on IBSS mode.
bbfb5652 3211 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
c8d86be3 3212 return false;
c8d86be3 3213
c8d86be3 3214 priv->ieee80211->ps = rtPsMode;
5521a513 3215
c8d86be3
GKH
3216 return true;
3217}
3218
fd882783 3219void LeisurePSEnter(struct r8180_priv *priv)
c8d86be3 3220{
fd882783 3221 if (priv->bLeisurePs) {
c8d86be3 3222 if (priv->ieee80211->ps == IEEE80211_PS_DISABLED)
c8d86be3 3223 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_MBCAST|IEEE80211_PS_UNICAST);//IEEE80211_PS_ENABLE
c8d86be3
GKH
3224 }
3225}
3226
fd882783 3227void LeisurePSLeave(struct r8180_priv *priv)
c8d86be3 3228{
fd882783 3229 if (priv->bLeisurePs) {
c8d86be3 3230 if (priv->ieee80211->ps != IEEE80211_PS_DISABLED)
c8d86be3 3231 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_DISABLED);
c8d86be3
GKH
3232 }
3233}
0370453f 3234
bbfb5652 3235void rtl8180_hw_wakeup_wq(struct work_struct *work)
c8d86be3 3236{
bf6aede7 3237 struct delayed_work *dwork = to_delayed_work(work);
bbfb5652 3238 struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, hw_wakeup_wq);
c8d86be3 3239 struct net_device *dev = ieee->dev;
c8d86be3 3240
c8d86be3 3241 rtl8180_hw_wakeup(dev);
c8d86be3
GKH
3242}
3243
bbfb5652 3244void rtl8180_hw_sleep_wq(struct work_struct *work)
c8d86be3 3245{
bf6aede7 3246 struct delayed_work *dwork = to_delayed_work(work);
bbfb5652 3247 struct ieee80211_device *ieee = container_of(dwork, struct ieee80211_device, hw_sleep_wq);
cb73da25 3248 struct net_device *dev = ieee->dev;
c8d86be3 3249
cb73da25 3250 rtl8180_hw_sleep_down(dev);
c8d86be3
GKH
3251}
3252
bbfb5652 3253static void MgntLinkKeepAlive(struct r8180_priv *priv)
c8d86be3
GKH
3254{
3255 if (priv->keepAliveLevel == 0)
3256 return;
3257
bbfb5652 3258 if (priv->ieee80211->state == IEEE80211_LINKED) {
c8d86be3
GKH
3259 //
3260 // Keep-Alive.
3261 //
c8d86be3 3262
bbfb5652 3263 if ((priv->keepAliveLevel == 2) ||
c8d86be3 3264 (priv->link_detect.LastNumTxUnicast == priv->NumTxUnicast &&
bbfb5652
PS
3265 priv->link_detect.LastNumRxUnicast == priv->ieee80211->NumRxUnicast)
3266 ) {
c8d86be3
GKH
3267 priv->link_detect.IdleCount++;
3268
3269 //
3270 // Send a Keep-Alive packet packet to AP if we had been idle for a while.
3271 //
bbfb5652 3272 if (priv->link_detect.IdleCount >= ((KEEP_ALIVE_INTERVAL / CHECK_FOR_HANG_PERIOD)-1)) {
c8d86be3
GKH
3273 priv->link_detect.IdleCount = 0;
3274 ieee80211_sta_ps_send_null_frame(priv->ieee80211, false);
3275 }
bbfb5652 3276 } else {
c8d86be3
GKH
3277 priv->link_detect.IdleCount = 0;
3278 }
3279 priv->link_detect.LastNumTxUnicast = priv->NumTxUnicast;
3280 priv->link_detect.LastNumRxUnicast = priv->ieee80211->NumRxUnicast;
3281 }
3282}
c8d86be3
GKH
3283
3284static u8 read_acadapter_file(char *filename);
fd882783 3285
c8d86be3
GKH
3286void rtl8180_watch_dog(struct net_device *dev)
3287{
3288 struct r8180_priv *priv = ieee80211_priv(dev);
3289 bool bEnterPS = false;
3290 bool bBusyTraffic = false;
3291 u32 TotalRxNum = 0;
3292 u16 SlotIndex = 0;
3293 u16 i = 0;
bbfb5652
PS
3294 if (priv->ieee80211->actscanning == false) {
3295 if ((priv->ieee80211->iw_mode != IW_MODE_ADHOC) && (priv->ieee80211->state == IEEE80211_NOLINK) && (priv->ieee80211->beinretry == false) && (priv->eRFPowerState == eRfOn))
c8d86be3 3296 IPSEnter(dev);
c8d86be3 3297 }
c8d86be3 3298 //YJ,add,080828,for link state check
bbfb5652 3299 if ((priv->ieee80211->state == IEEE80211_LINKED) && (priv->ieee80211->iw_mode == IW_MODE_INFRA)) {
c8d86be3
GKH
3300 SlotIndex = (priv->link_detect.SlotIndex++) % priv->link_detect.SlotNum;
3301 priv->link_detect.RxFrameNum[SlotIndex] = priv->ieee80211->NumRxDataInPeriod + priv->ieee80211->NumRxBcnInPeriod;
bbfb5652
PS
3302 for (i = 0; i < priv->link_detect.SlotNum; i++)
3303 TotalRxNum += priv->link_detect.RxFrameNum[i];
fd882783 3304
bbfb5652 3305 if (TotalRxNum == 0) {
c8d86be3
GKH
3306 priv->ieee80211->state = IEEE80211_ASSOCIATING;
3307 queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq);
3308 }
3309 }
3310
3311 //YJ,add,080828,for KeepAlive
3312 MgntLinkKeepAlive(priv);
3313
3314 //YJ,add,080828,for LPS
fd882783 3315 if (priv->PowerProfile == POWER_PROFILE_BATTERY)
c8d86be3 3316 priv->bLeisurePs = true;
fd882783 3317 else if (priv->PowerProfile == POWER_PROFILE_AC) {
c8d86be3 3318 LeisurePSLeave(priv);
bbfb5652 3319 priv->bLeisurePs = false;
c8d86be3 3320 }
c8d86be3 3321
bbfb5652 3322 if (priv->ieee80211->state == IEEE80211_LINKED) {
c8d86be3 3323 priv->link_detect.NumRxOkInPeriod = priv->ieee80211->NumRxDataInPeriod;
bbfb5652
PS
3324 if (priv->link_detect.NumRxOkInPeriod > 666 ||
3325 priv->link_detect.NumTxOkInPeriod > 666) {
c8d86be3
GKH
3326 bBusyTraffic = true;
3327 }
bbfb5652 3328 if (((priv->link_detect.NumRxOkInPeriod + priv->link_detect.NumTxOkInPeriod) > 8)
c8d86be3 3329 || (priv->link_detect.NumRxOkInPeriod > 2)) {
bbfb5652 3330 bEnterPS = false;
fd882783 3331 } else
bbfb5652 3332 bEnterPS = true;
c8d86be3 3333
fd882783 3334 if (bEnterPS)
c8d86be3 3335 LeisurePSEnter(priv);
fd882783 3336 else
c8d86be3 3337 LeisurePSLeave(priv);
fd882783 3338 } else
c8d86be3 3339 LeisurePSLeave(priv);
c8d86be3
GKH
3340 priv->link_detect.bBusyTraffic = bBusyTraffic;
3341 priv->link_detect.NumRxOkInPeriod = 0;
3342 priv->link_detect.NumTxOkInPeriod = 0;
3343 priv->ieee80211->NumRxDataInPeriod = 0;
3344 priv->ieee80211->NumRxBcnInPeriod = 0;
c8d86be3 3345}
fd882783 3346
c8d86be3
GKH
3347int _rtl8180_up(struct net_device *dev)
3348{
3349 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3 3350
bbfb5652 3351 priv->up = 1;
c8d86be3
GKH
3352
3353 DMESG("Bringing up iface");
c8d86be3
GKH
3354 rtl8185b_adapter_start(dev);
3355 rtl8185b_rx_enable(dev);
3356 rtl8185b_tx_enable(dev);
bbfb5652
PS
3357 if (priv->bInactivePs) {
3358 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
c8d86be3
GKH
3359 IPSLeave(dev);
3360 }
bbfb5652 3361 timer_rate_adaptive((unsigned long)dev);
c8d86be3 3362 watch_dog_adaptive((unsigned long)dev);
cb73da25 3363 if (priv->bSwAntennaDiverity)
c8d86be3 3364 SwAntennaDiversityTimerCallback(dev);
c8d86be3 3365 ieee80211_softmac_start_protocol(priv->ieee80211);
c8d86be3
GKH
3366 return 0;
3367}
3368
c8d86be3
GKH
3369int rtl8180_open(struct net_device *dev)
3370{
3371 struct r8180_priv *priv = ieee80211_priv(dev);
3372 int ret;
3373
3374 down(&priv->wx_sem);
3375 ret = rtl8180_up(dev);
3376 up(&priv->wx_sem);
3377 return ret;
c8d86be3
GKH
3378}
3379
c8d86be3
GKH
3380int rtl8180_up(struct net_device *dev)
3381{
3382 struct r8180_priv *priv = ieee80211_priv(dev);
3383
bbfb5652
PS
3384 if (priv->up == 1)
3385 return -1;
c8d86be3
GKH
3386
3387 return _rtl8180_up(dev);
3388}
3389
c8d86be3
GKH
3390int rtl8180_close(struct net_device *dev)
3391{
3392 struct r8180_priv *priv = ieee80211_priv(dev);
3393 int ret;
3394
3395 down(&priv->wx_sem);
3396 ret = rtl8180_down(dev);
3397 up(&priv->wx_sem);
3398
3399 return ret;
c8d86be3
GKH
3400}
3401
3402int rtl8180_down(struct net_device *dev)
3403{
3404 struct r8180_priv *priv = ieee80211_priv(dev);
3405
fd882783
BZ
3406 if (priv->up == 0)
3407 return -1;
c8d86be3 3408
bbfb5652 3409 priv->up = 0;
c8d86be3
GKH
3410
3411 ieee80211_softmac_stop_protocol(priv->ieee80211);
3412 /* FIXME */
3413 if (!netif_queue_stopped(dev))
3414 netif_stop_queue(dev);
3415 rtl8180_rtx_disable(dev);
3416 rtl8180_irq_disable(dev);
3417 del_timer_sync(&priv->watch_dog_timer);
fd882783
BZ
3418 del_timer_sync(&priv->rateadapter_timer);
3419 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
c8d86be3
GKH
3420 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
3421 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
3422 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
3423 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
3424 del_timer_sync(&priv->SwAntennaDiversityTimer);
bbfb5652
PS
3425 SetZebraRFPowerState8185(dev, eRfOff);
3426 memset(&(priv->ieee80211->current_network), 0, sizeof(struct ieee80211_network));
c8d86be3
GKH
3427 priv->ieee80211->state = IEEE80211_NOLINK;
3428 return 0;
3429}
3430
c8d86be3
GKH
3431void rtl8180_restart_wq(struct work_struct *work)
3432{
3433 struct r8180_priv *priv = container_of(work, struct r8180_priv, reset_wq);
3434 struct net_device *dev = priv->dev;
0370453f 3435
c8d86be3
GKH
3436 down(&priv->wx_sem);
3437
3438 rtl8180_commit(dev);
3439
3440 up(&priv->wx_sem);
3441}
3442
3443void rtl8180_restart(struct net_device *dev)
3444{
3445 struct r8180_priv *priv = ieee80211_priv(dev);
fd882783 3446
c8d86be3 3447 schedule_work(&priv->reset_wq);
c8d86be3
GKH
3448}
3449
c8d86be3
GKH
3450void rtl8180_commit(struct net_device *dev)
3451{
3452 struct r8180_priv *priv = ieee80211_priv(dev);
3453
fd882783
BZ
3454 if (priv->up == 0)
3455 return ;
3456
c8d86be3 3457 del_timer_sync(&priv->watch_dog_timer);
fd882783
BZ
3458 del_timer_sync(&priv->rateadapter_timer);
3459 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
c8d86be3
GKH
3460 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
3461 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
3462 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
3463 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
3464 del_timer_sync(&priv->SwAntennaDiversityTimer);
3465 ieee80211_softmac_stop_protocol(priv->ieee80211);
3466 rtl8180_irq_disable(dev);
3467 rtl8180_rtx_disable(dev);
3468 _rtl8180_up(dev);
3469}
3470
c8d86be3
GKH
3471static void r8180_set_multicast(struct net_device *dev)
3472{
3473 struct r8180_priv *priv = ieee80211_priv(dev);
3474 short promisc;
3475
bbfb5652 3476 promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
c8d86be3
GKH
3477
3478 if (promisc != priv->promisc)
3479 rtl8180_restart(dev);
3480
3481 priv->promisc = promisc;
c8d86be3
GKH
3482}
3483
c8d86be3
GKH
3484int r8180_set_mac_adr(struct net_device *dev, void *mac)
3485{
3486 struct r8180_priv *priv = ieee80211_priv(dev);
3487 struct sockaddr *addr = mac;
3488
3489 down(&priv->wx_sem);
3490
3491 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3492
bbfb5652 3493 if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
c8d86be3
GKH
3494 memcpy(priv->ieee80211->current_network.bssid, dev->dev_addr, ETH_ALEN);
3495
3496 if (priv->up) {
3497 rtl8180_down(dev);
3498 rtl8180_up(dev);
3499 }
3500
3501 up(&priv->wx_sem);
3502
3503 return 0;
3504}
3505
3506/* based on ipw2200 driver */
3507int rtl8180_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3508{
3509 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3 3510 struct iwreq *wrq = (struct iwreq *) rq;
bbfb5652 3511 int ret = -1;
fd882783 3512
c8d86be3 3513 switch (cmd) {
fd882783 3514 case RTL_IOCTL_WPA_SUPPLICANT:
c8d86be3
GKH
3515 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data);
3516 return ret;
fd882783 3517 default:
c8d86be3
GKH
3518 return -EOPNOTSUPP;
3519 }
3520
3521 return -EOPNOTSUPP;
3522}
3523
727ae303
AB
3524static const struct net_device_ops rtl8180_netdev_ops = {
3525 .ndo_open = rtl8180_open,
3526 .ndo_stop = rtl8180_close,
3527 .ndo_get_stats = rtl8180_stats,
3528 .ndo_tx_timeout = rtl8180_restart,
3529 .ndo_do_ioctl = rtl8180_ioctl,
3530 .ndo_set_multicast_list = r8180_set_multicast,
3531 .ndo_set_mac_address = r8180_set_mac_adr,
3532 .ndo_validate_addr = eth_validate_addr,
3533 .ndo_change_mtu = eth_change_mtu,
df574b8e 3534 .ndo_start_xmit = ieee80211_rtl_xmit,
727ae303 3535};
c8d86be3
GKH
3536
3537static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
3538 const struct pci_device_id *id)
3539{
3540 unsigned long ioaddr = 0;
3541 struct net_device *dev = NULL;
bbfb5652 3542 struct r8180_priv *priv = NULL;
c8d86be3
GKH
3543 u8 unit = 0;
3544
c8d86be3 3545 unsigned long pmem_start, pmem_len, pmem_flags;
c8d86be3
GKH
3546
3547 DMESG("Configuring chip resources");
3548
bbfb5652 3549 if (pci_enable_device(pdev)) {
c8d86be3
GKH
3550 DMESG("Failed to enable PCI device");
3551 return -EIO;
3552 }
3553
3554 pci_set_master(pdev);
c8d86be3 3555 pci_set_dma_mask(pdev, 0xffffff00ULL);
bbfb5652 3556 pci_set_consistent_dma_mask(pdev, 0xffffff00ULL);
c8d86be3
GKH
3557 dev = alloc_ieee80211(sizeof(struct r8180_priv));
3558 if (!dev)
3559 return -ENOMEM;
3560 priv = ieee80211_priv(dev);
3561 priv->ieee80211 = netdev_priv(dev);
3562
c8d86be3
GKH
3563 pci_set_drvdata(pdev, dev);
3564 SET_NETDEV_DEV(dev, &pdev->dev);
3565
3566 priv = ieee80211_priv(dev);
fd882783 3567 priv->pdev = pdev;
c8d86be3
GKH
3568
3569 pmem_start = pci_resource_start(pdev, 1);
3570 pmem_len = pci_resource_len(pdev, 1);
bbfb5652 3571 pmem_flags = pci_resource_flags(pdev, 1);
c8d86be3
GKH
3572
3573 if (!(pmem_flags & IORESOURCE_MEM)) {
3574 DMESG("region #1 not a MMIO resource, aborting");
3575 goto fail;
3576 }
3577
bbfb5652 3578 if (!request_mem_region(pmem_start, pmem_len, RTL8180_MODULE_NAME)) {
c8d86be3
GKH
3579 DMESG("request_mem_region failed!");
3580 goto fail;
3581 }
3582
bbfb5652
PS
3583 ioaddr = (unsigned long)ioremap_nocache(pmem_start, pmem_len);
3584 if (ioaddr == (unsigned long)NULL) {
c8d86be3 3585 DMESG("ioremap failed!");
c8d86be3
GKH
3586 goto fail1;
3587 }
3588
3589 dev->mem_start = ioaddr; // shared mem start
3590 dev->mem_end = ioaddr + pci_resource_len(pdev, 0); // shared mem end
3591
c8d86be3
GKH
3592 pci_read_config_byte(pdev, 0x05, &unit);
3593 pci_write_config_byte(pdev, 0x05, unit & (~0x04));
c8d86be3
GKH
3594
3595 dev->irq = pdev->irq;
3596 priv->irq = 0;
3597
727ae303 3598 dev->netdev_ops = &rtl8180_netdev_ops;
c8d86be3 3599 dev->wireless_handlers = &r8180_wx_handlers_def;
c8d86be3 3600
bbfb5652 3601 dev->type = ARPHRD_ETHER;
1994130e 3602 dev->watchdog_timeo = HZ*3;
c8d86be3 3603
bbfb5652 3604 if (dev_alloc_name(dev, ifname) < 0) {
cb73da25 3605 DMESG("Oops: devname already taken! Trying wlan%%d...\n");
c8d86be3 3606 ifname = "wlan%d";
c8d86be3 3607 dev_alloc_name(dev, ifname);
cb73da25 3608 }
c8d86be3 3609
bbfb5652 3610 if (rtl8180_init(dev) != 0) {
c8d86be3
GKH
3611 DMESG("Initialization failed");
3612 goto fail1;
3613 }
3614
3615 netif_carrier_off(dev);
3616
3617 register_netdev(dev);
3618
3619 rtl8180_proc_init_one(dev);
3620
3621 DMESG("Driver probe completed\n");
3622 return 0;
c8d86be3 3623fail1:
bbfb5652
PS
3624 if (dev->mem_start != (unsigned long)NULL) {
3625 iounmap((void *)dev->mem_start);
3626 release_mem_region(pci_resource_start(pdev, 1),
3627 pci_resource_len(pdev, 1));
c8d86be3 3628 }
c8d86be3 3629fail:
bbfb5652 3630 if (dev) {
c8d86be3
GKH
3631 if (priv->irq) {
3632 free_irq(dev->irq, dev);
bbfb5652 3633 dev->irq = 0;
c8d86be3
GKH
3634 }
3635 free_ieee80211(dev);
3636 }
3637
3638 pci_disable_device(pdev);
3639
3640 DMESG("wlan driver load failed\n");
3641 pci_set_drvdata(pdev, NULL);
3642 return -ENODEV;
c8d86be3
GKH
3643}
3644
c8d86be3
GKH
3645static void __devexit rtl8180_pci_remove(struct pci_dev *pdev)
3646{
3647 struct r8180_priv *priv;
3648 struct net_device *dev = pci_get_drvdata(pdev);
c8d86be3 3649
fd882783 3650 if (dev) {
c8d86be3
GKH
3651 unregister_netdev(dev);
3652
fd882783 3653 priv = ieee80211_priv(dev);
c8d86be3
GKH
3654
3655 rtl8180_proc_remove_one(dev);
3656 rtl8180_down(dev);
3657 priv->rf_close(dev);
3658 rtl8180_reset(dev);
c8d86be3 3659 mdelay(10);
c8d86be3 3660
bbfb5652
PS
3661 if (priv->irq) {
3662 DMESG("Freeing irq %d", dev->irq);
c8d86be3 3663 free_irq(dev->irq, dev);
bbfb5652 3664 priv->irq = 0;
c8d86be3
GKH
3665 }
3666
3667 free_rx_desc_ring(dev);
3668 free_tx_desc_rings(dev);
c8d86be3 3669
bbfb5652
PS
3670 if (dev->mem_start != (unsigned long)NULL) {
3671 iounmap((void *)dev->mem_start);
3672 release_mem_region(pci_resource_start(pdev, 1),
3673 pci_resource_len(pdev, 1));
c8d86be3 3674 }
c8d86be3
GKH
3675
3676 free_ieee80211(dev);
3677 }
3678 pci_disable_device(pdev);
3679
3680 DMESG("wlan driver removed\n");
3681}
3682
c8d86be3
GKH
3683/* fun with the built-in ieee80211 stack... */
3684extern int ieee80211_crypto_init(void);
3685extern void ieee80211_crypto_deinit(void);
3686extern int ieee80211_crypto_tkip_init(void);
3687extern void ieee80211_crypto_tkip_exit(void);
3688extern int ieee80211_crypto_ccmp_init(void);
3689extern void ieee80211_crypto_ccmp_exit(void);
3690extern int ieee80211_crypto_wep_init(void);
3691extern void ieee80211_crypto_wep_exit(void);
3692
3693static int __init rtl8180_pci_module_init(void)
3694{
3695 int ret;
3696
3697 ret = ieee80211_crypto_init();
3698 if (ret) {
3699 printk(KERN_ERR "ieee80211_crypto_init() failed %d\n", ret);
3700 return ret;
3701 }
3702 ret = ieee80211_crypto_tkip_init();
3703 if (ret) {
3704 printk(KERN_ERR "ieee80211_crypto_tkip_init() failed %d\n", ret);
3705 return ret;
3706 }
3707 ret = ieee80211_crypto_ccmp_init();
3708 if (ret) {
3709 printk(KERN_ERR "ieee80211_crypto_ccmp_init() failed %d\n", ret);
3710 return ret;
3711 }
3712 ret = ieee80211_crypto_wep_init();
3713 if (ret) {
3714 printk(KERN_ERR "ieee80211_crypto_wep_init() failed %d\n", ret);
3715 return ret;
3716 }
3717
bc568942 3718 printk(KERN_INFO "\nLinux kernel driver for RTL8180 / RTL8185 based WLAN cards\n");
c8d86be3
GKH
3719 printk(KERN_INFO "Copyright (c) 2004-2005, Andrea Merello\n");
3720 DMESG("Initializing module");
3721 DMESG("Wireless extensions version %d", WIRELESS_EXT);
3722 rtl8180_proc_module_init();
3723
fd882783 3724 if (pci_register_driver(&rtl8180_pci_driver)) {
c8d86be3 3725 DMESG("No device found");
c8d86be3
GKH
3726 return -ENODEV;
3727 }
3728 return 0;
3729}
3730
c8d86be3
GKH
3731static void __exit rtl8180_pci_module_exit(void)
3732{
bbfb5652 3733 pci_unregister_driver(&rtl8180_pci_driver);
c8d86be3 3734 rtl8180_proc_module_remove();
c8d86be3
GKH
3735 ieee80211_crypto_tkip_exit();
3736 ieee80211_crypto_ccmp_exit();
3737 ieee80211_crypto_wep_exit();
096c55d1 3738 ieee80211_crypto_deinit();
c8d86be3
GKH
3739 DMESG("Exiting");
3740}
3741
c8d86be3
GKH
3742void rtl8180_try_wake_queue(struct net_device *dev, int pri)
3743{
3744 unsigned long flags;
3745 short enough_desc;
3746 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3747
bbfb5652
PS
3748 spin_lock_irqsave(&priv->tx_lock, flags);
3749 enough_desc = check_nic_enought_desc(dev, pri);
3750 spin_unlock_irqrestore(&priv->tx_lock, flags);
c8d86be3 3751
bbfb5652 3752 if (enough_desc)
df574b8e 3753 ieee80211_rtl_wake_queue(priv->ieee80211);
c8d86be3
GKH
3754}
3755
bbfb5652 3756void rtl8180_tx_isr(struct net_device *dev, int pri, short error)
c8d86be3
GKH
3757{
3758 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH
3759 u32 *tail; //tail virtual addr
3760 u32 *head; //head virtual addr
3761 u32 *begin;//start of ring virtual addr
3762 u32 *nicv; //nic pointer virtual addr
c8d86be3
GKH
3763 u32 nic; //nic pointer physical addr
3764 u32 nicbegin;// start of ring physical addr
c8d86be3
GKH
3765 unsigned long flag;
3766 /* physical addr are ok on 32 bits since we set DMA mask*/
c8d86be3 3767 int offs;
bbfb5652 3768 int j, i;
c8d86be3 3769 int hd;
bbfb5652
PS
3770 if (error)
3771 priv->stats.txretry++; //tony 20060601
3772 spin_lock_irqsave(&priv->tx_lock, flag);
3773 switch (pri) {
c8d86be3
GKH
3774 case MANAGE_PRIORITY:
3775 tail = priv->txmapringtail;
3776 begin = priv->txmapring;
3777 head = priv->txmapringhead;
bbfb5652 3778 nic = read_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR);
c8d86be3
GKH
3779 nicbegin = priv->txmapringdma;
3780 break;
c8d86be3
GKH
3781 case BK_PRIORITY:
3782 tail = priv->txbkpringtail;
3783 begin = priv->txbkpring;
3784 head = priv->txbkpringhead;
bbfb5652 3785 nic = read_nic_dword(dev, TX_BKPRIORITY_RING_ADDR);
c8d86be3
GKH
3786 nicbegin = priv->txbkpringdma;
3787 break;
c8d86be3
GKH
3788 case BE_PRIORITY:
3789 tail = priv->txbepringtail;
3790 begin = priv->txbepring;
3791 head = priv->txbepringhead;
bbfb5652 3792 nic = read_nic_dword(dev, TX_BEPRIORITY_RING_ADDR);
c8d86be3
GKH
3793 nicbegin = priv->txbepringdma;
3794 break;
c8d86be3
GKH
3795 case VI_PRIORITY:
3796 tail = priv->txvipringtail;
3797 begin = priv->txvipring;
3798 head = priv->txvipringhead;
bbfb5652 3799 nic = read_nic_dword(dev, TX_VIPRIORITY_RING_ADDR);
c8d86be3
GKH
3800 nicbegin = priv->txvipringdma;
3801 break;
c8d86be3
GKH
3802 case VO_PRIORITY:
3803 tail = priv->txvopringtail;
3804 begin = priv->txvopring;
3805 head = priv->txvopringhead;
bbfb5652 3806 nic = read_nic_dword(dev, TX_VOPRIORITY_RING_ADDR);
c8d86be3
GKH
3807 nicbegin = priv->txvopringdma;
3808 break;
c8d86be3
GKH
3809 case HI_PRIORITY:
3810 tail = priv->txhpringtail;
3811 begin = priv->txhpring;
3812 head = priv->txhpringhead;
bbfb5652 3813 nic = read_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR);
c8d86be3
GKH
3814 nicbegin = priv->txhpringdma;
3815 break;
3816
3817 default:
bbfb5652 3818 spin_unlock_irqrestore(&priv->tx_lock, flag);
c8d86be3
GKH
3819 return ;
3820 }
fd882783 3821
bbfb5652
PS
3822 nicv = (u32 *)((nic - nicbegin) + (u8*)begin);
3823 if ((head <= tail && (nicv > tail || nicv < head)) ||
3824 (head > tail && (nicv > tail && nicv < head))) {
c8d86be3 3825 DMESGW("nic has lost pointer");
bbfb5652 3826 spin_unlock_irqrestore(&priv->tx_lock, flag);
c8d86be3
GKH
3827 rtl8180_restart(dev);
3828 return;
3829 }
3830
3831 /* we check all the descriptors between the head and the nic,
bbc9a991 3832 * but not the currently pointed by the nic (the next to be txed)
c8d86be3
GKH
3833 * and the previous of the pointed (might be in process ??)
3834 */
c8d86be3 3835 offs = (nic - nicbegin);
bbfb5652
PS
3836 offs = offs / 8 / 4;
3837 hd = (head - begin) / 8;
c8d86be3 3838
bbfb5652 3839 if (offs >= hd)
c8d86be3
GKH
3840 j = offs - hd;
3841 else
bbfb5652 3842 j = offs + (priv->txringcount-1-hd);
c8d86be3 3843
bbfb5652
PS
3844 j -= 2;
3845 if (j < 0)
3846 j = 0;
c8d86be3 3847
bbfb5652
PS
3848 for (i = 0; i < j; i++) {
3849 if ((*head) & (1<<31))
c8d86be3 3850 break;
bbfb5652 3851 if (((*head)&(0x10000000)) != 0) {
c8d86be3 3852 priv->CurrRetryCnt += (u16)((*head) & (0x000000ff));
fd882783 3853 if (!error)
c8d86be3 3854 priv->NumTxOkTotal++;
c8d86be3 3855 }
fd882783
BZ
3856
3857 if (!error)
c8d86be3 3858 priv->NumTxOkBytesTotal += (*(head+3)) & (0x00000fff);
fd882783 3859
bbfb5652 3860 *head = *head & ~(1<<31);
c8d86be3 3861
bbfb5652
PS
3862 if ((head - begin)/8 == priv->txringcount-1)
3863 head = begin;
c8d86be3 3864 else
bbfb5652 3865 head += 8;
c8d86be3 3866 }
c8d86be3 3867
c8d86be3
GKH
3868 /* the head has been moved to the last certainly TXed
3869 * (or at least processed by the nic) packet.
3870 * The driver take forcefully owning of all these packets
3871 * If the packet previous of the nic pointer has been
3872 * processed this doesn't matter: it will be checked
3873 * here at the next round. Anyway if no more packet are
3874 * TXed no memory leak occour at all.
3875 */
3876
bbfb5652 3877 switch (pri) {
c8d86be3
GKH
3878 case MANAGE_PRIORITY:
3879 priv->txmapringhead = head;
fd882783 3880
bbfb5652
PS
3881 if (priv->ack_tx_to_ieee) {
3882 if (rtl8180_is_tx_queue_empty(dev)) {
c8d86be3 3883 priv->ack_tx_to_ieee = 0;
bbfb5652 3884 ieee80211_ps_tx_ack(priv->ieee80211, !error);
c8d86be3 3885 }
c8d86be3
GKH
3886 }
3887 break;
c8d86be3
GKH
3888 case BK_PRIORITY:
3889 priv->txbkpringhead = head;
3890 break;
c8d86be3
GKH
3891 case BE_PRIORITY:
3892 priv->txbepringhead = head;
3893 break;
c8d86be3
GKH
3894 case VI_PRIORITY:
3895 priv->txvipringhead = head;
3896 break;
c8d86be3
GKH
3897 case VO_PRIORITY:
3898 priv->txvopringhead = head;
3899 break;
c8d86be3
GKH
3900 case HI_PRIORITY:
3901 priv->txhpringhead = head;
3902 break;
3903 }
3904
bbfb5652 3905 spin_unlock_irqrestore(&priv->tx_lock, flag);
c8d86be3
GKH
3906}
3907
c8d86be3
GKH
3908void rtl8180_tx_irq_wq(struct work_struct *work)
3909{
bf6aede7 3910 struct delayed_work *dwork = to_delayed_work(work);
bbfb5652
PS
3911 struct ieee80211_device * ieee = (struct ieee80211_device *)
3912 container_of(dwork, struct ieee80211_device, watch_dog_wq);
c8d86be3 3913 struct net_device *dev = ieee->dev;
0370453f 3914
bbfb5652 3915 rtl8180_tx_isr(dev, MANAGE_PRIORITY, 0);
c8d86be3
GKH
3916}
3917irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs)
3918{
3919 struct net_device *dev = (struct net_device *) netdev;
3920 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3921 unsigned long flags;
3922 u32 inta;
3923
3924 /* We should return IRQ_NONE, but for now let me keep this */
bbfb5652
PS
3925 if (priv->irq_enabled == 0)
3926 return IRQ_HANDLED;
c8d86be3 3927
bbfb5652 3928 spin_lock_irqsave(&priv->irq_th_lock, flags);
c8d86be3 3929
c8d86be3
GKH
3930 //ISR: 4bytes
3931 inta = read_nic_dword(dev, ISR);// & priv->IntrMask;
bbfb5652 3932 write_nic_dword(dev, ISR, inta); // reset int situation
c8d86be3
GKH
3933
3934 priv->stats.shints++;
3935
bbfb5652
PS
3936 if (!inta) {
3937 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
c8d86be3
GKH
3938 return IRQ_HANDLED;
3939 /*
3940 most probably we can safely return IRQ_NONE,
3941 but for now is better to avoid problems
3942 */
3943 }
3944
fd882783
BZ
3945 if (inta == 0xffff) {
3946 /* HW disappared */
3947 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
3948 return IRQ_HANDLED;
c8d86be3
GKH
3949 }
3950
3951 priv->stats.ints++;
c8d86be3 3952
bbfb5652
PS
3953 if (!netif_running(dev)) {
3954 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
c8d86be3
GKH
3955 return IRQ_HANDLED;
3956 }
3957
fd882783 3958 if (inta & ISR_TimeOut)
c8d86be3 3959 write_nic_dword(dev, TimerInt, 0);
c8d86be3 3960
fd882783 3961 if (inta & ISR_TBDOK)
c8d86be3 3962 priv->stats.txbeacon++;
c8d86be3 3963
fd882783 3964 if (inta & ISR_TBDER)
c8d86be3 3965 priv->stats.txbeaconerr++;
c8d86be3 3966
fd882783 3967 if (inta & IMR_TMGDOK)
bbfb5652 3968 rtl8180_tx_isr(dev, MANAGE_PRIORITY, 0);
c8d86be3 3969
bbfb5652 3970 if (inta & ISR_THPDER) {
c8d86be3 3971 priv->stats.txhperr++;
bbfb5652 3972 rtl8180_tx_isr(dev, HI_PRIORITY, 1);
c8d86be3
GKH
3973 priv->ieee80211->stats.tx_errors++;
3974 }
3975
bbfb5652 3976 if (inta & ISR_THPDOK) { //High priority tx ok
c8d86be3
GKH
3977 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
3978 priv->stats.txhpokint++;
bbfb5652 3979 rtl8180_tx_isr(dev, HI_PRIORITY, 0);
c8d86be3
GKH
3980 }
3981
bbfb5652 3982 if (inta & ISR_RER)
c8d86be3 3983 priv->stats.rxerr++;
bbfb5652
PS
3984
3985 if (inta & ISR_TBKDER) { //corresponding to BK_PRIORITY
c8d86be3
GKH
3986 priv->stats.txbkperr++;
3987 priv->ieee80211->stats.tx_errors++;
bbfb5652 3988 rtl8180_tx_isr(dev, BK_PRIORITY, 1);
c8d86be3
GKH
3989 rtl8180_try_wake_queue(dev, BE_PRIORITY);
3990 }
3991
bbfb5652 3992 if (inta & ISR_TBEDER) { //corresponding to BE_PRIORITY
c8d86be3
GKH
3993 priv->stats.txbeperr++;
3994 priv->ieee80211->stats.tx_errors++;
bbfb5652 3995 rtl8180_tx_isr(dev, BE_PRIORITY, 1);
c8d86be3
GKH
3996 rtl8180_try_wake_queue(dev, BE_PRIORITY);
3997 }
bbfb5652 3998 if (inta & ISR_TNPDER) { //corresponding to VO_PRIORITY
c8d86be3
GKH
3999 priv->stats.txnperr++;
4000 priv->ieee80211->stats.tx_errors++;
bbfb5652 4001 rtl8180_tx_isr(dev, NORM_PRIORITY, 1);
c8d86be3 4002 rtl8180_try_wake_queue(dev, NORM_PRIORITY);
c8d86be3
GKH
4003 }
4004
bbfb5652 4005 if (inta & ISR_TLPDER) { //corresponding to VI_PRIORITY
c8d86be3
GKH
4006 priv->stats.txlperr++;
4007 priv->ieee80211->stats.tx_errors++;
bbfb5652 4008 rtl8180_tx_isr(dev, LOW_PRIORITY, 1);
c8d86be3
GKH
4009 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
4010 }
4011
bbfb5652 4012 if (inta & ISR_ROK) {
c8d86be3
GKH
4013 priv->stats.rxint++;
4014 tasklet_schedule(&priv->irq_rx_tasklet);
4015 }
4016
bbfb5652 4017 if (inta & ISR_RQoSOK) {
c8d86be3
GKH
4018 priv->stats.rxint++;
4019 tasklet_schedule(&priv->irq_rx_tasklet);
4020 }
bbfb5652
PS
4021
4022 if (inta & ISR_BcnInt)
c8d86be3 4023 rtl8180_prepare_beacon(dev);
c8d86be3 4024
bbfb5652 4025 if (inta & ISR_RDU) {
c8d86be3
GKH
4026 DMESGW("No RX descriptor available");
4027 priv->stats.rxrdu++;
c8d86be3 4028 tasklet_schedule(&priv->irq_rx_tasklet);
c8d86be3 4029 }
fd882783 4030
bbfb5652 4031 if (inta & ISR_RXFOVW) {
c8d86be3
GKH
4032 priv->stats.rxoverflow++;
4033 tasklet_schedule(&priv->irq_rx_tasklet);
c8d86be3
GKH
4034 }
4035
fd882783
BZ
4036 if (inta & ISR_TXFOVW)
4037 priv->stats.txoverflow++;
c8d86be3 4038
bbfb5652 4039 if (inta & ISR_TNPDOK) { //Normal priority tx ok
c8d86be3 4040 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
c8d86be3 4041 priv->stats.txnpokint++;
bbfb5652 4042 rtl8180_tx_isr(dev, NORM_PRIORITY, 0);
c8d86be3
GKH
4043 }
4044
bbfb5652 4045 if (inta & ISR_TLPDOK) { //Low priority tx ok
c8d86be3 4046 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
c8d86be3 4047 priv->stats.txlpokint++;
bbfb5652 4048 rtl8180_tx_isr(dev, LOW_PRIORITY, 0);
c8d86be3
GKH
4049 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
4050 }
4051
bbfb5652 4052 if (inta & ISR_TBKDOK) { //corresponding to BK_PRIORITY
c8d86be3 4053 priv->stats.txbkpokint++;
c8d86be3 4054 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
bbfb5652 4055 rtl8180_tx_isr(dev, BK_PRIORITY, 0);
c8d86be3
GKH
4056 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4057 }
4058
bbfb5652 4059 if (inta & ISR_TBEDOK) { //corresponding to BE_PRIORITY
c8d86be3 4060 priv->stats.txbeperr++;
c8d86be3 4061 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
bbfb5652 4062 rtl8180_tx_isr(dev, BE_PRIORITY, 0);
c8d86be3
GKH
4063 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4064 }
c8d86be3 4065 force_pci_posting(dev);
bbfb5652 4066 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
c8d86be3
GKH
4067
4068 return IRQ_HANDLED;
4069}
4070
bbfb5652 4071void rtl8180_irq_rx_tasklet(struct r8180_priv *priv)
c8d86be3 4072{
c8d86be3 4073 rtl8180_rx(priv->dev);
c8d86be3
GKH
4074}
4075
c8d86be3
GKH
4076void GPIOChangeRFWorkItemCallBack(struct work_struct *work)
4077{
c8d86be3
GKH
4078 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, GPIOChangeRFWorkItem.work);
4079 struct net_device *dev = ieee->dev;
4080 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH
4081 u8 btPSR;
4082 u8 btConfig0;
4083 RT_RF_POWER_STATE eRfPowerStateToSet;
cb73da25 4084 bool bActuallySet = false;
c8d86be3
GKH
4085
4086 char *argv[3];
cb73da25 4087 static char *RadioPowerPath = "/etc/acpi/events/RadioPower.sh";
bbfb5652 4088 static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL};
c8d86be3 4089 static int readf_count = 0;
c8d86be3 4090
bbfb5652 4091 if (readf_count % 10 == 0)
c8d86be3
GKH
4092 priv->PowerProfile = read_acadapter_file("/proc/acpi/ac_adapter/AC0/state");
4093
4094 readf_count = (readf_count+1)%0xffff;
1994130e 4095 /* We should turn off LED before polling FF51[4]. */
c8d86be3 4096
1994130e
LF
4097 /* Turn off LED. */
4098 btPSR = read_nic_byte(dev, PSR);
4099 write_nic_byte(dev, PSR, (btPSR & ~BIT3));
c8d86be3 4100
1994130e
LF
4101 /* It need to delay 4us suggested by Jong, 2008-01-16 */
4102 udelay(4);
c8d86be3 4103
1994130e
LF
4104 /* HW radio On/Off according to the value of FF51[4](config0) */
4105 btConfig0 = btPSR = read_nic_byte(dev, CONFIG0);
c8d86be3 4106
1994130e 4107 eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff;
c8d86be3 4108
6de92dd6
LF
4109 /* Turn LED back on when radio enabled */
4110 if (eRfPowerStateToSet == eRfOn)
4111 write_nic_byte(dev, PSR, btPSR | BIT3);
c8d86be3 4112
1994130e
LF
4113 if ((priv->ieee80211->bHwRadioOff == true) &&
4114 (eRfPowerStateToSet == eRfOn)) {
4115 priv->ieee80211->bHwRadioOff = false;
4116 bActuallySet = true;
4117 } else if ((priv->ieee80211->bHwRadioOff == false) &&
4118 (eRfPowerStateToSet == eRfOff)) {
4119 priv->ieee80211->bHwRadioOff = true;
4120 bActuallySet = true;
4121 }
c8d86be3 4122
1994130e
LF
4123 if (bActuallySet) {
4124 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
4125
4126 /* To update the UI status for Power status changed */
4127 if (priv->ieee80211->bHwRadioOff == true)
4128 argv[1] = "RFOFF";
4129 else
4130 argv[1] = "RFON";
4131 argv[0] = RadioPowerPath;
4132 argv[2] = NULL;
4133
4134 call_usermodehelper(RadioPowerPath, argv, envp, 1);
4135 }
c8d86be3
GKH
4136}
4137
4138static u8 read_acadapter_file(char *filename)
4139{
c8d86be3
GKH
4140 return 0;
4141}
4142
c8d86be3
GKH
4143module_init(rtl8180_pci_module_init);
4144module_exit(rtl8180_pci_module_exit);