[net-next-2.6.git] / drivers / scsi / qla2xxx / qla_dbg.h

/*
 * QLogic Fibre Channel HBA Driver
 * Copyright (c)  2003-2008 QLogic Corporation
 *
 * See LICENSE.qla2xxx for copyright and licensing details.
 */

#include "qla_def.h"

/*
 * Driver debug definitions.
 */
/* #define QL_DEBUG_LEVEL_1  */ /* Output register accesses to COM1 */
/* #define QL_DEBUG_LEVEL_2  */ /* Output error msgs to COM1 */
/* #define QL_DEBUG_LEVEL_3  */ /* Output function trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_4  */ /* Output NVRAM trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_5  */ /* Output ring trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_6  */ /* Output WATCHDOG timer trace to COM1 */
/* #define QL_DEBUG_LEVEL_7  */ /* Output RISC load trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_8  */ /* Output ring saturation msgs to COM1 */
/* #define QL_DEBUG_LEVEL_9  */ /* Output IOCTL trace msgs */
/* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
/* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
/* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
/* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
/* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
/* #define QL_DEBUG_LEVEL_15 */ /* Output NPIV trace msgs */
/* #define QL_DEBUG_LEVEL_16 */ /* Output ISP84XX trace msgs */
/* #define QL_DEBUG_LEVEL_17 */ /* Output MULTI-Q trace messages */

/*
* Macros use for debugging the driver.
*/

#define DEBUG(x)	do { if (ql2xextended_error_logging) { x; } } while (0)

#if defined(QL_DEBUG_LEVEL_1)
#define DEBUG1(x)	do {x;} while (0)
#else
#define DEBUG1(x)	do {} while (0)
#endif

#define DEBUG2(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_3(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_3_11(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_9_10(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_11(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_13(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_16(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_17(x) 	do { if (ql2xextended_error_logging) { x; } } while (0)

#if defined(QL_DEBUG_LEVEL_3)
#define DEBUG3(x)	do {x;} while (0)
#define DEBUG3_11(x)	do {x;} while (0)
#else
#define DEBUG3(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_4)
#define DEBUG4(x)	do {x;} while (0)
#else
#define DEBUG4(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_5)
#define DEBUG5(x)          do {x;} while (0)
#else
#define DEBUG5(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_7)
#define DEBUG7(x)          do {x;} while (0)
#else
#define DEBUG7(x)	   do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_9)
#define DEBUG9(x)       do {x;} while (0)
#define DEBUG9_10(x)    do {x;} while (0)
#else
#define DEBUG9(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_10)
#define DEBUG10(x)      do {x;} while (0)
#define DEBUG9_10(x)	do {x;} while (0)
#else
#define DEBUG10(x)	do {} while (0)
  #if !defined(DEBUG9_10)
  #define DEBUG9_10(x)	do {} while (0)
  #endif
#endif

#if defined(QL_DEBUG_LEVEL_11)
#define DEBUG11(x)      do{x;} while(0)
#if !defined(DEBUG3_11)
#define DEBUG3_11(x)    do{x;} while(0)
#endif
#else
#define DEBUG11(x)	do{} while(0)
  #if !defined(QL_DEBUG_LEVEL_3)
  #define DEBUG3_11(x)	do{} while(0)
  #endif
#endif

#if defined(QL_DEBUG_LEVEL_12)
#define DEBUG12(x)      do {x;} while (0)
#else
#define DEBUG12(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_13)
#define DEBUG13(x)      do {x;} while (0)
#else
#define DEBUG13(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_14)
#define DEBUG14(x)      do {x;} while (0)
#else
#define DEBUG14(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_15)
#define DEBUG15(x)      do {x;} while (0)
#else
#define DEBUG15(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_16)
#define DEBUG16(x)	do {x;} while (0)
#else
#define DEBUG16(x)	do {} while (0)
#endif
/*
 * Firmware Dump structure definition
 */

struct qla2300_fw_dump {
	uint16_t hccr;
	uint16_t pbiu_reg[8];
	uint16_t risc_host_reg[8];
	uint16_t mailbox_reg[32];
	uint16_t resp_dma_reg[32];
	uint16_t dma_reg[48];
	uint16_t risc_hdw_reg[16];
	uint16_t risc_gp0_reg[16];
	uint16_t risc_gp1_reg[16];
	uint16_t risc_gp2_reg[16];
	uint16_t risc_gp3_reg[16];
	uint16_t risc_gp4_reg[16];
	uint16_t risc_gp5_reg[16];
	uint16_t risc_gp6_reg[16];
	uint16_t risc_gp7_reg[16];
	uint16_t frame_buf_hdw_reg[64];
	uint16_t fpm_b0_reg[64];
	uint16_t fpm_b1_reg[64];
	uint16_t risc_ram[0xf800];
	uint16_t stack_ram[0x1000];
	uint16_t data_ram[1];
};

struct qla2100_fw_dump {
	uint16_t hccr;
	uint16_t pbiu_reg[8];
	uint16_t mailbox_reg[32];
	uint16_t dma_reg[48];
	uint16_t risc_hdw_reg[16];
	uint16_t risc_gp0_reg[16];
	uint16_t risc_gp1_reg[16];
	uint16_t risc_gp2_reg[16];
	uint16_t risc_gp3_reg[16];
	uint16_t risc_gp4_reg[16];
	uint16_t risc_gp5_reg[16];
	uint16_t risc_gp6_reg[16];
	uint16_t risc_gp7_reg[16];
	uint16_t frame_buf_hdw_reg[16];
	uint16_t fpm_b0_reg[64];
	uint16_t fpm_b1_reg[64];
	uint16_t risc_ram[0xf000];
};

struct qla24xx_fw_dump {
	uint32_t host_status;
	uint32_t host_reg[32];
	uint32_t shadow_reg[7];
	uint16_t mailbox_reg[32];
	uint32_t xseq_gp_reg[128];
	uint32_t xseq_0_reg[16];
	uint32_t xseq_1_reg[16];
	uint32_t rseq_gp_reg[128];
	uint32_t rseq_0_reg[16];
	uint32_t rseq_1_reg[16];
	uint32_t rseq_2_reg[16];
	uint32_t cmd_dma_reg[16];
	uint32_t req0_dma_reg[15];
	uint32_t resp0_dma_reg[15];
	uint32_t req1_dma_reg[15];
	uint32_t xmt0_dma_reg[32];
	uint32_t xmt1_dma_reg[32];
	uint32_t xmt2_dma_reg[32];
	uint32_t xmt3_dma_reg[32];
	uint32_t xmt4_dma_reg[32];
	uint32_t xmt_data_dma_reg[16];
	uint32_t rcvt0_data_dma_reg[32];
	uint32_t rcvt1_data_dma_reg[32];
	uint32_t risc_gp_reg[128];
	uint32_t lmc_reg[112];
	uint32_t fpm_hdw_reg[192];
	uint32_t fb_hdw_reg[176];
	uint32_t code_ram[0x2000];
	uint32_t ext_mem[1];
};

struct qla25xx_fw_dump {
	uint32_t host_status;
	uint32_t host_risc_reg[32];
	uint32_t pcie_regs[4];
	uint32_t host_reg[32];
	uint32_t shadow_reg[11];
	uint32_t risc_io_reg;
	uint16_t mailbox_reg[32];
	uint32_t xseq_gp_reg[128];
	uint32_t xseq_0_reg[48];
	uint32_t xseq_1_reg[16];
	uint32_t rseq_gp_reg[128];
	uint32_t rseq_0_reg[32];
	uint32_t rseq_1_reg[16];
	uint32_t rseq_2_reg[16];
	uint32_t aseq_gp_reg[128];
	uint32_t aseq_0_reg[32];
	uint32_t aseq_1_reg[16];
	uint32_t aseq_2_reg[16];
	uint32_t cmd_dma_reg[16];
	uint32_t req0_dma_reg[15];
	uint32_t resp0_dma_reg[15];
	uint32_t req1_dma_reg[15];
	uint32_t xmt0_dma_reg[32];
	uint32_t xmt1_dma_reg[32];
	uint32_t xmt2_dma_reg[32];
	uint32_t xmt3_dma_reg[32];
	uint32_t xmt4_dma_reg[32];
	uint32_t xmt_data_dma_reg[16];
	uint32_t rcvt0_data_dma_reg[32];
	uint32_t rcvt1_data_dma_reg[32];
	uint32_t risc_gp_reg[128];
	uint32_t lmc_reg[128];
	uint32_t fpm_hdw_reg[192];
	uint32_t fb_hdw_reg[192];
	uint32_t code_ram[0x2000];
	uint32_t ext_mem[1];
};

#define EFT_NUM_BUFFERS		4
#define EFT_BYTES_PER_BUFFER	0x4000
#define EFT_SIZE		((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))

#define FCE_NUM_BUFFERS		64
#define FCE_BYTES_PER_BUFFER	0x400
#define FCE_SIZE		((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
#define fce_calc_size(b)	((FCE_BYTES_PER_BUFFER) * (b))

struct qla2xxx_fce_chain {
	uint32_t type;
	uint32_t chain_size;

	uint32_t size;
	uint32_t addr_l;
	uint32_t addr_h;
	uint32_t eregs[8];
};

struct qla2xxx_mq_chain {
	uint32_t type;
	uint32_t chain_size;

	uint32_t count;
	uint32_t qregs[4 * QLA_MQ_SIZE];
};

#define DUMP_CHAIN_VARIANT	0x80000000
#define DUMP_CHAIN_FCE		0x7FFFFAF0
#define DUMP_CHAIN_MQ		0x7FFFFAF1
#define DUMP_CHAIN_LAST		0x80000000

struct qla2xxx_fw_dump {
	uint8_t signature[4];
	uint32_t version;

	uint32_t fw_major_version;
	uint32_t fw_minor_version;
	uint32_t fw_subminor_version;
	uint32_t fw_attributes;

	uint32_t vendor;
	uint32_t device;
	uint32_t subsystem_vendor;
	uint32_t subsystem_device;

	uint32_t fixed_size;
	uint32_t mem_size;
	uint32_t req_q_size;
	uint32_t rsp_q_size;

	uint32_t eft_size;
	uint32_t eft_addr_l;
	uint32_t eft_addr_h;

	uint32_t header_size;

	union {
		struct qla2100_fw_dump isp21;
		struct qla2300_fw_dump isp23;
		struct qla24xx_fw_dump isp24;
		struct qla25xx_fw_dump isp25;
	} isp;
};
Commit	Line	Data
fa90c54f AV	1	/*
fa90c54f AV	2	* QLogic Fibre Channel HBA Driver
01e58d8e	3	* Copyright (c) 2003-2008 QLogic Corporation
1da177e4	4	*
fa90c54f AV	5	* See LICENSE.qla2xxx for copyright and licensing details.
fa90c54f AV	6	*/
73208dfd AC	7
	8	#include "qla_def.h"
	9
1da177e4 LT	10	/*
	11	* Driver debug definitions.
	12	*/
	13	/* #define QL_DEBUG_LEVEL_1 / / Output register accesses to COM1 */
	14	/* #define QL_DEBUG_LEVEL_2 / / Output error msgs to COM1 */
	15	/* #define QL_DEBUG_LEVEL_3 / / Output function trace msgs to COM1 */
	16	/* #define QL_DEBUG_LEVEL_4 / / Output NVRAM trace msgs to COM1 */
	17	/* #define QL_DEBUG_LEVEL_5 / / Output ring trace msgs to COM1 */
	18	/* #define QL_DEBUG_LEVEL_6 / / Output WATCHDOG timer trace to COM1 */
	19	/* #define QL_DEBUG_LEVEL_7 / / Output RISC load trace msgs to COM1 */
	20	/* #define QL_DEBUG_LEVEL_8 / / Output ring saturation msgs to COM1 */
	21	/* #define QL_DEBUG_LEVEL_9 / / Output IOCTL trace msgs */
	22	/* #define QL_DEBUG_LEVEL_10 / / Output IOCTL error msgs */
	23	/* #define QL_DEBUG_LEVEL_11 / / Output Mbx Cmd trace msgs */
	24	/* #define QL_DEBUG_LEVEL_12 / / Output IP trace msgs */
	25	/* #define QL_DEBUG_LEVEL_13 / / Output fdmi function trace msgs */
	26	/* #define QL_DEBUG_LEVEL_14 / / Output RSCN trace msgs */
2c3dfe3f	27	/* #define QL_DEBUG_LEVEL_15 / / Output NPIV trace msgs */
4d4df193	28	/* #define QL_DEBUG_LEVEL_16 / / Output ISP84XX trace msgs */
73208dfd	29	/* #define QL_DEBUG_LEVEL_17 / / Output MULTI-Q trace messages */
1da177e4 LT	30
	31	/*
	32	* Macros use for debugging the driver.
	33	*/
1da177e4	34
11010fec	35	#define DEBUG(x) do { if (ql2xextended_error_logging) { x; } } while (0)
1da177e4 LT	36
1da177e4 LT	37	#if defined(QL_DEBUG_LEVEL_1)
744f11fd	38	#define DEBUG1(x) do {x;} while (0)
1da177e4	39	#else
744f11fd	40	#define DEBUG1(x) do {} while (0)
1da177e4 LT	41	#endif
1da177e4 LT	42
11010fec AV	43	#define DEBUG2(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	44	#define DEBUG2_3(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	45	#define DEBUG2_3_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	46	#define DEBUG2_9_10(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	47	#define DEBUG2_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	48	#define DEBUG2_13(x) do { if (ql2xextended_error_logging) { x; } } while (0)
4d4df193	49	#define DEBUG2_16(x) do { if (ql2xextended_error_logging) { x; } } while (0)
73208dfd	50	#define DEBUG2_17(x) do { if (ql2xextended_error_logging) { x; } } while (0)
1da177e4 LT	51
1da177e4 LT	52	#if defined(QL_DEBUG_LEVEL_3)
744f11fd	53	#define DEBUG3(x) do {x;} while (0)
744f11fd	54	#define DEBUG3_11(x) do {x;} while (0)
1da177e4	55	#else
744f11fd	56	#define DEBUG3(x) do {} while (0)
1da177e4 LT	57	#endif
	58
	59	#if defined(QL_DEBUG_LEVEL_4)
744f11fd	60	#define DEBUG4(x) do {x;} while (0)
1da177e4	61	#else
744f11fd	62	#define DEBUG4(x) do {} while (0)
1da177e4 LT	63	#endif
	64
	65	#if defined(QL_DEBUG_LEVEL_5)
744f11fd	66	#define DEBUG5(x) do {x;} while (0)
1da177e4	67	#else
744f11fd	68	#define DEBUG5(x) do {} while (0)
1da177e4 LT	69	#endif
	70
	71	#if defined(QL_DEBUG_LEVEL_7)
744f11fd	72	#define DEBUG7(x) do {x;} while (0)
1da177e4	73	#else
744f11fd	74	#define DEBUG7(x) do {} while (0)
1da177e4 LT	75	#endif
	76
	77	#if defined(QL_DEBUG_LEVEL_9)
744f11fd AV	78	#define DEBUG9(x) do {x;} while (0)
744f11fd AV	79	#define DEBUG9_10(x) do {x;} while (0)
1da177e4	80	#else
744f11fd	81	#define DEBUG9(x) do {} while (0)
1da177e4 LT	82	#endif
	83
	84	#if defined(QL_DEBUG_LEVEL_10)
744f11fd	85	#define DEBUG10(x) do {x;} while (0)
744f11fd	86	#define DEBUG9_10(x) do {x;} while (0)
1da177e4	87	#else
744f11fd	88	#define DEBUG10(x) do {} while (0)
1da177e4	89	#if !defined(DEBUG9_10)
744f11fd	90	#define DEBUG9_10(x) do {} while (0)
1da177e4 LT	91	#endif
	92	#endif
	93
	94	#if defined(QL_DEBUG_LEVEL_11)
744f11fd	95	#define DEBUG11(x) do{x;} while(0)
1da177e4	96	#if !defined(DEBUG3_11)
744f11fd	97	#define DEBUG3_11(x) do{x;} while(0)
1da177e4 LT	98	#endif
1da177e4 LT	99	#else
744f11fd	100	#define DEBUG11(x) do{} while(0)
1da177e4	101	#if !defined(QL_DEBUG_LEVEL_3)
744f11fd	102	#define DEBUG3_11(x) do{} while(0)
1da177e4 LT	103	#endif
	104	#endif
	105
	106	#if defined(QL_DEBUG_LEVEL_12)
744f11fd	107	#define DEBUG12(x) do {x;} while (0)
1da177e4	108	#else
744f11fd	109	#define DEBUG12(x) do {} while (0)
1da177e4 LT	110	#endif
	111
	112	#if defined(QL_DEBUG_LEVEL_13)
	113	#define DEBUG13(x) do {x;} while (0)
	114	#else
	115	#define DEBUG13(x) do {} while (0)
	116	#endif
	117
	118	#if defined(QL_DEBUG_LEVEL_14)
	119	#define DEBUG14(x) do {x;} while (0)
	120	#else
	121	#define DEBUG14(x) do {} while (0)
	122	#endif
	123
2c3dfe3f SJ	124	#if defined(QL_DEBUG_LEVEL_15)
	125	#define DEBUG15(x) do {x;} while (0)
	126	#else
	127	#define DEBUG15(x) do {} while (0)
	128	#endif
	129
4d4df193 HK	130	#if defined(QL_DEBUG_LEVEL_16)
	131	#define DEBUG16(x) do {x;} while (0)
	132	#else
	133	#define DEBUG16(x) do {} while (0)
	134	#endif
1da177e4 LT	135	/*
	136	* Firmware Dump structure definition
	137	*/
1da177e4 LT	138
	139	struct qla2300_fw_dump {
	140	uint16_t hccr;
	141	uint16_t pbiu_reg[8];
	142	uint16_t risc_host_reg[8];
	143	uint16_t mailbox_reg[32];
	144	uint16_t resp_dma_reg[32];
	145	uint16_t dma_reg[48];
	146	uint16_t risc_hdw_reg[16];
	147	uint16_t risc_gp0_reg[16];
	148	uint16_t risc_gp1_reg[16];
	149	uint16_t risc_gp2_reg[16];
	150	uint16_t risc_gp3_reg[16];
	151	uint16_t risc_gp4_reg[16];
	152	uint16_t risc_gp5_reg[16];
	153	uint16_t risc_gp6_reg[16];
	154	uint16_t risc_gp7_reg[16];
	155	uint16_t frame_buf_hdw_reg[64];
	156	uint16_t fpm_b0_reg[64];
	157	uint16_t fpm_b1_reg[64];
	158	uint16_t risc_ram[0xf800];
	159	uint16_t stack_ram[0x1000];
	160	uint16_t data_ram[1];
	161	};
	162
	163	struct qla2100_fw_dump {
	164	uint16_t hccr;
	165	uint16_t pbiu_reg[8];
	166	uint16_t mailbox_reg[32];
	167	uint16_t dma_reg[48];
	168	uint16_t risc_hdw_reg[16];
	169	uint16_t risc_gp0_reg[16];
	170	uint16_t risc_gp1_reg[16];
	171	uint16_t risc_gp2_reg[16];
	172	uint16_t risc_gp3_reg[16];
	173	uint16_t risc_gp4_reg[16];
	174	uint16_t risc_gp5_reg[16];
	175	uint16_t risc_gp6_reg[16];
	176	uint16_t risc_gp7_reg[16];
	177	uint16_t frame_buf_hdw_reg[16];
	178	uint16_t fpm_b0_reg[64];
	179	uint16_t fpm_b1_reg[64];
	180	uint16_t risc_ram[0xf000];
	181	};
	182
6d9b61ed	183	struct qla24xx_fw_dump {
210d5350	184	uint32_t host_status;
6d9b61ed	185	uint32_t host_reg[32];
210d5350	186	uint32_t shadow_reg[7];
6d9b61ed AV	187	uint16_t mailbox_reg[32];
	188	uint32_t xseq_gp_reg[128];
	189	uint32_t xseq_0_reg[16];
	190	uint32_t xseq_1_reg[16];
	191	uint32_t rseq_gp_reg[128];
	192	uint32_t rseq_0_reg[16];
	193	uint32_t rseq_1_reg[16];
	194	uint32_t rseq_2_reg[16];
	195	uint32_t cmd_dma_reg[16];
	196	uint32_t req0_dma_reg[15];
	197	uint32_t resp0_dma_reg[15];
	198	uint32_t req1_dma_reg[15];
	199	uint32_t xmt0_dma_reg[32];
	200	uint32_t xmt1_dma_reg[32];
	201	uint32_t xmt2_dma_reg[32];
	202	uint32_t xmt3_dma_reg[32];
	203	uint32_t xmt4_dma_reg[32];
	204	uint32_t xmt_data_dma_reg[16];
	205	uint32_t rcvt0_data_dma_reg[32];
	206	uint32_t rcvt1_data_dma_reg[32];
	207	uint32_t risc_gp_reg[128];
6d9b61ed AV	208	uint32_t lmc_reg[112];
	209	uint32_t fpm_hdw_reg[192];
	210	uint32_t fb_hdw_reg[176];
	211	uint32_t code_ram[0x2000];
	212	uint32_t ext_mem[1];
	213	};
a7a167bf	214
c3a2f0df AV	215	struct qla25xx_fw_dump {
c3a2f0df AV	216	uint32_t host_status;
b5836927 AV	217	uint32_t host_risc_reg[32];
b5836927 AV	218	uint32_t pcie_regs[4];
c3a2f0df AV	219	uint32_t host_reg[32];
	220	uint32_t shadow_reg[11];
	221	uint32_t risc_io_reg;
	222	uint16_t mailbox_reg[32];
	223	uint32_t xseq_gp_reg[128];
	224	uint32_t xseq_0_reg[48];
	225	uint32_t xseq_1_reg[16];
	226	uint32_t rseq_gp_reg[128];
	227	uint32_t rseq_0_reg[32];
	228	uint32_t rseq_1_reg[16];
	229	uint32_t rseq_2_reg[16];
	230	uint32_t aseq_gp_reg[128];
	231	uint32_t aseq_0_reg[32];
	232	uint32_t aseq_1_reg[16];
	233	uint32_t aseq_2_reg[16];
	234	uint32_t cmd_dma_reg[16];
	235	uint32_t req0_dma_reg[15];
	236	uint32_t resp0_dma_reg[15];
	237	uint32_t req1_dma_reg[15];
	238	uint32_t xmt0_dma_reg[32];
	239	uint32_t xmt1_dma_reg[32];
	240	uint32_t xmt2_dma_reg[32];
	241	uint32_t xmt3_dma_reg[32];
	242	uint32_t xmt4_dma_reg[32];
	243	uint32_t xmt_data_dma_reg[16];
	244	uint32_t rcvt0_data_dma_reg[32];
	245	uint32_t rcvt1_data_dma_reg[32];
	246	uint32_t risc_gp_reg[128];
	247	uint32_t lmc_reg[128];
	248	uint32_t fpm_hdw_reg[192];
	249	uint32_t fb_hdw_reg[192];
	250	uint32_t code_ram[0x2000];
	251	uint32_t ext_mem[1];
	252	};
	253
a7a167bf AV	254	#define EFT_NUM_BUFFERS 4
	255	#define EFT_BYTES_PER_BUFFER 0x4000
	256	#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
	257
df613b96 AV	258	#define FCE_NUM_BUFFERS 64
	259	#define FCE_BYTES_PER_BUFFER 0x400
	260	#define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
	261	#define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b))
	262
	263	struct qla2xxx_fce_chain {
	264	uint32_t type;
	265	uint32_t chain_size;
	266
	267	uint32_t size;
	268	uint32_t addr_l;
	269	uint32_t addr_h;
	270	uint32_t eregs[8];
	271	};
	272
73208dfd AC	273	struct qla2xxx_mq_chain {
	274	uint32_t type;
	275	uint32_t chain_size;
	276
	277	uint32_t count;
	278	uint32_t qregs[4 * QLA_MQ_SIZE];
	279	};
	280
df613b96 AV	281	#define DUMP_CHAIN_VARIANT 0x80000000
df613b96 AV	282	#define DUMP_CHAIN_FCE 0x7FFFFAF0
73208dfd	283	#define DUMP_CHAIN_MQ 0x7FFFFAF1
df613b96 AV	284	#define DUMP_CHAIN_LAST 0x80000000
df613b96 AV	285
a7a167bf AV	286	struct qla2xxx_fw_dump {
	287	uint8_t signature[4];
	288	uint32_t version;
	289
	290	uint32_t fw_major_version;
	291	uint32_t fw_minor_version;
	292	uint32_t fw_subminor_version;
	293	uint32_t fw_attributes;
	294
	295	uint32_t vendor;
	296	uint32_t device;
	297	uint32_t subsystem_vendor;
	298	uint32_t subsystem_device;
	299
	300	uint32_t fixed_size;
	301	uint32_t mem_size;
	302	uint32_t req_q_size;
	303	uint32_t rsp_q_size;
	304
	305	uint32_t eft_size;
	306	uint32_t eft_addr_l;
	307	uint32_t eft_addr_h;
	308
	309	uint32_t header_size;
	310
	311	union {
	312	struct qla2100_fw_dump isp21;
	313	struct qla2300_fw_dump isp23;
	314	struct qla24xx_fw_dump isp24;
c3a2f0df	315	struct qla25xx_fw_dump isp25;
a7a167bf AV	316	} isp;
a7a167bf AV	317	};