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[SCSI] qla2xxx: Refactor qla data structures
[net-next-2.6.git] / drivers / scsi / qla2xxx / qla_dbg.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
01e58d8e 3 * Copyright (c) 2003-2008 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/delay.h>
10
a7a167bf 11static inline void
7b867cf7 12qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
a7a167bf
AV		 13{
14 fw_dump->fw_major_version = htonl(ha->fw_major_version);
15 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
16 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
17 fw_dump->fw_attributes = htonl(ha->fw_attributes);
18
19 fw_dump->vendor = htonl(ha->pdev->vendor);
20 fw_dump->device = htonl(ha->pdev->device);
21 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
22 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
23}
24
25static inline void *
7b867cf7 26qla2xxx_copy_queues(scsi_qla_host_t *vha, void *ptr)
a7a167bf 27{
7b867cf7
AC		 28 struct req_que *req = vha->hw->req;
29 struct rsp_que *rsp = vha->hw->rsp;
30
a7a167bf 31 /* Request queue. */
7b867cf7 32 memcpy(ptr, req->ring, req->length *
a7a167bf
AV		 33 sizeof(request_t));
34
35 /* Response queue. */
7b867cf7
AC		 36 ptr += req->length * sizeof(request_t);
37 memcpy(ptr, rsp->ring, rsp->length *
a7a167bf
AV		 38 sizeof(response_t));
39
7b867cf7 40 return ptr + (rsp->length * sizeof(response_t));
a7a167bf 41}
1da177e4 42
c3a2f0df 43static int
7b867cf7 44qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
c5722708 45 uint32_t ram_dwords, void **nxt)
c3a2f0df
AV		 46{
47 int rval;
c5722708
AV		 48 uint32_t cnt, stat, timer, dwords, idx;
49 uint16_t mb0;
c3a2f0df 50 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
c5722708
AV		 51 dma_addr_t dump_dma = ha->gid_list_dma;
52 uint32_t *dump = (uint32_t *)ha->gid_list;
c3a2f0df
AV		 53
54 rval = QLA_SUCCESS;
c5722708 55 mb0 = 0;
c3a2f0df 56
c5722708 57 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
c3a2f0df
AV		 58 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
59
c5722708
AV		 60 dwords = GID_LIST_SIZE / 4;
61 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
62 cnt += dwords, addr += dwords) {
63 if (cnt + dwords > ram_dwords)
64 dwords = ram_dwords - cnt;
c3a2f0df 65
c5722708
AV		 66 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
67 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
c3a2f0df 68
c5722708
AV		 69 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
70 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
71 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
72 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
c3a2f0df 73
c5722708
AV		 74 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
75 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
c3a2f0df
AV		 76 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
77
78 for (timer = 6000000; timer; timer--) {
79 /* Check for pending interrupts. */
80 stat = RD_REG_DWORD(&reg->host_status);
81 if (stat & HSRX_RISC_INT) {
82 stat &= 0xff;
83
84 if (stat == 0x1 || stat == 0x2 ||
85 stat == 0x10 || stat == 0x11) {
86 set_bit(MBX_INTERRUPT,
87 &ha->mbx_cmd_flags);
88
c5722708 89 mb0 = RD_REG_WORD(&reg->mailbox0);
c3a2f0df
AV		 90
91 WRT_REG_DWORD(&reg->hccr,
92 HCCRX_CLR_RISC_INT);
93 RD_REG_DWORD(&reg->hccr);
94 break;
95 }
96
97 /* Clear this intr; it wasn't a mailbox intr */
98 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
99 RD_REG_DWORD(&reg->hccr);
100 }
101 udelay(5);
102 }
103
104 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
c5722708
AV		 105 rval = mb0 & MBS_MASK;
106 for (idx = 0; idx < dwords; idx++)
107 ram[cnt + idx] = swab32(dump[idx]);
c3a2f0df
AV		 108 } else {
109 rval = QLA_FUNCTION_FAILED;
110 }
111 }
112
c5722708 113 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
c3a2f0df
AV		 114 return rval;
115}
116
c5722708 117static int
7b867cf7 118qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
c5722708
AV		 119 uint32_t cram_size, void **nxt)
120{
121 int rval;
122
123 /* Code RAM. */
124 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
125 if (rval != QLA_SUCCESS)
126 return rval;
127
128 /* External Memory. */
129 return qla24xx_dump_ram(ha, 0x100000, *nxt,
130 ha->fw_memory_size - 0x100000 + 1, nxt);
131}
132
c81d04c9
AV		 133static uint32_t *
134qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
135 uint32_t count, uint32_t *buf)
136{
137 uint32_t __iomem *dmp_reg;
138
139 WRT_REG_DWORD(&reg->iobase_addr, iobase);
140 dmp_reg = &reg->iobase_window;
141 while (count--)
142 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
143
144 return buf;
145}
146
147static inline int
148qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
149{
150 int rval = QLA_SUCCESS;
151 uint32_t cnt;
152
c3b058af
AV		 153 if (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE)
154 return rval;
155
156 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
157 for (cnt = 30000; (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
158 rval == QLA_SUCCESS; cnt--) {
159 if (cnt)
160 udelay(100);
161 else
162 rval = QLA_FUNCTION_TIMEOUT;
c81d04c9
AV		 163 }
164
165 return rval;
166}
167
168static int
7b867cf7 169qla24xx_soft_reset(struct qla_hw_data *ha)
c81d04c9
AV		 170{
171 int rval = QLA_SUCCESS;
172 uint32_t cnt;
173 uint16_t mb0, wd;
174 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
175
176 /* Reset RISC. */
177 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
178 for (cnt = 0; cnt < 30000; cnt++) {
179 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
180 break;
181
182 udelay(10);
183 }
184
185 WRT_REG_DWORD(&reg->ctrl_status,
186 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
187 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
188
189 udelay(100);
190 /* Wait for firmware to complete NVRAM accesses. */
191 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
192 for (cnt = 10000 ; cnt && mb0; cnt--) {
193 udelay(5);
194 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
195 barrier();
196 }
197
198 /* Wait for soft-reset to complete. */
199 for (cnt = 0; cnt < 30000; cnt++) {
200 if ((RD_REG_DWORD(&reg->ctrl_status) &
201 CSRX_ISP_SOFT_RESET) == 0)
202 break;
203
204 udelay(10);
205 }
206 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
207 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
208
209 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
210 rval == QLA_SUCCESS; cnt--) {
211 if (cnt)
212 udelay(100);
213 else
214 rval = QLA_FUNCTION_TIMEOUT;
215 }
216
217 return rval;
218}
219
c5722708 220static int
7b867cf7
AC		 221qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
222 uint16_t ram_words, void **nxt)
c5722708
AV		 223{
224 int rval;
225 uint32_t cnt, stat, timer, words, idx;
226 uint16_t mb0;
227 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
228 dma_addr_t dump_dma = ha->gid_list_dma;
229 uint16_t *dump = (uint16_t *)ha->gid_list;
230
231 rval = QLA_SUCCESS;
232 mb0 = 0;
233
234 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
235 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
236
237 words = GID_LIST_SIZE / 2;
238 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
239 cnt += words, addr += words) {
240 if (cnt + words > ram_words)
241 words = ram_words - cnt;
242
243 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
244 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
245
246 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
247 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
248 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
249 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
250
251 WRT_MAILBOX_REG(ha, reg, 4, words);
252 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
253
254 for (timer = 6000000; timer; timer--) {
255 /* Check for pending interrupts. */
256 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
257 if (stat & HSR_RISC_INT) {
258 stat &= 0xff;
259
260 if (stat == 0x1 || stat == 0x2) {
261 set_bit(MBX_INTERRUPT,
262 &ha->mbx_cmd_flags);
263
264 mb0 = RD_MAILBOX_REG(ha, reg, 0);
265
266 /* Release mailbox registers. */
267 WRT_REG_WORD(&reg->semaphore, 0);
268 WRT_REG_WORD(&reg->hccr,
269 HCCR_CLR_RISC_INT);
270 RD_REG_WORD(&reg->hccr);
271 break;
272 } else if (stat == 0x10 || stat == 0x11) {
273 set_bit(MBX_INTERRUPT,
274 &ha->mbx_cmd_flags);
275
276 mb0 = RD_MAILBOX_REG(ha, reg, 0);
277
278 WRT_REG_WORD(&reg->hccr,
279 HCCR_CLR_RISC_INT);
280 RD_REG_WORD(&reg->hccr);
281 break;
282 }
283
284 /* clear this intr; it wasn't a mailbox intr */
285 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
286 RD_REG_WORD(&reg->hccr);
287 }
288 udelay(5);
289 }
290
291 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
292 rval = mb0 & MBS_MASK;
293 for (idx = 0; idx < words; idx++)
294 ram[cnt + idx] = swab16(dump[idx]);
295 } else {
296 rval = QLA_FUNCTION_FAILED;
297 }
298 }
299
300 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
301 return rval;
302}
303
c81d04c9
AV		 304static inline void
305qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
306 uint16_t *buf)
307{
308 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
309
310 while (count--)
311 *buf++ = htons(RD_REG_WORD(dmp_reg++));
312}
313
1da177e4
LT		 314/**
315 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
316 * @ha: HA context
317 * @hardware_locked: Called with the hardware_lock
318 */
319void
7b867cf7 320qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 321{
322 int rval;
c5722708 323 uint32_t cnt;
7b867cf7 324 struct qla_hw_data *ha = vha->hw;
3d71644c 325 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 326 uint16_t __iomem *dmp_reg;
327 unsigned long flags;
328 struct qla2300_fw_dump *fw;
c5722708 329 void *nxt;
1da177e4 330
1da177e4
LT		 331 flags = 0;
332
333 if (!hardware_locked)
334 spin_lock_irqsave(&ha->hardware_lock, flags);
335
d4e3e04d 336 if (!ha->fw_dump) {
1da177e4 337 qla_printk(KERN_WARNING, ha,
d4e3e04d 338 "No buffer available for dump!!!\n");
1da177e4
LT		 339 goto qla2300_fw_dump_failed;
340 }
341
d4e3e04d 342 if (ha->fw_dumped) {
1da177e4 343 qla_printk(KERN_WARNING, ha,
d4e3e04d
AV		 344 "Firmware has been previously dumped (%p) -- ignoring "
345 "request...\n", ha->fw_dump);
1da177e4
LT		 346 goto qla2300_fw_dump_failed;
347 }
a7a167bf
AV		 348 fw = &ha->fw_dump->isp.isp23;
349 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 350
351 rval = QLA_SUCCESS;
a7a167bf 352 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 353
354 /* Pause RISC. */
fa2a1ce5 355 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 356 if (IS_QLA2300(ha)) {
357 for (cnt = 30000;
358 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
359 rval == QLA_SUCCESS; cnt--) {
360 if (cnt)
361 udelay(100);
362 else
363 rval = QLA_FUNCTION_TIMEOUT;
364 }
365 } else {
366 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
367 udelay(10);
368 }
369
370 if (rval == QLA_SUCCESS) {
c81d04c9 371 dmp_reg = &reg->flash_address;
fa2a1ce5 372 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 373 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 374
c81d04c9 375 dmp_reg = &reg->u.isp2300.req_q_in;
fa2a1ce5 376 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
a7a167bf 377 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 378
c81d04c9 379 dmp_reg = &reg->u.isp2300.mailbox0;
fa2a1ce5 380 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
a7a167bf 381 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 382
383 WRT_REG_WORD(&reg->ctrl_status, 0x40);
c81d04c9 384 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
1da177e4
LT		 385
386 WRT_REG_WORD(&reg->ctrl_status, 0x50);
c81d04c9 387 qla2xxx_read_window(reg, 48, fw->dma_reg);
1da177e4
LT		 388
389 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 390 dmp_reg = &reg->risc_hw;
fa2a1ce5 391 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 392 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 393
fa2a1ce5 394 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 395 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 396
fa2a1ce5 397 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 398 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 399
fa2a1ce5 400 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 401 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 402
fa2a1ce5 403 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 404 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 405
fa2a1ce5 406 WRT_REG_WORD(&reg->pcr, 0x2800);
c81d04c9 407 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 408
fa2a1ce5 409 WRT_REG_WORD(&reg->pcr, 0x2A00);
c81d04c9 410 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 411
fa2a1ce5 412 WRT_REG_WORD(&reg->pcr, 0x2C00);
c81d04c9 413 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 414
fa2a1ce5 415 WRT_REG_WORD(&reg->pcr, 0x2E00);
c81d04c9 416 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 417
fa2a1ce5 418 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 419 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
1da177e4 420
fa2a1ce5 421 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 422 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 423
fa2a1ce5 424 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 425 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 426
427 /* Reset RISC. */
428 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
429 for (cnt = 0; cnt < 30000; cnt++) {
430 if ((RD_REG_WORD(&reg->ctrl_status) &
431 CSR_ISP_SOFT_RESET) == 0)
432 break;
433
434 udelay(10);
435 }
436 }
437
438 if (!IS_QLA2300(ha)) {
439 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
440 rval == QLA_SUCCESS; cnt--) {
441 if (cnt)
442 udelay(100);
443 else
444 rval = QLA_FUNCTION_TIMEOUT;
445 }
446 }
447
c5722708
AV		 448 /* Get RISC SRAM. */
449 if (rval == QLA_SUCCESS)
450 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
451 sizeof(fw->risc_ram) / 2, &nxt);
1da177e4 452
c5722708
AV		 453 /* Get stack SRAM. */
454 if (rval == QLA_SUCCESS)
455 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
456 sizeof(fw->stack_ram) / 2, &nxt);
1da177e4 457
c5722708
AV		 458 /* Get data SRAM. */
459 if (rval == QLA_SUCCESS)
460 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
461 ha->fw_memory_size - 0x11000 + 1, &nxt);
1da177e4 462
a7a167bf 463 if (rval == QLA_SUCCESS)
7b867cf7 464 qla2xxx_copy_queues(vha, nxt);
a7a167bf 465
1da177e4
LT		 466 if (rval != QLA_SUCCESS) {
467 qla_printk(KERN_WARNING, ha,
468 "Failed to dump firmware (%x)!!!\n", rval);
d4e3e04d 469 ha->fw_dumped = 0;
1da177e4 470
1da177e4
LT		 471 } else {
472 qla_printk(KERN_INFO, ha,
473 "Firmware dump saved to temp buffer (%ld/%p).\n",
7b867cf7 474 vha->host_no, ha->fw_dump);
d4e3e04d 475 ha->fw_dumped = 1;
1da177e4
LT		 476 }
477
478qla2300_fw_dump_failed:
479 if (!hardware_locked)
480 spin_unlock_irqrestore(&ha->hardware_lock, flags);
481}
482
1da177e4
LT		 483/**
484 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
485 * @ha: HA context
486 * @hardware_locked: Called with the hardware_lock
487 */
488void
7b867cf7 489qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 490{
491 int rval;
492 uint32_t cnt, timer;
493 uint16_t risc_address;
494 uint16_t mb0, mb2;
7b867cf7 495 struct qla_hw_data *ha = vha->hw;
3d71644c 496 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 497 uint16_t __iomem *dmp_reg;
498 unsigned long flags;
499 struct qla2100_fw_dump *fw;
500
501 risc_address = 0;
502 mb0 = mb2 = 0;
503 flags = 0;
504
505 if (!hardware_locked)
506 spin_lock_irqsave(&ha->hardware_lock, flags);
507
d4e3e04d 508 if (!ha->fw_dump) {
1da177e4 509 qla_printk(KERN_WARNING, ha,
d4e3e04d 510 "No buffer available for dump!!!\n");
1da177e4
LT		 511 goto qla2100_fw_dump_failed;
512 }
513
d4e3e04d 514 if (ha->fw_dumped) {
1da177e4 515 qla_printk(KERN_WARNING, ha,
d4e3e04d
AV		 516 "Firmware has been previously dumped (%p) -- ignoring "
517 "request...\n", ha->fw_dump);
1da177e4
LT		 518 goto qla2100_fw_dump_failed;
519 }
a7a167bf
AV		 520 fw = &ha->fw_dump->isp.isp21;
521 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 522
523 rval = QLA_SUCCESS;
a7a167bf 524 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 525
526 /* Pause RISC. */
fa2a1ce5 527 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 528 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
529 rval == QLA_SUCCESS; cnt--) {
530 if (cnt)
531 udelay(100);
532 else
533 rval = QLA_FUNCTION_TIMEOUT;
534 }
535 if (rval == QLA_SUCCESS) {
c81d04c9 536 dmp_reg = &reg->flash_address;
fa2a1ce5 537 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 538 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 539
c81d04c9 540 dmp_reg = &reg->u.isp2100.mailbox0;
1da177e4 541 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
c81d04c9
AV		 542 if (cnt == 8)
543 dmp_reg = &reg->u_end.isp2200.mailbox8;
544
a7a167bf 545 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 546 }
547
c81d04c9 548 dmp_reg = &reg->u.isp2100.unused_2[0];
fa2a1ce5 549 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
a7a167bf 550 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 551
552 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 553 dmp_reg = &reg->risc_hw;
fa2a1ce5 554 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 555 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 556
fa2a1ce5 557 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 558 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 559
fa2a1ce5 560 WRT_REG_WORD(&reg->pcr, 0x2100);
c81d04c9 561 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 562
fa2a1ce5 563 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 564 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 565
fa2a1ce5 566 WRT_REG_WORD(&reg->pcr, 0x2300);
c81d04c9 567 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 568
fa2a1ce5 569 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 570 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 571
fa2a1ce5 572 WRT_REG_WORD(&reg->pcr, 0x2500);
c81d04c9 573 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 574
fa2a1ce5 575 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 576 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 577
fa2a1ce5 578 WRT_REG_WORD(&reg->pcr, 0x2700);
c81d04c9 579 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 580
fa2a1ce5 581 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 582 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
1da177e4 583
fa2a1ce5 584 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 585 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 586
fa2a1ce5 587 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 588 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 589
590 /* Reset the ISP. */
591 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
592 }
593
594 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
595 rval == QLA_SUCCESS; cnt--) {
596 if (cnt)
597 udelay(100);
598 else
599 rval = QLA_FUNCTION_TIMEOUT;
600 }
601
602 /* Pause RISC. */
603 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
604 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
605
fa2a1ce5 606 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 607 for (cnt = 30000;
608 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
609 rval == QLA_SUCCESS; cnt--) {
610 if (cnt)
611 udelay(100);
612 else
613 rval = QLA_FUNCTION_TIMEOUT;
614 }
615 if (rval == QLA_SUCCESS) {
616 /* Set memory configuration and timing. */
617 if (IS_QLA2100(ha))
618 WRT_REG_WORD(&reg->mctr, 0xf1);
619 else
620 WRT_REG_WORD(&reg->mctr, 0xf2);
621 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
622
623 /* Release RISC. */
624 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
625 }
626 }
627
628 if (rval == QLA_SUCCESS) {
629 /* Get RISC SRAM. */
630 risc_address = 0x1000;
631 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
632 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
633 }
634 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
635 cnt++, risc_address++) {
636 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
637 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
638
639 for (timer = 6000000; timer != 0; timer--) {
640 /* Check for pending interrupts. */
641 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
642 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
643 set_bit(MBX_INTERRUPT,
644 &ha->mbx_cmd_flags);
645
646 mb0 = RD_MAILBOX_REG(ha, reg, 0);
647 mb2 = RD_MAILBOX_REG(ha, reg, 2);
648
649 WRT_REG_WORD(&reg->semaphore, 0);
650 WRT_REG_WORD(&reg->hccr,
651 HCCR_CLR_RISC_INT);
652 RD_REG_WORD(&reg->hccr);
653 break;
654 }
655 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
656 RD_REG_WORD(&reg->hccr);
657 }
658 udelay(5);
659 }
660
661 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
662 rval = mb0 & MBS_MASK;
a7a167bf 663 fw->risc_ram[cnt] = htons(mb2);
1da177e4
LT		 664 } else {
665 rval = QLA_FUNCTION_FAILED;
666 }
667 }
668
a7a167bf 669 if (rval == QLA_SUCCESS)
7b867cf7 670 qla2xxx_copy_queues(vha, &fw->risc_ram[cnt]);
a7a167bf 671
1da177e4
LT		 672 if (rval != QLA_SUCCESS) {
673 qla_printk(KERN_WARNING, ha,
674 "Failed to dump firmware (%x)!!!\n", rval);
d4e3e04d 675 ha->fw_dumped = 0;
1da177e4 676
1da177e4
LT		 677 } else {
678 qla_printk(KERN_INFO, ha,
679 "Firmware dump saved to temp buffer (%ld/%p).\n",
7b867cf7 680 vha->host_no, ha->fw_dump);
d4e3e04d 681 ha->fw_dumped = 1;
1da177e4
LT		 682 }
683
684qla2100_fw_dump_failed:
685 if (!hardware_locked)
686 spin_unlock_irqrestore(&ha->hardware_lock, flags);
687}
688
6d9b61ed 689void
7b867cf7 690qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
6d9b61ed
AV		 691{
692 int rval;
c3a2f0df 693 uint32_t cnt;
6d9b61ed 694 uint32_t risc_address;
7b867cf7 695 struct qla_hw_data *ha = vha->hw;
6d9b61ed
AV		 696 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
697 uint32_t __iomem *dmp_reg;
698 uint32_t *iter_reg;
699 uint16_t __iomem *mbx_reg;
700 unsigned long flags;
701 struct qla24xx_fw_dump *fw;
702 uint32_t ext_mem_cnt;
c3a2f0df 703 void *nxt;
6d9b61ed
AV		 704
705 risc_address = ext_mem_cnt = 0;
6d9b61ed
AV		 706 flags = 0;
707
708 if (!hardware_locked)
709 spin_lock_irqsave(&ha->hardware_lock, flags);
710
d4e3e04d 711 if (!ha->fw_dump) {
6d9b61ed
AV		 712 qla_printk(KERN_WARNING, ha,
713 "No buffer available for dump!!!\n");
714 goto qla24xx_fw_dump_failed;
715 }
716
717 if (ha->fw_dumped) {
718 qla_printk(KERN_WARNING, ha,
719 "Firmware has been previously dumped (%p) -- ignoring "
d4e3e04d 720 "request...\n", ha->fw_dump);
6d9b61ed
AV		 721 goto qla24xx_fw_dump_failed;
722 }
a7a167bf
AV		 723 fw = &ha->fw_dump->isp.isp24;
724 qla2xxx_prep_dump(ha, ha->fw_dump);
6d9b61ed 725
a7a167bf 726 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed
AV		 727
728 /* Pause RISC. */
c81d04c9
AV		 729 rval = qla24xx_pause_risc(reg);
730 if (rval != QLA_SUCCESS)
731 goto qla24xx_fw_dump_failed_0;
732
733 /* Host interface registers. */
734 dmp_reg = &reg->flash_addr;
735 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
736 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
737
738 /* Disable interrupts. */
739 WRT_REG_DWORD(&reg->ictrl, 0);
740 RD_REG_DWORD(&reg->ictrl);
741
742 /* Shadow registers. */
743 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
744 RD_REG_DWORD(&reg->iobase_addr);
745 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
746 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
747
748 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
749 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
750
751 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
752 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
753
754 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
755 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
756
757 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
758 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
759
760 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
761 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
762
763 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
764 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
765
766 /* Mailbox registers. */
767 mbx_reg = &reg->mailbox0;
768 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
769 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
770
771 /* Transfer sequence registers. */
772 iter_reg = fw->xseq_gp_reg;
773 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
774 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
775 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
776 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
777 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
778 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
779 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
780 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
781
782 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
783 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
784
785 /* Receive sequence registers. */
786 iter_reg = fw->rseq_gp_reg;
787 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
788 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
789 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
790 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
791 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
792 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
793 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
794 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
795
796 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
797 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
798 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
799
800 /* Command DMA registers. */
801 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
802
803 /* Queues. */
804 iter_reg = fw->req0_dma_reg;
805 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
806 dmp_reg = &reg->iobase_q;
807 for (cnt = 0; cnt < 7; cnt++)
808 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
809
810 iter_reg = fw->resp0_dma_reg;
811 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
812 dmp_reg = &reg->iobase_q;
813 for (cnt = 0; cnt < 7; cnt++)
814 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
815
816 iter_reg = fw->req1_dma_reg;
817 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
818 dmp_reg = &reg->iobase_q;
819 for (cnt = 0; cnt < 7; cnt++)
820 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
821
822 /* Transmit DMA registers. */
823 iter_reg = fw->xmt0_dma_reg;
824 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
825 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
826
827 iter_reg = fw->xmt1_dma_reg;
828 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
829 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
830
831 iter_reg = fw->xmt2_dma_reg;
832 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
833 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
834
835 iter_reg = fw->xmt3_dma_reg;
836 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
837 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
838
839 iter_reg = fw->xmt4_dma_reg;
840 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
841 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
842
843 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
844
845 /* Receive DMA registers. */
846 iter_reg = fw->rcvt0_data_dma_reg;
847 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
848 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
849
850 iter_reg = fw->rcvt1_data_dma_reg;
851 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
852 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
853
854 /* RISC registers. */
855 iter_reg = fw->risc_gp_reg;
856 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
857 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
858 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
859 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
860 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
861 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
862 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
863 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
864
865 /* Local memory controller registers. */
866 iter_reg = fw->lmc_reg;
867 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
868 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
869 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
870 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
871 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
872 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
873 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
874
875 /* Fibre Protocol Module registers. */
876 iter_reg = fw->fpm_hdw_reg;
877 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
878 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
879 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
880 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
881 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
882 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
883 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
884 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
885 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
886 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
887 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
888 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
889
890 /* Frame Buffer registers. */
891 iter_reg = fw->fb_hdw_reg;
892 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
893 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
894 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
895 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
896 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
897 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
898 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
899 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
900 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
901 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
902 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
903
904 rval = qla24xx_soft_reset(ha);
905 if (rval != QLA_SUCCESS)
906 goto qla24xx_fw_dump_failed_0;
907
908 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 909 &nxt);
c81d04c9
AV		 910 if (rval != QLA_SUCCESS)
911 goto qla24xx_fw_dump_failed_0;
912
7b867cf7 913 nxt = qla2xxx_copy_queues(vha, nxt);
c81d04c9
AV		 914 if (ha->eft)
915 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
916
917qla24xx_fw_dump_failed_0:
c3a2f0df
AV		 918 if (rval != QLA_SUCCESS) {
919 qla_printk(KERN_WARNING, ha,
920 "Failed to dump firmware (%x)!!!\n", rval);
921 ha->fw_dumped = 0;
6d9b61ed 922
c3a2f0df
AV		 923 } else {
924 qla_printk(KERN_INFO, ha,
925 "Firmware dump saved to temp buffer (%ld/%p).\n",
7b867cf7 926 vha->host_no, ha->fw_dump);
c3a2f0df
AV		 927 ha->fw_dumped = 1;
928 }
6d9b61ed 929
c3a2f0df
AV		 930qla24xx_fw_dump_failed:
931 if (!hardware_locked)
932 spin_unlock_irqrestore(&ha->hardware_lock, flags);
933}
6d9b61ed 934
c3a2f0df 935void
7b867cf7 936qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
c3a2f0df
AV		 937{
938 int rval;
939 uint32_t cnt;
940 uint32_t risc_address;
7b867cf7 941 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 942 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
943 uint32_t __iomem *dmp_reg;
944 uint32_t *iter_reg;
945 uint16_t __iomem *mbx_reg;
946 unsigned long flags;
947 struct qla25xx_fw_dump *fw;
948 uint32_t ext_mem_cnt;
949 void *nxt;
df613b96 950 struct qla2xxx_fce_chain *fcec;
6d9b61ed 951
c3a2f0df
AV		 952 risc_address = ext_mem_cnt = 0;
953 flags = 0;
6d9b61ed 954
c3a2f0df
AV		 955 if (!hardware_locked)
956 spin_lock_irqsave(&ha->hardware_lock, flags);
6d9b61ed 957
c3a2f0df
AV		 958 if (!ha->fw_dump) {
959 qla_printk(KERN_WARNING, ha,
960 "No buffer available for dump!!!\n");
961 goto qla25xx_fw_dump_failed;
962 }
6d9b61ed 963
c3a2f0df
AV		 964 if (ha->fw_dumped) {
965 qla_printk(KERN_WARNING, ha,
966 "Firmware has been previously dumped (%p) -- ignoring "
967 "request...\n", ha->fw_dump);
968 goto qla25xx_fw_dump_failed;
969 }
970 fw = &ha->fw_dump->isp.isp25;
971 qla2xxx_prep_dump(ha, ha->fw_dump);
b5836927 972 ha->fw_dump->version = __constant_htonl(2);
6d9b61ed 973
c3a2f0df 974 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed 975
c3a2f0df 976 /* Pause RISC. */
c81d04c9
AV		 977 rval = qla24xx_pause_risc(reg);
978 if (rval != QLA_SUCCESS)
979 goto qla25xx_fw_dump_failed_0;
980
b5836927
AV		 981 /* Host/Risc registers. */
982 iter_reg = fw->host_risc_reg;
983 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
984 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
985
986 /* PCIe registers. */
987 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
988 RD_REG_DWORD(&reg->iobase_addr);
989 WRT_REG_DWORD(&reg->iobase_window, 0x01);
990 dmp_reg = &reg->iobase_c4;
991 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
992 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
993 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
994 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
995 WRT_REG_DWORD(&reg->iobase_window, 0x00);
996 RD_REG_DWORD(&reg->iobase_window);
997
c81d04c9
AV		 998 /* Host interface registers. */
999 dmp_reg = &reg->flash_addr;
1000 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1001 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1002
1003 /* Disable interrupts. */
1004 WRT_REG_DWORD(&reg->ictrl, 0);
1005 RD_REG_DWORD(&reg->ictrl);
1006
1007 /* Shadow registers. */
1008 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1009 RD_REG_DWORD(&reg->iobase_addr);
1010 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1011 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1012
1013 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1014 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1015
1016 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1017 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1018
1019 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1020 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1021
1022 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1023 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1024
1025 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1026 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1027
1028 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1029 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1030
1031 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1032 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1033
1034 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1035 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1036
1037 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1038 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1039
1040 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1041 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1042
1043 /* RISC I/O register. */
1044 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1045 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1046
1047 /* Mailbox registers. */
1048 mbx_reg = &reg->mailbox0;
1049 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1050 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1051
1052 /* Transfer sequence registers. */
1053 iter_reg = fw->xseq_gp_reg;
1054 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1055 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1056 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1057 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1058 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1059 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1060 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1061 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1062
1063 iter_reg = fw->xseq_0_reg;
1064 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1065 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1066 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1067
1068 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1069
1070 /* Receive sequence registers. */
1071 iter_reg = fw->rseq_gp_reg;
1072 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1073 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1074 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1075 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1076 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1077 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1078 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1079 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1080
1081 iter_reg = fw->rseq_0_reg;
1082 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1083 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1084
1085 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1086 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1087
1088 /* Auxiliary sequence registers. */
1089 iter_reg = fw->aseq_gp_reg;
1090 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1091 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1092 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1093 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1094 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1095 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1096 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1097 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1098
1099 iter_reg = fw->aseq_0_reg;
1100 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1101 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1102
1103 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1104 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1105
1106 /* Command DMA registers. */
1107 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1108
1109 /* Queues. */
1110 iter_reg = fw->req0_dma_reg;
1111 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1112 dmp_reg = &reg->iobase_q;
1113 for (cnt = 0; cnt < 7; cnt++)
1114 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1115
1116 iter_reg = fw->resp0_dma_reg;
1117 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1118 dmp_reg = &reg->iobase_q;
1119 for (cnt = 0; cnt < 7; cnt++)
1120 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1121
1122 iter_reg = fw->req1_dma_reg;
1123 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1124 dmp_reg = &reg->iobase_q;
1125 for (cnt = 0; cnt < 7; cnt++)
1126 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1127
1128 /* Transmit DMA registers. */
1129 iter_reg = fw->xmt0_dma_reg;
1130 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1131 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1132
1133 iter_reg = fw->xmt1_dma_reg;
1134 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1135 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1136
1137 iter_reg = fw->xmt2_dma_reg;
1138 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1139 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1140
1141 iter_reg = fw->xmt3_dma_reg;
1142 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1143 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1144
1145 iter_reg = fw->xmt4_dma_reg;
1146 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1147 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1148
1149 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1150
1151 /* Receive DMA registers. */
1152 iter_reg = fw->rcvt0_data_dma_reg;
1153 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1154 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1155
1156 iter_reg = fw->rcvt1_data_dma_reg;
1157 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1158 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1159
1160 /* RISC registers. */
1161 iter_reg = fw->risc_gp_reg;
1162 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1163 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1164 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1165 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1166 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1167 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1168 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1169 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1170
1171 /* Local memory controller registers. */
1172 iter_reg = fw->lmc_reg;
1173 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1174 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1175 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1176 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1177 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1178 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1179 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1180 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1181
1182 /* Fibre Protocol Module registers. */
1183 iter_reg = fw->fpm_hdw_reg;
1184 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1185 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1186 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1187 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1188 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1189 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1190 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1191 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1192 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1193 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1194 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1195 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1196
1197 /* Frame Buffer registers. */
1198 iter_reg = fw->fb_hdw_reg;
1199 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1200 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1201 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1202 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1203 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1204 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1205 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1206 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1207 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1208 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1209 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1210 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1211
1212 rval = qla24xx_soft_reset(ha);
1213 if (rval != QLA_SUCCESS)
1214 goto qla25xx_fw_dump_failed_0;
1215
1216 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1217 &nxt);
c81d04c9
AV		 1218 if (rval != QLA_SUCCESS)
1219 goto qla25xx_fw_dump_failed_0;
1220
df613b96 1221 /* Fibre Channel Trace Buffer. */
7b867cf7 1222 nxt = qla2xxx_copy_queues(vha, nxt);
c81d04c9
AV		 1223 if (ha->eft)
1224 memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
1225
df613b96
AV		 1226 /* Fibre Channel Event Buffer. */
1227 if (!ha->fce)
1228 goto qla25xx_fw_dump_failed_0;
1229
1230 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1231
1232 fcec = nxt + ntohl(ha->fw_dump->eft_size);
1233 fcec->type = __constant_htonl(DUMP_CHAIN_FCE | DUMP_CHAIN_LAST);
1234 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
1235 fce_calc_size(ha->fce_bufs));
1236 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
1237 fcec->addr_l = htonl(LSD(ha->fce_dma));
1238 fcec->addr_h = htonl(MSD(ha->fce_dma));
1239
1240 iter_reg = fcec->eregs;
1241 for (cnt = 0; cnt < 8; cnt++)
1242 *iter_reg++ = htonl(ha->fce_mb[cnt]);
1243
1244 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
1245
c81d04c9 1246qla25xx_fw_dump_failed_0:
c3a2f0df
AV		 1247 if (rval != QLA_SUCCESS) {
1248 qla_printk(KERN_WARNING, ha,
1249 "Failed to dump firmware (%x)!!!\n", rval);
1250 ha->fw_dumped = 0;
6d9b61ed
AV		 1251
1252 } else {
1253 qla_printk(KERN_INFO, ha,
1254 "Firmware dump saved to temp buffer (%ld/%p).\n",
7b867cf7 1255 vha->host_no, ha->fw_dump);
6d9b61ed
AV		 1256 ha->fw_dumped = 1;
1257 }
1258
c3a2f0df 1259qla25xx_fw_dump_failed:
6d9b61ed
AV		 1260 if (!hardware_locked)
1261 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1262}
1263
1da177e4
LT		 1264/****************************************************************************/
1265/* Driver Debug Functions. */
1266/****************************************************************************/
1267
fa2a1ce5 1268void
7b867cf7 1269qla2x00_dump_regs(scsi_qla_host_t *vha)
1da177e4 1270{
6afd9763 1271 int i;
7b867cf7 1272 struct qla_hw_data *ha = vha->hw;
3d71644c 1273 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6afd9763
AV		 1274 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
1275 uint16_t __iomem *mbx_reg;
1276
1277 mbx_reg = IS_FWI2_CAPABLE(ha) ? &reg24->mailbox0:
1278 MAILBOX_REG(ha, reg, 0);
1da177e4
LT		 1279
1280 printk("Mailbox registers:\n");
6afd9763 1281 for (i = 0; i < 6; i++)
7b867cf7 1282 printk("scsi(%ld): mbox %d 0x%04x \n", vha->host_no, i,
6afd9763 1283 RD_REG_WORD(mbx_reg++));
1da177e4
LT		 1284}
1285
1286
1287void
fa2a1ce5 1288qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1da177e4
LT		 1289{
1290 uint32_t cnt;
1291 uint8_t c;
1292
1293 printk(" 0 1 2 3 4 5 6 7 8 9 "
1294 "Ah Bh Ch Dh Eh Fh\n");
1295 printk("----------------------------------------"
1296 "----------------------\n");
1297
1298 for (cnt = 0; cnt < size;) {
1299 c = *b++;
1300 printk("%02x",(uint32_t) c);
1301 cnt++;
1302 if (!(cnt % 16))
1303 printk("\n");
1304 else
1305 printk(" ");
1306 }
1307 if (cnt % 16)
1308 printk("\n");
1309}
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