[net-next-2.6.git] / drivers / pcmcia / sa11xx_base.c

/*======================================================================

    Device driver for the PCMCIA control functionality of StrongARM
    SA-1100 microprocessors.

    The contents of this file are subject to the Mozilla Public
    License Version 1.1 (the "License"); you may not use this file
    except in compliance with the License. You may obtain a copy of
    the License at http://www.mozilla.org/MPL/

    Software distributed under the License is distributed on an "AS
    IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
    implied. See the License for the specific language governing
    rights and limitations under the License.

    The initial developer of the original code is John G. Dorsey
    <john+@cs.cmu.edu>.  Portions created by John G. Dorsey are
    Copyright (C) 1999 John G. Dorsey.  All Rights Reserved.

    Alternatively, the contents of this file may be used under the
    terms of the GNU Public License version 2 (the "GPL"), in which
    case the provisions of the GPL are applicable instead of the
    above.  If you wish to allow the use of your version of this file
    only under the terms of the GPL and not to allow others to use
    your version of this file under the MPL, indicate your decision
    by deleting the provisions above and replace them with the notice
    and other provisions required by the GPL.  If you do not delete
    the provisions above, a recipient may use your version of this
    file under either the MPL or the GPL.

======================================================================*/

#include <linux/module.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/slab.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/system.h>

#include "soc_common.h"
#include "sa11xx_base.h"


/*
 * sa1100_pcmcia_default_mecr_timing
 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 *
 * Calculate MECR clock wait states for given CPU clock
 * speed and command wait state. This function can be over-
 * written by a board specific version.
 *
 * The default is to simply calculate the BS values as specified in
 * the INTEL SA1100 development manual
 * "Expansion Memory (PCMCIA) Configuration Register (MECR)"
 * that's section 10.2.5 in _my_ version of the manual ;)
 */
static unsigned int
sa1100_pcmcia_default_mecr_timing(struct soc_pcmcia_socket *skt,
				  unsigned int cpu_speed,
				  unsigned int cmd_time)
{
	return sa1100_pcmcia_mecr_bs(cmd_time, cpu_speed);
}

/* sa1100_pcmcia_set_mecr()
 * ^^^^^^^^^^^^^^^^^^^^^^^^
 *
 * set MECR value for socket <sock> based on this sockets
 * io, mem and attribute space access speed.
 * Call board specific BS value calculation to allow boards
 * to tweak the BS values.
 */
static int
sa1100_pcmcia_set_mecr(struct soc_pcmcia_socket *skt, unsigned int cpu_clock)
{
	struct soc_pcmcia_timing timing;
	u32 mecr, old_mecr;
	unsigned long flags;
	unsigned int bs_io, bs_mem, bs_attr;

	soc_common_pcmcia_get_timing(skt, &timing);

	bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io);
	bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem);
	bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr);

	local_irq_save(flags);

	old_mecr = mecr = MECR;
	MECR_FAST_SET(mecr, skt->nr, 0);
	MECR_BSIO_SET(mecr, skt->nr, bs_io);
	MECR_BSA_SET(mecr, skt->nr, bs_attr);
	MECR_BSM_SET(mecr, skt->nr, bs_mem);
	if (old_mecr != mecr)
		MECR = mecr;

	local_irq_restore(flags);

	debug(skt, 2, "FAST %X  BSM %X  BSA %X  BSIO %X\n",
	      MECR_FAST_GET(mecr, skt->nr),
	      MECR_BSM_GET(mecr, skt->nr), MECR_BSA_GET(mecr, skt->nr),
	      MECR_BSIO_GET(mecr, skt->nr));

	return 0;
}

#ifdef CONFIG_CPU_FREQ
static int
sa1100_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
			       unsigned long val,
			       struct cpufreq_freqs *freqs)
{
	switch (val) {
	case CPUFREQ_PRECHANGE:
		if (freqs->new > freqs->old)
			sa1100_pcmcia_set_mecr(skt, freqs->new);
		break;

	case CPUFREQ_POSTCHANGE:
		if (freqs->new < freqs->old)
			sa1100_pcmcia_set_mecr(skt, freqs->new);
		break;
	case CPUFREQ_RESUMECHANGE:
		sa1100_pcmcia_set_mecr(skt, freqs->new);
		break;
	}

	return 0;
}

#endif

static int
sa1100_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
{
	return sa1100_pcmcia_set_mecr(skt, cpufreq_get(0));
}

static int
sa1100_pcmcia_show_timing(struct soc_pcmcia_socket *skt, char *buf)
{
	struct soc_pcmcia_timing timing;
	unsigned int clock = cpufreq_get(0);
	unsigned long mecr = MECR;
	char *p = buf;

	soc_common_pcmcia_get_timing(skt, &timing);

	p+=sprintf(p, "I/O      : %u (%u)\n", timing.io,
		   sa1100_pcmcia_cmd_time(clock, MECR_BSIO_GET(mecr, skt->nr)));

	p+=sprintf(p, "attribute: %u (%u)\n", timing.attr,
		   sa1100_pcmcia_cmd_time(clock, MECR_BSA_GET(mecr, skt->nr)));

	p+=sprintf(p, "common   : %u (%u)\n", timing.mem,
		   sa1100_pcmcia_cmd_time(clock, MECR_BSM_GET(mecr, skt->nr)));

	return p - buf;
}

static const char *skt_names[] = {
	"PCMCIA socket 0",
	"PCMCIA socket 1",
};

#define SKT_DEV_INFO_SIZE(n) \
	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))

int sa11xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
{
	skt->res_skt.start = _PCMCIA(skt->nr);
	skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
	skt->res_skt.name = skt_names[skt->nr];
	skt->res_skt.flags = IORESOURCE_MEM;

	skt->res_io.start = _PCMCIAIO(skt->nr);
	skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
	skt->res_io.name = "io";
	skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;

	skt->res_mem.start = _PCMCIAMem(skt->nr);
	skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
	skt->res_mem.name = "memory";
	skt->res_mem.flags = IORESOURCE_MEM;

	skt->res_attr.start = _PCMCIAAttr(skt->nr);
	skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
	skt->res_attr.name = "attribute";
	skt->res_attr.flags = IORESOURCE_MEM;

	return soc_pcmcia_add_one(skt);
}
EXPORT_SYMBOL(sa11xx_drv_pcmcia_add_one);

void sa11xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
{
	/*
	 * set default MECR calculation if the board specific
	 * code did not specify one...
	 */
	if (!ops->get_timing)
		ops->get_timing = sa1100_pcmcia_default_mecr_timing;

	/* Provide our SA11x0 specific timing routines. */
	ops->set_timing  = sa1100_pcmcia_set_timing;
	ops->show_timing = sa1100_pcmcia_show_timing;
#ifdef CONFIG_CPU_FREQ
	ops->frequency_change = sa1100_pcmcia_frequency_change;
#endif
}
EXPORT_SYMBOL(sa11xx_drv_pcmcia_ops);

int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops,
			    int first, int nr)
{
	struct skt_dev_info *sinfo;
	struct soc_pcmcia_socket *skt;
	int i, ret = 0;

	sa11xx_drv_pcmcia_ops(ops);

	sinfo = kzalloc(SKT_DEV_INFO_SIZE(nr), GFP_KERNEL);
	if (!sinfo)
		return -ENOMEM;

	sinfo->nskt = nr;

	/* Initiliaze processor specific parameters */
	for (i = 0; i < nr; i++) {
		skt = &sinfo->skt[i];

		skt->nr = first + i;
		skt->ops = ops;
		skt->socket.owner = ops->owner;
		skt->socket.dev.parent = dev;
		skt->socket.pci_irq = NO_IRQ;

		ret = sa11xx_drv_pcmcia_add_one(skt);
		if (ret)
			break;
	}

	if (ret) {
		while (--i >= 0)
			soc_pcmcia_remove_one(&sinfo->skt[i]);
		kfree(sinfo);
	} else {
		dev_set_drvdata(dev, sinfo);
	}

	return ret;
}
EXPORT_SYMBOL(sa11xx_drv_pcmcia_probe);

static int __init sa11xx_pcmcia_init(void)
{
	return 0;
}
fs_initcall(sa11xx_pcmcia_init);

static void __exit sa11xx_pcmcia_exit(void) {}

module_exit(sa11xx_pcmcia_exit);

MODULE_AUTHOR("John Dorsey <john+@cs.cmu.edu>");
MODULE_DESCRIPTION("Linux PCMCIA Card Services: SA-11xx core socket driver");
MODULE_LICENSE("Dual MPL/GPL");
Commit	Line	Data
1da177e4 LT	1	/*======================================================================
	2
	3	Device driver for the PCMCIA control functionality of StrongARM
	4	SA-1100 microprocessors.
	5
	6	The contents of this file are subject to the Mozilla Public
	7	License Version 1.1 (the "License"); you may not use this file
	8	except in compliance with the License. You may obtain a copy of
	9	the License at http://www.mozilla.org/MPL/
	10
	11	Software distributed under the License is distributed on an "AS
	12	IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
	13	implied. See the License for the specific language governing
	14	rights and limitations under the License.
	15
	16	The initial developer of the original code is John G. Dorsey
	17	<john+@cs.cmu.edu>. Portions created by John G. Dorsey are
	18	Copyright (C) 1999 John G. Dorsey. All Rights Reserved.
	19
	20	Alternatively, the contents of this file may be used under the
	21	terms of the GNU Public License version 2 (the "GPL"), in which
	22	case the provisions of the GPL are applicable instead of the
	23	above. If you wish to allow the use of your version of this file
	24	only under the terms of the GPL and not to allow others to use
	25	your version of this file under the MPL, indicate your decision
	26	by deleting the provisions above and replace them with the notice
	27	and other provisions required by the GPL. If you do not delete
	28	the provisions above, a recipient may use your version of this
	29	file under either the MPL or the GPL.
	30
	31	======================================================================*/
	32
	33	#include <linux/module.h>
	34	#include <linux/init.h>
1da177e4 LT	35	#include <linux/cpufreq.h>
	36	#include <linux/ioport.h>
	37	#include <linux/kernel.h>
	38	#include <linux/spinlock.h>
99730225	39	#include <linux/io.h>
5a0e3ad6	40	#include <linux/slab.h>
1da177e4	41
a09e64fb	42	#include <mach/hardware.h>
1da177e4 LT	43	#include <asm/irq.h>
	44	#include <asm/system.h>
	45
	46	#include "soc_common.h"
	47	#include "sa11xx_base.h"
	48
	49
	50	/*
	51	* sa1100_pcmcia_default_mecr_timing
	52	* ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
	53	*
	54	* Calculate MECR clock wait states for given CPU clock
	55	* speed and command wait state. This function can be over-
	56	* written by a board specific version.
	57	*
	58	* The default is to simply calculate the BS values as specified in
	59	* the INTEL SA1100 development manual
	60	* "Expansion Memory (PCMCIA) Configuration Register (MECR)"
	61	* that's section 10.2.5 in _my_ version of the manual ;)
	62	*/
	63	static unsigned int
	64	sa1100_pcmcia_default_mecr_timing(struct soc_pcmcia_socket *skt,
	65	unsigned int cpu_speed,
	66	unsigned int cmd_time)
	67	{
	68	return sa1100_pcmcia_mecr_bs(cmd_time, cpu_speed);
	69	}
	70
	71	/* sa1100_pcmcia_set_mecr()
	72	* ^^^^^^^^^^^^^^^^^^^^^^^^
	73	*
	74	* set MECR value for socket <sock> based on this sockets
	75	* io, mem and attribute space access speed.
	76	* Call board specific BS value calculation to allow boards
	77	* to tweak the BS values.
	78	*/
	79	static int
	80	sa1100_pcmcia_set_mecr(struct soc_pcmcia_socket *skt, unsigned int cpu_clock)
	81	{
	82	struct soc_pcmcia_timing timing;
	83	u32 mecr, old_mecr;
	84	unsigned long flags;
	85	unsigned int bs_io, bs_mem, bs_attr;
	86
	87	soc_common_pcmcia_get_timing(skt, &timing);
	88
	89	bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io);
	90	bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem);
	91	bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr);
	92
	93	local_irq_save(flags);
	94
	95	old_mecr = mecr = MECR;
	96	MECR_FAST_SET(mecr, skt->nr, 0);
	97	MECR_BSIO_SET(mecr, skt->nr, bs_io);
	98	MECR_BSA_SET(mecr, skt->nr, bs_attr);
	99	MECR_BSM_SET(mecr, skt->nr, bs_mem);
	100	if (old_mecr != mecr)
	101	MECR = mecr;
	102
	103	local_irq_restore(flags);
	104
	105	debug(skt, 2, "FAST %X BSM %X BSA %X BSIO %X\n",
	106	MECR_FAST_GET(mecr, skt->nr),
107	MECR_BSM_GET(mecr, skt->nr), MECR_BSA_GET(mecr, skt->nr),
108	MECR_BSIO_GET(mecr, skt->nr));
109
110	return 0;
111	}
112
113	#ifdef CONFIG_CPU_FREQ
114	static int
115	sa1100_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
116	unsigned long val,
117	struct cpufreq_freqs *freqs)
118	{
119	switch (val) {
120	case CPUFREQ_PRECHANGE:
121	if (freqs->new > freqs->old)
122	sa1100_pcmcia_set_mecr(skt, freqs->new);
123	break;
124
125	case CPUFREQ_POSTCHANGE:
126	if (freqs->new < freqs->old)
127	sa1100_pcmcia_set_mecr(skt, freqs->new);
128	break;
129	case CPUFREQ_RESUMECHANGE:
130	sa1100_pcmcia_set_mecr(skt, freqs->new);
131	break;
132	}
133
134	return 0;
135	}
136
137	#endif
138
139	static int
140	sa1100_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
141	{
142	return sa1100_pcmcia_set_mecr(skt, cpufreq_get(0));
143	}
144
145	static int
146	sa1100_pcmcia_show_timing(struct soc_pcmcia_socket skt, char buf)
147	{
148	struct soc_pcmcia_timing timing;
149	unsigned int clock = cpufreq_get(0);
150	unsigned long mecr = MECR;
151	char *p = buf;
152
153	soc_common_pcmcia_get_timing(skt, &timing);
154
155	p+=sprintf(p, "I/O : %u (%u)\n", timing.io,
156	sa1100_pcmcia_cmd_time(clock, MECR_BSIO_GET(mecr, skt->nr)));
157
158	p+=sprintf(p, "attribute: %u (%u)\n", timing.attr,
159	sa1100_pcmcia_cmd_time(clock, MECR_BSA_GET(mecr, skt->nr)));
160
161	p+=sprintf(p, "common : %u (%u)\n", timing.mem,
162	sa1100_pcmcia_cmd_time(clock, MECR_BSM_GET(mecr, skt->nr)));
163
164	return p - buf;
165	}
166
b393c696 EM	167	static const char *skt_names[] = {
	168	"PCMCIA socket 0",
	169	"PCMCIA socket 1",
	170	};
	171
	172	#define SKT_DEV_INFO_SIZE(n) \
	173	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
	174
701a5dc0	175	int sa11xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
da4f0073 RKAL	176	{
	177	skt->res_skt.start = _PCMCIA(skt->nr);
	178	skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
	179	skt->res_skt.name = skt_names[skt->nr];
	180	skt->res_skt.flags = IORESOURCE_MEM;
	181
	182	skt->res_io.start = _PCMCIAIO(skt->nr);
	183	skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
	184	skt->res_io.name = "io";
	185	skt->res_io.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
	186
	187	skt->res_mem.start = _PCMCIAMem(skt->nr);
	188	skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
	189	skt->res_mem.name = "memory";
	190	skt->res_mem.flags = IORESOURCE_MEM;
	191
	192	skt->res_attr.start = _PCMCIAAttr(skt->nr);
	193	skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
	194	skt->res_attr.name = "attribute";
	195	skt->res_attr.flags = IORESOURCE_MEM;
	196
	197	return soc_pcmcia_add_one(skt);
	198	}
701a5dc0	199	EXPORT_SYMBOL(sa11xx_drv_pcmcia_add_one);
da4f0073	200
701a5dc0	201	void sa11xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
1da177e4 LT	202	{
	203	/*
	204	* set default MECR calculation if the board specific
	205	* code did not specify one...
	206	*/
	207	if (!ops->get_timing)
	208	ops->get_timing = sa1100_pcmcia_default_mecr_timing;
	209
	210	/* Provide our SA11x0 specific timing routines. */
	211	ops->set_timing = sa1100_pcmcia_set_timing;
	212	ops->show_timing = sa1100_pcmcia_show_timing;
	213	#ifdef CONFIG_CPU_FREQ
	214	ops->frequency_change = sa1100_pcmcia_frequency_change;
	215	#endif
701a5dc0 RKAL	216	}
	217	EXPORT_SYMBOL(sa11xx_drv_pcmcia_ops);
	218
	219	int sa11xx_drv_pcmcia_probe(struct device dev, struct pcmcia_low_level ops,
	220	int first, int nr)
	221	{
	222	struct skt_dev_info *sinfo;
	223	struct soc_pcmcia_socket *skt;
	224	int i, ret = 0;
	225
	226	sa11xx_drv_pcmcia_ops(ops);
1da177e4	227
da4f0073 RKAL	228	sinfo = kzalloc(SKT_DEV_INFO_SIZE(nr), GFP_KERNEL);
	229	if (!sinfo)
	230	return -ENOMEM;
	231
	232	sinfo->nskt = nr;
	233
	234	/* Initiliaze processor specific parameters */
	235	for (i = 0; i < nr; i++) {
	236	skt = &sinfo->skt[i];
	237
	238	skt->nr = first + i;
da4f0073 RKAL	239	skt->ops = ops;
	240	skt->socket.owner = ops->owner;
	241	skt->socket.dev.parent = dev;
66024db5	242	skt->socket.pci_irq = NO_IRQ;
da4f0073 RKAL	243
	244	ret = sa11xx_drv_pcmcia_add_one(skt);
	245	if (ret)
	246	break;
	247	}
	248
	249	if (ret) {
	250	while (--i >= 0)
	251	soc_pcmcia_remove_one(&sinfo->skt[i]);
	252	kfree(sinfo);
	253	} else {
	254	dev_set_drvdata(dev, sinfo);
	255	}
	256
	257	return ret;
1da177e4 LT	258	}
	259	EXPORT_SYMBOL(sa11xx_drv_pcmcia_probe);
	260
	261	static int __init sa11xx_pcmcia_init(void)
	262	{
	263	return 0;
	264	}
f36598ae	265	fs_initcall(sa11xx_pcmcia_init);
1da177e4 LT	266
	267	static void __exit sa11xx_pcmcia_exit(void) {}
	268
	269	module_exit(sa11xx_pcmcia_exit);
	270
	271	MODULE_AUTHOR("John Dorsey <john+@cs.cmu.edu>");
	272	MODULE_DESCRIPTION("Linux PCMCIA Card Services: SA-11xx core socket driver");
	273	MODULE_LICENSE("Dual MPL/GPL");