]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/wireless/rt2x00/rt61pci.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[net-next-2.6.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
95ea3627
ID		 34#include <linux/pci.h>
35#include <linux/eeprom_93cx6.h>
36
37#include "rt2x00.h"
38#include "rt2x00pci.h"
39#include "rt61pci.h"
40
008c4482
ID		 41/*
42 * Allow hardware encryption to be disabled.
43 */
44static int modparam_nohwcrypt = 0;
45module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
46MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
47
95ea3627
ID		 48/*
49 * Register access.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
b34e620f 55 * between each attempt. When the busy bit is still set at that time,
95ea3627
ID		 56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 */
c9c3b1a5
ID		 59#define WAIT_FOR_BBP(__dev, __reg) \
60 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61#define WAIT_FOR_RF(__dev, __reg) \
62 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63#define WAIT_FOR_MCU(__dev, __reg) \
64 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65 H2M_MAILBOX_CSR_OWNER, (__reg))
95ea3627 66
0e14f6d3 67static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
8ff48a8b
ID		 72 mutex_lock(&rt2x00dev->csr_mutex);
73
95ea3627 74 /*
c9c3b1a5
ID		 75 * Wait until the BBP becomes available, afterwards we
76 * can safely write the new data into the register.
95ea3627 77 */
c9c3b1a5
ID		 78 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
79 reg = 0;
80 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
81 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
82 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
83 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
84
85 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
86 }
8ff48a8b 87
8ff48a8b 88 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 89}
90
0e14f6d3 91static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 92 const unsigned int word, u8 *value)
93{
94 u32 reg;
95
8ff48a8b
ID		 96 mutex_lock(&rt2x00dev->csr_mutex);
97
95ea3627 98 /*
c9c3b1a5
ID		 99 * Wait until the BBP becomes available, afterwards we
100 * can safely write the read request into the register.
101 * After the data has been written, we wait until hardware
102 * returns the correct value, if at any time the register
103 * doesn't become available in time, reg will be 0xffffffff
104 * which means we return 0xff to the caller.
95ea3627 105 */
c9c3b1a5
ID		 106 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
107 reg = 0;
108 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
109 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
110 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 111
c9c3b1a5 112 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
95ea3627 113
c9c3b1a5
ID		 114 WAIT_FOR_BBP(rt2x00dev, &reg);
115 }
95ea3627
ID		 116
117 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
8ff48a8b 118
8ff48a8b 119 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 120}
121
0e14f6d3 122static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 123 const unsigned int word, const u32 value)
124{
125 u32 reg;
95ea3627 126
8ff48a8b
ID		 127 mutex_lock(&rt2x00dev->csr_mutex);
128
c9c3b1a5
ID		 129 /*
130 * Wait until the RF becomes available, afterwards we
131 * can safely write the new data into the register.
132 */
133 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
134 reg = 0;
135 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
136 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
137 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
138 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
139
140 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
141 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 142 }
143
8ff48a8b 144 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 145}
146
0e14f6d3 147static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 148 const u8 command, const u8 token,
149 const u8 arg0, const u8 arg1)
150{
151 u32 reg;
152
8ff48a8b
ID		 153 mutex_lock(&rt2x00dev->csr_mutex);
154
c9c3b1a5
ID		 155 /*
156 * Wait until the MCU becomes available, afterwards we
157 * can safely write the new data into the register.
158 */
159 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
160 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
161 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
162 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
163 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
164 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
165
166 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
167 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
168 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
169 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
170 }
8ff48a8b 171
8ff48a8b
ID		 172 mutex_unlock(&rt2x00dev->csr_mutex);
173
95ea3627
ID		 174}
175
176static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
177{
178 struct rt2x00_dev *rt2x00dev = eeprom->data;
179 u32 reg;
180
181 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
182
183 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
184 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
185 eeprom->reg_data_clock =
186 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
187 eeprom->reg_chip_select =
188 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
189}
190
191static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
192{
193 struct rt2x00_dev *rt2x00dev = eeprom->data;
194 u32 reg = 0;
195
196 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
197 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
198 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
199 !!eeprom->reg_data_clock);
200 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
201 !!eeprom->reg_chip_select);
202
203 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
204}
205
206#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 207static const struct rt2x00debug rt61pci_rt2x00debug = {
208 .owner = THIS_MODULE,
209 .csr = {
743b97ca
ID		 210 .read = rt2x00pci_register_read,
211 .write = rt2x00pci_register_write,
212 .flags = RT2X00DEBUGFS_OFFSET,
213 .word_base = CSR_REG_BASE,
95ea3627
ID		 214 .word_size = sizeof(u32),
215 .word_count = CSR_REG_SIZE / sizeof(u32),
216 },
217 .eeprom = {
218 .read = rt2x00_eeprom_read,
219 .write = rt2x00_eeprom_write,
743b97ca 220 .word_base = EEPROM_BASE,
95ea3627
ID		 221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt61pci_bbp_read,
226 .write = rt61pci_bbp_write,
743b97ca 227 .word_base = BBP_BASE,
95ea3627
ID		 228 .word_size = sizeof(u8),
229 .word_count = BBP_SIZE / sizeof(u8),
230 },
231 .rf = {
232 .read = rt2x00_rf_read,
233 .write = rt61pci_rf_write,
743b97ca 234 .word_base = RF_BASE,
95ea3627
ID		 235 .word_size = sizeof(u32),
236 .word_count = RF_SIZE / sizeof(u32),
237 },
238};
239#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
240
95ea3627
ID		 241static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
242{
243 u32 reg;
244
245 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 246 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 247}
95ea3627 248
771fd565 249#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 250static void rt61pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 251 enum led_brightness brightness)
252{
253 struct rt2x00_led *led =
254 container_of(led_cdev, struct rt2x00_led, led_dev);
255 unsigned int enabled = brightness != LED_OFF;
256 unsigned int a_mode =
257 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
258 unsigned int bg_mode =
259 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
260
261 if (led->type == LED_TYPE_RADIO) {
262 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
263 MCU_LEDCS_RADIO_STATUS, enabled);
264
265 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
266 (led->rt2x00dev->led_mcu_reg & 0xff),
267 ((led->rt2x00dev->led_mcu_reg >> 8)));
268 } else if (led->type == LED_TYPE_ASSOC) {
269 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
270 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
271 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
272 MCU_LEDCS_LINK_A_STATUS, a_mode);
273
274 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
275 (led->rt2x00dev->led_mcu_reg & 0xff),
276 ((led->rt2x00dev->led_mcu_reg >> 8)));
277 } else if (led->type == LED_TYPE_QUALITY) {
278 /*
279 * The brightness is divided into 6 levels (0 - 5),
280 * this means we need to convert the brightness
281 * argument into the matching level within that range.
282 */
283 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
284 brightness / (LED_FULL / 6), 0);
285 }
286}
a2e1d52a
ID		 287
288static int rt61pci_blink_set(struct led_classdev *led_cdev,
289 unsigned long *delay_on,
290 unsigned long *delay_off)
291{
292 struct rt2x00_led *led =
293 container_of(led_cdev, struct rt2x00_led, led_dev);
294 u32 reg;
295
296 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
297 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
298 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
299 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
300
301 return 0;
302}
475433be
ID		 303
304static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
305 struct rt2x00_led *led,
306 enum led_type type)
307{
308 led->rt2x00dev = rt2x00dev;
309 led->type = type;
310 led->led_dev.brightness_set = rt61pci_brightness_set;
311 led->led_dev.blink_set = rt61pci_blink_set;
312 led->flags = LED_INITIALIZED;
313}
771fd565 314#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 315
95ea3627
ID		 316/*
317 * Configuration handlers.
318 */
61e754f4
ID		 319static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
320 struct rt2x00lib_crypto *crypto,
321 struct ieee80211_key_conf *key)
322{
323 struct hw_key_entry key_entry;
324 struct rt2x00_field32 field;
325 u32 mask;
326 u32 reg;
327
328 if (crypto->cmd == SET_KEY) {
329 /*
330 * rt2x00lib can't determine the correct free
331 * key_idx for shared keys. We have 1 register
332 * with key valid bits. The goal is simple, read
333 * the register, if that is full we have no slots
334 * left.
335 * Note that each BSS is allowed to have up to 4
336 * shared keys, so put a mask over the allowed
337 * entries.
338 */
339 mask = (0xf << crypto->bssidx);
340
341 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
342 reg &= mask;
343
344 if (reg && reg == mask)
345 return -ENOSPC;
346
acaf908d 347 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 348
349 /*
350 * Upload key to hardware
351 */
352 memcpy(key_entry.key, crypto->key,
353 sizeof(key_entry.key));
354 memcpy(key_entry.tx_mic, crypto->tx_mic,
355 sizeof(key_entry.tx_mic));
356 memcpy(key_entry.rx_mic, crypto->rx_mic,
357 sizeof(key_entry.rx_mic));
358
359 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
360 rt2x00pci_register_multiwrite(rt2x00dev, reg,
361 &key_entry, sizeof(key_entry));
362
363 /*
364 * The cipher types are stored over 2 registers.
365 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
366 * bssidx 1 and 2 keys are stored in SEC_CSR5.
367 * Using the correct defines correctly will cause overhead,
368 * so just calculate the correct offset.
369 */
370 if (key->hw_key_idx < 8) {
371 field.bit_offset = (3 * key->hw_key_idx);
372 field.bit_mask = 0x7 << field.bit_offset;
373
374 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
375 rt2x00_set_field32(&reg, field, crypto->cipher);
376 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
377 } else {
378 field.bit_offset = (3 * (key->hw_key_idx - 8));
379 field.bit_mask = 0x7 << field.bit_offset;
380
381 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
382 rt2x00_set_field32(&reg, field, crypto->cipher);
383 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
384 }
385
386 /*
387 * The driver does not support the IV/EIV generation
388 * in hardware. However it doesn't support the IV/EIV
389 * inside the ieee80211 frame either, but requires it
b34e620f 390 * to be provided separately for the descriptor.
61e754f4
ID		 391 * rt2x00lib will cut the IV/EIV data out of all frames
392 * given to us by mac80211, but we must tell mac80211
393 * to generate the IV/EIV data.
394 */
395 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
396 }
397
398 /*
399 * SEC_CSR0 contains only single-bit fields to indicate
400 * a particular key is valid. Because using the FIELD32()
b34e620f 401 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 402 * a calculation to determine the correct bit directly.
403 */
404 mask = 1 << key->hw_key_idx;
405
406 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
407 if (crypto->cmd == SET_KEY)
408 reg |= mask;
409 else if (crypto->cmd == DISABLE_KEY)
410 reg &= ~mask;
411 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
412
413 return 0;
414}
415
416static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
417 struct rt2x00lib_crypto *crypto,
418 struct ieee80211_key_conf *key)
419{
420 struct hw_pairwise_ta_entry addr_entry;
421 struct hw_key_entry key_entry;
422 u32 mask;
423 u32 reg;
424
425 if (crypto->cmd == SET_KEY) {
426 /*
427 * rt2x00lib can't determine the correct free
428 * key_idx for pairwise keys. We have 2 registers
b34e620f
TLSC		 429 * with key valid bits. The goal is simple: read
430 * the first register. If that is full, move to
61e754f4 431 * the next register.
b34e620f
TLSC		 432 * When both registers are full, we drop the key.
433 * Otherwise, we use the first invalid entry.
61e754f4
ID		 434 */
435 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
436 if (reg && reg == ~0) {
437 key->hw_key_idx = 32;
438 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
439 if (reg && reg == ~0)
440 return -ENOSPC;
441 }
442
acaf908d 443 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 444
445 /*
446 * Upload key to hardware
447 */
448 memcpy(key_entry.key, crypto->key,
449 sizeof(key_entry.key));
450 memcpy(key_entry.tx_mic, crypto->tx_mic,
451 sizeof(key_entry.tx_mic));
452 memcpy(key_entry.rx_mic, crypto->rx_mic,
453 sizeof(key_entry.rx_mic));
454
455 memset(&addr_entry, 0, sizeof(addr_entry));
456 memcpy(&addr_entry, crypto->address, ETH_ALEN);
457 addr_entry.cipher = crypto->cipher;
458
459 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
460 rt2x00pci_register_multiwrite(rt2x00dev, reg,
461 &key_entry, sizeof(key_entry));
462
463 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
464 rt2x00pci_register_multiwrite(rt2x00dev, reg,
465 &addr_entry, sizeof(addr_entry));
466
467 /*
b34e620f
TLSC		 468 * Enable pairwise lookup table for given BSS idx.
469 * Without this, received frames will not be decrypted
61e754f4
ID		 470 * by the hardware.
471 */
472 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
473 reg |= (1 << crypto->bssidx);
474 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
475
476 /*
477 * The driver does not support the IV/EIV generation
478 * in hardware. However it doesn't support the IV/EIV
479 * inside the ieee80211 frame either, but requires it
3ad2f3fb 480 * to be provided separately for the descriptor.
61e754f4
ID		 481 * rt2x00lib will cut the IV/EIV data out of all frames
482 * given to us by mac80211, but we must tell mac80211
483 * to generate the IV/EIV data.
484 */
485 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
486 }
487
488 /*
489 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
490 * a particular key is valid. Because using the FIELD32()
b34e620f 491 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 492 * a calculation to determine the correct bit directly.
493 */
494 if (key->hw_key_idx < 32) {
495 mask = 1 << key->hw_key_idx;
496
497 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
498 if (crypto->cmd == SET_KEY)
499 reg |= mask;
500 else if (crypto->cmd == DISABLE_KEY)
501 reg &= ~mask;
502 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
503 } else {
504 mask = 1 << (key->hw_key_idx - 32);
505
506 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
507 if (crypto->cmd == SET_KEY)
508 reg |= mask;
509 else if (crypto->cmd == DISABLE_KEY)
510 reg &= ~mask;
511 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
512 }
513
514 return 0;
515}
516
3a643d24
ID		 517static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
518 const unsigned int filter_flags)
519{
520 u32 reg;
521
522 /*
523 * Start configuration steps.
524 * Note that the version error will always be dropped
525 * and broadcast frames will always be accepted since
526 * there is no filter for it at this time.
527 */
528 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
529 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
530 !(filter_flags & FIF_FCSFAIL));
531 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
532 !(filter_flags & FIF_PLCPFAIL));
533 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 534 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
3a643d24
ID		 535 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
536 !(filter_flags & FIF_PROMISC_IN_BSS));
537 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 538 !(filter_flags & FIF_PROMISC_IN_BSS) &&
539 !rt2x00dev->intf_ap_count);
3a643d24
ID		 540 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
541 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
542 !(filter_flags & FIF_ALLMULTI));
543 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
544 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
545 !(filter_flags & FIF_CONTROL));
546 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
547}
548
6bb40dd1
ID		 549static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
550 struct rt2x00_intf *intf,
551 struct rt2x00intf_conf *conf,
552 const unsigned int flags)
95ea3627 553{
6bb40dd1
ID		 554 unsigned int beacon_base;
555 u32 reg;
95ea3627 556
6bb40dd1
ID		 557 if (flags & CONFIG_UPDATE_TYPE) {
558 /*
559 * Clear current synchronisation setup.
b34e620f 560 * For the Beacon base registers, we only need to clear
6bb40dd1
ID		 561 * the first byte since that byte contains the VALID and OWNER
562 * bits which (when set to 0) will invalidate the entire beacon.
563 */
564 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 565 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 566
6bb40dd1
ID		 567 /*
568 * Enable synchronisation.
569 */
570 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 571 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 572 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 573 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
575 }
95ea3627 576
6bb40dd1
ID		 577 if (flags & CONFIG_UPDATE_MAC) {
578 reg = le32_to_cpu(conf->mac[1]);
579 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
580 conf->mac[1] = cpu_to_le32(reg);
95ea3627 581
6bb40dd1
ID		 582 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
583 conf->mac, sizeof(conf->mac));
584 }
95ea3627 585
6bb40dd1
ID		 586 if (flags & CONFIG_UPDATE_BSSID) {
587 reg = le32_to_cpu(conf->bssid[1]);
588 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
589 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 590
6bb40dd1
ID		 591 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
592 conf->bssid, sizeof(conf->bssid));
593 }
95ea3627
ID		 594}
595
3a643d24
ID		 596static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
597 struct rt2x00lib_erp *erp)
95ea3627 598{
95ea3627 599 u32 reg;
95ea3627
ID		 600
601 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 602 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 603 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
95ea3627
ID		 604 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
605
606 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
8a566afe 607 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
4f5af6eb 608 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 609 !!erp->short_preamble);
95ea3627 610 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 611
e4ea1c40 612 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 613
8a566afe
ID		 614 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
615 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
616 erp->beacon_int * 16);
617 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
618
e4ea1c40
ID		 619 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
620 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
621 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 622
e4ea1c40
ID		 623 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
624 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
625 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
626 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
627 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 628}
629
630static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 631 struct antenna_setup *ant)
95ea3627
ID		 632{
633 u8 r3;
634 u8 r4;
635 u8 r77;
636
637 rt61pci_bbp_read(rt2x00dev, 3, &r3);
638 rt61pci_bbp_read(rt2x00dev, 4, &r4);
639 rt61pci_bbp_read(rt2x00dev, 77, &r77);
640
5122d898 641 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
e4cd2ff8
ID		 642
643 /*
644 * Configure the RX antenna.
645 */
addc81bd 646 switch (ant->rx) {
95ea3627 647 case ANTENNA_HW_DIVERSITY:
acaa410d 648 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 649 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 650 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 651 break;
652 case ANTENNA_A:
acaa410d 653 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 654 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 655 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 656 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
657 else
658 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 659 break;
660 case ANTENNA_B:
a4fe07d9 661 default:
acaa410d 662 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 663 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 664 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 665 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
666 else
667 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 668 break;
669 }
670
671 rt61pci_bbp_write(rt2x00dev, 77, r77);
672 rt61pci_bbp_write(rt2x00dev, 3, r3);
673 rt61pci_bbp_write(rt2x00dev, 4, r4);
674}
675
676static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 677 struct antenna_setup *ant)
95ea3627
ID		 678{
679 u8 r3;
680 u8 r4;
681 u8 r77;
682
683 rt61pci_bbp_read(rt2x00dev, 3, &r3);
684 rt61pci_bbp_read(rt2x00dev, 4, &r4);
685 rt61pci_bbp_read(rt2x00dev, 77, &r77);
686
5122d898 687 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
95ea3627
ID		 688 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
689 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
690
e4cd2ff8
ID		 691 /*
692 * Configure the RX antenna.
693 */
addc81bd 694 switch (ant->rx) {
95ea3627 695 case ANTENNA_HW_DIVERSITY:
acaa410d 696 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 697 break;
698 case ANTENNA_A:
acaa410d
MN		 699 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
700 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 701 break;
702 case ANTENNA_B:
a4fe07d9 703 default:
acaa410d
MN		 704 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
705 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 706 break;
707 }
708
709 rt61pci_bbp_write(rt2x00dev, 77, r77);
710 rt61pci_bbp_write(rt2x00dev, 3, r3);
711 rt61pci_bbp_write(rt2x00dev, 4, r4);
712}
713
714static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
715 const int p1, const int p2)
716{
717 u32 reg;
718
719 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
720
acaa410d
MN		 721 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
722 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
723
724 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
725 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
726
727 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 728}
729
730static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 731 struct antenna_setup *ant)
95ea3627 732{
95ea3627
ID		 733 u8 r3;
734 u8 r4;
735 u8 r77;
736
737 rt61pci_bbp_read(rt2x00dev, 3, &r3);
738 rt61pci_bbp_read(rt2x00dev, 4, &r4);
739 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 740
e4cd2ff8
ID		 741 /*
742 * Configure the RX antenna.
743 */
744 switch (ant->rx) {
745 case ANTENNA_A:
acaa410d
MN		 746 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
747 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
748 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 749 break;
e4cd2ff8
ID		 750 case ANTENNA_HW_DIVERSITY:
751 /*
a4fe07d9
ID		 752 * FIXME: Antenna selection for the rf 2529 is very confusing
753 * in the legacy driver. Just default to antenna B until the
754 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 755 */
756 case ANTENNA_B:
a4fe07d9 757 default:
acaa410d
MN		 758 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
759 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
760 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 761 break;
762 }
763
e4cd2ff8 764 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 765 rt61pci_bbp_write(rt2x00dev, 3, r3);
766 rt61pci_bbp_write(rt2x00dev, 4, r4);
767}
768
769struct antenna_sel {
770 u8 word;
771 /*
772 * value[0] -> non-LNA
773 * value[1] -> LNA
774 */
775 u8 value[2];
776};
777
778static const struct antenna_sel antenna_sel_a[] = {
779 { 96, { 0x58, 0x78 } },
780 { 104, { 0x38, 0x48 } },
781 { 75, { 0xfe, 0x80 } },
782 { 86, { 0xfe, 0x80 } },
783 { 88, { 0xfe, 0x80 } },
784 { 35, { 0x60, 0x60 } },
785 { 97, { 0x58, 0x58 } },
786 { 98, { 0x58, 0x58 } },
787};
788
789static const struct antenna_sel antenna_sel_bg[] = {
790 { 96, { 0x48, 0x68 } },
791 { 104, { 0x2c, 0x3c } },
792 { 75, { 0xfe, 0x80 } },
793 { 86, { 0xfe, 0x80 } },
794 { 88, { 0xfe, 0x80 } },
795 { 35, { 0x50, 0x50 } },
796 { 97, { 0x48, 0x48 } },
797 { 98, { 0x48, 0x48 } },
798};
799
e4ea1c40
ID		 800static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
801 struct antenna_setup *ant)
95ea3627
ID		 802{
803 const struct antenna_sel *sel;
804 unsigned int lna;
805 unsigned int i;
806 u32 reg;
807
a4fe07d9
ID		 808 /*
809 * We should never come here because rt2x00lib is supposed
810 * to catch this and send us the correct antenna explicitely.
811 */
812 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
813 ant->tx == ANTENNA_SW_DIVERSITY);
814
8318d78a 815 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 816 sel = antenna_sel_a;
817 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 818 } else {
819 sel = antenna_sel_bg;
820 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 821 }
822
acaa410d
MN		 823 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
824 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
825
826 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
827
ddc827f9 828 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 829 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 830 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 831 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 832
95ea3627
ID		 833 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
834
5122d898 835 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
addc81bd 836 rt61pci_config_antenna_5x(rt2x00dev, ant);
5122d898 837 else if (rt2x00_rf(rt2x00dev, RF2527))
addc81bd 838 rt61pci_config_antenna_2x(rt2x00dev, ant);
5122d898 839 else if (rt2x00_rf(rt2x00dev, RF2529)) {
95ea3627 840 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 841 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 842 else
addc81bd 843 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 844 }
845}
846
e4ea1c40
ID		 847static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
848 struct rt2x00lib_conf *libconf)
849{
850 u16 eeprom;
851 short lna_gain = 0;
852
853 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
854 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
855 lna_gain += 14;
856
857 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
858 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
859 } else {
860 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
861 lna_gain += 14;
862
863 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
864 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
865 }
866
867 rt2x00dev->lna_gain = lna_gain;
868}
869
870static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
871 struct rf_channel *rf, const int txpower)
872{
873 u8 r3;
874 u8 r94;
875 u8 smart;
876
877 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
878 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
879
5122d898 880 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
e4ea1c40
ID		 881
882 rt61pci_bbp_read(rt2x00dev, 3, &r3);
883 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
884 rt61pci_bbp_write(rt2x00dev, 3, r3);
885
886 r94 = 6;
887 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
888 r94 += txpower - MAX_TXPOWER;
889 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
890 r94 += txpower;
891 rt61pci_bbp_write(rt2x00dev, 94, r94);
892
893 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
894 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
895 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
896 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
897
898 udelay(200);
899
900 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
901 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
902 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
903 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
904
905 udelay(200);
906
907 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
908 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
909 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
910 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
911
912 msleep(1);
913}
914
915static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
916 const int txpower)
917{
918 struct rf_channel rf;
919
920 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
921 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
922 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
923 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
924
925 rt61pci_config_channel(rt2x00dev, &rf, txpower);
926}
927
928static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5c58ee51 929 struct rt2x00lib_conf *libconf)
95ea3627
ID		 930{
931 u32 reg;
932
e4ea1c40
ID		 933 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
934 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
935 libconf->conf->long_frame_max_tx_count);
936 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
937 libconf->conf->short_frame_max_tx_count);
938 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
939}
95ea3627 940
7d7f19cc
ID		 941static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
942 struct rt2x00lib_conf *libconf)
943{
944 enum dev_state state =
945 (libconf->conf->flags & IEEE80211_CONF_PS) ?
946 STATE_SLEEP : STATE_AWAKE;
947 u32 reg;
948
949 if (state == STATE_SLEEP) {
950 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
951 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 952 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 953 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
954 libconf->conf->listen_interval - 1);
955 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
956
957 /* We must first disable autowake before it can be enabled */
958 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
959 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
960
961 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
962 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
963
964 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
965 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
966 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
967
968 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
969 } else {
970 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
971 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
972 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
973 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
974 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
975 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
976
977 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
978 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
979 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
980
981 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
982 }
983}
984
95ea3627 985static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 986 struct rt2x00lib_conf *libconf,
987 const unsigned int flags)
95ea3627 988{
ba2ab471
ID		 989 /* Always recalculate LNA gain before changing configuration */
990 rt61pci_config_lna_gain(rt2x00dev, libconf);
991
e4ea1c40 992 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 993 rt61pci_config_channel(rt2x00dev, &libconf->rf,
994 libconf->conf->power_level);
e4ea1c40
ID		 995 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
996 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 997 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 998 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
999 rt61pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 1000 if (flags & IEEE80211_CONF_CHANGE_PS)
1001 rt61pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 1002}
1003
95ea3627
ID		 1004/*
1005 * Link tuning
1006 */
ebcf26da
ID		 1007static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1008 struct link_qual *qual)
95ea3627
ID		 1009{
1010 u32 reg;
1011
1012 /*
1013 * Update FCS error count from register.
1014 */
1015 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 1016 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 1017
1018 /*
1019 * Update False CCA count from register.
1020 */
1021 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 1022 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 1023}
1024
5352ff65
ID		 1025static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1026 struct link_qual *qual, u8 vgc_level)
eb20b4e8 1027{
5352ff65 1028 if (qual->vgc_level != vgc_level) {
eb20b4e8 1029 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 1030 qual->vgc_level = vgc_level;
1031 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 1032 }
1033}
1034
5352ff65
ID		 1035static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1036 struct link_qual *qual)
95ea3627 1037{
5352ff65 1038 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 1039}
1040
5352ff65
ID		 1041static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1042 struct link_qual *qual, const u32 count)
95ea3627 1043{
95ea3627
ID		 1044 u8 up_bound;
1045 u8 low_bound;
1046
95ea3627
ID		 1047 /*
1048 * Determine r17 bounds.
1049 */
1497074a 1050 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1051 low_bound = 0x28;
1052 up_bound = 0x48;
1053 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1054 low_bound += 0x10;
1055 up_bound += 0x10;
1056 }
1057 } else {
1058 low_bound = 0x20;
1059 up_bound = 0x40;
1060 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1061 low_bound += 0x10;
1062 up_bound += 0x10;
1063 }
1064 }
1065
6bb40dd1
ID		 1066 /*
1067 * If we are not associated, we should go straight to the
1068 * dynamic CCA tuning.
1069 */
1070 if (!rt2x00dev->intf_associated)
1071 goto dynamic_cca_tune;
1072
95ea3627
ID		 1073 /*
1074 * Special big-R17 for very short distance
1075 */
5352ff65
ID		 1076 if (qual->rssi >= -35) {
1077 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 1078 return;
1079 }
1080
1081 /*
1082 * Special big-R17 for short distance
1083 */
5352ff65
ID		 1084 if (qual->rssi >= -58) {
1085 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1086 return;
1087 }
1088
1089 /*
1090 * Special big-R17 for middle-short distance
1091 */
5352ff65
ID		 1092 if (qual->rssi >= -66) {
1093 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 1094 return;
1095 }
1096
1097 /*
1098 * Special mid-R17 for middle distance
1099 */
5352ff65
ID		 1100 if (qual->rssi >= -74) {
1101 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1102 return;
1103 }
1104
1105 /*
1106 * Special case: Change up_bound based on the rssi.
1107 * Lower up_bound when rssi is weaker then -74 dBm.
1108 */
5352ff65 1109 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1110 if (low_bound > up_bound)
1111 up_bound = low_bound;
1112
5352ff65
ID		 1113 if (qual->vgc_level > up_bound) {
1114 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1115 return;
1116 }
1117
6bb40dd1
ID		 1118dynamic_cca_tune:
1119
95ea3627
ID		 1120 /*
1121 * r17 does not yet exceed upper limit, continue and base
1122 * the r17 tuning on the false CCA count.
1123 */
5352ff65
ID		 1124 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1125 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1126 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1127 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 1128}
1129
1130/*
a7f3a06c 1131 * Firmware functions
95ea3627
ID		 1132 */
1133static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1134{
49e721ec 1135 u16 chip;
95ea3627
ID		 1136 char *fw_name;
1137
49e721ec
GW		 1138 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1139 switch (chip) {
1140 case RT2561_PCI_ID:
95ea3627
ID		 1141 fw_name = FIRMWARE_RT2561;
1142 break;
49e721ec 1143 case RT2561s_PCI_ID:
95ea3627
ID		 1144 fw_name = FIRMWARE_RT2561s;
1145 break;
49e721ec 1146 case RT2661_PCI_ID:
95ea3627
ID		 1147 fw_name = FIRMWARE_RT2661;
1148 break;
1149 default:
1150 fw_name = NULL;
1151 break;
1152 }
1153
1154 return fw_name;
1155}
1156
0cbe0064
ID		 1157static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1158 const u8 *data, const size_t len)
a7f3a06c 1159{
0cbe0064 1160 u16 fw_crc;
a7f3a06c
ID		 1161 u16 crc;
1162
1163 /*
0cbe0064
ID		 1164 * Only support 8kb firmware files.
1165 */
1166 if (len != 8192)
1167 return FW_BAD_LENGTH;
1168
1169 /*
b34e620f
TLSC		 1170 * The last 2 bytes in the firmware array are the crc checksum itself.
1171 * This means that we should never pass those 2 bytes to the crc
a7f3a06c
ID		 1172 * algorithm.
1173 */
0cbe0064
ID		 1174 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1175
1176 /*
1177 * Use the crc itu-t algorithm.
1178 */
a7f3a06c
ID		 1179 crc = crc_itu_t(0, data, len - 2);
1180 crc = crc_itu_t_byte(crc, 0);
1181 crc = crc_itu_t_byte(crc, 0);
1182
0cbe0064 1183 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1184}
1185
0cbe0064
ID		 1186static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1187 const u8 *data, const size_t len)
95ea3627
ID		 1188{
1189 int i;
1190 u32 reg;
1191
1192 /*
1193 * Wait for stable hardware.
1194 */
1195 for (i = 0; i < 100; i++) {
1196 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1197 if (reg)
1198 break;
1199 msleep(1);
1200 }
1201
1202 if (!reg) {
1203 ERROR(rt2x00dev, "Unstable hardware.\n");
1204 return -EBUSY;
1205 }
1206
1207 /*
1208 * Prepare MCU and mailbox for firmware loading.
1209 */
1210 reg = 0;
1211 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1212 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1213 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1214 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1215 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1216
1217 /*
1218 * Write firmware to device.
1219 */
1220 reg = 0;
1221 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1222 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1223 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1224
1225 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1226 data, len);
1227
1228 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1229 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1230
1231 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1232 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1233
1234 for (i = 0; i < 100; i++) {
1235 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1236 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1237 break;
1238 msleep(1);
1239 }
1240
1241 if (i == 100) {
1242 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1243 return -EBUSY;
1244 }
1245
e6d3e902
ID		 1246 /*
1247 * Hardware needs another millisecond before it is ready.
1248 */
1249 msleep(1);
1250
95ea3627
ID		 1251 /*
1252 * Reset MAC and BBP registers.
1253 */
1254 reg = 0;
1255 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1256 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1257 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1258
1259 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1260 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1261 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1262 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1263
1264 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1265 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1266 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1267
1268 return 0;
1269}
1270
a7f3a06c
ID		 1271/*
1272 * Initialization functions.
1273 */
798b7adb 1274static bool rt61pci_get_entry_state(struct queue_entry *entry)
95ea3627 1275{
b8be63ff 1276 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1277 u32 word;
1278
798b7adb
ID		 1279 if (entry->queue->qid == QID_RX) {
1280 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 1281
798b7adb
ID		 1282 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1283 } else {
1284 rt2x00_desc_read(entry_priv->desc, 0, &word);
1285
1286 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1287 rt2x00_get_field32(word, TXD_W0_VALID));
1288 }
95ea3627
ID		 1289}
1290
798b7adb 1291static void rt61pci_clear_entry(struct queue_entry *entry)
95ea3627 1292{
b8be63ff 1293 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 1294 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 1295 u32 word;
1296
798b7adb
ID		 1297 if (entry->queue->qid == QID_RX) {
1298 rt2x00_desc_read(entry_priv->desc, 5, &word);
1299 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1300 skbdesc->skb_dma);
1301 rt2x00_desc_write(entry_priv->desc, 5, word);
1302
1303 rt2x00_desc_read(entry_priv->desc, 0, &word);
1304 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1305 rt2x00_desc_write(entry_priv->desc, 0, word);
1306 } else {
1307 rt2x00_desc_read(entry_priv->desc, 0, &word);
1308 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1309 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1310 rt2x00_desc_write(entry_priv->desc, 0, word);
1311 }
95ea3627
ID		 1312}
1313
181d6902 1314static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1315{
b8be63ff 1316 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 1317 u32 reg;
1318
95ea3627
ID		 1319 /*
1320 * Initialize registers.
1321 */
1322 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1323 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1324 rt2x00dev->tx[0].limit);
95ea3627 1325 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1326 rt2x00dev->tx[1].limit);
95ea3627 1327 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1328 rt2x00dev->tx[2].limit);
95ea3627 1329 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1330 rt2x00dev->tx[3].limit);
95ea3627
ID		 1331 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1332
1333 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1334 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1335 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1336 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1337
b8be63ff 1338 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1339 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c 1340 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
b8be63ff 1341 entry_priv->desc_dma);
95ea3627
ID		 1342 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1343
b8be63ff 1344 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1345 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c 1346 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
b8be63ff 1347 entry_priv->desc_dma);
95ea3627
ID		 1348 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1349
b8be63ff 1350 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1351 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c 1352 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
b8be63ff 1353 entry_priv->desc_dma);
95ea3627
ID		 1354 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1355
b8be63ff 1356 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1357 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c 1358 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
b8be63ff 1359 entry_priv->desc_dma);
95ea3627
ID		 1360 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1361
95ea3627 1362 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1363 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1364 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1365 rt2x00dev->rx->desc_size / 4);
1366 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1367 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1368
b8be63ff 1369 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1370 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c 1371 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
b8be63ff 1372 entry_priv->desc_dma);
95ea3627
ID		 1373 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1374
1375 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1376 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1377 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1378 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1379 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1380 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1381
1382 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1383 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1384 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1385 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1386 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1387 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1388
1389 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1390 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1391 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1392
1393 return 0;
1394}
1395
1396static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1397{
1398 u32 reg;
1399
1400 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1401 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1402 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1403 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1404 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1405
1406 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1407 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1408 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1409 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1410 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1411 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1412 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1413 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1414 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1415 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1416
1417 /*
1418 * CCK TXD BBP registers
1419 */
1420 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1421 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1422 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1423 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1424 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1425 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1426 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1427 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1428 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1429 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1430
1431 /*
1432 * OFDM TXD BBP registers
1433 */
1434 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1435 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1436 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1437 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1438 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1439 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1440 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1441 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1442
1443 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1444 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1445 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1446 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1447 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1448 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1449
1450 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1451 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1452 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1453 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1454 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1455 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1456
1f909162
ID		 1457 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1458 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1459 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1460 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1461 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1462 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1463 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1464 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1465
95ea3627
ID		 1466 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1467
1468 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1469
1470 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1471 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1472 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1473
1474 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1475
1476 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1477 return -EBUSY;
1478
1479 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1480
1481 /*
1482 * Invalidate all Shared Keys (SEC_CSR0),
1483 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1484 */
1485 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1486 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1487 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1488
1489 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1490 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1491 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1492 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1493
1494 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1495
1496 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1497
1498 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1499
6bb40dd1
ID		 1500 /*
1501 * Clear all beacons
1502 * For the Beacon base registers we only need to clear
1503 * the first byte since that byte contains the VALID and OWNER
1504 * bits which (when set to 0) will invalidate the entire beacon.
1505 */
1506 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1507 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1508 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1509 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1510
95ea3627
ID		 1511 /*
1512 * We must clear the error counters.
1513 * These registers are cleared on read,
1514 * so we may pass a useless variable to store the value.
1515 */
1516 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1517 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1518 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1519
1520 /*
1521 * Reset MAC and BBP registers.
1522 */
1523 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1524 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1525 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1526 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1527
1528 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1529 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1530 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1531 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1532
1533 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1534 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1535 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1536
1537 return 0;
1538}
1539
2b08da3f 1540static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1541{
1542 unsigned int i;
95ea3627
ID		 1543 u8 value;
1544
1545 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1546 rt61pci_bbp_read(rt2x00dev, 0, &value);
1547 if ((value != 0xff) && (value != 0x00))
2b08da3f 1548 return 0;
95ea3627
ID		 1549 udelay(REGISTER_BUSY_DELAY);
1550 }
1551
1552 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1553 return -EACCES;
2b08da3f
ID		 1554}
1555
1556static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1557{
1558 unsigned int i;
1559 u16 eeprom;
1560 u8 reg_id;
1561 u8 value;
1562
1563 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1564 return -EACCES;
95ea3627 1565
95ea3627
ID		 1566 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1567 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1568 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1569 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1570 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1571 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1572 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1573 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1574 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1575 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1576 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1577 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1578 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1579 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1580 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1581 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1582 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1583 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1584 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1585 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1586 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1587 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1588 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1589 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1590
95ea3627
ID		 1591 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1592 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1593
1594 if (eeprom != 0xffff && eeprom != 0x0000) {
1595 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1596 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1597 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1598 }
1599 }
95ea3627
ID		 1600
1601 return 0;
1602}
1603
1604/*
1605 * Device state switch handlers.
1606 */
1607static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1608 enum dev_state state)
1609{
1610 u32 reg;
1611
1612 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1613 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1614 (state == STATE_RADIO_RX_OFF) ||
1615 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1616 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1617}
1618
1619static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1620 enum dev_state state)
1621{
1622 int mask = (state == STATE_RADIO_IRQ_OFF);
1623 u32 reg;
1624
1625 /*
1626 * When interrupts are being enabled, the interrupt registers
1627 * should clear the register to assure a clean state.
1628 */
1629 if (state == STATE_RADIO_IRQ_ON) {
1630 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1631 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1632
1633 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1634 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1635 }
1636
1637 /*
1638 * Only toggle the interrupts bits we are going to use.
1639 * Non-checked interrupt bits are disabled by default.
1640 */
1641 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1642 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1643 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1644 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1645 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1646 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1647
1648 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1649 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1650 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1651 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1652 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1653 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1654 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1655 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1656 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1657 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1658}
1659
1660static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1661{
1662 u32 reg;
1663
1664 /*
1665 * Initialize all registers.
1666 */
2b08da3f
ID		 1667 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1668 rt61pci_init_registers(rt2x00dev) ||
1669 rt61pci_init_bbp(rt2x00dev)))
95ea3627 1670 return -EIO;
95ea3627
ID		 1671
1672 /*
1673 * Enable RX.
1674 */
1675 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1676 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1677 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1678
95ea3627
ID		 1679 return 0;
1680}
1681
1682static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1683{
95ea3627 1684 /*
a2c9b652 1685 * Disable power
95ea3627 1686 */
a2c9b652 1687 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1688}
1689
1690static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1691{
1692 u32 reg;
1693 unsigned int i;
1694 char put_to_sleep;
95ea3627
ID		 1695
1696 put_to_sleep = (state != STATE_AWAKE);
1697
1698 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1699 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1700 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1701 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1702
1703 /*
1704 * Device is not guaranteed to be in the requested state yet.
1705 * We must wait until the register indicates that the
1706 * device has entered the correct state.
1707 */
1708 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1709 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1710 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1711 if (state == !put_to_sleep)
95ea3627
ID		 1712 return 0;
1713 msleep(10);
1714 }
1715
95ea3627
ID		 1716 return -EBUSY;
1717}
1718
1719static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1720 enum dev_state state)
1721{
1722 int retval = 0;
1723
1724 switch (state) {
1725 case STATE_RADIO_ON:
1726 retval = rt61pci_enable_radio(rt2x00dev);
1727 break;
1728 case STATE_RADIO_OFF:
1729 rt61pci_disable_radio(rt2x00dev);
1730 break;
1731 case STATE_RADIO_RX_ON:
61667d8d 1732 case STATE_RADIO_RX_ON_LINK:
95ea3627 1733 case STATE_RADIO_RX_OFF:
61667d8d 1734 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1735 rt61pci_toggle_rx(rt2x00dev, state);
1736 break;
1737 case STATE_RADIO_IRQ_ON:
1738 case STATE_RADIO_IRQ_OFF:
1739 rt61pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1740 break;
1741 case STATE_DEEP_SLEEP:
1742 case STATE_SLEEP:
1743 case STATE_STANDBY:
1744 case STATE_AWAKE:
1745 retval = rt61pci_set_state(rt2x00dev, state);
1746 break;
1747 default:
1748 retval = -ENOTSUPP;
1749 break;
1750 }
1751
2b08da3f
ID		 1752 if (unlikely(retval))
1753 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1754 state, retval);
1755
95ea3627
ID		 1756 return retval;
1757}
1758
1759/*
1760 * TX descriptor initialization
1761 */
1762static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
61e754f4
ID		 1763 struct sk_buff *skb,
1764 struct txentry_desc *txdesc)
95ea3627 1765{
181d6902 1766 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1767 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1768 u32 word;
1769
1770 /*
1771 * Start writing the descriptor words.
1772 */
1773 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1774 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1775 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1776 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1777 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
61e754f4 1778 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1779 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1780 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
4de36fe5 1781 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
95ea3627
ID		 1782 rt2x00_desc_write(txd, 1, word);
1783
1784 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1785 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1786 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1787 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1788 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1789 rt2x00_desc_write(txd, 2, word);
1790
61e754f4 1791 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1792 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1793 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
61e754f4
ID		 1794 }
1795
95ea3627 1796 rt2x00_desc_read(txd, 5, &word);
4de36fe5
GW		 1797 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1798 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1799 skbdesc->entry->entry_idx);
95ea3627 1800 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1801 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1802 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1803 rt2x00_desc_write(txd, 5, word);
1804
4de36fe5
GW		 1805 rt2x00_desc_read(txd, 6, &word);
1806 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
c4da0048 1807 skbdesc->skb_dma);
4de36fe5
GW		 1808 rt2x00_desc_write(txd, 6, word);
1809
d7bafff3
AB		 1810 if (skbdesc->desc_len > TXINFO_SIZE) {
1811 rt2x00_desc_read(txd, 11, &word);
d56d453a 1812 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
d7bafff3
AB		 1813 rt2x00_desc_write(txd, 11, word);
1814 }
95ea3627
ID		 1815
1816 rt2x00_desc_read(txd, 0, &word);
1817 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1818 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1819 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1820 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1821 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1822 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1823 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1824 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1825 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1826 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1827 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1828 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1829 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
61e754f4
ID		 1830 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1831 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1832 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1833 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1834 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
d56d453a 1835 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1836 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1837 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
61e754f4 1838 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627
ID		 1839 rt2x00_desc_write(txd, 0, word);
1840}
1841
1842/*
1843 * TX data initialization
1844 */
bd88a781
ID		 1845static void rt61pci_write_beacon(struct queue_entry *entry)
1846{
1847 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1848 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1849 unsigned int beacon_base;
1850 u32 reg;
1851
1852 /*
1853 * Disable beaconing while we are reloading the beacon data,
1854 * otherwise we might be sending out invalid data.
1855 */
1856 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781
ID		 1857 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1858 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1859
1860 /*
1861 * Write entire beacon with descriptor to register.
1862 */
1863 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1864 rt2x00pci_register_multiwrite(rt2x00dev,
1865 beacon_base,
1866 skbdesc->desc, skbdesc->desc_len);
1867 rt2x00pci_register_multiwrite(rt2x00dev,
1868 beacon_base + skbdesc->desc_len,
1869 entry->skb->data, entry->skb->len);
1870
1871 /*
1872 * Clean up beacon skb.
1873 */
1874 dev_kfree_skb_any(entry->skb);
1875 entry->skb = NULL;
1876}
1877
95ea3627 1878static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1879 const enum data_queue_qid queue)
95ea3627
ID		 1880{
1881 u32 reg;
1882
e58c6aca 1883 if (queue == QID_BEACON) {
95ea3627
ID		 1884 /*
1885 * For Wi-Fi faily generated beacons between participating
1886 * stations. Set TBTT phase adaptive adjustment step to 8us.
1887 */
1888 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1889
1890 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1891 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1892 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1893 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1894 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1895 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1896 }
1897 return;
1898 }
1899
1900 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
e58c6aca
ID		 1901 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1902 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1903 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1904 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
95ea3627
ID		 1905 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1906}
1907
a2c9b652
ID		 1908static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1909 const enum data_queue_qid qid)
1910{
1911 u32 reg;
1912
1913 if (qid == QID_BEACON) {
1914 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1915 return;
1916 }
1917
1918 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1919 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE));
1920 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK));
1921 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI));
1922 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO));
1923 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1924}
1925
95ea3627
ID		 1926/*
1927 * RX control handlers
1928 */
1929static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1930{
ba2ab471 1931 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1932 u8 lna;
1933
1934 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1935 switch (lna) {
1936 case 3:
ba2ab471 1937 offset += 90;
95ea3627
ID		 1938 break;
1939 case 2:
ba2ab471 1940 offset += 74;
95ea3627
ID		 1941 break;
1942 case 1:
ba2ab471 1943 offset += 64;
95ea3627
ID		 1944 break;
1945 default:
1946 return 0;
1947 }
1948
8318d78a 1949 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1950 if (lna == 3 || lna == 2)
1951 offset += 10;
95ea3627
ID		 1952 }
1953
1954 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1955}
1956
181d6902 1957static void rt61pci_fill_rxdone(struct queue_entry *entry,
55887511 1958 struct rxdone_entry_desc *rxdesc)
95ea3627 1959{
61e754f4 1960 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1961 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1962 u32 word0;
1963 u32 word1;
1964
b8be63ff
ID		 1965 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1966 rt2x00_desc_read(entry_priv->desc, 1, &word1);
95ea3627 1967
4150c572 1968 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1969 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1970
61e754f4
ID		 1971 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1972 rxdesc->cipher =
1973 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1974 rxdesc->cipher_status =
1975 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1976 }
1977
1978 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1979 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
1980 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
74415edb
ID		 1981 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1982
61e754f4 1983 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
74415edb 1984 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
61e754f4
ID		 1985
1986 /*
1987 * Hardware has stripped IV/EIV data from 802.11 frame during
b34e620f 1988 * decryption. It has provided the data separately but rt2x00lib
61e754f4
ID		 1989 * should decide if it should be reinserted.
1990 */
1991 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1992
1993 /*
1994 * FIXME: Legacy driver indicates that the frame does
1995 * contain the Michael Mic. Unfortunately, in rt2x00
1996 * the MIC seems to be missing completely...
1997 */
1998 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1999
2000 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2001 rxdesc->flags |= RX_FLAG_DECRYPTED;
2002 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2003 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2004 }
2005
95ea3627
ID		 2006 /*
2007 * Obtain the status about this packet.
89993890
ID		 2008 * When frame was received with an OFDM bitrate,
2009 * the signal is the PLCP value. If it was received with
2010 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 2011 */
181d6902 2012 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
61e754f4 2013 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
181d6902 2014 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 2015
19d30e02
ID		 2016 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2017 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 2018 else
2019 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 2020 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2021 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 2022}
2023
2024/*
2025 * Interrupt functions.
2026 */
2027static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2028{
181d6902
ID		 2029 struct data_queue *queue;
2030 struct queue_entry *entry;
2031 struct queue_entry *entry_done;
b8be63ff 2032 struct queue_entry_priv_pci *entry_priv;
181d6902 2033 struct txdone_entry_desc txdesc;
95ea3627
ID		 2034 u32 word;
2035 u32 reg;
2036 u32 old_reg;
2037 int type;
2038 int index;
95ea3627
ID		 2039
2040 /*
2041 * During each loop we will compare the freshly read
2042 * STA_CSR4 register value with the value read from
2043 * the previous loop. If the 2 values are equal then
b34e620f 2044 * we should stop processing because the chance is
95ea3627
ID		 2045 * quite big that the device has been unplugged and
2046 * we risk going into an endless loop.
2047 */
2048 old_reg = 0;
2049
2050 while (1) {
2051 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2052 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2053 break;
2054
2055 if (old_reg == reg)
2056 break;
2057 old_reg = reg;
2058
2059 /*
2060 * Skip this entry when it contains an invalid
181d6902 2061 * queue identication number.
95ea3627
ID		 2062 */
2063 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 2064 queue = rt2x00queue_get_queue(rt2x00dev, type);
2065 if (unlikely(!queue))
95ea3627
ID		 2066 continue;
2067
2068 /*
2069 * Skip this entry when it contains an invalid
2070 * index number.
2071 */
2072 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 2073 if (unlikely(index >= queue->limit))
95ea3627
ID		 2074 continue;
2075
181d6902 2076 entry = &queue->entries[index];
b8be63ff
ID		 2077 entry_priv = entry->priv_data;
2078 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 2079
2080 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2081 !rt2x00_get_field32(word, TXD_W0_VALID))
2082 return;
2083
181d6902 2084 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 2085 while (entry != entry_done) {
181d6902
ID		 2086 /* Catch up.
2087 * Just report any entries we missed as failed.
2088 */
62bc060b 2089 WARNING(rt2x00dev,
181d6902
ID		 2090 "TX status report missed for entry %d\n",
2091 entry_done->entry_idx);
2092
fb55f4d1
ID		 2093 txdesc.flags = 0;
2094 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
181d6902
ID		 2095 txdesc.retry = 0;
2096
d74f5ba4 2097 rt2x00lib_txdone(entry_done, &txdesc);
181d6902 2098 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 2099 }
2100
95ea3627
ID		 2101 /*
2102 * Obtain the status about this packet.
2103 */
fb55f4d1
ID		 2104 txdesc.flags = 0;
2105 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2106 case 0: /* Success, maybe with retry */
2107 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2108 break;
2109 case 6: /* Failure, excessive retries */
2110 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2111 /* Don't break, this is a failed frame! */
2112 default: /* Failure */
2113 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2114 }
181d6902 2115 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 2116
d74f5ba4 2117 rt2x00lib_txdone(entry, &txdesc);
95ea3627
ID		 2118 }
2119}
2120
2121static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2122{
2123 struct rt2x00_dev *rt2x00dev = dev_instance;
2124 u32 reg_mcu;
2125 u32 reg;
2126
2127 /*
2128 * Get the interrupt sources & saved to local variable.
2129 * Write register value back to clear pending interrupts.
2130 */
2131 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2132 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2133
2134 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2135 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2136
2137 if (!reg && !reg_mcu)
2138 return IRQ_NONE;
2139
0262ab0d 2140 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
95ea3627
ID		 2141 return IRQ_HANDLED;
2142
2143 /*
2144 * Handle interrupts, walk through all bits
2145 * and run the tasks, the bits are checked in order of
2146 * priority.
2147 */
2148
2149 /*
2150 * 1 - Rx ring done interrupt.
2151 */
2152 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2153 rt2x00pci_rxdone(rt2x00dev);
2154
2155 /*
2156 * 2 - Tx ring done interrupt.
2157 */
2158 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2159 rt61pci_txdone(rt2x00dev);
2160
2161 /*
2162 * 3 - Handle MCU command done.
2163 */
2164 if (reg_mcu)
2165 rt2x00pci_register_write(rt2x00dev,
2166 M2H_CMD_DONE_CSR, 0xffffffff);
2167
2168 return IRQ_HANDLED;
2169}
2170
2171/*
2172 * Device probe functions.
2173 */
2174static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2175{
2176 struct eeprom_93cx6 eeprom;
2177 u32 reg;
2178 u16 word;
2179 u8 *mac;
2180 s8 value;
2181
2182 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2183
2184 eeprom.data = rt2x00dev;
2185 eeprom.register_read = rt61pci_eepromregister_read;
2186 eeprom.register_write = rt61pci_eepromregister_write;
2187 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2188 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2189 eeprom.reg_data_in = 0;
2190 eeprom.reg_data_out = 0;
2191 eeprom.reg_data_clock = 0;
2192 eeprom.reg_chip_select = 0;
2193
2194 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2195 EEPROM_SIZE / sizeof(u16));
2196
2197 /*
2198 * Start validation of the data that has been read.
2199 */
2200 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2201 if (!is_valid_ether_addr(mac)) {
2202 random_ether_addr(mac);
e174961c 2203 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 2204 }
2205
2206 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2207 if (word == 0xffff) {
2208 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 2209 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2210 ANTENNA_B);
2211 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2212 ANTENNA_B);
95ea3627
ID		 2213 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2214 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2215 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2216 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2217 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2218 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2219 }
2220
2221 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2222 if (word == 0xffff) {
2223 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2224 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
91581b62
ID		 2225 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2226 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
95ea3627
ID		 2227 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2228 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2229 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2230 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2231 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2232 }
2233
2234 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2235 if (word == 0xffff) {
2236 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2237 LED_MODE_DEFAULT);
2238 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2239 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2240 }
2241
2242 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2243 if (word == 0xffff) {
2244 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2245 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2246 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2247 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2248 }
2249
2250 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2251 if (word == 0xffff) {
2252 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2253 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2254 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2255 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2256 } else {
2257 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2258 if (value < -10 || value > 10)
2259 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2260 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2261 if (value < -10 || value > 10)
2262 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2263 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2264 }
2265
2266 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2267 if (word == 0xffff) {
2268 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2269 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2270 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 2271 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 2272 } else {
2273 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2274 if (value < -10 || value > 10)
2275 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2276 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2277 if (value < -10 || value > 10)
2278 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2279 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2280 }
2281
2282 return 0;
2283}
2284
2285static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2286{
2287 u32 reg;
2288 u16 value;
2289 u16 eeprom;
95ea3627
ID		 2290
2291 /*
2292 * Read EEPROM word for configuration.
2293 */
2294 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2295
2296 /*
2297 * Identify RF chipset.
95ea3627 2298 */
95ea3627
ID		 2299 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2300 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
49e721ec
GW		 2301 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2302 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
95ea3627 2303
5122d898
GW		 2304 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2305 !rt2x00_rf(rt2x00dev, RF5325) &&
2306 !rt2x00_rf(rt2x00dev, RF2527) &&
2307 !rt2x00_rf(rt2x00dev, RF2529)) {
95ea3627
ID		 2308 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2309 return -ENODEV;
2310 }
2311
e4cd2ff8 2312 /*
49513481 2313 * Determine number of antennas.
e4cd2ff8
ID		 2314 */
2315 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2316 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2317
95ea3627
ID		 2318 /*
2319 * Identify default antenna configuration.
2320 */
addc81bd 2321 rt2x00dev->default_ant.tx =
95ea3627 2322 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 2323 rt2x00dev->default_ant.rx =
95ea3627
ID		 2324 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2325
2326 /*
2327 * Read the Frame type.
2328 */
2329 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2330 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2331
95ea3627 2332 /*
b34e620f 2333 * Detect if this device has a hardware controlled radio.
95ea3627
ID		 2334 */
2335 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2336 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 2337
2338 /*
2339 * Read frequency offset and RF programming sequence.
2340 */
2341 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2342 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2343 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2344
2345 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2346
2347 /*
2348 * Read external LNA informations.
2349 */
2350 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2351
2352 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2353 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2354 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2355 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2356
e4cd2ff8 2357 /*
b34e620f 2358 * When working with a RF2529 chip without double antenna,
e4cd2ff8
ID		 2359 * the antenna settings should be gathered from the NIC
2360 * eeprom word.
2361 */
5122d898 2362 if (rt2x00_rf(rt2x00dev, RF2529) &&
e4cd2ff8 2363 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
91581b62
ID		 2364 rt2x00dev->default_ant.rx =
2365 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2366 rt2x00dev->default_ant.tx =
2367 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
e4cd2ff8
ID		 2368
2369 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2370 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2371 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2372 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2373 }
2374
95ea3627
ID		 2375 /*
2376 * Store led settings, for correct led behaviour.
2377 * If the eeprom value is invalid,
2378 * switch to default led mode.
2379 */
771fd565 2380#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627 2381 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
a9450b70
ID		 2382 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2383
475433be
ID		 2384 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2385 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2386 if (value == LED_MODE_SIGNAL_STRENGTH)
2387 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2388 LED_TYPE_QUALITY);
95ea3627 2389
a9450b70
ID		 2390 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2391 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2392 rt2x00_get_field16(eeprom,
2393 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2394 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2395 rt2x00_get_field16(eeprom,
2396 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2397 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2398 rt2x00_get_field16(eeprom,
2399 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2400 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2401 rt2x00_get_field16(eeprom,
2402 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2403 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2404 rt2x00_get_field16(eeprom,
2405 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2406 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2407 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2408 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2409 rt2x00_get_field16(eeprom,
2410 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2411 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2412 rt2x00_get_field16(eeprom,
2413 EEPROM_LED_POLARITY_RDY_A));
771fd565 2414#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 2415
2416 return 0;
2417}
2418
2419/*
2420 * RF value list for RF5225 & RF5325
2421 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2422 */
2423static const struct rf_channel rf_vals_noseq[] = {
2424 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2425 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2426 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2427 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2428 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2429 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2430 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2431 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2432 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2433 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2434 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2435 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2436 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2437 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2438
2439 /* 802.11 UNI / HyperLan 2 */
2440 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2441 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2442 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2443 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2444 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2445 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2446 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2447 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2448
2449 /* 802.11 HyperLan 2 */
2450 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2451 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2452 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2453 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2454 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2455 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2456 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2457 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2458 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2459 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2460
2461 /* 802.11 UNII */
2462 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2463 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2464 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2465 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2466 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2467 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2468
2469 /* MMAC(Japan)J52 ch 34,38,42,46 */
2470 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2471 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2472 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2473 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2474};
2475
2476/*
2477 * RF value list for RF5225 & RF5325
2478 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2479 */
2480static const struct rf_channel rf_vals_seq[] = {
2481 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2482 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2483 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2484 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2485 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2486 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2487 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2488 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2489 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2490 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2491 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2492 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2493 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2494 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2495
2496 /* 802.11 UNI / HyperLan 2 */
2497 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2498 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2499 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2500 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2501 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2502 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2503 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2504 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2505
2506 /* 802.11 HyperLan 2 */
2507 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2508 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2509 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2510 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2511 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2512 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2513 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2514 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2515 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2516 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2517
2518 /* 802.11 UNII */
2519 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2520 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2521 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2522 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2523 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2524 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2525
2526 /* MMAC(Japan)J52 ch 34,38,42,46 */
2527 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2528 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2529 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2530 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2531};
2532
8c5e7a5f 2533static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2534{
2535 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2536 struct channel_info *info;
2537 char *tx_power;
95ea3627
ID		 2538 unsigned int i;
2539
93b6bd26
GW		 2540 /*
2541 * Disable powersaving as default.
2542 */
2543 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2544
95ea3627
ID		 2545 /*
2546 * Initialize all hw fields.
2547 */
2548 rt2x00dev->hw->flags =
566bfe5a 2549 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2550 IEEE80211_HW_SIGNAL_DBM |
2551 IEEE80211_HW_SUPPORTS_PS |
2552 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2553
14a3bf89 2554 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2555 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2556 rt2x00_eeprom_addr(rt2x00dev,
2557 EEPROM_MAC_ADDR_0));
2558
95ea3627
ID		 2559 /*
2560 * Initialize hw_mode information.
2561 */
31562e80
ID		 2562 spec->supported_bands = SUPPORT_BAND_2GHZ;
2563 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2564
2565 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2566 spec->num_channels = 14;
2567 spec->channels = rf_vals_noseq;
2568 } else {
2569 spec->num_channels = 14;
2570 spec->channels = rf_vals_seq;
2571 }
2572
5122d898 2573 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
31562e80 2574 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627 2575 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
8c5e7a5f
ID		 2576 }
2577
2578 /*
2579 * Create channel information array
2580 */
2581 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2582 if (!info)
2583 return -ENOMEM;
2584
2585 spec->channels_info = info;
95ea3627 2586
8c5e7a5f
ID		 2587 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2588 for (i = 0; i < 14; i++)
2589 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2590
8c5e7a5f
ID		 2591 if (spec->num_channels > 14) {
2592 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2593 for (i = 14; i < spec->num_channels; i++)
2594 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2595 }
8c5e7a5f
ID		 2596
2597 return 0;
95ea3627
ID		 2598}
2599
2600static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2601{
2602 int retval;
2603
117839bd
PR		 2604 /*
2605 * Disable power saving.
2606 */
2607 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2608
95ea3627
ID		 2609 /*
2610 * Allocate eeprom data.
2611 */
2612 retval = rt61pci_validate_eeprom(rt2x00dev);
2613 if (retval)
2614 return retval;
2615
2616 retval = rt61pci_init_eeprom(rt2x00dev);
2617 if (retval)
2618 return retval;
2619
2620 /*
2621 * Initialize hw specifications.
2622 */
8c5e7a5f
ID		 2623 retval = rt61pci_probe_hw_mode(rt2x00dev);
2624 if (retval)
2625 return retval;
95ea3627 2626
1afcfd54
IP		 2627 /*
2628 * This device has multiple filters for control frames,
2629 * but has no a separate filter for PS Poll frames.
2630 */
2631 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2632
95ea3627 2633 /*
c4da0048 2634 * This device requires firmware and DMA mapped skbs.
95ea3627 2635 */
066cb637 2636 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
c4da0048 2637 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
008c4482
ID		 2638 if (!modparam_nohwcrypt)
2639 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2640
2641 /*
2642 * Set the rssi offset.
2643 */
2644 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2645
2646 return 0;
2647}
2648
2649/*
2650 * IEEE80211 stack callback functions.
2651 */
2af0a570
ID		 2652static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2653 const struct ieee80211_tx_queue_params *params)
2654{
2655 struct rt2x00_dev *rt2x00dev = hw->priv;
2656 struct data_queue *queue;
2657 struct rt2x00_field32 field;
2658 int retval;
2659 u32 reg;
5e790023 2660 u32 offset;
2af0a570
ID		 2661
2662 /*
2663 * First pass the configuration through rt2x00lib, that will
2664 * update the queue settings and validate the input. After that
2665 * we are free to update the registers based on the value
2666 * in the queue parameter.
2667 */
2668 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2669 if (retval)
2670 return retval;
2671
5e790023
ID		 2672 /*
2673 * We only need to perform additional register initialization
b34e620f 2674 * for WMM queues.
5e790023
ID		 2675 */
2676 if (queue_idx >= 4)
2677 return 0;
2678
2af0a570
ID		 2679 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2680
2681 /* Update WMM TXOP register */
5e790023
ID		 2682 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2683 field.bit_offset = (queue_idx & 1) * 16;
2684 field.bit_mask = 0xffff << field.bit_offset;
2685
2686 rt2x00pci_register_read(rt2x00dev, offset, &reg);
2687 rt2x00_set_field32(&reg, field, queue->txop);
2688 rt2x00pci_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2689
2690 /* Update WMM registers */
2691 field.bit_offset = queue_idx * 4;
2692 field.bit_mask = 0xf << field.bit_offset;
2693
2694 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2695 rt2x00_set_field32(&reg, field, queue->aifs);
2696 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2697
2698 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2699 rt2x00_set_field32(&reg, field, queue->cw_min);
2700 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2701
2702 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2703 rt2x00_set_field32(&reg, field, queue->cw_max);
2704 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2705
2706 return 0;
2707}
2708
95ea3627
ID		 2709static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2710{
2711 struct rt2x00_dev *rt2x00dev = hw->priv;
2712 u64 tsf;
2713 u32 reg;
2714
2715 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2716 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2717 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2718 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2719
2720 return tsf;
2721}
2722
95ea3627
ID		 2723static const struct ieee80211_ops rt61pci_mac80211_ops = {
2724 .tx = rt2x00mac_tx,
4150c572
JB		 2725 .start = rt2x00mac_start,
2726 .stop = rt2x00mac_stop,
95ea3627
ID		 2727 .add_interface = rt2x00mac_add_interface,
2728 .remove_interface = rt2x00mac_remove_interface,
2729 .config = rt2x00mac_config,
3a643d24 2730 .configure_filter = rt2x00mac_configure_filter,
930c06f2 2731 .set_tim = rt2x00mac_set_tim,
61e754f4 2732 .set_key = rt2x00mac_set_key,
95ea3627 2733 .get_stats = rt2x00mac_get_stats,
471b3efd 2734 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2735 .conf_tx = rt61pci_conf_tx,
95ea3627 2736 .get_tsf = rt61pci_get_tsf,
e47a5cdd 2737 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 2738};
2739
2740static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2741 .irq_handler = rt61pci_interrupt,
2742 .probe_hw = rt61pci_probe_hw,
2743 .get_firmware_name = rt61pci_get_firmware_name,
0cbe0064 2744 .check_firmware = rt61pci_check_firmware,
95ea3627
ID		 2745 .load_firmware = rt61pci_load_firmware,
2746 .initialize = rt2x00pci_initialize,
2747 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 2748 .get_entry_state = rt61pci_get_entry_state,
2749 .clear_entry = rt61pci_clear_entry,
95ea3627 2750 .set_device_state = rt61pci_set_device_state,
95ea3627 2751 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2752 .link_stats = rt61pci_link_stats,
2753 .reset_tuner = rt61pci_reset_tuner,
2754 .link_tuner = rt61pci_link_tuner,
2755 .write_tx_desc = rt61pci_write_tx_desc,
2756 .write_tx_data = rt2x00pci_write_tx_data,
bd88a781 2757 .write_beacon = rt61pci_write_beacon,
95ea3627 2758 .kick_tx_queue = rt61pci_kick_tx_queue,
a2c9b652 2759 .kill_tx_queue = rt61pci_kill_tx_queue,
95ea3627 2760 .fill_rxdone = rt61pci_fill_rxdone,
61e754f4
ID		 2761 .config_shared_key = rt61pci_config_shared_key,
2762 .config_pairwise_key = rt61pci_config_pairwise_key,
3a643d24 2763 .config_filter = rt61pci_config_filter,
6bb40dd1 2764 .config_intf = rt61pci_config_intf,
72810379 2765 .config_erp = rt61pci_config_erp,
e4ea1c40 2766 .config_ant = rt61pci_config_ant,
95ea3627
ID		 2767 .config = rt61pci_config,
2768};
2769
181d6902
ID		 2770static const struct data_queue_desc rt61pci_queue_rx = {
2771 .entry_num = RX_ENTRIES,
2772 .data_size = DATA_FRAME_SIZE,
2773 .desc_size = RXD_DESC_SIZE,
b8be63ff 2774 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2775};
2776
2777static const struct data_queue_desc rt61pci_queue_tx = {
2778 .entry_num = TX_ENTRIES,
2779 .data_size = DATA_FRAME_SIZE,
2780 .desc_size = TXD_DESC_SIZE,
b8be63ff 2781 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2782};
2783
2784static const struct data_queue_desc rt61pci_queue_bcn = {
6bb40dd1 2785 .entry_num = 4 * BEACON_ENTRIES,
78720897 2786 .data_size = 0, /* No DMA required for beacons */
181d6902 2787 .desc_size = TXINFO_SIZE,
b8be63ff 2788 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2789};
2790
95ea3627 2791static const struct rt2x00_ops rt61pci_ops = {
04d0362e
GW		 2792 .name = KBUILD_MODNAME,
2793 .max_sta_intf = 1,
2794 .max_ap_intf = 4,
2795 .eeprom_size = EEPROM_SIZE,
2796 .rf_size = RF_SIZE,
2797 .tx_queues = NUM_TX_QUEUES,
e6218cc4 2798 .extra_tx_headroom = 0,
04d0362e
GW		 2799 .rx = &rt61pci_queue_rx,
2800 .tx = &rt61pci_queue_tx,
2801 .bcn = &rt61pci_queue_bcn,
2802 .lib = &rt61pci_rt2x00_ops,
2803 .hw = &rt61pci_mac80211_ops,
95ea3627 2804#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 2805 .debugfs = &rt61pci_rt2x00debug,
95ea3627
ID		 2806#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2807};
2808
2809/*
2810 * RT61pci module information.
2811 */
a3aa1884 2812static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
95ea3627
ID		 2813 /* RT2561s */
2814 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2815 /* RT2561 v2 */
2816 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2817 /* RT2661 */
2818 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2819 { 0, }
2820};
2821
2822MODULE_AUTHOR(DRV_PROJECT);
2823MODULE_VERSION(DRV_VERSION);
2824MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2825MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2826 "PCI & PCMCIA chipset based cards");
2827MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2828MODULE_FIRMWARE(FIRMWARE_RT2561);
2829MODULE_FIRMWARE(FIRMWARE_RT2561s);
2830MODULE_FIRMWARE(FIRMWARE_RT2661);
2831MODULE_LICENSE("GPL");
2832
2833static struct pci_driver rt61pci_driver = {
2360157c 2834 .name = KBUILD_MODNAME,
95ea3627
ID		 2835 .id_table = rt61pci_device_table,
2836 .probe = rt2x00pci_probe,
2837 .remove = __devexit_p(rt2x00pci_remove),
2838 .suspend = rt2x00pci_suspend,
2839 .resume = rt2x00pci_resume,
2840};
2841
2842static int __init rt61pci_init(void)
2843{
2844 return pci_register_driver(&rt61pci_driver);
2845}
2846
2847static void __exit rt61pci_exit(void)
2848{
2849 pci_unregister_driver(&rt61pci_driver);
2850}
2851
2852module_init(rt61pci_init);
2853module_exit(rt61pci_exit);
Clone of davem's net-next-2.6 tree