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Commit | Line | Data |
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55624204 S |
1 | /* |
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
5a0e3ad6 | 17 | #include <linux/slab.h> |
10598c12 | 18 | #include <linux/pm_qos_params.h> |
5a0e3ad6 | 19 | |
55624204 S |
20 | #include "ath9k.h" |
21 | ||
22 | static char *dev_info = "ath9k"; | |
23 | ||
24 | MODULE_AUTHOR("Atheros Communications"); | |
25 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
26 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
27 | MODULE_LICENSE("Dual BSD/GPL"); | |
28 | ||
29 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
30 | module_param_named(debug, ath9k_debug, uint, 0); | |
31 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
32 | ||
33 | int modparam_nohwcrypt; | |
34 | module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); | |
35 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); | |
36 | ||
93dbbcc4 | 37 | int led_blink; |
9a75c2ff VN |
38 | module_param_named(blink, led_blink, int, 0444); |
39 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); | |
40 | ||
55624204 S |
41 | /* We use the hw_value as an index into our private channel structure */ |
42 | ||
43 | #define CHAN2G(_freq, _idx) { \ | |
44 | .center_freq = (_freq), \ | |
45 | .hw_value = (_idx), \ | |
46 | .max_power = 20, \ | |
47 | } | |
48 | ||
49 | #define CHAN5G(_freq, _idx) { \ | |
50 | .band = IEEE80211_BAND_5GHZ, \ | |
51 | .center_freq = (_freq), \ | |
52 | .hw_value = (_idx), \ | |
53 | .max_power = 20, \ | |
54 | } | |
55 | ||
56 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
57 | * on 5 MHz steps, we support the channels which we know | |
58 | * we have calibration data for all cards though to make | |
59 | * this static */ | |
f209f529 | 60 | static const struct ieee80211_channel ath9k_2ghz_chantable[] = { |
55624204 S |
61 | CHAN2G(2412, 0), /* Channel 1 */ |
62 | CHAN2G(2417, 1), /* Channel 2 */ | |
63 | CHAN2G(2422, 2), /* Channel 3 */ | |
64 | CHAN2G(2427, 3), /* Channel 4 */ | |
65 | CHAN2G(2432, 4), /* Channel 5 */ | |
66 | CHAN2G(2437, 5), /* Channel 6 */ | |
67 | CHAN2G(2442, 6), /* Channel 7 */ | |
68 | CHAN2G(2447, 7), /* Channel 8 */ | |
69 | CHAN2G(2452, 8), /* Channel 9 */ | |
70 | CHAN2G(2457, 9), /* Channel 10 */ | |
71 | CHAN2G(2462, 10), /* Channel 11 */ | |
72 | CHAN2G(2467, 11), /* Channel 12 */ | |
73 | CHAN2G(2472, 12), /* Channel 13 */ | |
74 | CHAN2G(2484, 13), /* Channel 14 */ | |
75 | }; | |
76 | ||
77 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
78 | * on 5 MHz steps, we support the channels which we know | |
79 | * we have calibration data for all cards though to make | |
80 | * this static */ | |
f209f529 | 81 | static const struct ieee80211_channel ath9k_5ghz_chantable[] = { |
55624204 S |
82 | /* _We_ call this UNII 1 */ |
83 | CHAN5G(5180, 14), /* Channel 36 */ | |
84 | CHAN5G(5200, 15), /* Channel 40 */ | |
85 | CHAN5G(5220, 16), /* Channel 44 */ | |
86 | CHAN5G(5240, 17), /* Channel 48 */ | |
87 | /* _We_ call this UNII 2 */ | |
88 | CHAN5G(5260, 18), /* Channel 52 */ | |
89 | CHAN5G(5280, 19), /* Channel 56 */ | |
90 | CHAN5G(5300, 20), /* Channel 60 */ | |
91 | CHAN5G(5320, 21), /* Channel 64 */ | |
92 | /* _We_ call this "Middle band" */ | |
93 | CHAN5G(5500, 22), /* Channel 100 */ | |
94 | CHAN5G(5520, 23), /* Channel 104 */ | |
95 | CHAN5G(5540, 24), /* Channel 108 */ | |
96 | CHAN5G(5560, 25), /* Channel 112 */ | |
97 | CHAN5G(5580, 26), /* Channel 116 */ | |
98 | CHAN5G(5600, 27), /* Channel 120 */ | |
99 | CHAN5G(5620, 28), /* Channel 124 */ | |
100 | CHAN5G(5640, 29), /* Channel 128 */ | |
101 | CHAN5G(5660, 30), /* Channel 132 */ | |
102 | CHAN5G(5680, 31), /* Channel 136 */ | |
103 | CHAN5G(5700, 32), /* Channel 140 */ | |
104 | /* _We_ call this UNII 3 */ | |
105 | CHAN5G(5745, 33), /* Channel 149 */ | |
106 | CHAN5G(5765, 34), /* Channel 153 */ | |
107 | CHAN5G(5785, 35), /* Channel 157 */ | |
108 | CHAN5G(5805, 36), /* Channel 161 */ | |
109 | CHAN5G(5825, 37), /* Channel 165 */ | |
110 | }; | |
111 | ||
112 | /* Atheros hardware rate code addition for short premble */ | |
113 | #define SHPCHECK(__hw_rate, __flags) \ | |
114 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) | |
115 | ||
116 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
117 | .bitrate = (_bitrate), \ | |
118 | .flags = (_flags), \ | |
119 | .hw_value = (_hw_rate), \ | |
120 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
121 | } | |
122 | ||
123 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
124 | RATE(10, 0x1b, 0), | |
125 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), | |
126 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), | |
127 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), | |
128 | RATE(60, 0x0b, 0), | |
129 | RATE(90, 0x0f, 0), | |
130 | RATE(120, 0x0a, 0), | |
131 | RATE(180, 0x0e, 0), | |
132 | RATE(240, 0x09, 0), | |
133 | RATE(360, 0x0d, 0), | |
134 | RATE(480, 0x08, 0), | |
135 | RATE(540, 0x0c, 0), | |
136 | }; | |
137 | ||
285f2dda | 138 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
139 | |
140 | /* | |
141 | * Read and write, they both share the same lock. We do this to serialize | |
142 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
143 | * as the FIFO on these devices can only accept sanely 2 requests. | |
144 | */ | |
145 | ||
146 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
147 | { | |
148 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
149 | struct ath_common *common = ath9k_hw_common(ah); | |
150 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
151 | ||
152 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
153 | unsigned long flags; | |
154 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
155 | iowrite32(val, sc->mem + reg_offset); | |
156 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
157 | } else | |
158 | iowrite32(val, sc->mem + reg_offset); | |
159 | } | |
160 | ||
161 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
162 | { | |
163 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
164 | struct ath_common *common = ath9k_hw_common(ah); | |
165 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
166 | u32 val; | |
167 | ||
168 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
169 | unsigned long flags; | |
170 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
171 | val = ioread32(sc->mem + reg_offset); | |
172 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
173 | } else | |
174 | val = ioread32(sc->mem + reg_offset); | |
175 | return val; | |
176 | } | |
177 | ||
178 | static const struct ath_ops ath9k_common_ops = { | |
179 | .read = ath9k_ioread32, | |
180 | .write = ath9k_iowrite32, | |
181 | }; | |
182 | ||
10598c12 VN |
183 | struct pm_qos_request_list ath9k_pm_qos_req; |
184 | ||
55624204 S |
185 | /**************************/ |
186 | /* Initialization */ | |
187 | /**************************/ | |
188 | ||
189 | static void setup_ht_cap(struct ath_softc *sc, | |
190 | struct ieee80211_sta_ht_cap *ht_info) | |
191 | { | |
3bb065a7 FF |
192 | struct ath_hw *ah = sc->sc_ah; |
193 | struct ath_common *common = ath9k_hw_common(ah); | |
55624204 | 194 | u8 tx_streams, rx_streams; |
3bb065a7 | 195 | int i, max_streams; |
55624204 S |
196 | |
197 | ht_info->ht_supported = true; | |
198 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
199 | IEEE80211_HT_CAP_SM_PS | | |
200 | IEEE80211_HT_CAP_SGI_40 | | |
201 | IEEE80211_HT_CAP_DSSSCCK40; | |
202 | ||
b0a33448 LR |
203 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) |
204 | ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; | |
205 | ||
6473d24d VT |
206 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) |
207 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
208 | ||
55624204 S |
209 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
210 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
211 | ||
3bb065a7 FF |
212 | if (AR_SREV_9300_20_OR_LATER(ah)) |
213 | max_streams = 3; | |
214 | else | |
215 | max_streams = 2; | |
216 | ||
7a37081e | 217 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
074a8c0d FF |
218 | if (max_streams >= 2) |
219 | ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; | |
220 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
221 | } | |
222 | ||
55624204 S |
223 | /* set up supported mcs set */ |
224 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
61389f3e S |
225 | tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams); |
226 | rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams); | |
3bb065a7 FF |
227 | |
228 | ath_print(common, ATH_DBG_CONFIG, | |
229 | "TX streams %d, RX streams: %d\n", | |
230 | tx_streams, rx_streams); | |
55624204 S |
231 | |
232 | if (tx_streams != rx_streams) { | |
55624204 S |
233 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
234 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
235 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
236 | } | |
237 | ||
3bb065a7 FF |
238 | for (i = 0; i < rx_streams; i++) |
239 | ht_info->mcs.rx_mask[i] = 0xff; | |
55624204 S |
240 | |
241 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; | |
242 | } | |
243 | ||
244 | static int ath9k_reg_notifier(struct wiphy *wiphy, | |
245 | struct regulatory_request *request) | |
246 | { | |
247 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
248 | struct ath_wiphy *aphy = hw->priv; | |
249 | struct ath_softc *sc = aphy->sc; | |
250 | struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah); | |
251 | ||
252 | return ath_reg_notifier_apply(wiphy, request, reg); | |
253 | } | |
254 | ||
255 | /* | |
256 | * This function will allocate both the DMA descriptor structure, and the | |
257 | * buffers it contains. These are used to contain the descriptors used | |
258 | * by the system. | |
259 | */ | |
260 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
261 | struct list_head *head, const char *name, | |
4adfcded | 262 | int nbuf, int ndesc, bool is_tx) |
55624204 S |
263 | { |
264 | #define DS2PHYS(_dd, _ds) \ | |
265 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
266 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
267 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
268 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
4adfcded | 269 | u8 *ds; |
55624204 | 270 | struct ath_buf *bf; |
4adfcded | 271 | int i, bsize, error, desc_len; |
55624204 S |
272 | |
273 | ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", | |
274 | name, nbuf, ndesc); | |
275 | ||
276 | INIT_LIST_HEAD(head); | |
4adfcded VT |
277 | |
278 | if (is_tx) | |
279 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
280 | else | |
281 | desc_len = sizeof(struct ath_desc); | |
282 | ||
55624204 | 283 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 284 | if ((desc_len % 4) != 0) { |
55624204 S |
285 | ath_print(common, ATH_DBG_FATAL, |
286 | "ath_desc not DWORD aligned\n"); | |
4adfcded | 287 | BUG_ON((desc_len % 4) != 0); |
55624204 S |
288 | error = -ENOMEM; |
289 | goto fail; | |
290 | } | |
291 | ||
4adfcded | 292 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
293 | |
294 | /* | |
295 | * Need additional DMA memory because we can't use | |
296 | * descriptors that cross the 4K page boundary. Assume | |
297 | * one skipped descriptor per 4K page. | |
298 | */ | |
299 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
300 | u32 ndesc_skipped = | |
301 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
302 | u32 dma_len; | |
303 | ||
304 | while (ndesc_skipped) { | |
4adfcded | 305 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
306 | dd->dd_desc_len += dma_len; |
307 | ||
308 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 309 | } |
55624204 S |
310 | } |
311 | ||
312 | /* allocate descriptors */ | |
313 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, | |
314 | &dd->dd_desc_paddr, GFP_KERNEL); | |
315 | if (dd->dd_desc == NULL) { | |
316 | error = -ENOMEM; | |
317 | goto fail; | |
318 | } | |
4adfcded | 319 | ds = (u8 *) dd->dd_desc; |
55624204 S |
320 | ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
321 | name, ds, (u32) dd->dd_desc_len, | |
322 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
323 | ||
324 | /* allocate buffers */ | |
325 | bsize = sizeof(struct ath_buf) * nbuf; | |
326 | bf = kzalloc(bsize, GFP_KERNEL); | |
327 | if (bf == NULL) { | |
328 | error = -ENOMEM; | |
329 | goto fail2; | |
330 | } | |
331 | dd->dd_bufptr = bf; | |
332 | ||
4adfcded | 333 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { |
55624204 S |
334 | bf->bf_desc = ds; |
335 | bf->bf_daddr = DS2PHYS(dd, ds); | |
336 | ||
337 | if (!(sc->sc_ah->caps.hw_caps & | |
338 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
339 | /* | |
340 | * Skip descriptor addresses which can cause 4KB | |
341 | * boundary crossing (addr + length) with a 32 dword | |
342 | * descriptor fetch. | |
343 | */ | |
344 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
345 | BUG_ON((caddr_t) bf->bf_desc >= | |
346 | ((caddr_t) dd->dd_desc + | |
347 | dd->dd_desc_len)); | |
348 | ||
4adfcded | 349 | ds += (desc_len * ndesc); |
55624204 S |
350 | bf->bf_desc = ds; |
351 | bf->bf_daddr = DS2PHYS(dd, ds); | |
352 | } | |
353 | } | |
354 | list_add_tail(&bf->list, head); | |
355 | } | |
356 | return 0; | |
357 | fail2: | |
358 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
359 | dd->dd_desc_paddr); | |
360 | fail: | |
361 | memset(dd, 0, sizeof(*dd)); | |
362 | return error; | |
363 | #undef ATH_DESC_4KB_BOUND_CHECK | |
364 | #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED | |
365 | #undef DS2PHYS | |
366 | } | |
367 | ||
285f2dda | 368 | static void ath9k_init_crypto(struct ath_softc *sc) |
55624204 | 369 | { |
285f2dda S |
370 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
371 | int i = 0; | |
55624204 S |
372 | |
373 | /* Get the hardware key cache size. */ | |
285f2dda | 374 | common->keymax = sc->sc_ah->caps.keycache_size; |
55624204 S |
375 | if (common->keymax > ATH_KEYMAX) { |
376 | ath_print(common, ATH_DBG_ANY, | |
377 | "Warning, using only %u entries in %u key cache\n", | |
378 | ATH_KEYMAX, common->keymax); | |
379 | common->keymax = ATH_KEYMAX; | |
380 | } | |
381 | ||
382 | /* | |
383 | * Reset the key cache since some parts do not | |
384 | * reset the contents on initial power up. | |
385 | */ | |
386 | for (i = 0; i < common->keymax; i++) | |
040e539e | 387 | ath_hw_keyreset(common, (u16) i); |
55624204 | 388 | |
55624204 | 389 | /* |
285f2dda S |
390 | * Check whether the separate key cache entries |
391 | * are required to handle both tx+rx MIC keys. | |
392 | * With split mic keys the number of stations is limited | |
393 | * to 27 otherwise 59. | |
55624204 | 394 | */ |
117675d0 BR |
395 | if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) |
396 | common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED; | |
285f2dda S |
397 | } |
398 | ||
399 | static int ath9k_init_btcoex(struct ath_softc *sc) | |
400 | { | |
066dae93 FF |
401 | struct ath_txq *txq; |
402 | int r; | |
285f2dda S |
403 | |
404 | switch (sc->sc_ah->btcoex_hw.scheme) { | |
405 | case ATH_BTCOEX_CFG_NONE: | |
406 | break; | |
407 | case ATH_BTCOEX_CFG_2WIRE: | |
408 | ath9k_hw_btcoex_init_2wire(sc->sc_ah); | |
409 | break; | |
410 | case ATH_BTCOEX_CFG_3WIRE: | |
411 | ath9k_hw_btcoex_init_3wire(sc->sc_ah); | |
412 | r = ath_init_btcoex_timer(sc); | |
413 | if (r) | |
414 | return -1; | |
066dae93 FF |
415 | txq = sc->tx.txq_map[WME_AC_BE]; |
416 | ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum); | |
285f2dda S |
417 | sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; |
418 | break; | |
419 | default: | |
420 | WARN_ON(1); | |
421 | break; | |
422 | } | |
423 | ||
424 | return 0; | |
425 | } | |
426 | ||
427 | static int ath9k_init_queues(struct ath_softc *sc) | |
428 | { | |
285f2dda S |
429 | int i = 0; |
430 | ||
285f2dda | 431 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 432 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
433 | |
434 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; | |
435 | ath_cabq_update(sc); | |
436 | ||
066dae93 FF |
437 | for (i = 0; i < WME_NUM_AC; i++) |
438 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); | |
55624204 | 439 | |
285f2dda | 440 | return 0; |
285f2dda S |
441 | } |
442 | ||
f209f529 | 443 | static int ath9k_init_channels_rates(struct ath_softc *sc) |
285f2dda | 444 | { |
f209f529 FF |
445 | void *channels; |
446 | ||
cac4220b FF |
447 | BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + |
448 | ARRAY_SIZE(ath9k_5ghz_chantable) != | |
449 | ATH9K_NUM_CHANNELS); | |
450 | ||
d4659912 | 451 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { |
f209f529 FF |
452 | channels = kmemdup(ath9k_2ghz_chantable, |
453 | sizeof(ath9k_2ghz_chantable), GFP_KERNEL); | |
454 | if (!channels) | |
455 | return -ENOMEM; | |
456 | ||
457 | sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; | |
285f2dda S |
458 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; |
459 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
460 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
461 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
462 | sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
463 | ARRAY_SIZE(ath9k_legacy_rates); | |
55624204 S |
464 | } |
465 | ||
d4659912 | 466 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { |
f209f529 FF |
467 | channels = kmemdup(ath9k_5ghz_chantable, |
468 | sizeof(ath9k_5ghz_chantable), GFP_KERNEL); | |
469 | if (!channels) { | |
470 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) | |
471 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
472 | return -ENOMEM; | |
473 | } | |
474 | ||
475 | sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; | |
285f2dda S |
476 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; |
477 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
478 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
479 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
480 | ath9k_legacy_rates + 4; | |
481 | sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
482 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
483 | } | |
f209f529 | 484 | return 0; |
285f2dda | 485 | } |
55624204 | 486 | |
285f2dda S |
487 | static void ath9k_init_misc(struct ath_softc *sc) |
488 | { | |
489 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
490 | int i = 0; | |
491 | ||
285f2dda | 492 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 S |
493 | |
494 | sc->config.txpowlimit = ATH_TXPOWER_MAX; | |
495 | ||
285f2dda | 496 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
55624204 S |
497 | sc->sc_flags |= SC_OP_TXAGGR; |
498 | sc->sc_flags |= SC_OP_RXAGGR; | |
499 | } | |
500 | ||
285f2dda S |
501 | common->tx_chainmask = sc->sc_ah->caps.tx_chainmask; |
502 | common->rx_chainmask = sc->sc_ah->caps.rx_chainmask; | |
55624204 | 503 | |
8fe65368 | 504 | ath9k_hw_set_diversity(sc->sc_ah, true); |
285f2dda | 505 | sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah); |
55624204 | 506 | |
364734fa | 507 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
55624204 | 508 | |
285f2dda | 509 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 510 | |
55624204 S |
511 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
512 | sc->beacon.bslot[i] = NULL; | |
513 | sc->beacon.bslot_aphy[i] = NULL; | |
514 | } | |
102885a5 VT |
515 | |
516 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
517 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
285f2dda | 518 | } |
55624204 | 519 | |
285f2dda S |
520 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid, |
521 | const struct ath_bus_ops *bus_ops) | |
522 | { | |
523 | struct ath_hw *ah = NULL; | |
524 | struct ath_common *common; | |
525 | int ret = 0, i; | |
526 | int csz = 0; | |
55624204 | 527 | |
285f2dda S |
528 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); |
529 | if (!ah) | |
530 | return -ENOMEM; | |
531 | ||
532 | ah->hw_version.devid = devid; | |
533 | ah->hw_version.subsysid = subsysid; | |
534 | sc->sc_ah = ah; | |
535 | ||
536 | common = ath9k_hw_common(ah); | |
537 | common->ops = &ath9k_common_ops; | |
538 | common->bus_ops = bus_ops; | |
539 | common->ah = ah; | |
540 | common->hw = sc->hw; | |
541 | common->priv = sc; | |
542 | common->debug_mask = ath9k_debug; | |
20b25744 | 543 | spin_lock_init(&common->cc_lock); |
285f2dda S |
544 | |
545 | spin_lock_init(&sc->wiphy_lock); | |
285f2dda S |
546 | spin_lock_init(&sc->sc_serial_rw); |
547 | spin_lock_init(&sc->sc_pm_lock); | |
548 | mutex_init(&sc->mutex); | |
549 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | |
550 | tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, | |
551 | (unsigned long)sc); | |
552 | ||
553 | /* | |
554 | * Cache line size is used to size and align various | |
555 | * structures used to communicate with the hardware. | |
556 | */ | |
557 | ath_read_cachesize(common, &csz); | |
558 | common->cachelsz = csz << 2; /* convert to bytes */ | |
559 | ||
d70357d5 | 560 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 561 | ret = ath9k_hw_init(ah); |
d70357d5 | 562 | if (ret) |
285f2dda | 563 | goto err_hw; |
55624204 | 564 | |
285f2dda S |
565 | ret = ath9k_init_debug(ah); |
566 | if (ret) { | |
567 | ath_print(common, ATH_DBG_FATAL, | |
568 | "Unable to create debugfs files\n"); | |
569 | goto err_debug; | |
55624204 S |
570 | } |
571 | ||
285f2dda S |
572 | ret = ath9k_init_queues(sc); |
573 | if (ret) | |
574 | goto err_queues; | |
575 | ||
576 | ret = ath9k_init_btcoex(sc); | |
577 | if (ret) | |
578 | goto err_btcoex; | |
579 | ||
f209f529 FF |
580 | ret = ath9k_init_channels_rates(sc); |
581 | if (ret) | |
582 | goto err_btcoex; | |
583 | ||
285f2dda | 584 | ath9k_init_crypto(sc); |
285f2dda S |
585 | ath9k_init_misc(sc); |
586 | ||
55624204 | 587 | return 0; |
285f2dda S |
588 | |
589 | err_btcoex: | |
55624204 S |
590 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
591 | if (ATH_TXQ_SETUP(sc, i)) | |
592 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda S |
593 | err_queues: |
594 | ath9k_exit_debug(ah); | |
595 | err_debug: | |
596 | ath9k_hw_deinit(ah); | |
597 | err_hw: | |
598 | tasklet_kill(&sc->intr_tq); | |
599 | tasklet_kill(&sc->bcon_tasklet); | |
55624204 | 600 | |
285f2dda S |
601 | kfree(ah); |
602 | sc->sc_ah = NULL; | |
603 | ||
604 | return ret; | |
55624204 S |
605 | } |
606 | ||
babcbc29 FF |
607 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
608 | { | |
609 | struct ieee80211_supported_band *sband; | |
610 | struct ieee80211_channel *chan; | |
611 | struct ath_hw *ah = sc->sc_ah; | |
612 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
613 | int i; | |
614 | ||
615 | sband = &sc->sbands[band]; | |
616 | for (i = 0; i < sband->n_channels; i++) { | |
617 | chan = &sband->channels[i]; | |
618 | ah->curchan = &ah->channels[chan->hw_value]; | |
619 | ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20); | |
620 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); | |
621 | chan->max_power = reg->max_power_level / 2; | |
622 | } | |
623 | } | |
624 | ||
625 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
626 | { | |
627 | struct ath_hw *ah = sc->sc_ah; | |
628 | struct ath9k_channel *curchan = ah->curchan; | |
629 | ||
630 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
631 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | |
632 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
633 | ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); | |
634 | ||
635 | ah->curchan = curchan; | |
636 | } | |
637 | ||
285f2dda | 638 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 639 | { |
285f2dda S |
640 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
641 | ||
55624204 S |
642 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
643 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
644 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 S |
645 | IEEE80211_HW_SUPPORTS_PS | |
646 | IEEE80211_HW_PS_NULLFUNC_STACK | | |
05df4986 VN |
647 | IEEE80211_HW_SPECTRUM_MGMT | |
648 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; | |
55624204 | 649 | |
5ffaf8a3 LR |
650 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
651 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
652 | ||
55624204 S |
653 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt) |
654 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; | |
655 | ||
656 | hw->wiphy->interface_modes = | |
657 | BIT(NL80211_IFTYPE_AP) | | |
e51f3eff | 658 | BIT(NL80211_IFTYPE_WDS) | |
55624204 S |
659 | BIT(NL80211_IFTYPE_STATION) | |
660 | BIT(NL80211_IFTYPE_ADHOC) | | |
661 | BIT(NL80211_IFTYPE_MESH_POINT); | |
662 | ||
008443de LR |
663 | if (AR_SREV_5416(sc->sc_ah)) |
664 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
55624204 S |
665 | |
666 | hw->queues = 4; | |
667 | hw->max_rates = 4; | |
668 | hw->channel_change_time = 5000; | |
669 | hw->max_listen_interval = 10; | |
65896510 | 670 | hw->max_rate_tries = 10; |
55624204 S |
671 | hw->sta_data_size = sizeof(struct ath_node); |
672 | hw->vif_data_size = sizeof(struct ath_vif); | |
673 | ||
6e5c2b4e | 674 | #ifdef CONFIG_ATH9K_RATE_CONTROL |
55624204 | 675 | hw->rate_control_algorithm = "ath9k_rate_control"; |
6e5c2b4e | 676 | #endif |
55624204 | 677 | |
d4659912 | 678 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
55624204 S |
679 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
680 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
d4659912 | 681 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
55624204 S |
682 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
683 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
285f2dda S |
684 | |
685 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { | |
d4659912 | 686 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
285f2dda | 687 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); |
d4659912 | 688 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
285f2dda S |
689 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); |
690 | } | |
691 | ||
692 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
693 | } |
694 | ||
285f2dda | 695 | int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, |
55624204 S |
696 | const struct ath_bus_ops *bus_ops) |
697 | { | |
698 | struct ieee80211_hw *hw = sc->hw; | |
9fa23e17 | 699 | struct ath_wiphy *aphy = hw->priv; |
55624204 S |
700 | struct ath_common *common; |
701 | struct ath_hw *ah; | |
285f2dda | 702 | int error = 0; |
55624204 S |
703 | struct ath_regulatory *reg; |
704 | ||
285f2dda S |
705 | /* Bring up device */ |
706 | error = ath9k_init_softc(devid, sc, subsysid, bus_ops); | |
55624204 | 707 | if (error != 0) |
285f2dda | 708 | goto error_init; |
55624204 S |
709 | |
710 | ah = sc->sc_ah; | |
711 | common = ath9k_hw_common(ah); | |
285f2dda | 712 | ath9k_set_hw_capab(sc, hw); |
55624204 | 713 | |
285f2dda | 714 | /* Initialize regulatory */ |
55624204 S |
715 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
716 | ath9k_reg_notifier); | |
717 | if (error) | |
285f2dda | 718 | goto error_regd; |
55624204 S |
719 | |
720 | reg = &common->regulatory; | |
721 | ||
285f2dda | 722 | /* Setup TX DMA */ |
55624204 S |
723 | error = ath_tx_init(sc, ATH_TXBUF); |
724 | if (error != 0) | |
285f2dda | 725 | goto error_tx; |
55624204 | 726 | |
285f2dda | 727 | /* Setup RX DMA */ |
55624204 S |
728 | error = ath_rx_init(sc, ATH_RXBUF); |
729 | if (error != 0) | |
285f2dda | 730 | goto error_rx; |
55624204 | 731 | |
babcbc29 FF |
732 | ath9k_init_txpower_limits(sc); |
733 | ||
285f2dda | 734 | /* Register with mac80211 */ |
55624204 | 735 | error = ieee80211_register_hw(hw); |
285f2dda S |
736 | if (error) |
737 | goto error_register; | |
55624204 | 738 | |
285f2dda | 739 | /* Handle world regulatory */ |
55624204 S |
740 | if (!ath_is_world_regd(reg)) { |
741 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
742 | if (error) | |
285f2dda | 743 | goto error_world; |
55624204 S |
744 | } |
745 | ||
347809fc | 746 | INIT_WORK(&sc->hw_check_work, ath_hw_check); |
9f42c2b6 | 747 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); |
285f2dda S |
748 | INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work); |
749 | INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work); | |
750 | sc->wiphy_scheduler_int = msecs_to_jiffies(500); | |
9fa23e17 | 751 | aphy->last_rssi = ATH_RSSI_DUMMY_MARKER; |
55624204 | 752 | |
285f2dda | 753 | ath_init_leds(sc); |
55624204 S |
754 | ath_start_rfkill_poll(sc); |
755 | ||
10598c12 VN |
756 | pm_qos_add_request(&ath9k_pm_qos_req, PM_QOS_CPU_DMA_LATENCY, |
757 | PM_QOS_DEFAULT_VALUE); | |
758 | ||
55624204 S |
759 | return 0; |
760 | ||
285f2dda S |
761 | error_world: |
762 | ieee80211_unregister_hw(hw); | |
763 | error_register: | |
764 | ath_rx_cleanup(sc); | |
765 | error_rx: | |
766 | ath_tx_cleanup(sc); | |
767 | error_tx: | |
768 | /* Nothing */ | |
769 | error_regd: | |
770 | ath9k_deinit_softc(sc); | |
771 | error_init: | |
55624204 S |
772 | return error; |
773 | } | |
774 | ||
775 | /*****************************/ | |
776 | /* De-Initialization */ | |
777 | /*****************************/ | |
778 | ||
285f2dda | 779 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 780 | { |
285f2dda | 781 | int i = 0; |
55624204 | 782 | |
f209f529 FF |
783 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) |
784 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
785 | ||
786 | if (sc->sbands[IEEE80211_BAND_5GHZ].channels) | |
787 | kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels); | |
788 | ||
285f2dda S |
789 | if ((sc->btcoex.no_stomp_timer) && |
790 | sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) | |
791 | ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer); | |
55624204 | 792 | |
285f2dda S |
793 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
794 | if (ATH_TXQ_SETUP(sc, i)) | |
795 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
796 | ||
797 | ath9k_exit_debug(sc->sc_ah); | |
798 | ath9k_hw_deinit(sc->sc_ah); | |
799 | ||
800 | tasklet_kill(&sc->intr_tq); | |
801 | tasklet_kill(&sc->bcon_tasklet); | |
736b3a27 S |
802 | |
803 | kfree(sc->sc_ah); | |
804 | sc->sc_ah = NULL; | |
55624204 S |
805 | } |
806 | ||
285f2dda | 807 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
808 | { |
809 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
810 | int i = 0; |
811 | ||
812 | ath9k_ps_wakeup(sc); | |
813 | ||
55624204 | 814 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 815 | ath_deinit_leds(sc); |
55624204 S |
816 | |
817 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
818 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
819 | if (aphy == NULL) | |
820 | continue; | |
821 | sc->sec_wiphy[i] = NULL; | |
822 | ieee80211_unregister_hw(aphy->hw); | |
823 | ieee80211_free_hw(aphy->hw); | |
824 | } | |
285f2dda | 825 | |
55624204 | 826 | ieee80211_unregister_hw(hw); |
e8364bb8 | 827 | pm_qos_remove_request(&ath9k_pm_qos_req); |
55624204 S |
828 | ath_rx_cleanup(sc); |
829 | ath_tx_cleanup(sc); | |
285f2dda | 830 | ath9k_deinit_softc(sc); |
447a42c2 | 831 | kfree(sc->sec_wiphy); |
55624204 S |
832 | } |
833 | ||
834 | void ath_descdma_cleanup(struct ath_softc *sc, | |
835 | struct ath_descdma *dd, | |
836 | struct list_head *head) | |
837 | { | |
838 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
839 | dd->dd_desc_paddr); | |
840 | ||
841 | INIT_LIST_HEAD(head); | |
842 | kfree(dd->dd_bufptr); | |
843 | memset(dd, 0, sizeof(*dd)); | |
844 | } | |
845 | ||
55624204 S |
846 | /************************/ |
847 | /* Module Hooks */ | |
848 | /************************/ | |
849 | ||
850 | static int __init ath9k_init(void) | |
851 | { | |
852 | int error; | |
853 | ||
854 | /* Register rate control algorithm */ | |
855 | error = ath_rate_control_register(); | |
856 | if (error != 0) { | |
857 | printk(KERN_ERR | |
858 | "ath9k: Unable to register rate control " | |
859 | "algorithm: %d\n", | |
860 | error); | |
861 | goto err_out; | |
862 | } | |
863 | ||
864 | error = ath9k_debug_create_root(); | |
865 | if (error) { | |
866 | printk(KERN_ERR | |
867 | "ath9k: Unable to create debugfs root: %d\n", | |
868 | error); | |
869 | goto err_rate_unregister; | |
870 | } | |
871 | ||
872 | error = ath_pci_init(); | |
873 | if (error < 0) { | |
874 | printk(KERN_ERR | |
875 | "ath9k: No PCI devices found, driver not installed.\n"); | |
876 | error = -ENODEV; | |
877 | goto err_remove_root; | |
878 | } | |
879 | ||
880 | error = ath_ahb_init(); | |
881 | if (error < 0) { | |
882 | error = -ENODEV; | |
883 | goto err_pci_exit; | |
884 | } | |
885 | ||
886 | return 0; | |
887 | ||
888 | err_pci_exit: | |
889 | ath_pci_exit(); | |
890 | ||
891 | err_remove_root: | |
892 | ath9k_debug_remove_root(); | |
893 | err_rate_unregister: | |
894 | ath_rate_control_unregister(); | |
895 | err_out: | |
896 | return error; | |
897 | } | |
898 | module_init(ath9k_init); | |
899 | ||
900 | static void __exit ath9k_exit(void) | |
901 | { | |
902 | ath_ahb_exit(); | |
903 | ath_pci_exit(); | |
904 | ath9k_debug_remove_root(); | |
905 | ath_rate_control_unregister(); | |
906 | printk(KERN_INFO "%s: Driver unloaded\n", dev_info); | |
907 | } | |
908 | module_exit(ath9k_exit); |