[net-next-2.6.git] / drivers / net / tokenring / abyss.h

/* 
 * abyss.h: Header for the abyss tms380tr module
 *
 * Authors:
 * - Adam Fritzler
 */

#ifndef __LINUX_MADGETR_H
#define __LINUX_MADGETR_H

#ifdef __KERNEL__

/*
 * For Madge Smart 16/4 PCI Mk2.  Since we increment the base address
 * to get everything correct for the TMS SIF, we do these as negatives
 * as they fall below the SIF in addressing.
 */
#define PCIBM2_INT_STATUS_REG          ((short)-15)/* 0x01 */
#define PCIBM2_INT_CONTROL_REG         ((short)-14)/* 0x02 */
#define PCIBM2_RESET_REG               ((short)-12)/* 0x04 */
#define PCIBM2_SEEPROM_REG             ((short)-9) /* 0x07 */

#define PCIBM2_INT_CONTROL_REG_SINTEN           0x02
#define PCIBM2_INT_CONTROL_REG_PCI_ERR_ENABLE   0x80
#define PCIBM2_INT_STATUS_REG_PCI_ERR           0x80

#define PCIBM2_RESET_REG_CHIP_NRES              0x01
#define PCIBM2_RESET_REG_FIFO_NRES              0x02
#define PCIBM2_RESET_REG_SIF_NRES               0x04

#define PCIBM2_FIFO_THRESHOLD   0x21
#define PCIBM2_BURST_LENGTH     0x22

/*
 * Bits in PCIBM2_SEEPROM_REG.
 */
#define AT24_ENABLE             0x04
#define AT24_DATA               0x02
#define AT24_CLOCK              0x01

/*
 * AT24 Commands.
 */
#define AT24_WRITE              0xA0
#define AT24_READ               0xA1

/*
 * Addresses in AT24 SEEPROM.
 */
#define PCIBM2_SEEPROM_BIA          0x12
#define PCIBM2_SEEPROM_RING_SPEED   0x18
#define PCIBM2_SEEPROM_RAM_SIZE     0x1A
#define PCIBM2_SEEPROM_HWF1         0x1C
#define PCIBM2_SEEPROM_HWF2         0x1E


#endif /* __KERNEL__ */
#endif /* __LINUX_MADGETR_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* abyss.h: Header for the abyss tms380tr module
	3	*
	4	* Authors:
726a6459	5	* - Adam Fritzler
1da177e4 LT	6	*/
	7
	8	#ifndef __LINUX_MADGETR_H
	9	#define __LINUX_MADGETR_H
	10
	11	#ifdef __KERNEL__
	12
	13	/*
	14	* For Madge Smart 16/4 PCI Mk2. Since we increment the base address
	15	* to get everything correct for the TMS SIF, we do these as negatives
	16	* as they fall below the SIF in addressing.
	17	*/
	18	#define PCIBM2_INT_STATUS_REG ((short)-15)/* 0x01 */
	19	#define PCIBM2_INT_CONTROL_REG ((short)-14)/* 0x02 */
	20	#define PCIBM2_RESET_REG ((short)-12)/* 0x04 */
	21	#define PCIBM2_SEEPROM_REG ((short)-9) /* 0x07 */
	22
	23	#define PCIBM2_INT_CONTROL_REG_SINTEN 0x02
	24	#define PCIBM2_INT_CONTROL_REG_PCI_ERR_ENABLE 0x80
	25	#define PCIBM2_INT_STATUS_REG_PCI_ERR 0x80
	26
	27	#define PCIBM2_RESET_REG_CHIP_NRES 0x01
	28	#define PCIBM2_RESET_REG_FIFO_NRES 0x02
	29	#define PCIBM2_RESET_REG_SIF_NRES 0x04
	30
	31	#define PCIBM2_FIFO_THRESHOLD 0x21
	32	#define PCIBM2_BURST_LENGTH 0x22
	33
	34	/*
	35	* Bits in PCIBM2_SEEPROM_REG.
	36	*/
	37	#define AT24_ENABLE 0x04
	38	#define AT24_DATA 0x02
	39	#define AT24_CLOCK 0x01
	40
	41	/*
	42	* AT24 Commands.
	43	*/
	44	#define AT24_WRITE 0xA0
	45	#define AT24_READ 0xA1
	46
	47	/*
	48	* Addresses in AT24 SEEPROM.
	49	*/
	50	#define PCIBM2_SEEPROM_BIA 0x12
	51	#define PCIBM2_SEEPROM_RING_SPEED 0x18
	52	#define PCIBM2_SEEPROM_RAM_SIZE 0x1A
	53	#define PCIBM2_SEEPROM_HWF1 0x1C
	54	#define PCIBM2_SEEPROM_HWF2 0x1E
	55
	56
	57	#endif /* __KERNEL__ */
	58	#endif /* __LINUX_MADGETR_H */