[net-next-2.6.git] / drivers / net / stmmac / stmmac_mdio.c

/*******************************************************************************
  STMMAC Ethernet Driver -- MDIO bus implementation
  Provides Bus interface for MII registers

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Carl Shaw <carl.shaw@st.com>
  Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <linux/mii.h>
#include <linux/phy.h>
#include <linux/slab.h>

#include "stmmac.h"

#define MII_BUSY 0x00000001
#define MII_WRITE 0x00000002

/**
 * stmmac_mdio_read
 * @bus: points to the mii_bus structure
 * @phyaddr: MII addr reg bits 15-11
 * @phyreg: MII addr reg bits 10-6
 * Description: it reads data from the MII register from within the phy device.
 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
 * accessing the PHY registers.
 * Fortunately, it seems this has no drawback for the 7109 MAC.
 */
static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
{
	struct net_device *ndev = bus->priv;
	struct stmmac_priv *priv = netdev_priv(ndev);
	unsigned int mii_address = priv->hw->mii.addr;
	unsigned int mii_data = priv->hw->mii.data;

	int data;
	u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
			((phyreg << 6) & (0x000007C0)));
	regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);

	do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
	writel(regValue, priv->ioaddr + mii_address);
	do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);

	/* Read the data from the MII data register */
	data = (int)readl(priv->ioaddr + mii_data);

	return data;
}

/**
 * stmmac_mdio_write
 * @bus: points to the mii_bus structure
 * @phyaddr: MII addr reg bits 15-11
 * @phyreg: MII addr reg bits 10-6
 * @phydata: phy data
 * Description: it writes the data into the MII register from within the device.
 */
static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
			     u16 phydata)
{
	struct net_device *ndev = bus->priv;
	struct stmmac_priv *priv = netdev_priv(ndev);
	unsigned int mii_address = priv->hw->mii.addr;
	unsigned int mii_data = priv->hw->mii.data;

	u16 value =
	    (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
	    | MII_WRITE;

	value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);


	/* Wait until any existing MII operation is complete */
	do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);

	/* Set the MII address register to write */
	writel(phydata, priv->ioaddr + mii_data);
	writel(value, priv->ioaddr + mii_address);

	/* Wait until any existing MII operation is complete */
	do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);

	return 0;
}

/**
 * stmmac_mdio_reset
 * @bus: points to the mii_bus structure
 * Description: reset the MII bus
 */
static int stmmac_mdio_reset(struct mii_bus *bus)
{
	struct net_device *ndev = bus->priv;
	struct stmmac_priv *priv = netdev_priv(ndev);
	unsigned int mii_address = priv->hw->mii.addr;

	if (priv->phy_reset) {
		pr_debug("stmmac_mdio_reset: calling phy_reset\n");
		priv->phy_reset(priv->plat->bsp_priv);
	}

	/* This is a workaround for problems with the STE101P PHY.
	 * It doesn't complete its reset until at least one clock cycle
	 * on MDC, so perform a dummy mdio read.
	 */
	writel(0, priv->ioaddr + mii_address);

	return 0;
}

/**
 * stmmac_mdio_register
 * @ndev: net device structure
 * Description: it registers the MII bus
 */
int stmmac_mdio_register(struct net_device *ndev)
{
	int err = 0;
	struct mii_bus *new_bus;
	int *irqlist;
	struct stmmac_priv *priv = netdev_priv(ndev);
	int addr, found;

	new_bus = mdiobus_alloc();
	if (new_bus == NULL)
		return -ENOMEM;

	irqlist = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
	if (irqlist == NULL) {
		err = -ENOMEM;
		goto irqlist_alloc_fail;
	}

	/* Assign IRQ to phy at address phy_addr */
	if (priv->phy_addr != -1)
		irqlist[priv->phy_addr] = priv->phy_irq;

	new_bus->name = "STMMAC MII Bus";
	new_bus->read = &stmmac_mdio_read;
	new_bus->write = &stmmac_mdio_write;
	new_bus->reset = &stmmac_mdio_reset;
	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
	new_bus->priv = ndev;
	new_bus->irq = irqlist;
	new_bus->phy_mask = priv->phy_mask;
	new_bus->parent = priv->device;
	err = mdiobus_register(new_bus);
	if (err != 0) {
		pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
		goto bus_register_fail;
	}

	priv->mii = new_bus;

	found = 0;
	for (addr = 0; addr < 32; addr++) {
		struct phy_device *phydev = new_bus->phy_map[addr];
		if (phydev) {
			if (priv->phy_addr == -1) {
				priv->phy_addr = addr;
				phydev->irq = priv->phy_irq;
				irqlist[addr] = priv->phy_irq;
			}
			pr_info("%s: PHY ID %08x at %d IRQ %d (%s)%s\n",
			       ndev->name, phydev->phy_id, addr,
			       phydev->irq, dev_name(&phydev->dev),
			       (addr == priv->phy_addr) ? " active" : "");
			found = 1;
		}
	}

	if (!found)
		pr_warning("%s: No PHY found\n", ndev->name);

	return 0;
bus_register_fail:
	kfree(irqlist);
irqlist_alloc_fail:
	kfree(new_bus);
	return err;
}

/**
 * stmmac_mdio_unregister
 * @ndev: net device structure
 * Description: it unregisters the MII bus
 */
int stmmac_mdio_unregister(struct net_device *ndev)
{
	struct stmmac_priv *priv = netdev_priv(ndev);

	mdiobus_unregister(priv->mii);
	priv->mii->priv = NULL;
	kfree(priv->mii);

	return 0;
}
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	STMMAC Ethernet Driver -- MDIO bus implementation
	3	Provides Bus interface for MII registers
	4
	5	Copyright (C) 2007-2009 STMicroelectronics Ltd
	6
	7	This program is free software; you can redistribute it and/or modify it
	8	under the terms and conditions of the GNU General Public License,
	9	version 2, as published by the Free Software Foundation.
	10
	11	This program is distributed in the hope it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	more details.
	15
	16	You should have received a copy of the GNU General Public License along with
	17	this program; if not, write to the Free Software Foundation, Inc.,
	18	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19
	20	The full GNU General Public License is included in this distribution in
	21	the file called "COPYING".
	22
	23	Author: Carl Shaw <carl.shaw@st.com>
	24	Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	25	*******************************************************************************/
	26
47dd7a54 GC	27	#include <linux/mii.h>
47dd7a54 GC	28	#include <linux/phy.h>
5a0e3ad6	29	#include <linux/slab.h>
47dd7a54 GC	30
	31	#include "stmmac.h"
	32
	33	#define MII_BUSY 0x00000001
	34	#define MII_WRITE 0x00000002
	35
	36	/**
	37	* stmmac_mdio_read
	38	* @bus: points to the mii_bus structure
	39	* @phyaddr: MII addr reg bits 15-11
	40	* @phyreg: MII addr reg bits 10-6
	41	* Description: it reads data from the MII register from within the phy device.
	42	* For the 7111 GMAC, we must set the bit 0 in the MII address register while
	43	* accessing the PHY registers.
	44	* Fortunately, it seems this has no drawback for the 7109 MAC.
	45	*/
	46	static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
	47	{
	48	struct net_device *ndev = bus->priv;
	49	struct stmmac_priv *priv = netdev_priv(ndev);
db98a0b0 GC	50	unsigned int mii_address = priv->hw->mii.addr;
db98a0b0 GC	51	unsigned int mii_data = priv->hw->mii.data;
47dd7a54 GC	52
	53	int data;
	54	u16 regValue = (((phyaddr << 11) & (0x0000F800)) \|
	55	((phyreg << 6) & (0x000007C0)));
9dfeb4d9	56	regValue \|= MII_BUSY \| ((priv->plat->clk_csr & 7) << 2);
47dd7a54	57
ad01b7d4 GC	58	do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
	59	writel(regValue, priv->ioaddr + mii_address);
	60	do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
47dd7a54 GC	61
47dd7a54 GC	62	/* Read the data from the MII data register */
ad01b7d4	63	data = (int)readl(priv->ioaddr + mii_data);
47dd7a54 GC	64
	65	return data;
	66	}
	67
	68	/**
	69	* stmmac_mdio_write
	70	* @bus: points to the mii_bus structure
	71	* @phyaddr: MII addr reg bits 15-11
	72	* @phyreg: MII addr reg bits 10-6
	73	* @phydata: phy data
	74	* Description: it writes the data into the MII register from within the device.
	75	*/
	76	static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
	77	u16 phydata)
	78	{
	79	struct net_device *ndev = bus->priv;
	80	struct stmmac_priv *priv = netdev_priv(ndev);
db98a0b0 GC	81	unsigned int mii_address = priv->hw->mii.addr;
db98a0b0 GC	82	unsigned int mii_data = priv->hw->mii.data;
47dd7a54 GC	83
	84	u16 value =
	85	(((phyaddr << 11) & (0x0000F800)) \| ((phyreg << 6) & (0x000007C0)))
	86	\| MII_WRITE;
	87
9dfeb4d9	88	value \|= MII_BUSY \| ((priv->plat->clk_csr & 7) << 2);
dfb8fb96	89
47dd7a54 GC	90
47dd7a54 GC	91	/* Wait until any existing MII operation is complete */
ad01b7d4	92	do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
47dd7a54 GC	93
47dd7a54 GC	94	/* Set the MII address register to write */
ad01b7d4 GC	95	writel(phydata, priv->ioaddr + mii_data);
ad01b7d4 GC	96	writel(value, priv->ioaddr + mii_address);
47dd7a54 GC	97
47dd7a54 GC	98	/* Wait until any existing MII operation is complete */
ad01b7d4	99	do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
47dd7a54 GC	100
	101	return 0;
	102	}
	103
	104	/**
	105	* stmmac_mdio_reset
	106	* @bus: points to the mii_bus structure
	107	* Description: reset the MII bus
	108	*/
	109	static int stmmac_mdio_reset(struct mii_bus *bus)
	110	{
	111	struct net_device *ndev = bus->priv;
	112	struct stmmac_priv *priv = netdev_priv(ndev);
db98a0b0	113	unsigned int mii_address = priv->hw->mii.addr;
47dd7a54 GC	114
	115	if (priv->phy_reset) {
	116	pr_debug("stmmac_mdio_reset: calling phy_reset\n");
9dfeb4d9	117	priv->phy_reset(priv->plat->bsp_priv);
47dd7a54 GC	118	}
	119
	120	/* This is a workaround for problems with the STE101P PHY.
	121	* It doesn't complete its reset until at least one clock cycle
	122	* on MDC, so perform a dummy mdio read.
	123	*/
ad01b7d4	124	writel(0, priv->ioaddr + mii_address);
47dd7a54 GC	125
	126	return 0;
	127	}
	128
	129	/**
	130	* stmmac_mdio_register
	131	* @ndev: net device structure
	132	* Description: it registers the MII bus
	133	*/
	134	int stmmac_mdio_register(struct net_device *ndev)
	135	{
	136	int err = 0;
	137	struct mii_bus *new_bus;
	138	int *irqlist;
	139	struct stmmac_priv *priv = netdev_priv(ndev);
	140	int addr, found;
	141
	142	new_bus = mdiobus_alloc();
	143	if (new_bus == NULL)
	144	return -ENOMEM;
	145
	146	irqlist = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
	147	if (irqlist == NULL) {
	148	err = -ENOMEM;
	149	goto irqlist_alloc_fail;
	150	}
	151
	152	/* Assign IRQ to phy at address phy_addr */
	153	if (priv->phy_addr != -1)
	154	irqlist[priv->phy_addr] = priv->phy_irq;
	155
	156	new_bus->name = "STMMAC MII Bus";
	157	new_bus->read = &stmmac_mdio_read;
	158	new_bus->write = &stmmac_mdio_write;
	159	new_bus->reset = &stmmac_mdio_reset;
9dfeb4d9	160	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
47dd7a54 GC	161	new_bus->priv = ndev;
	162	new_bus->irq = irqlist;
	163	new_bus->phy_mask = priv->phy_mask;
	164	new_bus->parent = priv->device;
	165	err = mdiobus_register(new_bus);
	166	if (err != 0) {
	167	pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
	168	goto bus_register_fail;
	169	}
	170
	171	priv->mii = new_bus;
	172
	173	found = 0;
	174	for (addr = 0; addr < 32; addr++) {
	175	struct phy_device *phydev = new_bus->phy_map[addr];
	176	if (phydev) {
	177	if (priv->phy_addr == -1) {
	178	priv->phy_addr = addr;
	179	phydev->irq = priv->phy_irq;
	180	irqlist[addr] = priv->phy_irq;
	181	}
	182	pr_info("%s: PHY ID %08x at %d IRQ %d (%s)%s\n",
	183	ndev->name, phydev->phy_id, addr,
	184	phydev->irq, dev_name(&phydev->dev),
	185	(addr == priv->phy_addr) ? " active" : "");
	186	found = 1;
	187	}
	188	}
	189
	190	if (!found)
	191	pr_warning("%s: No PHY found\n", ndev->name);
	192
	193	return 0;
	194	bus_register_fail:
	195	kfree(irqlist);
	196	irqlist_alloc_fail:
	197	kfree(new_bus);
	198	return err;
	199	}
	200
	201	/**
	202	* stmmac_mdio_unregister
	203	* @ndev: net device structure
	204	* Description: it unregisters the MII bus
	205	*/
	206	int stmmac_mdio_unregister(struct net_device *ndev)
	207	{
	208	struct stmmac_priv *priv = netdev_priv(ndev);
	209
	210	mdiobus_unregister(priv->mii);
	211	priv->mii->priv = NULL;
	212	kfree(priv->mii);
	213
	214	return 0;
	215	}