[net-next-2.6.git] / drivers / net / stmmac / stmmac_mdio.c

/*******************************************************************************
  STMMAC Ethernet Driver -- MDIO bus implementation
  Provides Bus interface for MII registers

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Carl Shaw <carl.shaw@st.com>
  Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <linux/mii.h>
#include <linux/phy.h>

#include "stmmac.h"

#define MII_BUSY 0x00000001
#define MII_WRITE 0x00000002

/**
 * stmmac_mdio_read
 * @bus: points to the mii_bus structure
 * @phyaddr: MII addr reg bits 15-11
 * @phyreg: MII addr reg bits 10-6
 * Description: it reads data from the MII register from within the phy device.
 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
 * accessing the PHY registers.
 * Fortunately, it seems this has no drawback for the 7109 MAC.
 */
static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
{
	struct net_device *ndev = bus->priv;
	struct stmmac_priv *priv = netdev_priv(ndev);
	unsigned long ioaddr = ndev->base_addr;
	unsigned int mii_address = priv->hw->mii.addr;
	unsigned int mii_data = priv->hw->mii.data;

	int data;
	u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
			((phyreg << 6) & (0x000007C0)));
	regValue |= MII_BUSY;	/* in case of GMAC */

	do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
	writel(regValue, ioaddr + mii_address);
	do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);

	/* Read the data from the MII data register */
	data = (int)readl(ioaddr + mii_data);

	return data;
}

/**
 * stmmac_mdio_write
 * @bus: points to the mii_bus structure
 * @phyaddr: MII addr reg bits 15-11
 * @phyreg: MII addr reg bits 10-6
 * @phydata: phy data
 * Description: it writes the data into the MII register from within the device.
 */
static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
			     u16 phydata)
{
	struct net_device *ndev = bus->priv;
	struct stmmac_priv *priv = netdev_priv(ndev);
	unsigned long ioaddr = ndev->base_addr;
	unsigned int mii_address = priv->hw->mii.addr;
	unsigned int mii_data = priv->hw->mii.data;

	u16 value =
	    (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
	    | MII_WRITE;

	value |= MII_BUSY;

	/* Wait until any existing MII operation is complete */
	do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);

	/* Set the MII address register to write */
	writel(phydata, ioaddr + mii_data);
	writel(value, ioaddr + mii_address);

	/* Wait until any existing MII operation is complete */
	do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);

	return 0;
}

/**
 * stmmac_mdio_reset
 * @bus: points to the mii_bus structure
 * Description: reset the MII bus
 */
static int stmmac_mdio_reset(struct mii_bus *bus)
{
	struct net_device *ndev = bus->priv;
	struct stmmac_priv *priv = netdev_priv(ndev);
	unsigned long ioaddr = ndev->base_addr;
	unsigned int mii_address = priv->hw->mii.addr;

	if (priv->phy_reset) {
		pr_debug("stmmac_mdio_reset: calling phy_reset\n");
		priv->phy_reset(priv->bsp_priv);
	}

	/* This is a workaround for problems with the STE101P PHY.
	 * It doesn't complete its reset until at least one clock cycle
	 * on MDC, so perform a dummy mdio read.
	 */
	writel(0, ioaddr + mii_address);

	return 0;
}

/**
 * stmmac_mdio_register
 * @ndev: net device structure
 * Description: it registers the MII bus
 */
int stmmac_mdio_register(struct net_device *ndev)
{
	int err = 0;
	struct mii_bus *new_bus;
	int *irqlist;
	struct stmmac_priv *priv = netdev_priv(ndev);
	int addr, found;

	new_bus = mdiobus_alloc();
	if (new_bus == NULL)
		return -ENOMEM;

	irqlist = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
	if (irqlist == NULL) {
		err = -ENOMEM;
		goto irqlist_alloc_fail;
	}

	/* Assign IRQ to phy at address phy_addr */
	if (priv->phy_addr != -1)
		irqlist[priv->phy_addr] = priv->phy_irq;

	new_bus->name = "STMMAC MII Bus";
	new_bus->read = &stmmac_mdio_read;
	new_bus->write = &stmmac_mdio_write;
	new_bus->reset = &stmmac_mdio_reset;
	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
	new_bus->priv = ndev;
	new_bus->irq = irqlist;
	new_bus->phy_mask = priv->phy_mask;
	new_bus->parent = priv->device;
	err = mdiobus_register(new_bus);
	if (err != 0) {
		pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
		goto bus_register_fail;
	}

	priv->mii = new_bus;

	found = 0;
	for (addr = 0; addr < 32; addr++) {
		struct phy_device *phydev = new_bus->phy_map[addr];
		if (phydev) {
			if (priv->phy_addr == -1) {
				priv->phy_addr = addr;
				phydev->irq = priv->phy_irq;
				irqlist[addr] = priv->phy_irq;
			}
			pr_info("%s: PHY ID %08x at %d IRQ %d (%s)%s\n",
			       ndev->name, phydev->phy_id, addr,
			       phydev->irq, dev_name(&phydev->dev),
			       (addr == priv->phy_addr) ? " active" : "");
			found = 1;
		}
	}

	if (!found)
		pr_warning("%s: No PHY found\n", ndev->name);

	return 0;
bus_register_fail:
	kfree(irqlist);
irqlist_alloc_fail:
	kfree(new_bus);
	return err;
}

/**
 * stmmac_mdio_unregister
 * @ndev: net device structure
 * Description: it unregisters the MII bus
 */
int stmmac_mdio_unregister(struct net_device *ndev)
{
	struct stmmac_priv *priv = netdev_priv(ndev);

	mdiobus_unregister(priv->mii);
	priv->mii->priv = NULL;
	kfree(priv->mii);

	return 0;
}
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	STMMAC Ethernet Driver -- MDIO bus implementation
	3	Provides Bus interface for MII registers
	4
	5	Copyright (C) 2007-2009 STMicroelectronics Ltd
	6
	7	This program is free software; you can redistribute it and/or modify it
	8	under the terms and conditions of the GNU General Public License,
	9	version 2, as published by the Free Software Foundation.
	10
	11	This program is distributed in the hope it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	more details.
	15
	16	You should have received a copy of the GNU General Public License along with
	17	this program; if not, write to the Free Software Foundation, Inc.,
	18	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19
	20	The full GNU General Public License is included in this distribution in
	21	the file called "COPYING".
	22
	23	Author: Carl Shaw <carl.shaw@st.com>
	24	Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	25	*******************************************************************************/
	26
47dd7a54 GC	27	#include <linux/mii.h>
	28	#include <linux/phy.h>
	29
	30	#include "stmmac.h"
	31
	32	#define MII_BUSY 0x00000001
	33	#define MII_WRITE 0x00000002
	34
	35	/**
	36	* stmmac_mdio_read
	37	* @bus: points to the mii_bus structure
	38	* @phyaddr: MII addr reg bits 15-11
	39	* @phyreg: MII addr reg bits 10-6
	40	* Description: it reads data from the MII register from within the phy device.
	41	* For the 7111 GMAC, we must set the bit 0 in the MII address register while
	42	* accessing the PHY registers.
	43	* Fortunately, it seems this has no drawback for the 7109 MAC.
	44	*/
	45	static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
	46	{
	47	struct net_device *ndev = bus->priv;
	48	struct stmmac_priv *priv = netdev_priv(ndev);
	49	unsigned long ioaddr = ndev->base_addr;
db98a0b0 GC	50	unsigned int mii_address = priv->hw->mii.addr;
db98a0b0 GC	51	unsigned int mii_data = priv->hw->mii.data;
47dd7a54 GC	52
	53	int data;
	54	u16 regValue = (((phyaddr << 11) & (0x0000F800)) \|
	55	((phyreg << 6) & (0x000007C0)));
	56	regValue \|= MII_BUSY; /* in case of GMAC */
	57
	58	do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
	59	writel(regValue, ioaddr + mii_address);
	60	do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
	61
	62	/* Read the data from the MII data register */
	63	data = (int)readl(ioaddr + mii_data);
	64
	65	return data;
	66	}
	67
	68	/**
	69	* stmmac_mdio_write
	70	* @bus: points to the mii_bus structure
	71	* @phyaddr: MII addr reg bits 15-11
	72	* @phyreg: MII addr reg bits 10-6
	73	* @phydata: phy data
	74	* Description: it writes the data into the MII register from within the device.
	75	*/
	76	static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
	77	u16 phydata)
	78	{
	79	struct net_device *ndev = bus->priv;
	80	struct stmmac_priv *priv = netdev_priv(ndev);
	81	unsigned long ioaddr = ndev->base_addr;
db98a0b0 GC	82	unsigned int mii_address = priv->hw->mii.addr;
db98a0b0 GC	83	unsigned int mii_data = priv->hw->mii.data;
47dd7a54 GC	84
	85	u16 value =
	86	(((phyaddr << 11) & (0x0000F800)) \| ((phyreg << 6) & (0x000007C0)))
	87	\| MII_WRITE;
	88
	89	value \|= MII_BUSY;
	90
	91	/* Wait until any existing MII operation is complete */
	92	do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
	93
	94	/* Set the MII address register to write */
	95	writel(phydata, ioaddr + mii_data);
	96	writel(value, ioaddr + mii_address);
	97
	98	/* Wait until any existing MII operation is complete */
	99	do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1);
	100
	101	return 0;
	102	}
	103
	104	/**
	105	* stmmac_mdio_reset
	106	* @bus: points to the mii_bus structure
	107	* Description: reset the MII bus
	108	*/
	109	static int stmmac_mdio_reset(struct mii_bus *bus)
	110	{
	111	struct net_device *ndev = bus->priv;
	112	struct stmmac_priv *priv = netdev_priv(ndev);
	113	unsigned long ioaddr = ndev->base_addr;
db98a0b0	114	unsigned int mii_address = priv->hw->mii.addr;
47dd7a54 GC	115
	116	if (priv->phy_reset) {
	117	pr_debug("stmmac_mdio_reset: calling phy_reset\n");
	118	priv->phy_reset(priv->bsp_priv);
	119	}
	120
	121	/* This is a workaround for problems with the STE101P PHY.
	122	* It doesn't complete its reset until at least one clock cycle
	123	* on MDC, so perform a dummy mdio read.
	124	*/
	125	writel(0, ioaddr + mii_address);
	126
	127	return 0;
	128	}
	129
	130	/**
	131	* stmmac_mdio_register
	132	* @ndev: net device structure
	133	* Description: it registers the MII bus
	134	*/
	135	int stmmac_mdio_register(struct net_device *ndev)
	136	{
	137	int err = 0;
	138	struct mii_bus *new_bus;
	139	int *irqlist;
	140	struct stmmac_priv *priv = netdev_priv(ndev);
	141	int addr, found;
	142
	143	new_bus = mdiobus_alloc();
	144	if (new_bus == NULL)
	145	return -ENOMEM;
	146
	147	irqlist = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
	148	if (irqlist == NULL) {
	149	err = -ENOMEM;
	150	goto irqlist_alloc_fail;
	151	}
	152
	153	/* Assign IRQ to phy at address phy_addr */
	154	if (priv->phy_addr != -1)
	155	irqlist[priv->phy_addr] = priv->phy_irq;
	156
	157	new_bus->name = "STMMAC MII Bus";
	158	new_bus->read = &stmmac_mdio_read;
	159	new_bus->write = &stmmac_mdio_write;
	160	new_bus->reset = &stmmac_mdio_reset;
	161	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
	162	new_bus->priv = ndev;
	163	new_bus->irq = irqlist;
	164	new_bus->phy_mask = priv->phy_mask;
	165	new_bus->parent = priv->device;
	166	err = mdiobus_register(new_bus);
	167	if (err != 0) {
	168	pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
	169	goto bus_register_fail;
	170	}
	171
	172	priv->mii = new_bus;
	173
	174	found = 0;
	175	for (addr = 0; addr < 32; addr++) {
	176	struct phy_device *phydev = new_bus->phy_map[addr];
	177	if (phydev) {
	178	if (priv->phy_addr == -1) {
179	priv->phy_addr = addr;
180	phydev->irq = priv->phy_irq;
181	irqlist[addr] = priv->phy_irq;
182	}
183	pr_info("%s: PHY ID %08x at %d IRQ %d (%s)%s\n",
184	ndev->name, phydev->phy_id, addr,
185	phydev->irq, dev_name(&phydev->dev),
186	(addr == priv->phy_addr) ? " active" : "");
187	found = 1;
188	}
189	}
190
191	if (!found)
192	pr_warning("%s: No PHY found\n", ndev->name);
193
194	return 0;
195	bus_register_fail:
196	kfree(irqlist);
197	irqlist_alloc_fail:
198	kfree(new_bus);
199	return err;
200	}
201
202	/**
203	* stmmac_mdio_unregister
204	* @ndev: net device structure
205	* Description: it unregisters the MII bus
206	*/
207	int stmmac_mdio_unregister(struct net_device *ndev)
208	{
209	struct stmmac_priv *priv = netdev_priv(ndev);
210
211	mdiobus_unregister(priv->mii);
212	priv->mii->priv = NULL;
213	kfree(priv->mii);
214
215	return 0;
216	}