]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/sky2.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Revert "sky2: don't do GRO on second port"
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
5a0e3ad6 36#include <linux/slab.h>
c9bdd4b5 37#include <net/ip.h>
cd28ab6a
SH		 38#include <linux/tcp.h>
39#include <linux/in.h>
40#include <linux/delay.h>
91c86df5 41#include <linux/workqueue.h>
d1f13708 42#include <linux/if_vlan.h>
d70cd51a 43#include <linux/prefetch.h>
3cf26753 44#include <linux/debugfs.h>
ef743d33 45#include <linux/mii.h>
cd28ab6a
SH		 46
47#include <asm/irq.h>
48
d1f13708
SH		 49#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
50#define SKY2_VLAN_TAG_USED 1
51#endif
52
cd28ab6a
SH		 53#include "sky2.h"
54
55#define DRV_NAME "sky2"
e0a67e2d 56#define DRV_VERSION "1.28"
cd28ab6a
SH		 57
58/*
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
14d0263f 61 * similar to Tigon3.
cd28ab6a
SH		 62 */
63
14d0263f 64#define RX_LE_SIZE 1024
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 66#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 68
ee5f68fe 69/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 70 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
71#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 72#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
efe91932 73#define TX_MAX_PENDING 1024
ee5f68fe 74#define TX_DEF_PENDING 127
cd28ab6a 75
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
060b946c 82#define RING_NEXT(x, s) (((x)+1) & ((s)-1))
cb5d9547 83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
e6cac9ba 101static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 143 { 0 }
144};
793b883e 145
cd28ab6a
SH		 146MODULE_DEVICE_TABLE(pci, sky2_id_table);
147
148/* Avoid conditionals by using array */
149static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
150static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 151static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 152
d1b139c0
SH		 153static void sky2_set_multicast(struct net_device *dev);
154
af043aa5 155/* Access to PHY via serial interconnect */
ef743d33 156static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 157{
158 int i;
159
160 gma_write16(hw, port, GM_SMI_DATA, val);
161 gma_write16(hw, port, GM_SMI_CTRL,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163
164 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 165 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
166 if (ctrl == 0xffff)
167 goto io_error;
168
169 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 170 return 0;
af043aa5
SH		 171
172 udelay(10);
cd28ab6a 173 }
ef743d33 174
060b946c 175 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 176 return -ETIMEDOUT;
af043aa5
SH		 177
178io_error:
179 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
180 return -EIO;
cd28ab6a
SH		 181}
182
ef743d33 183static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 184{
185 int i;
186
793b883e 187 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 188 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
189
190 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 191 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
192 if (ctrl == 0xffff)
193 goto io_error;
194
195 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 196 *val = gma_read16(hw, port, GM_SMI_DATA);
197 return 0;
198 }
199
af043aa5 200 udelay(10);
cd28ab6a
SH		 201 }
202
af043aa5 203 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 204 return -ETIMEDOUT;
af043aa5
SH		 205io_error:
206 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
207 return -EIO;
ef743d33
SH		 208}
209
af043aa5 210static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 211{
212 u16 v;
af043aa5 213 __gm_phy_read(hw, port, reg, &v);
ef743d33 214 return v;
cd28ab6a
SH		 215}
216
5afa0a9c 217
ae306cca
SH		 218static void sky2_power_on(struct sky2_hw *hw)
219{
220 /* switch power to VCC (WA for VAUX problem) */
221 sky2_write8(hw, B0_POWER_CTRL,
222 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 223
ae306cca
SH		 224 /* disable Core Clock Division, */
225 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 226
4b7c47aa 227 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 228 /* enable bits are inverted */
229 sky2_write8(hw, B2_Y2_CLK_GATE,
230 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
231 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
232 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
233 else
234 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 235
ea76e635 236 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 237 u32 reg;
5afa0a9c 238
b32f40c4 239 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 240
b32f40c4 241 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 242 /* set all bits to 0 except bits 15..12 and 8 */
243 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 244 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 245
b32f40c4 246 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 247 /* set all bits to 0 except bits 28 & 27 */
248 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 249 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 250
b32f40c4 251 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 252
5f8ae5c5 253 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
254
8f70920f
SH		 255 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
256 reg = sky2_read32(hw, B2_GP_IO);
257 reg |= GLB_GPIO_STAT_RACE_DIS;
258 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 259
260 sky2_read32(hw, B2_GP_IO);
5afa0a9c 261 }
10547ae2
SH		 262
263 /* Turn on "driver loaded" LED */
264 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 265}
5afa0a9c 266
ae306cca
SH		 267static void sky2_power_aux(struct sky2_hw *hw)
268{
4b7c47aa 269 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 270 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
271 else
272 /* enable bits are inverted */
273 sky2_write8(hw, B2_Y2_CLK_GATE,
274 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
275 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
276 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
277
c23ddf8f
SH		 278 /* switch power to VAUX if supported and PME from D3cold */
279 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
280 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 281 sky2_write8(hw, B0_POWER_CTRL,
282 (PC_VAUX_ENA | PC_VCC_ENA |
283 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 284
285 /* turn off "driver loaded LED" */
286 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 287}
288
d3bcfbeb 289static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 290{
291 u16 reg;
292
293 /* disable all GMAC IRQ's */
294 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 295
cd28ab6a
SH		 296 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
297 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
300
301 reg = gma_read16(hw, port, GM_RX_CTRL);
302 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
303 gma_write16(hw, port, GM_RX_CTRL, reg);
304}
305
16ad91e1
SH		 306/* flow control to advertise bits */
307static const u16 copper_fc_adv[] = {
308 [FC_NONE] = 0,
309 [FC_TX] = PHY_M_AN_ASP,
310 [FC_RX] = PHY_M_AN_PC,
311 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
312};
313
314/* flow control to advertise bits when using 1000BaseX */
315static const u16 fiber_fc_adv[] = {
df3fe1f3 316 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 317 [FC_TX] = PHY_M_P_ASYM_MD_X,
318 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 319 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 320};
321
322/* flow control to GMA disable bits */
323static const u16 gm_fc_disable[] = {
324 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
325 [FC_TX] = GM_GPCR_FC_RX_DIS,
326 [FC_RX] = GM_GPCR_FC_TX_DIS,
327 [FC_BOTH] = 0,
328};
329
330
cd28ab6a
SH		 331static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
332{
333 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 334 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 335
0ea065e5 336 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 337 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 338 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
339
340 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 341 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 342 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
343
53419c68 344 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 345 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 346 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 347 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
348 else
53419c68
SH		 349 /* set master & slave downshift counter to 1x */
350 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 351
352 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
353 }
354
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 356 if (sky2_is_copper(hw)) {
05745c4a 357 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 358 /* enable automatic crossover */
359 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 360
361 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
362 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
363 u16 spec;
364
365 /* Enable Class A driver for FE+ A0 */
366 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
367 spec |= PHY_M_FESC_SEL_CL_A;
368 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
369 }
cd28ab6a
SH		 370 } else {
371 /* disable energy detect */
372 ctrl &= ~PHY_M_PC_EN_DET_MSK;
373
374 /* enable automatic crossover */
375 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
376
53419c68 377 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 378 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
379 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 380 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 381 ctrl &= ~PHY_M_PC_DSC_MSK;
382 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
383 }
384 }
cd28ab6a
SH		 385 } else {
386 /* workaround for deviation #4.88 (CRC errors) */
387 /* disable Automatic Crossover */
388
389 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 390 }
cd28ab6a 391
b89165f2
SH		 392 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
393
394 /* special setup for PHY 88E1112 Fiber */
ea76e635 395 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 396 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 397
b89165f2
SH		 398 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
399 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
400 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
401 ctrl &= ~PHY_M_MAC_MD_MSK;
402 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
403 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
404
405 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 406 /* select page 1 to access Fiber registers */
407 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 408
409 /* for SFP-module set SIGDET polarity to low */
410 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
411 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 412 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 413 }
b89165f2
SH		 414
415 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 416 }
417
7800fddc 418 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 419 ct1000 = 0;
420 adv = PHY_AN_CSMA;
2eaba1a2 421 reg = 0;
cd28ab6a 422
0ea065e5 423 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 424 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 425 if (sky2->advertising & ADVERTISED_1000baseT_Full)
426 ct1000 |= PHY_M_1000C_AFD;
427 if (sky2->advertising & ADVERTISED_1000baseT_Half)
428 ct1000 |= PHY_M_1000C_AHD;
429 if (sky2->advertising & ADVERTISED_100baseT_Full)
430 adv |= PHY_M_AN_100_FD;
431 if (sky2->advertising & ADVERTISED_100baseT_Half)
432 adv |= PHY_M_AN_100_HD;
433 if (sky2->advertising & ADVERTISED_10baseT_Full)
434 adv |= PHY_M_AN_10_FD;
435 if (sky2->advertising & ADVERTISED_10baseT_Half)
436 adv |= PHY_M_AN_10_HD;
709c6e7b 437
b89165f2
SH		 438 } else { /* special defines for FIBER (88E1040S only) */
439 if (sky2->advertising & ADVERTISED_1000baseT_Full)
440 adv |= PHY_M_AN_1000X_AFD;
441 if (sky2->advertising & ADVERTISED_1000baseT_Half)
442 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 443 }
cd28ab6a
SH		 444
445 /* Restart Auto-negotiation */
446 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 } else {
448 /* forced speed/duplex settings */
449 ct1000 = PHY_M_1000C_MSE;
450
0ea065e5
SH		 451 /* Disable auto update for duplex flow control and duplex */
452 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 453
454 switch (sky2->speed) {
455 case SPEED_1000:
456 ctrl |= PHY_CT_SP1000;
2eaba1a2 457 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 458 break;
459 case SPEED_100:
460 ctrl |= PHY_CT_SP100;
2eaba1a2 461 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 462 break;
463 }
464
2eaba1a2
SH		 465 if (sky2->duplex == DUPLEX_FULL) {
466 reg |= GM_GPCR_DUP_FULL;
467 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 468 } else if (sky2->speed < SPEED_1000)
469 sky2->flow_mode = FC_NONE;
0ea065e5 470 }
2eaba1a2 471
0ea065e5
SH		 472 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
473 if (sky2_is_copper(hw))
474 adv |= copper_fc_adv[sky2->flow_mode];
475 else
476 adv |= fiber_fc_adv[sky2->flow_mode];
477 } else {
478 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 479 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 480
481 /* Forward pause packets to GMAC? */
16ad91e1 482 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
484 else
485 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 486 }
487
2eaba1a2
SH		 488 gma_write16(hw, port, GM_GP_CTRL, reg);
489
05745c4a 490 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 491 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
492
493 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
494 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
495
496 /* Setup Phy LED's */
497 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
498 ledover = 0;
499
500 switch (hw->chip_id) {
501 case CHIP_ID_YUKON_FE:
502 /* on 88E3082 these bits are at 11..9 (shifted left) */
503 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
504
505 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
506
507 /* delete ACT LED control bits */
508 ctrl &= ~PHY_M_FELP_LED1_MSK;
509 /* change ACT LED control to blink mode */
510 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
511 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
512 break;
513
05745c4a
SH		 514 case CHIP_ID_YUKON_FE_P:
515 /* Enable Link Partner Next Page */
516 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
517 ctrl |= PHY_M_PC_ENA_LIP_NP;
518
519 /* disable Energy Detect and enable scrambler */
520 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
521 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
522
523 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
524 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
525 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
526 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
527
528 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
529 break;
530
cd28ab6a 531 case CHIP_ID_YUKON_XL:
793b883e 532 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 533
534 /* select page 3 to access LED control register */
535 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
536
537 /* set LED Function Control register */
ed6d32c7
SH		 538 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
539 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
540 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
541 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
542 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 543
544 /* set Polarity Control register */
545 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 546 (PHY_M_POLC_LS1_P_MIX(4) |
547 PHY_M_POLC_IS0_P_MIX(4) |
548 PHY_M_POLC_LOS_CTRL(2) |
549 PHY_M_POLC_INIT_CTRL(2) |
550 PHY_M_POLC_STA1_CTRL(2) |
551 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 552
553 /* restore page register */
793b883e 554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 555 break;
93745494 556
ed6d32c7 557 case CHIP_ID_YUKON_EC_U:
93745494 558 case CHIP_ID_YUKON_EX:
ed4d4161 559 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 560 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
561
562 /* select page 3 to access LED control register */
563 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
564
565 /* set LED Function Control register */
566 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
567 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
568 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
569 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
570 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
571
572 /* set Blink Rate in LED Timer Control Register */
573 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
574 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
575 /* restore page register */
576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
577 break;
cd28ab6a
SH		 578
579 default:
580 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
581 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 582
cd28ab6a 583 /* turn off the Rx LED (LED_RX) */
a84d0a3d 584 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 585 }
586
0ce8b98d 587 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 588 /* apply fixes in PHY AFE */
ed6d32c7
SH		 589 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
590
977bdf06 591 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 592 gm_phy_write(hw, port, 0x18, 0xaa99);
593 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 594
0ce8b98d
SH		 595 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
596 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
597 gm_phy_write(hw, port, 0x18, 0xa204);
598 gm_phy_write(hw, port, 0x17, 0x2002);
599 }
977bdf06
SH		 600
601 /* set page register to 0 */
9467a8fc 602 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 603 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
604 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
605 /* apply workaround for integrated resistors calibration */
606 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
607 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 608 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
609 /* apply fixes in PHY AFE */
610 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
611
612 /* apply RDAC termination workaround */
613 gm_phy_write(hw, port, 24, 0x2800);
614 gm_phy_write(hw, port, 23, 0x2001);
615
616 /* set page register back to 0 */
617 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 618 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
619 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 620 /* no effect on Yukon-XL */
977bdf06 621 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 622
8e95a202
JP		 623 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
624 sky2->speed == SPEED_100) {
977bdf06 625 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 626 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 627 }
cd28ab6a 628
977bdf06
SH		 629 if (ledover)
630 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
631
632 }
2eaba1a2 633
d571b694 634 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 635 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 636 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
637 else
638 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
639}
640
b96936da
SH		 641static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
642static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
643
644static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 645{
646 u32 reg1;
d3bcfbeb 647
a40ccc68 648 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 649 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 650 reg1 &= ~phy_power[port];
d3bcfbeb 651
4b7c47aa 652 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ff35164e
SH		 653 reg1 |= coma_mode[port];
654
b32f40c4 655 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 657 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 658
659 if (hw->chip_id == CHIP_ID_YUKON_FE)
660 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
661 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
662 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 663}
167f53d0 664
b96936da
SH		 665static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
666{
667 u32 reg1;
db99b988
SH		 668 u16 ctrl;
669
670 /* release GPHY Control reset */
671 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
672
673 /* release GMAC reset */
674 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
675
676 if (hw->flags & SKY2_HW_NEWER_PHY) {
677 /* select page 2 to access MAC control register */
678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
679
680 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
681 /* allow GMII Power Down */
682 ctrl &= ~PHY_M_MAC_GMIF_PUP;
683 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
684
685 /* set page register back to 0 */
686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
687 }
688
689 /* setup General Purpose Control Register */
690 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 691 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
692 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
693 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 694
695 if (hw->chip_id != CHIP_ID_YUKON_EC) {
696 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 697 /* select page 2 to access MAC control register */
698 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 699
e484d5f5 700 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 701 /* enable Power Down */
702 ctrl |= PHY_M_PC_POW_D_ENA;
703 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 704
705 /* set page register back to 0 */
706 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 707 }
708
709 /* set IEEE compatible Power Down Mode (dev. #4.99) */
710 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
711 }
b96936da 712
a40ccc68 713 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 714 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 715 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 716 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 717 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 718}
719
38000a94
BP		 720/* Enable Rx/Tx */
721static void sky2_enable_rx_tx(struct sky2_port *sky2)
722{
723 struct sky2_hw *hw = sky2->hw;
724 unsigned port = sky2->port;
725 u16 reg;
726
727 reg = gma_read16(hw, port, GM_GP_CTRL);
728 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
729 gma_write16(hw, port, GM_GP_CTRL, reg);
730}
731
1b537565
SH		 732/* Force a renegotiation */
733static void sky2_phy_reinit(struct sky2_port *sky2)
734{
e07b1aa8 735 spin_lock_bh(&sky2->phy_lock);
1b537565 736 sky2_phy_init(sky2->hw, sky2->port);
38000a94 737 sky2_enable_rx_tx(sky2);
e07b1aa8 738 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 739}
740
e3173832
SH		 741/* Put device in state to listen for Wake On Lan */
742static void sky2_wol_init(struct sky2_port *sky2)
743{
744 struct sky2_hw *hw = sky2->hw;
745 unsigned port = sky2->port;
746 enum flow_control save_mode;
747 u16 ctrl;
e3173832
SH		 748
749 /* Bring hardware out of reset */
750 sky2_write16(hw, B0_CTST, CS_RST_CLR);
751 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
752
753 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
754 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
755
756 /* Force to 10/100
757 * sky2_reset will re-enable on resume
758 */
759 save_mode = sky2->flow_mode;
760 ctrl = sky2->advertising;
761
762 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
763 sky2->flow_mode = FC_NONE;
b96936da
SH		 764
765 spin_lock_bh(&sky2->phy_lock);
766 sky2_phy_power_up(hw, port);
767 sky2_phy_init(hw, port);
768 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 769
770 sky2->flow_mode = save_mode;
771 sky2->advertising = ctrl;
772
773 /* Set GMAC to no flow control and auto update for speed/duplex */
774 gma_write16(hw, port, GM_GP_CTRL,
775 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
776 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
777
778 /* Set WOL address */
779 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
780 sky2->netdev->dev_addr, ETH_ALEN);
781
782 /* Turn on appropriate WOL control bits */
783 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
784 ctrl = 0;
785 if (sky2->wol & WAKE_PHY)
786 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
787 else
788 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
789
790 if (sky2->wol & WAKE_MAGIC)
791 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
792 else
a419aef8 793 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 794
795 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
796 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
797
5f8ae5c5 798 /* Disable PiG firmware */
799 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
800
e3173832
SH		 801 /* block receiver */
802 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 803}
804
69161611
SH		 805static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
806{
05745c4a
SH		 807 struct net_device *dev = hw->dev[port];
808
ed4d4161
SH		 809 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
810 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 811 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 812 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 813 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
814 } else if (dev->mtu > ETH_DATA_LEN) {
815 /* set Tx GMAC FIFO Almost Empty Threshold */
816 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
817 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 818
44dde56d 819 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
820 } else
821 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 822}
823
cd28ab6a
SH		 824static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
825{
826 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
827 u16 reg;
25cccecc 828 u32 rx_reg;
cd28ab6a
SH		 829 int i;
830 const u8 *addr = hw->dev[port]->dev_addr;
831
f350339c
SH		 832 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
833 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 834
835 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
836
4b7c47aa 837 if (hw->chip_id == CHIP_ID_YUKON_XL &&
838 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
839 port == 1) {
cd28ab6a
SH		 840 /* WA DEV_472 -- looks like crossed wires on port 2 */
841 /* clear GMAC 1 Control reset */
842 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
843 do {
844 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
845 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
846 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
847 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
848 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
849 }
850
793b883e 851 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 852
2eaba1a2
SH		 853 /* Enable Transmit FIFO Underrun */
854 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
855
e07b1aa8 856 spin_lock_bh(&sky2->phy_lock);
b96936da 857 sky2_phy_power_up(hw, port);
cd28ab6a 858 sky2_phy_init(hw, port);
e07b1aa8 859 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 860
861 /* MIB clear */
862 reg = gma_read16(hw, port, GM_PHY_ADDR);
863 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
864
43f2f104
SH		 865 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
866 gma_read16(hw, port, i);
cd28ab6a
SH		 867 gma_write16(hw, port, GM_PHY_ADDR, reg);
868
869 /* transmit control */
870 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
871
872 /* receive control reg: unicast + multicast + no FCS */
873 gma_write16(hw, port, GM_RX_CTRL,
793b883e 874 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 875
876 /* transmit flow control */
877 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
878
879 /* transmit parameter */
880 gma_write16(hw, port, GM_TX_PARAM,
881 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
882 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
883 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
884 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
885
886 /* serial mode register */
887 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 888 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 889
6b1a3aef 890 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 891 reg |= GM_SMOD_JUMBO_ENA;
892
c1cd0a85 893 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
894 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
895 reg |= GM_NEW_FLOW_CTRL;
896
cd28ab6a
SH		 897 gma_write16(hw, port, GM_SERIAL_MODE, reg);
898
cd28ab6a
SH		 899 /* virtual address for data */
900 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
901
793b883e
SH		 902 /* physical address: used for pause frames */
903 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
904
905 /* ignore counter overflows */
cd28ab6a
SH		 906 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
907 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
908 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
909
910 /* Configure Rx MAC FIFO */
911 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 912 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 913 if (hw->chip_id == CHIP_ID_YUKON_EX ||
914 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 915 rx_reg |= GMF_RX_OVER_ON;
69161611 916
25cccecc 917 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 918
798fdd07
SH		 919 if (hw->chip_id == CHIP_ID_YUKON_XL) {
920 /* Hardware errata - clear flush mask */
921 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
922 } else {
923 /* Flush Rx MAC FIFO on any flow control or error */
924 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
925 }
cd28ab6a 926
8df9a876 927 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 928 reg = RX_GMF_FL_THR_DEF + 1;
929 /* Another magic mystery workaround from sk98lin */
930 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
931 hw->chip_rev == CHIP_REV_YU_FE2_A0)
932 reg = 0x178;
933 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 934
935 /* Configure Tx MAC FIFO */
936 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
937 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 938
e0c28116 939 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 940 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 941 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 942 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
943 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 944 reg = 1568 / 8;
945 else
946 reg = 1024 / 8;
947 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
948 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 949
69161611 950 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 951 }
952
e970d1f8
SH		 953 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
954 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
955 /* disable dynamic watermark */
956 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
957 reg &= ~TX_DYN_WM_ENA;
958 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
959 }
cd28ab6a
SH		 960}
961
67712901
SH		 962/* Assign Ram Buffer allocation to queue */
963static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 964{
67712901
SH		 965 u32 end;
966
967 /* convert from K bytes to qwords used for hw register */
968 start *= 1024/8;
969 space *= 1024/8;
970 end = start + space - 1;
793b883e 971
cd28ab6a
SH		 972 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
973 sky2_write32(hw, RB_ADDR(q, RB_START), start);
974 sky2_write32(hw, RB_ADDR(q, RB_END), end);
975 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
976 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
977
978 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 979 u32 tp = space - space/4;
793b883e 980
1c28f6ba
SH		 981 /* On receive queue's set the thresholds
982 * give receiver priority when > 3/4 full
983 * send pause when down to 2K
984 */
985 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
986 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 987
1c28f6ba
SH		 988 tp = space - 2048/8;
989 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
990 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 991 } else {
992 /* Enable store & forward on Tx queue's because
993 * Tx FIFO is only 1K on Yukon
994 */
995 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
996 }
997
998 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 999 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 1000}
1001
cd28ab6a 1002/* Setup Bus Memory Interface */
af4ed7e6 1003static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 1004{
1005 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1006 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1007 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 1008 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 1009}
1010
cd28ab6a
SH		 1011/* Setup prefetch unit registers. This is the interface between
1012 * hardware and driver list elements
1013 */
8cc048e3 1014static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1015 dma_addr_t addr, u32 last)
cd28ab6a 1016{
cd28ab6a
SH		 1017 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1018 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1019 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1020 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1021 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1022 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1023
1024 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1025}
1026
9b289c33 1027static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1028{
9b289c33 1029 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1030
ee5f68fe 1031 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1032 le->ctrl = 0;
793b883e
SH		 1033 return le;
1034}
cd28ab6a 1035
88f5f0ca
SH		 1036static void tx_init(struct sky2_port *sky2)
1037{
1038 struct sky2_tx_le *le;
1039
1040 sky2->tx_prod = sky2->tx_cons = 0;
1041 sky2->tx_tcpsum = 0;
1042 sky2->tx_last_mss = 0;
1043
9b289c33 1044 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1045 le->addr = 0;
1046 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1047 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1048}
1049
290d4de5
SH		 1050/* Update chip's next pointer */
1051static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1052{
50432cb5 1053 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1054 wmb();
50432cb5
SH		 1055 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1056
1057 /* Synchronize I/O on since next processor may write to tail */
1058 mmiowb();
cd28ab6a
SH		 1059}
1060
793b883e 1061
cd28ab6a
SH		 1062static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1063{
1064 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1065 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1066 le->ctrl = 0;
cd28ab6a
SH		 1067 return le;
1068}
1069
060b946c 1070static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
39ef110b
MM		 1071{
1072 unsigned size;
1073
1074 /* Space needed for frame data + headers rounded up */
1075 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1076
1077 /* Stopping point for hardware truncation */
1078 return (size - 8) / sizeof(u32);
1079}
1080
060b946c 1081static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
39ef110b
MM		 1082{
1083 struct rx_ring_info *re;
1084 unsigned size;
1085
1086 /* Space needed for frame data + headers rounded up */
1087 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1088
1089 sky2->rx_nfrags = size >> PAGE_SHIFT;
1090 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1091
1092 /* Compute residue after pages */
1093 size -= sky2->rx_nfrags << PAGE_SHIFT;
1094
1095 /* Optimize to handle small packets and headers */
1096 if (size < copybreak)
1097 size = copybreak;
1098 if (size < ETH_HLEN)
1099 size = ETH_HLEN;
1100
1101 return size;
1102}
1103
14d0263f 1104/* Build description to hardware for one receive segment */
060b946c 1105static void sky2_rx_add(struct sky2_port *sky2, u8 op,
14d0263f 1106 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1107{
1108 struct sky2_rx_le *le;
1109
86c6887e 1110 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1111 le = sky2_next_rx(sky2);
86c6887e 1112 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1113 le->opcode = OP_ADDR64 | HW_OWNER;
1114 }
793b883e 1115
cd28ab6a 1116 le = sky2_next_rx(sky2);
d6e74b6b 1117 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1118 le->length = cpu_to_le16(len);
14d0263f 1119 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1120}
1121
14d0263f
SH		 1122/* Build description to hardware for one possibly fragmented skb */
1123static void sky2_rx_submit(struct sky2_port *sky2,
1124 const struct rx_ring_info *re)
1125{
1126 int i;
1127
1128 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1129
1130 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1131 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1132}
1133
1134
454e6cb6 1135static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1136 unsigned size)
1137{
1138 struct sk_buff *skb = re->skb;
1139 int i;
1140
1141 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1142 if (pci_dma_mapping_error(pdev, re->data_addr))
1143 goto mapping_error;
454e6cb6 1144
7cd26ce5 1145 dma_unmap_len_set(re, data_size, size);
14d0263f 1146
3fbd9187 1147 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1148 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1149
1150 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1151 frag->page_offset,
1152 frag->size,
14d0263f 1153 PCI_DMA_FROMDEVICE);
3fbd9187 1154
1155 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1156 goto map_page_error;
1157 }
454e6cb6 1158 return 0;
3fbd9187 1159
1160map_page_error:
1161 while (--i >= 0) {
1162 pci_unmap_page(pdev, re->frag_addr[i],
1163 skb_shinfo(skb)->frags[i].size,
1164 PCI_DMA_FROMDEVICE);
1165 }
1166
7cd26ce5 1167 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
3fbd9187 1168 PCI_DMA_FROMDEVICE);
1169
1170mapping_error:
1171 if (net_ratelimit())
1172 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1173 skb->dev->name);
1174 return -EIO;
14d0263f
SH		 1175}
1176
1177static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1178{
1179 struct sk_buff *skb = re->skb;
1180 int i;
1181
7cd26ce5 1182 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
14d0263f
SH		 1183 PCI_DMA_FROMDEVICE);
1184
1185 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1186 pci_unmap_page(pdev, re->frag_addr[i],
1187 skb_shinfo(skb)->frags[i].size,
1188 PCI_DMA_FROMDEVICE);
1189}
793b883e 1190
cd28ab6a
SH		 1191/* Tell chip where to start receive checksum.
1192 * Actually has two checksums, but set both same to avoid possible byte
1193 * order problems.
1194 */
793b883e 1195static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1196{
ea76e635 1197 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1198
ea76e635
SH		 1199 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1200 le->ctrl = 0;
1201 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1202
ea76e635
SH		 1203 sky2_write32(sky2->hw,
1204 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1205 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1206 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1207}
1208
bf73130d
SH		 1209/* Enable/disable receive hash calculation (RSS) */
1210static void rx_set_rss(struct net_device *dev)
1211{
1212 struct sky2_port *sky2 = netdev_priv(dev);
1213 struct sky2_hw *hw = sky2->hw;
1214 int i, nkeys = 4;
1215
1216 /* Supports IPv6 and other modes */
1217 if (hw->flags & SKY2_HW_NEW_LE) {
1218 nkeys = 10;
1219 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1220 }
1221
1222 /* Program RSS initial values */
1223 if (dev->features & NETIF_F_RXHASH) {
1224 u32 key[nkeys];
1225
1226 get_random_bytes(key, nkeys * sizeof(u32));
1227 for (i = 0; i < nkeys; i++)
1228 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1229 key[i]);
1230
1231 /* Need to turn on (undocumented) flag to make hashing work */
1232 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1233 RX_STFW_ENA);
1234
1235 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1236 BMU_ENA_RX_RSS_HASH);
1237 } else
1238 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1239 BMU_DIS_RX_RSS_HASH);
1240}
1241
6b1a3aef
SH		 1242/*
1243 * The RX Stop command will not work for Yukon-2 if the BMU does not
1244 * reach the end of packet and since we can't make sure that we have
1245 * incoming data, we must reset the BMU while it is not doing a DMA
1246 * transfer. Since it is possible that the RX path is still active,
1247 * the RX RAM buffer will be stopped first, so any possible incoming
1248 * data will not trigger a DMA. After the RAM buffer is stopped, the
1249 * BMU is polled until any DMA in progress is ended and only then it
1250 * will be reset.
1251 */
1252static void sky2_rx_stop(struct sky2_port *sky2)
1253{
1254 struct sky2_hw *hw = sky2->hw;
1255 unsigned rxq = rxqaddr[sky2->port];
1256 int i;
1257
1258 /* disable the RAM Buffer receive queue */
1259 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1260
1261 for (i = 0; i < 0xffff; i++)
1262 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1263 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1264 goto stopped;
1265
ada1db5c 1266 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef
SH		 1267stopped:
1268 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1269
1270 /* reset the Rx prefetch unit */
1271 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1272 mmiowb();
6b1a3aef 1273}
793b883e 1274
d571b694 1275/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1276static void sky2_rx_clean(struct sky2_port *sky2)
1277{
1278 unsigned i;
1279
1280 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1281 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1282 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1283
1284 if (re->skb) {
14d0263f 1285 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1286 kfree_skb(re->skb);
1287 re->skb = NULL;
1288 }
1289 }
1290}
1291
ef743d33
SH		 1292/* Basic MII support */
1293static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1294{
1295 struct mii_ioctl_data *data = if_mii(ifr);
1296 struct sky2_port *sky2 = netdev_priv(dev);
1297 struct sky2_hw *hw = sky2->hw;
1298 int err = -EOPNOTSUPP;
1299
1300 if (!netif_running(dev))
1301 return -ENODEV; /* Phy still in reset */
1302
d89e1343 1303 switch (cmd) {
ef743d33
SH		 1304 case SIOCGMIIPHY:
1305 data->phy_id = PHY_ADDR_MARV;
1306
1307 /* fallthru */
1308 case SIOCGMIIREG: {
1309 u16 val = 0;
91c86df5 1310
e07b1aa8 1311 spin_lock_bh(&sky2->phy_lock);
ef743d33 1312 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1313 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1314
ef743d33
SH		 1315 data->val_out = val;
1316 break;
1317 }
1318
1319 case SIOCSMIIREG:
e07b1aa8 1320 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1321 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1322 data->val_in);
e07b1aa8 1323 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1324 break;
1325 }
1326 return err;
1327}
1328
d1f13708 1329#ifdef SKY2_VLAN_TAG_USED
d494eacd 1330static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1331{
d494eacd 1332 if (onoff) {
3d4e66f5
SH		 1333 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1334 RX_VLAN_STRIP_ON);
1335 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1336 TX_VLAN_TAG_ON);
1337 } else {
1338 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1339 RX_VLAN_STRIP_OFF);
1340 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1341 TX_VLAN_TAG_OFF);
1342 }
d494eacd
SH		 1343}
1344
1345static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1346{
1347 struct sky2_port *sky2 = netdev_priv(dev);
1348 struct sky2_hw *hw = sky2->hw;
1349 u16 port = sky2->port;
1350
1351 netif_tx_lock_bh(dev);
1352 napi_disable(&hw->napi);
1353
1354 sky2->vlgrp = grp;
1355 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1356
d1d08d12 1357 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1358 napi_enable(&hw->napi);
2bb8c262 1359 netif_tx_unlock_bh(dev);
d1f13708
SH		 1360}
1361#endif
1362
bd1c6869
SH		 1363/* Amount of required worst case padding in rx buffer */
1364static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1365{
1366 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1367}
1368
82788c7a 1369/*
14d0263f
SH		 1370 * Allocate an skb for receiving. If the MTU is large enough
1371 * make the skb non-linear with a fragment list of pages.
82788c7a 1372 */
14d0263f 1373static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1374{
1375 struct sk_buff *skb;
14d0263f 1376 int i;
82788c7a 1377
724b6942
SH		 1378 skb = netdev_alloc_skb(sky2->netdev,
1379 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1380 if (!skb)
1381 goto nomem;
1382
39dbd958 1383 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1384 unsigned char *start;
1385 /*
1386 * Workaround for a bug in FIFO that cause hang
1387 * if the FIFO if the receive buffer is not 64 byte aligned.
1388 * The buffer returned from netdev_alloc_skb is
1389 * aligned except if slab debugging is enabled.
1390 */
f03b8654
SH		 1391 start = PTR_ALIGN(skb->data, 8);
1392 skb_reserve(skb, start - skb->data);
bd1c6869 1393 } else
f03b8654 1394 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1395
1396 for (i = 0; i < sky2->rx_nfrags; i++) {
1397 struct page *page = alloc_page(GFP_ATOMIC);
1398
1399 if (!page)
1400 goto free_partial;
1401 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1402 }
1403
1404 return skb;
14d0263f
SH		 1405free_partial:
1406 kfree_skb(skb);
1407nomem:
1408 return NULL;
82788c7a
SH		 1409}
1410
55c9dd35
SH		 1411static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1412{
1413 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1414}
1415
200ac492
MM		 1416static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1417{
1418 struct sky2_hw *hw = sky2->hw;
1419 unsigned i;
1420
1421 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1422
1423 /* Fill Rx ring */
1424 for (i = 0; i < sky2->rx_pending; i++) {
1425 struct rx_ring_info *re = sky2->rx_ring + i;
1426
1427 re->skb = sky2_rx_alloc(sky2);
1428 if (!re->skb)
1429 return -ENOMEM;
1430
1431 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1432 dev_kfree_skb(re->skb);
1433 re->skb = NULL;
1434 return -ENOMEM;
1435 }
1436 }
1437 return 0;
1438}
1439
cd28ab6a 1440/*
200ac492 1441 * Setup receiver buffer pool.
14d0263f
SH		 1442 * Normal case this ends up creating one list element for skb
1443 * in the receive ring. Worst case if using large MTU and each
1444 * allocation falls on a different 64 bit region, that results
1445 * in 6 list elements per ring entry.
1446 * One element is used for checksum enable/disable, and one
1447 * extra to avoid wrap.
cd28ab6a 1448 */
200ac492 1449static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1450{
6b1a3aef 1451 struct sky2_hw *hw = sky2->hw;
14d0263f 1452 struct rx_ring_info *re;
6b1a3aef 1453 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1454 unsigned i, thresh;
cd28ab6a 1455
6b1a3aef 1456 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1457 sky2_qset(hw, rxq);
977bdf06 1458
c3905bc4
SH		 1459 /* On PCI express lowering the watermark gives better performance */
1460 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1461 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1462
1463 /* These chips have no ram buffer?
1464 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1465 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c1cd0a85 1466 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
f449c7c1 1467 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1468
6b1a3aef
SH		 1469 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1470
ea76e635
SH		 1471 if (!(hw->flags & SKY2_HW_NEW_LE))
1472 rx_set_checksum(sky2);
14d0263f 1473
bf73130d
SH		 1474 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1475 rx_set_rss(sky2->netdev);
1476
200ac492 1477 /* submit Rx ring */
793b883e 1478 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1479 re = sky2->rx_ring + i;
14d0263f 1480 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1481 }
1482
a1433ac4
SH		 1483 /*
1484 * The receiver hangs if it receives frames larger than the
1485 * packet buffer. As a workaround, truncate oversize frames, but
1486 * the register is limited to 9 bits, so if you do frames > 2052
1487 * you better get the MTU right!
1488 */
39ef110b 1489 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1490 if (thresh > 0x1ff)
1491 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1492 else {
1493 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1494 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1495 }
1496
6b1a3aef 1497 /* Tell chip about available buffers */
55c9dd35 1498 sky2_rx_update(sky2, rxq);
877c8570
SH		 1499
1500 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1501 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1502 /*
1503 * Disable flushing of non ASF packets;
1504 * must be done after initializing the BMUs;
1505 * drivers without ASF support should do this too, otherwise
1506 * it may happen that they cannot run on ASF devices;
1507 * remember that the MAC FIFO isn't reset during initialization.
1508 */
1509 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1510 }
1511
1512 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1513 /* Enable RX Home Address & Routing Header checksum fix */
1514 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1515 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1516
1517 /* Enable TX Home Address & Routing Header checksum fix */
1518 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1519 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1520 }
cd28ab6a
SH		 1521}
1522
90bbebb4
MM		 1523static int sky2_alloc_buffers(struct sky2_port *sky2)
1524{
1525 struct sky2_hw *hw = sky2->hw;
1526
1527 /* must be power of 2 */
1528 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1529 sky2->tx_ring_size *
1530 sizeof(struct sky2_tx_le),
1531 &sky2->tx_le_map);
1532 if (!sky2->tx_le)
1533 goto nomem;
1534
1535 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1536 GFP_KERNEL);
1537 if (!sky2->tx_ring)
1538 goto nomem;
1539
1540 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1541 &sky2->rx_le_map);
1542 if (!sky2->rx_le)
1543 goto nomem;
1544 memset(sky2->rx_le, 0, RX_LE_BYTES);
1545
1546 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1547 GFP_KERNEL);
1548 if (!sky2->rx_ring)
1549 goto nomem;
1550
200ac492 1551 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1552nomem:
1553 return -ENOMEM;
1554}
1555
1556static void sky2_free_buffers(struct sky2_port *sky2)
1557{
1558 struct sky2_hw *hw = sky2->hw;
1559
200ac492
MM		 1560 sky2_rx_clean(sky2);
1561
90bbebb4
MM		 1562 if (sky2->rx_le) {
1563 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1564 sky2->rx_le, sky2->rx_le_map);
1565 sky2->rx_le = NULL;
1566 }
1567 if (sky2->tx_le) {
1568 pci_free_consistent(hw->pdev,
1569 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1570 sky2->tx_le, sky2->tx_le_map);
1571 sky2->tx_le = NULL;
1572 }
1573 kfree(sky2->tx_ring);
1574 kfree(sky2->rx_ring);
1575
1576 sky2->tx_ring = NULL;
1577 sky2->rx_ring = NULL;
1578}
1579
ea0f71e5 1580static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1581{
cd28ab6a
SH		 1582 struct sky2_hw *hw = sky2->hw;
1583 unsigned port = sky2->port;
ea0f71e5
MM		 1584 u32 ramsize;
1585 int cap;
843a46f4 1586 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1587
ea0f71e5
MM		 1588 tx_init(sky2);
1589
ee7abb04
SH		 1590 /*
1591 * On dual port PCI-X card, there is an problem where status
1592 * can be received out of order due to split transactions
843a46f4 1593 */
ee7abb04
SH		 1594 if (otherdev && netif_running(otherdev) &&
1595 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1596 u16 cmd;
1597
b32f40c4 1598 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1599 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1600 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1601 }
cd28ab6a 1602
cd28ab6a
SH		 1603 sky2_mac_init(hw, port);
1604
e0c28116
SH		 1605 /* Register is number of 4K blocks on internal RAM buffer. */
1606 ramsize = sky2_read8(hw, B2_E_0) * 4;
1607 if (ramsize > 0) {
67712901 1608 u32 rxspace;
cd28ab6a 1609
ada1db5c 1610 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1611 if (ramsize < 16)
1612 rxspace = ramsize / 2;
1613 else
1614 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1615
67712901
SH		 1616 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1617 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1618
1619 /* Make sure SyncQ is disabled */
1620 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1621 RB_RST_SET);
1622 }
793b883e 1623
af4ed7e6 1624 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1625
69161611
SH		 1626 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1627 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1628 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1629
977bdf06 1630 /* Set almost empty threshold */
8e95a202
JP		 1631 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1632 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1633 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1634
6b1a3aef 1635 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1636 sky2->tx_ring_size - 1);
cd28ab6a 1637
d494eacd
SH		 1638#ifdef SKY2_VLAN_TAG_USED
1639 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1640#endif
1641
200ac492 1642 sky2_rx_start(sky2);
ea0f71e5
MM		 1643}
1644
1645/* Bring up network interface. */
1646static int sky2_up(struct net_device *dev)
1647{
1648 struct sky2_port *sky2 = netdev_priv(dev);
1649 struct sky2_hw *hw = sky2->hw;
1650 unsigned port = sky2->port;
1651 u32 imask;
1652 int err;
1653
1654 netif_carrier_off(dev);
1655
1656 err = sky2_alloc_buffers(sky2);
1657 if (err)
1658 goto err_out;
1659
1660 sky2_hw_up(sky2);
cd28ab6a 1661
cd28ab6a 1662 /* Enable interrupts from phy/mac for port */
e07b1aa8 1663 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1664 imask |= portirq_msk[port];
e07b1aa8 1665 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1666 sky2_read32(hw, B0_IMSK);
e07b1aa8 1667
6c35abae 1668 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1669
cd28ab6a
SH		 1670 return 0;
1671
1672err_out:
90bbebb4 1673 sky2_free_buffers(sky2);
cd28ab6a
SH		 1674 return err;
1675}
1676
793b883e 1677/* Modular subtraction in ring */
ee5f68fe 1678static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1679{
ee5f68fe 1680 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1681}
cd28ab6a 1682
793b883e
SH		 1683/* Number of list elements available for next tx */
1684static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1685{
ee5f68fe 1686 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1687}
1688
793b883e 1689/* Estimate of number of transmit list elements required */
28bd181a 1690static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1691{
793b883e
SH		 1692 unsigned count;
1693
07e31637
SH		 1694 count = (skb_shinfo(skb)->nr_frags + 1)
1695 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1696
89114afd 1697 if (skb_is_gso(skb))
793b883e 1698 ++count;
07e31637
SH		 1699 else if (sizeof(dma_addr_t) == sizeof(u32))
1700 ++count; /* possible vlan */
793b883e 1701
84fa7933 1702 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1703 ++count;
1704
1705 return count;
cd28ab6a
SH		 1706}
1707
f6815077 1708static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1709{
1710 if (re->flags & TX_MAP_SINGLE)
7cd26ce5
FT		 1711 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1712 dma_unmap_len(re, maplen),
6b84daca
SH		 1713 PCI_DMA_TODEVICE);
1714 else if (re->flags & TX_MAP_PAGE)
7cd26ce5
FT		 1715 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1716 dma_unmap_len(re, maplen),
6b84daca 1717 PCI_DMA_TODEVICE);
f6815077 1718 re->flags = 0;
6b84daca
SH		 1719}
1720
793b883e
SH		 1721/*
1722 * Put one packet in ring for transmit.
1723 * A single packet can generate multiple list elements, and
1724 * the number of ring elements will probably be less than the number
1725 * of list elements used.
1726 */
61357325
SH		 1727static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1728 struct net_device *dev)
cd28ab6a
SH		 1729{
1730 struct sky2_port *sky2 = netdev_priv(dev);
1731 struct sky2_hw *hw = sky2->hw;
d1f13708 1732 struct sky2_tx_le *le = NULL;
6cdbbdf3 1733 struct tx_ring_info *re;
9b289c33 1734 unsigned i, len;
cd28ab6a 1735 dma_addr_t mapping;
5dce95e5
SH		 1736 u32 upper;
1737 u16 slot;
cd28ab6a
SH		 1738 u16 mss;
1739 u8 ctrl;
1740
2bb8c262
SH		 1741 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1742 return NETDEV_TX_BUSY;
cd28ab6a 1743
cd28ab6a
SH		 1744 len = skb_headlen(skb);
1745 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1746
454e6cb6
SH		 1747 if (pci_dma_mapping_error(hw->pdev, mapping))
1748 goto mapping_error;
1749
9b289c33 1750 slot = sky2->tx_prod;
6c35abae
JP		 1751 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1752 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1753
86c6887e 1754 /* Send high bits if needed */
5dce95e5
SH		 1755 upper = upper_32_bits(mapping);
1756 if (upper != sky2->tx_last_upper) {
9b289c33 1757 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1758 le->addr = cpu_to_le32(upper);
1759 sky2->tx_last_upper = upper;
793b883e 1760 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1761 }
cd28ab6a
SH		 1762
1763 /* Check for TCP Segmentation Offload */
7967168c 1764 mss = skb_shinfo(skb)->gso_size;
793b883e 1765 if (mss != 0) {
ea76e635
SH		 1766
1767 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1768 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1769
1770 if (mss != sky2->tx_last_mss) {
9b289c33 1771 le = get_tx_le(sky2, &slot);
69161611 1772 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1773
1774 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1775 le->opcode = OP_MSS | HW_OWNER;
1776 else
1777 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1778 sky2->tx_last_mss = mss;
1779 }
cd28ab6a
SH		 1780 }
1781
cd28ab6a 1782 ctrl = 0;
d1f13708
SH		 1783#ifdef SKY2_VLAN_TAG_USED
1784 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1785 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1786 if (!le) {
9b289c33 1787 le = get_tx_le(sky2, &slot);
f65b138c 1788 le->addr = 0;
d1f13708 1789 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1790 } else
1791 le->opcode |= OP_VLAN;
1792 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1793 ctrl |= INS_VLAN;
1794 }
1795#endif
1796
1797 /* Handle TCP checksum offload */
84fa7933 1798 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1799 /* On Yukon EX (some versions) encoding change. */
ea76e635 1800 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1801 ctrl |= CALSUM; /* auto checksum */
1802 else {
1803 const unsigned offset = skb_transport_offset(skb);
1804 u32 tcpsum;
1805
1806 tcpsum = offset << 16; /* sum start */
1807 tcpsum |= offset + skb->csum_offset; /* sum write */
1808
1809 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1810 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1811 ctrl |= UDPTCP;
1812
1813 if (tcpsum != sky2->tx_tcpsum) {
1814 sky2->tx_tcpsum = tcpsum;
1815
9b289c33 1816 le = get_tx_le(sky2, &slot);
69161611
SH		 1817 le->addr = cpu_to_le32(tcpsum);
1818 le->length = 0; /* initial checksum value */
1819 le->ctrl = 1; /* one packet */
1820 le->opcode = OP_TCPLISW | HW_OWNER;
1821 }
1d179332 1822 }
cd28ab6a
SH		 1823 }
1824
6b84daca
SH		 1825 re = sky2->tx_ring + slot;
1826 re->flags = TX_MAP_SINGLE;
7cd26ce5
FT		 1827 dma_unmap_addr_set(re, mapaddr, mapping);
1828 dma_unmap_len_set(re, maplen, len);
6b84daca 1829
9b289c33 1830 le = get_tx_le(sky2, &slot);
d6e74b6b 1831 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1832 le->length = cpu_to_le16(len);
1833 le->ctrl = ctrl;
793b883e 1834 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1835
cd28ab6a
SH		 1836
1837 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1838 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1839
1840 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1841 frag->size, PCI_DMA_TODEVICE);
86c6887e 1842
454e6cb6
SH		 1843 if (pci_dma_mapping_error(hw->pdev, mapping))
1844 goto mapping_unwind;
1845
5dce95e5
SH		 1846 upper = upper_32_bits(mapping);
1847 if (upper != sky2->tx_last_upper) {
9b289c33 1848 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1849 le->addr = cpu_to_le32(upper);
1850 sky2->tx_last_upper = upper;
793b883e 1851 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1852 }
1853
6b84daca
SH		 1854 re = sky2->tx_ring + slot;
1855 re->flags = TX_MAP_PAGE;
7cd26ce5
FT		 1856 dma_unmap_addr_set(re, mapaddr, mapping);
1857 dma_unmap_len_set(re, maplen, frag->size);
6b84daca 1858
9b289c33 1859 le = get_tx_le(sky2, &slot);
d6e74b6b 1860 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1861 le->length = cpu_to_le16(frag->size);
1862 le->ctrl = ctrl;
793b883e 1863 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1864 }
6cdbbdf3 1865
6b84daca 1866 re->skb = skb;
cd28ab6a
SH		 1867 le->ctrl |= EOP;
1868
9b289c33
MM		 1869 sky2->tx_prod = slot;
1870
97bda706
SH		 1871 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1872 netif_stop_queue(dev);
b19666d9 1873
290d4de5 1874 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1875
cd28ab6a 1876 return NETDEV_TX_OK;
454e6cb6
SH		 1877
1878mapping_unwind:
ee5f68fe 1879 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1880 re = sky2->tx_ring + i;
1881
6b84daca 1882 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1883 }
1884
454e6cb6
SH		 1885mapping_error:
1886 if (net_ratelimit())
1887 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1888 dev_kfree_skb(skb);
1889 return NETDEV_TX_OK;
cd28ab6a
SH		 1890}
1891
cd28ab6a 1892/*
793b883e
SH		 1893 * Free ring elements from starting at tx_cons until "done"
1894 *
481cea4a
SH		 1895 * NB:
1896 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1897 * buffers so make sure not to free skb to early.
481cea4a
SH		 1898 * 2. This may run in parallel start_xmit because the it only
1899 * looks at the tail of the queue of FIFO (tx_cons), not
1900 * the head (tx_prod)
cd28ab6a 1901 */
d11c13e7 1902static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1903{
d11c13e7 1904 struct net_device *dev = sky2->netdev;
291ea614 1905 unsigned idx;
cd28ab6a 1906
ee5f68fe 1907 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1908
291ea614 1909 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1910 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1911 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1912 struct sk_buff *skb = re->skb;
291ea614 1913
6b84daca 1914 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1915
6b84daca 1916 if (skb) {
6c35abae
JP		 1917 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1918 "tx done %u\n", idx);
3cf26753 1919
7138a0f5 1920 dev->stats.tx_packets++;
bd1c6869
SH		 1921 dev->stats.tx_bytes += skb->len;
1922
f6815077 1923 re->skb = NULL;
724b6942 1924 dev_kfree_skb_any(skb);
2bf56fe2 1925
ee5f68fe 1926 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1927 }
793b883e 1928 }
793b883e 1929
291ea614 1930 sky2->tx_cons = idx;
50432cb5 1931 smp_mb();
cd28ab6a
SH		 1932}
1933
264bb4fa 1934static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1935{
a510996b
MM		 1936 /* Disable Force Sync bit and Enable Alloc bit */
1937 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1938 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1939
1940 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1941 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1942 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1943
1944 /* Reset the PCI FIFO of the async Tx queue */
1945 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1946 BMU_RST_SET | BMU_FIFO_RST);
1947
1948 /* Reset the Tx prefetch units */
1949 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1950 PREF_UNIT_RST_SET);
1951
1952 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1953 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1954}
1955
f2b31cb3 1956static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 1957{
cd28ab6a
SH		 1958 struct sky2_hw *hw = sky2->hw;
1959 unsigned port = sky2->port;
f2b31cb3 1960 u16 ctrl;
cd28ab6a 1961
d104acaf
SH		 1962 /* Force flow control off */
1963 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1964
cd28ab6a
SH		 1965 /* Stop transmitter */
1966 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1967 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1968
1969 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1970 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1971
1972 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1973 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1974 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1975
1976 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1977
1978 /* Workaround shared GMAC reset */
8e95a202
JP		 1979 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1980 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1981 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1982
cd28ab6a 1983 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1984
6c83504f
SH		 1985 /* Force any delayed status interrrupt and NAPI */
1986 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1987 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1988 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1989 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1990
a947a39d
MM		 1991 sky2_rx_stop(sky2);
1992
0da6d7b3 1993 spin_lock_bh(&sky2->phy_lock);
b96936da 1994 sky2_phy_power_down(hw, port);
0da6d7b3 1995 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1996
264bb4fa
MM		 1997 sky2_tx_reset(hw, port);
1998
481cea4a
SH		 1999 /* Free any pending frames stuck in HW queue */
2000 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 2001}
2002
2003/* Network shutdown */
2004static int sky2_down(struct net_device *dev)
2005{
2006 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 2007 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 2008
2009 /* Never really got started! */
2010 if (!sky2->tx_le)
2011 return 0;
2012
6c35abae 2013 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 2014
8a0c9228
MM		 2015 /* Disable port IRQ */
2016 sky2_write32(hw, B0_IMSK,
2017 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2018 sky2_read32(hw, B0_IMSK);
2019
2020 synchronize_irq(hw->pdev->irq);
2021 napi_synchronize(&hw->napi);
2022
f2b31cb3 2023 sky2_hw_down(sky2);
481cea4a 2024
90bbebb4 2025 sky2_free_buffers(sky2);
1b537565 2026
cd28ab6a
SH		 2027 return 0;
2028}
2029
2030static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2031{
ea76e635 2032 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 2033 return SPEED_1000;
2034
05745c4a
SH		 2035 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2036 if (aux & PHY_M_PS_SPEED_100)
2037 return SPEED_100;
2038 else
2039 return SPEED_10;
2040 }
cd28ab6a
SH		 2041
2042 switch (aux & PHY_M_PS_SPEED_MSK) {
2043 case PHY_M_PS_SPEED_1000:
2044 return SPEED_1000;
2045 case PHY_M_PS_SPEED_100:
2046 return SPEED_100;
2047 default:
2048 return SPEED_10;
2049 }
2050}
2051
2052static void sky2_link_up(struct sky2_port *sky2)
2053{
2054 struct sky2_hw *hw = sky2->hw;
2055 unsigned port = sky2->port;
16ad91e1
SH		 2056 static const char *fc_name[] = {
2057 [FC_NONE] = "none",
2058 [FC_TX] = "tx",
2059 [FC_RX] = "rx",
2060 [FC_BOTH] = "both",
2061 };
cd28ab6a 2062
38000a94 2063 sky2_enable_rx_tx(sky2);
cd28ab6a
SH		 2064
2065 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2066
2067 netif_carrier_on(sky2->netdev);
cd28ab6a 2068
75e80683 2069 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2070
cd28ab6a 2071 /* Turn on link LED */
793b883e 2072 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2073 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2074
6c35abae
JP		 2075 netif_info(sky2, link, sky2->netdev,
2076 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2077 sky2->speed,
2078 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2079 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2080}
2081
2082static void sky2_link_down(struct sky2_port *sky2)
2083{
2084 struct sky2_hw *hw = sky2->hw;
2085 unsigned port = sky2->port;
2086 u16 reg;
2087
2088 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2089
2090 reg = gma_read16(hw, port, GM_GP_CTRL);
2091 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2092 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2093
cd28ab6a 2094 netif_carrier_off(sky2->netdev);
cd28ab6a 2095
809aaaae 2096 /* Turn off link LED */
cd28ab6a
SH		 2097 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2098
6c35abae 2099 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2100
cd28ab6a
SH		 2101 sky2_phy_init(hw, port);
2102}
2103
16ad91e1
SH		 2104static enum flow_control sky2_flow(int rx, int tx)
2105{
2106 if (rx)
2107 return tx ? FC_BOTH : FC_RX;
2108 else
2109 return tx ? FC_TX : FC_NONE;
2110}
2111
793b883e
SH		 2112static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2113{
2114 struct sky2_hw *hw = sky2->hw;
2115 unsigned port = sky2->port;
da4c1ff4 2116 u16 advert, lpa;
793b883e 2117
da4c1ff4 2118 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2119 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2120 if (lpa & PHY_M_AN_RF) {
ada1db5c 2121 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2122 return -1;
2123 }
2124
793b883e 2125 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2126 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2127 return -1;
2128 }
2129
793b883e 2130 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2131 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2132
da4c1ff4
SH		 2133 /* Since the pause result bits seem to in different positions on
2134 * different chips. look at registers.
2135 */
ea76e635 2136 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2137 /* Shift for bits in fiber PHY */
2138 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2139 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2140
2141 if (advert & ADVERTISE_1000XPAUSE)
2142 advert |= ADVERTISE_PAUSE_CAP;
2143 if (advert & ADVERTISE_1000XPSE_ASYM)
2144 advert |= ADVERTISE_PAUSE_ASYM;
2145 if (lpa & LPA_1000XPAUSE)
2146 lpa |= LPA_PAUSE_CAP;
2147 if (lpa & LPA_1000XPAUSE_ASYM)
2148 lpa |= LPA_PAUSE_ASYM;
2149 }
793b883e 2150
da4c1ff4
SH		 2151 sky2->flow_status = FC_NONE;
2152 if (advert & ADVERTISE_PAUSE_CAP) {
2153 if (lpa & LPA_PAUSE_CAP)
2154 sky2->flow_status = FC_BOTH;
2155 else if (advert & ADVERTISE_PAUSE_ASYM)
2156 sky2->flow_status = FC_RX;
2157 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2158 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2159 sky2->flow_status = FC_TX;
2160 }
793b883e 2161
8e95a202
JP		 2162 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2163 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2164 sky2->flow_status = FC_NONE;
2eaba1a2 2165
da4c1ff4 2166 if (sky2->flow_status & FC_TX)
793b883e
SH		 2167 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2168 else
2169 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2170
2171 return 0;
2172}
cd28ab6a 2173
e07b1aa8
SH		 2174/* Interrupt from PHY */
2175static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2176{
e07b1aa8
SH		 2177 struct net_device *dev = hw->dev[port];
2178 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2179 u16 istatus, phystat;
2180
ebc646f6
SH		 2181 if (!netif_running(dev))
2182 return;
2183
e07b1aa8
SH		 2184 spin_lock(&sky2->phy_lock);
2185 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2186 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2187
6c35abae
JP		 2188 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2189 istatus, phystat);
cd28ab6a 2190
0ea065e5 2191 if (istatus & PHY_M_IS_AN_COMPL) {
9badba25 2192 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2193 !netif_carrier_ok(dev))
793b883e
SH		 2194 sky2_link_up(sky2);
2195 goto out;
2196 }
cd28ab6a 2197
793b883e
SH		 2198 if (istatus & PHY_M_IS_LSP_CHANGE)
2199 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2200
793b883e
SH		 2201 if (istatus & PHY_M_IS_DUP_CHANGE)
2202 sky2->duplex =
2203 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2204
793b883e
SH		 2205 if (istatus & PHY_M_IS_LST_CHANGE) {
2206 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2207 sky2_link_up(sky2);
793b883e
SH		 2208 else
2209 sky2_link_down(sky2);
cd28ab6a 2210 }
793b883e 2211out:
e07b1aa8 2212 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2213}
2214
0f5aac70
SH		 2215/* Special quick link interrupt (Yukon-2 Optima only) */
2216static void sky2_qlink_intr(struct sky2_hw *hw)
2217{
2218 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2219 u32 imask;
2220 u16 phy;
2221
2222 /* disable irq */
2223 imask = sky2_read32(hw, B0_IMSK);
2224 imask &= ~Y2_IS_PHY_QLNK;
2225 sky2_write32(hw, B0_IMSK, imask);
2226
2227 /* reset PHY Link Detect */
2228 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2229 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2230 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2231 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2232
2233 sky2_link_up(sky2);
2234}
2235
62335ab0 2236/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2237 * and tx queue is full (stopped).
2238 */
cd28ab6a
SH		 2239static void sky2_tx_timeout(struct net_device *dev)
2240{
2241 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2242 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2243
6c35abae 2244 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2245
ada1db5c
JP		 2246 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2247 sky2->tx_cons, sky2->tx_prod,
2248 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2249 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2250
81906791
SH		 2251 /* can't restart safely under softirq */
2252 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2253}
2254
2255static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2256{
6b1a3aef
SH		 2257 struct sky2_port *sky2 = netdev_priv(dev);
2258 struct sky2_hw *hw = sky2->hw;
b628ed98 2259 unsigned port = sky2->port;
6b1a3aef
SH		 2260 int err;
2261 u16 ctl, mode;
e07b1aa8 2262 u32 imask;
cd28ab6a 2263
44dde56d 2264 /* MTU size outside the spec */
cd28ab6a
SH		 2265 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2266 return -EINVAL;
2267
44dde56d 2268 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2269 if (new_mtu > ETH_DATA_LEN &&
2270 (hw->chip_id == CHIP_ID_YUKON_FE ||
2271 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2272 return -EINVAL;
2273
44dde56d 2274 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2275 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2276 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2277
6b1a3aef
SH		 2278 if (!netif_running(dev)) {
2279 dev->mtu = new_mtu;
2280 return 0;
2281 }
2282
e07b1aa8 2283 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2284 sky2_write32(hw, B0_IMSK, 0);
2285
018d1c66 2286 dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 2287 napi_disable(&hw->napi);
df01093b 2288 netif_tx_disable(dev);
018d1c66 2289
e07b1aa8
SH		 2290 synchronize_irq(hw->pdev->irq);
2291
39dbd958 2292 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2293 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2294
2295 ctl = gma_read16(hw, port, GM_GP_CTRL);
2296 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2297 sky2_rx_stop(sky2);
2298 sky2_rx_clean(sky2);
cd28ab6a
SH		 2299
2300 dev->mtu = new_mtu;
14d0263f 2301
6b1a3aef
SH		 2302 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2303 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2304
2305 if (dev->mtu > ETH_DATA_LEN)
2306 mode |= GM_SMOD_JUMBO_ENA;
2307
b628ed98 2308 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2309
b628ed98 2310 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2311
200ac492
MM		 2312 err = sky2_alloc_rx_skbs(sky2);
2313 if (!err)
2314 sky2_rx_start(sky2);
2315 else
2316 sky2_rx_clean(sky2);
e07b1aa8 2317 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2318
d1d08d12 2319 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2320 napi_enable(&hw->napi);
2321
1b537565
SH		 2322 if (err)
2323 dev_close(dev);
2324 else {
b628ed98 2325 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2326
1b537565
SH		 2327 netif_wake_queue(dev);
2328 }
2329
cd28ab6a
SH		 2330 return err;
2331}
2332
14d0263f
SH		 2333/* For small just reuse existing skb for next receive */
2334static struct sk_buff *receive_copy(struct sky2_port *sky2,
2335 const struct rx_ring_info *re,
2336 unsigned length)
2337{
2338 struct sk_buff *skb;
2339
89d71a66 2340 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2341 if (likely(skb)) {
14d0263f
SH		 2342 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2343 length, PCI_DMA_FROMDEVICE);
d626f62b 2344 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2345 skb->ip_summed = re->skb->ip_summed;
2346 skb->csum = re->skb->csum;
2347 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2348 length, PCI_DMA_FROMDEVICE);
2349 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2350 skb_put(skb, length);
14d0263f
SH		 2351 }
2352 return skb;
2353}
2354
2355/* Adjust length of skb with fragments to match received data */
2356static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2357 unsigned int length)
2358{
2359 int i, num_frags;
2360 unsigned int size;
2361
2362 /* put header into skb */
2363 size = min(length, hdr_space);
2364 skb->tail += size;
2365 skb->len += size;
2366 length -= size;
2367
2368 num_frags = skb_shinfo(skb)->nr_frags;
2369 for (i = 0; i < num_frags; i++) {
2370 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2371
2372 if (length == 0) {
2373 /* don't need this page */
2374 __free_page(frag->page);
2375 --skb_shinfo(skb)->nr_frags;
2376 } else {
2377 size = min(length, (unsigned) PAGE_SIZE);
2378
2379 frag->size = size;
2380 skb->data_len += size;
2381 skb->truesize += size;
2382 skb->len += size;
2383 length -= size;
2384 }
2385 }
2386}
2387
2388/* Normal packet - take skb from ring element and put in a new one */
2389static struct sk_buff *receive_new(struct sky2_port *sky2,
2390 struct rx_ring_info *re,
2391 unsigned int length)
2392{
3fbd9187 2393 struct sk_buff *skb;
2394 struct rx_ring_info nre;
14d0263f
SH		 2395 unsigned hdr_space = sky2->rx_data_size;
2396
3fbd9187 2397 nre.skb = sky2_rx_alloc(sky2);
2398 if (unlikely(!nre.skb))
2399 goto nobuf;
2400
2401 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2402 goto nomap;
14d0263f
SH		 2403
2404 skb = re->skb;
2405 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2406 prefetch(skb->data);
3fbd9187 2407 *re = nre;
14d0263f
SH		 2408
2409 if (skb_shinfo(skb)->nr_frags)
2410 skb_put_frags(skb, hdr_space, length);
2411 else
489b10c1 2412 skb_put(skb, length);
14d0263f 2413 return skb;
3fbd9187 2414
2415nomap:
2416 dev_kfree_skb(nre.skb);
2417nobuf:
2418 return NULL;
14d0263f
SH		 2419}
2420
cd28ab6a
SH		 2421/*
2422 * Receive one packet.
d571b694 2423 * For larger packets, get new buffer.
cd28ab6a 2424 */
497d7c86 2425static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2426 u16 length, u32 status)
2427{
497d7c86 2428 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2429 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2430 struct sk_buff *skb = NULL;
d6532232
SH		 2431 u16 count = (status & GMR_FS_LEN) >> 16;
2432
2433#ifdef SKY2_VLAN_TAG_USED
2434 /* Account for vlan tag */
2435 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2436 count -= VLAN_HLEN;
2437#endif
cd28ab6a 2438
6c35abae
JP		 2439 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2440 "rx slot %u status 0x%x len %d\n",
2441 sky2->rx_next, status, length);
cd28ab6a 2442
793b883e 2443 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2444 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2445
3b12e014
SH		 2446 /* This chip has hardware problems that generates bogus status.
2447 * So do only marginal checking and expect higher level protocols
2448 * to handle crap frames.
2449 */
2450 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2451 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2452 length != count)
2453 goto okay;
2454
42eeea01 2455 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2456 goto error;
2457
42eeea01
SH		 2458 if (!(status & GMR_FS_RX_OK))
2459 goto resubmit;
2460
d6532232
SH		 2461 /* if length reported by DMA does not match PHY, packet was truncated */
2462 if (length != count)
3b12e014 2463 goto len_error;
71749531 2464
3b12e014 2465okay:
14d0263f
SH		 2466 if (length < copybreak)
2467 skb = receive_copy(sky2, re, length);
2468 else
2469 skb = receive_new(sky2, re, length);
90c30335
SH		 2470
2471 dev->stats.rx_dropped += (skb == NULL);
2472
793b883e 2473resubmit:
14d0263f 2474 sky2_rx_submit(sky2, re);
79e57d32 2475
cd28ab6a
SH		 2476 return skb;
2477
3b12e014 2478len_error:
71749531
SH		 2479 /* Truncation of overlength packets
2480 causes PHY length to not match MAC length */
7138a0f5 2481 ++dev->stats.rx_length_errors;
6c35abae
JP		 2482 if (net_ratelimit())
2483 netif_info(sky2, rx_err, dev,
2484 "rx length error: status %#x length %d\n",
2485 status, length);
d6532232 2486 goto resubmit;
71749531 2487
cd28ab6a 2488error:
7138a0f5 2489 ++dev->stats.rx_errors;
b6d77734 2490 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2491 dev->stats.rx_over_errors++;
b6d77734
SH		 2492 goto resubmit;
2493 }
6e15b712 2494
6c35abae
JP		 2495 if (net_ratelimit())
2496 netif_info(sky2, rx_err, dev,
2497 "rx error, status 0x%x length %d\n", status, length);
793b883e
SH		 2498
2499 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2500 dev->stats.rx_length_errors++;
cd28ab6a 2501 if (status & GMR_FS_FRAGMENT)
7138a0f5 2502 dev->stats.rx_frame_errors++;
cd28ab6a 2503 if (status & GMR_FS_CRC_ERR)
7138a0f5 2504 dev->stats.rx_crc_errors++;
79e57d32 2505
793b883e 2506 goto resubmit;
cd28ab6a
SH		 2507}
2508
e07b1aa8
SH		 2509/* Transmit complete */
2510static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2511{
e07b1aa8 2512 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2513
8a0c9228 2514 if (netif_running(dev)) {
e07b1aa8 2515 sky2_tx_complete(sky2, last);
8a0c9228
MM		 2516
2517 /* Wake unless it's detached, and called e.g. from sky2_down() */
2518 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2519 netif_wake_queue(dev);
2520 }
cd28ab6a
SH		 2521}
2522
5e4e7573 2523static inline void sky2_skb_rx(const struct sky2_port *sky2,
37e5a243
SH		 2524 u32 status, struct sk_buff *skb)
2525{
2526#ifdef SKY2_VLAN_TAG_USED
5e4e7573 2527 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
37e5a243 2528 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
5e4e7573 2529 if (skb->ip_summed == CHECKSUM_NONE)
37e5a243
SH		 2530 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2531 else
5e4e7573
DM		 2532 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2533 vlan_tag, skb);
37e5a243
SH		 2534 return;
2535 }
2536#endif
5e4e7573 2537 if (skb->ip_summed == CHECKSUM_NONE)
37e5a243
SH		 2538 netif_receive_skb(skb);
2539 else
5e4e7573 2540 napi_gro_receive(&sky2->hw->napi, skb);
37e5a243
SH		 2541}
2542
bf15fe99
SH		 2543static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2544 unsigned packets, unsigned bytes)
2545{
2546 if (packets) {
2547 struct net_device *dev = hw->dev[port];
2548
2549 dev->stats.rx_packets += packets;
2550 dev->stats.rx_bytes += bytes;
2551 dev->last_rx = jiffies;
2552 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2553 }
2554}
2555
375c5688 2556static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2557{
2558 /* If this happens then driver assuming wrong format for chip type */
2559 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2560
2561 /* Both checksum counters are programmed to start at
2562 * the same offset, so unless there is a problem they
2563 * should match. This failure is an early indication that
2564 * hardware receive checksumming won't work.
2565 */
2566 if (likely((u16)(status >> 16) == (u16)status)) {
2567 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2568 skb->ip_summed = CHECKSUM_COMPLETE;
2569 skb->csum = le16_to_cpu(status);
2570 } else {
2571 dev_notice(&sky2->hw->pdev->dev,
2572 "%s: receive checksum problem (status = %#x)\n",
2573 sky2->netdev->name, status);
2574
2575 /* Disable checksum offload */
2576 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2577 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2578 BMU_DIS_RX_CHKSUM);
2579 }
2580}
2581
bf73130d
SH		 2582static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2583{
2584 struct sk_buff *skb;
2585
2586 skb = sky2->rx_ring[sky2->rx_next].skb;
2587 skb->rxhash = le32_to_cpu(status);
2588}
2589
e07b1aa8 2590/* Process status response ring */
26691830 2591static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2592{
e07b1aa8 2593 int work_done = 0;
bf15fe99
SH		 2594 unsigned int total_bytes[2] = { 0 };
2595 unsigned int total_packets[2] = { 0 };
a8fd6266 2596
af2a58ac 2597 rmb();
26691830 2598 do {
55c9dd35 2599 struct sky2_port *sky2;
13210ce5 2600 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2601 unsigned port;
13210ce5 2602 struct net_device *dev;
cd28ab6a 2603 struct sk_buff *skb;
cd28ab6a
SH		 2604 u32 status;
2605 u16 length;
ab5adecb
SH		 2606 u8 opcode = le->opcode;
2607
2608 if (!(opcode & HW_OWNER))
2609 break;
cd28ab6a 2610
efe91932 2611 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
bea86103 2612
ab5adecb 2613 port = le->css & CSS_LINK_BIT;
69161611 2614 dev = hw->dev[port];
13210ce5 2615 sky2 = netdev_priv(dev);
f65b138c
SH		 2616 length = le16_to_cpu(le->length);
2617 status = le32_to_cpu(le->status);
cd28ab6a 2618
ab5adecb
SH		 2619 le->opcode = 0;
2620 switch (opcode & ~HW_OWNER) {
cd28ab6a 2621 case OP_RXSTAT:
bf15fe99
SH		 2622 total_packets[port]++;
2623 total_bytes[port] += length;
90c30335 2624
497d7c86 2625 skb = sky2_receive(dev, length, status);
90c30335 2626 if (!skb)
55c9dd35 2627 break;
13210ce5 2628
69161611 2629 /* This chip reports checksum status differently */
05745c4a 2630 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2631 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2632 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2633 (le->css & CSS_TCPUDPCSOK))
2634 skb->ip_summed = CHECKSUM_UNNECESSARY;
2635 else
2636 skb->ip_summed = CHECKSUM_NONE;
2637 }
2638
13210ce5 2639 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2640
5e4e7573 2641 sky2_skb_rx(sky2, status, skb);
13210ce5 2642
22e11703 2643 /* Stop after net poll weight */
13210ce5
SH		 2644 if (++work_done >= to_do)
2645 goto exit_loop;
cd28ab6a
SH		 2646 break;
2647
d1f13708
SH		 2648#ifdef SKY2_VLAN_TAG_USED
2649 case OP_RXVLAN:
2650 sky2->rx_tag = length;
2651 break;
2652
2653 case OP_RXCHKSVLAN:
2654 sky2->rx_tag = length;
2655 /* fall through */
2656#endif
cd28ab6a 2657 case OP_RXCHKS:
375c5688 2658 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2659 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2660 break;
2661
bf73130d
SH		 2662 case OP_RSS_HASH:
2663 sky2_rx_hash(sky2, status);
2664 break;
2665
cd28ab6a 2666 case OP_TXINDEXLE:
13b97b74 2667 /* TX index reports status for both ports */
f55925d7 2668 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2669 if (hw->dev[1])
2670 sky2_tx_done(hw->dev[1],
2671 ((status >> 24) & 0xff)
2672 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2673 break;
2674
cd28ab6a
SH		 2675 default:
2676 if (net_ratelimit())
ada1db5c 2677 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2678 }
26691830 2679 } while (hw->st_idx != idx);
cd28ab6a 2680
fe2a24df
SH		 2681 /* Fully processed status ring so clear irq */
2682 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2683
13210ce5 2684exit_loop:
bf15fe99
SH		 2685 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2686 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2687
e07b1aa8 2688 return work_done;
cd28ab6a
SH		 2689}
2690
2691static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2692{
2693 struct net_device *dev = hw->dev[port];
2694
3be92a70 2695 if (net_ratelimit())
ada1db5c 2696 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2697
2698 if (status & Y2_IS_PAR_RD1) {
3be92a70 2699 if (net_ratelimit())
ada1db5c 2700 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2701 /* Clear IRQ */
2702 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2703 }
2704
2705 if (status & Y2_IS_PAR_WR1) {
3be92a70 2706 if (net_ratelimit())
ada1db5c 2707 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2708
2709 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2710 }
2711
2712 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2713 if (net_ratelimit())
ada1db5c 2714 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2715 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2716 }
2717
2718 if (status & Y2_IS_PAR_RX1) {
3be92a70 2719 if (net_ratelimit())
ada1db5c 2720 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2721 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2722 }
2723
2724 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2725 if (net_ratelimit())
ada1db5c 2726 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2727 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2728 }
2729}
2730
2731static void sky2_hw_intr(struct sky2_hw *hw)
2732{
555382cb 2733 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2734 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2735 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2736
2737 status &= hwmsk;
cd28ab6a 2738
793b883e 2739 if (status & Y2_IS_TIST_OV)
cd28ab6a 2740 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2741
2742 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2743 u16 pci_err;
2744
a40ccc68 2745 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2746 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2747 if (net_ratelimit())
555382cb 2748 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2749 pci_err);
cd28ab6a 2750
b32f40c4 2751 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2752 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2753 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2754 }
2755
2756 if (status & Y2_IS_PCI_EXP) {
d571b694 2757 /* PCI-Express uncorrectable Error occurred */
555382cb 2758 u32 err;
cd28ab6a 2759
a40ccc68 2760 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2761 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2762 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2763 0xfffffffful);
3be92a70 2764 if (net_ratelimit())
555382cb 2765 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2766
7782c8c4 2767 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2768 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2769 }
2770
2771 if (status & Y2_HWE_L1_MASK)
2772 sky2_hw_error(hw, 0, status);
2773 status >>= 8;
2774 if (status & Y2_HWE_L1_MASK)
2775 sky2_hw_error(hw, 1, status);
2776}
2777
2778static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2779{
2780 struct net_device *dev = hw->dev[port];
2781 struct sky2_port *sky2 = netdev_priv(dev);
2782 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2783
6c35abae 2784 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2785
a3caeada
SH		 2786 if (status & GM_IS_RX_CO_OV)
2787 gma_read16(hw, port, GM_RX_IRQ_SRC);
2788
2789 if (status & GM_IS_TX_CO_OV)
2790 gma_read16(hw, port, GM_TX_IRQ_SRC);
2791
cd28ab6a 2792 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2793 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2794 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2795 }
2796
2797 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2798 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2799 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2800 }
cd28ab6a
SH		 2801}
2802
40b01727 2803/* This should never happen it is a bug. */
c119731d 2804static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2805{
2806 struct net_device *dev = hw->dev[port];
c119731d 2807 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2808
ada1db5c 2809 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2810 dev->name, (unsigned) q, (unsigned) idx,
2811 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2812
40b01727 2813 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2814}
cd28ab6a 2815
75e80683
SH		 2816static int sky2_rx_hung(struct net_device *dev)
2817{
2818 struct sky2_port *sky2 = netdev_priv(dev);
2819 struct sky2_hw *hw = sky2->hw;
2820 unsigned port = sky2->port;
2821 unsigned rxq = rxqaddr[port];
2822 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2823 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2824 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2825 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2826
2827 /* If idle and MAC or PCI is stuck */
2828 if (sky2->check.last == dev->last_rx &&
2829 ((mac_rp == sky2->check.mac_rp &&
2830 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2831 /* Check if the PCI RX hang */
2832 (fifo_rp == sky2->check.fifo_rp &&
2833 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2834 netdev_printk(KERN_DEBUG, dev,
2835 "hung mac %d:%d fifo %d (%d:%d)\n",
2836 mac_lev, mac_rp, fifo_lev,
2837 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2838 return 1;
2839 } else {
2840 sky2->check.last = dev->last_rx;
2841 sky2->check.mac_rp = mac_rp;
2842 sky2->check.mac_lev = mac_lev;
2843 sky2->check.fifo_rp = fifo_rp;
2844 sky2->check.fifo_lev = fifo_lev;
2845 return 0;
2846 }
2847}
2848
32c2c300 2849static void sky2_watchdog(unsigned long arg)
d27ed387 2850{
01bd7564 2851 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2852
75e80683 2853 /* Check for lost IRQ once a second */
32c2c300 2854 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2855 napi_schedule(&hw->napi);
75e80683
SH		 2856 } else {
2857 int i, active = 0;
2858
2859 for (i = 0; i < hw->ports; i++) {
bea3348e 2860 struct net_device *dev = hw->dev[i];
75e80683
SH		 2861 if (!netif_running(dev))
2862 continue;
2863 ++active;
2864
2865 /* For chips with Rx FIFO, check if stuck */
39dbd958 2866 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 2867 sky2_rx_hung(dev)) {
ada1db5c 2868 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 2869 schedule_work(&hw->restart_work);
2870 return;
2871 }
2872 }
2873
2874 if (active == 0)
2875 return;
32c2c300 2876 }
01bd7564 2877
75e80683 2878 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2879}
2880
40b01727
SH		 2881/* Hardware/software error handling */
2882static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2883{
40b01727
SH		 2884 if (net_ratelimit())
2885 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2886
1e5f1283
SH		 2887 if (status & Y2_IS_HW_ERR)
2888 sky2_hw_intr(hw);
d257924e 2889
1e5f1283
SH		 2890 if (status & Y2_IS_IRQ_MAC1)
2891 sky2_mac_intr(hw, 0);
cd28ab6a 2892
1e5f1283
SH		 2893 if (status & Y2_IS_IRQ_MAC2)
2894 sky2_mac_intr(hw, 1);
cd28ab6a 2895
1e5f1283 2896 if (status & Y2_IS_CHK_RX1)
c119731d 2897 sky2_le_error(hw, 0, Q_R1);
d257924e 2898
1e5f1283 2899 if (status & Y2_IS_CHK_RX2)
c119731d 2900 sky2_le_error(hw, 1, Q_R2);
d257924e 2901
1e5f1283 2902 if (status & Y2_IS_CHK_TXA1)
c119731d 2903 sky2_le_error(hw, 0, Q_XA1);
d257924e 2904
1e5f1283 2905 if (status & Y2_IS_CHK_TXA2)
c119731d 2906 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2907}
2908
bea3348e 2909static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2910{
bea3348e 2911 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2912 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2913 int work_done = 0;
26691830 2914 u16 idx;
40b01727
SH		 2915
2916 if (unlikely(status & Y2_IS_ERROR))
2917 sky2_err_intr(hw, status);
2918
2919 if (status & Y2_IS_IRQ_PHY1)
2920 sky2_phy_intr(hw, 0);
2921
2922 if (status & Y2_IS_IRQ_PHY2)
2923 sky2_phy_intr(hw, 1);
cd28ab6a 2924
0f5aac70
SH		 2925 if (status & Y2_IS_PHY_QLNK)
2926 sky2_qlink_intr(hw);
2927
26691830
SH		 2928 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2929 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2930
2931 if (work_done >= work_limit)
26691830
SH		 2932 goto done;
2933 }
6f535763 2934
26691830
SH		 2935 napi_complete(napi);
2936 sky2_read32(hw, B0_Y2_SP_LISR);
2937done:
6f535763 2938
bea3348e 2939 return work_done;
e07b1aa8
SH		 2940}
2941
7d12e780 2942static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2943{
2944 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2945 u32 status;
2946
2947 /* Reading this mask interrupts as side effect */
2948 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2949 if (status == 0 || status == ~0)
2950 return IRQ_NONE;
793b883e 2951
e07b1aa8 2952 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2953
2954 napi_schedule(&hw->napi);
793b883e 2955
cd28ab6a
SH		 2956 return IRQ_HANDLED;
2957}
2958
2959#ifdef CONFIG_NET_POLL_CONTROLLER
2960static void sky2_netpoll(struct net_device *dev)
2961{
2962 struct sky2_port *sky2 = netdev_priv(dev);
2963
bea3348e 2964 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2965}
2966#endif
2967
2968/* Chip internal frequency for clock calculations */
05745c4a 2969static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2970{
793b883e 2971 switch (hw->chip_id) {
cd28ab6a 2972 case CHIP_ID_YUKON_EC:
5a5b1ea0 2973 case CHIP_ID_YUKON_EC_U:
93745494 2974 case CHIP_ID_YUKON_EX:
ed4d4161 2975 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2976 case CHIP_ID_YUKON_UL_2:
0f5aac70 2977 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2978 return 125;
2979
cd28ab6a 2980 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2981 return 100;
2982
2983 case CHIP_ID_YUKON_FE_P:
2984 return 50;
2985
2986 case CHIP_ID_YUKON_XL:
2987 return 156;
2988
2989 default:
2990 BUG();
cd28ab6a
SH		 2991 }
2992}
2993
fb17358f 2994static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2995{
fb17358f 2996 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2997}
2998
fb17358f 2999static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 3000{
fb17358f 3001 return clk / sky2_mhz(hw);
cd28ab6a
SH		 3002}
3003
fb17358f 3004
e3173832 3005static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 3006{
b89165f2 3007 u8 t8;
cd28ab6a 3008
167f53d0 3009 /* Enable all clocks and check for bad PCI access */
b32f40c4 3010 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 3011
cd28ab6a 3012 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 3013
cd28ab6a 3014 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 3015 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3016
060b946c 3017 switch (hw->chip_id) {
ea76e635 3018 case CHIP_ID_YUKON_XL:
39dbd958 3019 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
bf73130d
SH		 3020 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3021 hw->flags |= SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3022 break;
3023
3024 case CHIP_ID_YUKON_EC_U:
3025 hw->flags = SKY2_HW_GIGABIT
3026 | SKY2_HW_NEWER_PHY
3027 | SKY2_HW_ADV_POWER_CTL;
3028 break;
3029
3030 case CHIP_ID_YUKON_EX:
3031 hw->flags = SKY2_HW_GIGABIT
3032 | SKY2_HW_NEWER_PHY
3033 | SKY2_HW_NEW_LE
3034 | SKY2_HW_ADV_POWER_CTL;
3035
3036 /* New transmit checksum */
3037 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3038 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3039 break;
3040
3041 case CHIP_ID_YUKON_EC:
3042 /* This rev is really old, and requires untested workarounds */
3043 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3044 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3045 return -EOPNOTSUPP;
3046 }
bf73130d 3047 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3048 break;
3049
3050 case CHIP_ID_YUKON_FE:
bf73130d 3051 hw->flags = SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3052 break;
3053
05745c4a
SH		 3054 case CHIP_ID_YUKON_FE_P:
3055 hw->flags = SKY2_HW_NEWER_PHY
3056 | SKY2_HW_NEW_LE
3057 | SKY2_HW_AUTO_TX_SUM
3058 | SKY2_HW_ADV_POWER_CTL;
3059 break;
ed4d4161
SH		 3060
3061 case CHIP_ID_YUKON_SUPR:
3062 hw->flags = SKY2_HW_GIGABIT
3063 | SKY2_HW_NEWER_PHY
3064 | SKY2_HW_NEW_LE
3065 | SKY2_HW_AUTO_TX_SUM
3066 | SKY2_HW_ADV_POWER_CTL;
3067 break;
3068
0ce8b98d 3069 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3070 hw->flags = SKY2_HW_GIGABIT
3071 | SKY2_HW_ADV_POWER_CTL;
3072 break;
3073
0f5aac70 3074 case CHIP_ID_YUKON_OPT:
0ce8b98d 3075 hw->flags = SKY2_HW_GIGABIT
b338682d 3076 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3077 | SKY2_HW_ADV_POWER_CTL;
3078 break;
3079
ea76e635 3080 default:
b02a9258
SH		 3081 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3082 hw->chip_id);
cd28ab6a
SH		 3083 return -EOPNOTSUPP;
3084 }
3085
ea76e635
SH		 3086 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3087 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3088 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3089
e3173832
SH		 3090 hw->ports = 1;
3091 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3092 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3093 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3094 ++hw->ports;
3095 }
3096
74a61ebf
MM		 3097 if (sky2_read8(hw, B2_E_0))
3098 hw->flags |= SKY2_HW_RAM_BUFFER;
3099
e3173832
SH		 3100 return 0;
3101}
3102
3103static void sky2_reset(struct sky2_hw *hw)
3104{
555382cb 3105 struct pci_dev *pdev = hw->pdev;
e3173832 3106 u16 status;
555382cb
SH		 3107 int i, cap;
3108 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3109
cd28ab6a 3110 /* disable ASF */
acd12dde 3111 if (hw->chip_id == CHIP_ID_YUKON_EX
3112 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3113 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3114 status = sky2_read16(hw, HCU_CCSR);
3115 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3116 HCU_CCSR_UC_STATE_MSK);
acd12dde 3117 /*
3118 * CPU clock divider shouldn't be used because
3119 * - ASF firmware may malfunction
3120 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3121 */
3122 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3123 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3124 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3125 } else
3126 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3127 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3128
3129 /* do a SW reset */
3130 sky2_write8(hw, B0_CTST, CS_RST_SET);
3131 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3132
ac93a394
SH		 3133 /* allow writes to PCI config */
3134 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3135
cd28ab6a 3136 /* clear PCI errors, if any */
b32f40c4 3137 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3138 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3139 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3140
3141 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3142
555382cb
SH		 3143 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3144 if (cap) {
7782c8c4
SH		 3145 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3146 0xfffffffful);
555382cb
SH		 3147
3148 /* If error bit is stuck on ignore it */
3149 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3150 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3151 else
555382cb
SH		 3152 hwe_mask |= Y2_IS_PCI_EXP;
3153 }
cd28ab6a 3154
ae306cca 3155 sky2_power_on(hw);
a40ccc68 3156 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3157
3158 for (i = 0; i < hw->ports; i++) {
3159 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3160 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3161
ed4d4161
SH		 3162 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3163 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3164 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3165 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3166 | GMC_BYP_RETR_ON);
877c8570
SH		 3167
3168 }
3169
3170 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3171 /* enable MACSec clock gating */
3172 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3173 }
3174
0f5aac70
SH		 3175 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3176 u16 reg;
3177 u32 msk;
3178
3179 if (hw->chip_rev == 0) {
3180 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3181 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3182
3183 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3184 reg = 10;
3185 } else {
3186 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3187 reg = 3;
3188 }
3189
3190 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3191
3192 /* reset PHY Link Detect */
a40ccc68 3193 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3194 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3195 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3196 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3197
3198
3199 /* enable PHY Quick Link */
3200 msk = sky2_read32(hw, B0_IMSK);
3201 msk |= Y2_IS_PHY_QLNK;
3202 sky2_write32(hw, B0_IMSK, msk);
3203
3204 /* check if PSMv2 was running before */
3205 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3206 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3207 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3208 /* restore the PCIe Link Control register */
3209 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3210 }
a40ccc68 3211 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3212
3213 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3214 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3215 }
3216
793b883e
SH		 3217 /* Clear I2C IRQ noise */
3218 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3219
3220 /* turn off hardware timer (unused) */
3221 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3222 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3223
69634ee7
SH		 3224 /* Turn off descriptor polling */
3225 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3226
3227 /* Turn off receive timestamp */
3228 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3229 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3230
3231 /* enable the Tx Arbiters */
3232 for (i = 0; i < hw->ports; i++)
3233 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3234
3235 /* Initialize ram interface */
3236 for (i = 0; i < hw->ports; i++) {
793b883e 3237 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3238
3239 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3240 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3241 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3242 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3243 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3244 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3245 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3246 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3247 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3248 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3249 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3250 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3251 }
3252
555382cb 3253 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3254
cd28ab6a 3255 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3256 sky2_gmac_reset(hw, i);
cd28ab6a 3257
efe91932 3258 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
cd28ab6a
SH		 3259 hw->st_idx = 0;
3260
3261 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3262 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3263
3264 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3265 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3266
3267 /* Set the list last index */
efe91932 3268 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
cd28ab6a 3269
290d4de5
SH		 3270 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3271 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3272
290d4de5
SH		 3273 /* set Status-FIFO ISR watermark */
3274 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3275 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3276 else
3277 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3278
290d4de5 3279 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3280 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3281 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3282
793b883e 3283 /* enable status unit */
cd28ab6a
SH		 3284 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3285
3286 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3287 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3288 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3289}
3290
af18d8b8
SH		 3291/* Take device down (offline).
3292 * Equivalent to doing dev_stop() but this does not
3293 * inform upper layers of the transistion.
3294 */
3295static void sky2_detach(struct net_device *dev)
3296{
3297 if (netif_running(dev)) {
c36531b9 3298 netif_tx_lock(dev);
af18d8b8 3299 netif_device_detach(dev); /* stop txq */
c36531b9 3300 netif_tx_unlock(dev);
af18d8b8
SH		 3301 sky2_down(dev);
3302 }
3303}
3304
3305/* Bring device back after doing sky2_detach */
3306static int sky2_reattach(struct net_device *dev)
3307{
3308 int err = 0;
3309
3310 if (netif_running(dev)) {
3311 err = sky2_up(dev);
3312 if (err) {
ada1db5c 3313 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3314 dev_close(dev);
3315 } else {
3316 netif_device_attach(dev);
3317 sky2_set_multicast(dev);
3318 }
3319 }
3320
3321 return err;
3322}
3323
d72ff8fa 3324static void sky2_all_down(struct sky2_hw *hw)
81906791 3325{
af18d8b8 3326 int i;
81906791 3327
d72ff8fa 3328 sky2_read32(hw, B0_IMSK);
8cfcbe99 3329 sky2_write32(hw, B0_IMSK, 0);
93135a3b
MM		 3330 synchronize_irq(hw->pdev->irq);
3331 napi_disable(&hw->napi);
8a0c9228
MM		 3332
3333 for (i = 0; i < hw->ports; i++) {
3334 struct net_device *dev = hw->dev[i];
3335 struct sky2_port *sky2 = netdev_priv(dev);
3336
3337 if (!netif_running(dev))
3338 continue;
3339
3340 netif_carrier_off(dev);
3341 netif_tx_disable(dev);
3342 sky2_hw_down(sky2);
3343 }
d72ff8fa 3344}
8a0c9228 3345
d72ff8fa
MM		 3346static void sky2_all_up(struct sky2_hw *hw)
3347{
3348 u32 imask = Y2_IS_BASE;
3349 int i;
81906791 3350
8a0c9228
MM		 3351 for (i = 0; i < hw->ports; i++) {
3352 struct net_device *dev = hw->dev[i];
3353 struct sky2_port *sky2 = netdev_priv(dev);
3354
3355 if (!netif_running(dev))
3356 continue;
3357
3358 sky2_hw_up(sky2);
37652522 3359 sky2_set_multicast(dev);
d72ff8fa 3360 imask |= portirq_msk[i];
8a0c9228
MM		 3361 netif_wake_queue(dev);
3362 }
3363
3364 sky2_write32(hw, B0_IMSK, imask);
3365 sky2_read32(hw, B0_IMSK);
3366
3367 sky2_read32(hw, B0_Y2_SP_LISR);
3368 napi_enable(&hw->napi);
d72ff8fa
MM		 3369}
3370
3371static void sky2_restart(struct work_struct *work)
3372{
3373 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3374
3375 rtnl_lock();
3376
3377 sky2_all_down(hw);
3378 sky2_reset(hw);
3379 sky2_all_up(hw);
81906791 3380
81906791
SH		 3381 rtnl_unlock();
3382}
3383
e3173832
SH		 3384static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3385{
3386 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3387}
3388
3389static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3390{
3391 const struct sky2_port *sky2 = netdev_priv(dev);
3392
3393 wol->supported = sky2_wol_supported(sky2->hw);
3394 wol->wolopts = sky2->wol;
3395}
3396
3397static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3398{
3399 struct sky2_port *sky2 = netdev_priv(dev);
3400 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3401
8e95a202
JP		 3402 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3403 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3404 return -EOPNOTSUPP;
3405
3406 sky2->wol = wol->wolopts;
cd28ab6a
SH		 3407 return 0;
3408}
3409
28bd181a 3410static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3411{
b89165f2
SH		 3412 if (sky2_is_copper(hw)) {
3413 u32 modes = SUPPORTED_10baseT_Half
3414 | SUPPORTED_10baseT_Full
3415 | SUPPORTED_100baseT_Half
3416 | SUPPORTED_100baseT_Full
3417 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3418
ea76e635 3419 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3420 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3421 | SUPPORTED_1000baseT_Full;
3422 return modes;
cd28ab6a 3423 } else
b89165f2
SH		 3424 return SUPPORTED_1000baseT_Half
3425 | SUPPORTED_1000baseT_Full
3426 | SUPPORTED_Autoneg
3427 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3428}
3429
793b883e 3430static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3431{
3432 struct sky2_port *sky2 = netdev_priv(dev);
3433 struct sky2_hw *hw = sky2->hw;
3434
3435 ecmd->transceiver = XCVR_INTERNAL;
3436 ecmd->supported = sky2_supported_modes(hw);
3437 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3438 if (sky2_is_copper(hw)) {
cd28ab6a 3439 ecmd->port = PORT_TP;
b89165f2
SH		 3440 ecmd->speed = sky2->speed;
3441 } else {
3442 ecmd->speed = SPEED_1000;
cd28ab6a 3443 ecmd->port = PORT_FIBRE;
b89165f2 3444 }
cd28ab6a
SH		 3445
3446 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3447 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3448 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3449 ecmd->duplex = sky2->duplex;
3450 return 0;
3451}
3452
3453static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3454{
3455 struct sky2_port *sky2 = netdev_priv(dev);
3456 const struct sky2_hw *hw = sky2->hw;
3457 u32 supported = sky2_supported_modes(hw);
3458
3459 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3460 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3461 ecmd->advertising = supported;
3462 sky2->duplex = -1;
3463 sky2->speed = -1;
3464 } else {
3465 u32 setting;
3466
793b883e 3467 switch (ecmd->speed) {
cd28ab6a
SH		 3468 case SPEED_1000:
3469 if (ecmd->duplex == DUPLEX_FULL)
3470 setting = SUPPORTED_1000baseT_Full;
3471 else if (ecmd->duplex == DUPLEX_HALF)
3472 setting = SUPPORTED_1000baseT_Half;
3473 else
3474 return -EINVAL;
3475 break;
3476 case SPEED_100:
3477 if (ecmd->duplex == DUPLEX_FULL)
3478 setting = SUPPORTED_100baseT_Full;
3479 else if (ecmd->duplex == DUPLEX_HALF)
3480 setting = SUPPORTED_100baseT_Half;
3481 else
3482 return -EINVAL;
3483 break;
3484
3485 case SPEED_10:
3486 if (ecmd->duplex == DUPLEX_FULL)
3487 setting = SUPPORTED_10baseT_Full;
3488 else if (ecmd->duplex == DUPLEX_HALF)
3489 setting = SUPPORTED_10baseT_Half;
3490 else
3491 return -EINVAL;
3492 break;
3493 default:
3494 return -EINVAL;
3495 }
3496
3497 if ((setting & supported) == 0)
3498 return -EINVAL;
3499
3500 sky2->speed = ecmd->speed;
3501 sky2->duplex = ecmd->duplex;
0ea065e5 3502 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3503 }
3504
cd28ab6a
SH		 3505 sky2->advertising = ecmd->advertising;
3506
d1b139c0 3507 if (netif_running(dev)) {
1b537565 3508 sky2_phy_reinit(sky2);
d1b139c0
SH		 3509 sky2_set_multicast(dev);
3510 }
cd28ab6a
SH		 3511
3512 return 0;
3513}
3514
3515static void sky2_get_drvinfo(struct net_device *dev,
3516 struct ethtool_drvinfo *info)
3517{
3518 struct sky2_port *sky2 = netdev_priv(dev);
3519
3520 strcpy(info->driver, DRV_NAME);
3521 strcpy(info->version, DRV_VERSION);
3522 strcpy(info->fw_version, "N/A");
3523 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3524}
3525
3526static const struct sky2_stat {
793b883e
SH		 3527 char name[ETH_GSTRING_LEN];
3528 u16 offset;
cd28ab6a
SH		 3529} sky2_stats[] = {
3530 { "tx_bytes", GM_TXO_OK_HI },
3531 { "rx_bytes", GM_RXO_OK_HI },
3532 { "tx_broadcast", GM_TXF_BC_OK },
3533 { "rx_broadcast", GM_RXF_BC_OK },
3534 { "tx_multicast", GM_TXF_MC_OK },
3535 { "rx_multicast", GM_RXF_MC_OK },
3536 { "tx_unicast", GM_TXF_UC_OK },
3537 { "rx_unicast", GM_RXF_UC_OK },
3538 { "tx_mac_pause", GM_TXF_MPAUSE },
3539 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3540 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3541 { "late_collision",GM_TXF_LAT_COL },
3542 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3543 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3544 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3545
d2604540 3546 { "rx_short", GM_RXF_SHT },
cd28ab6a 3547 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3548 { "rx_64_byte_packets", GM_RXF_64B },
3549 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3550 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3551 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3552 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3553 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3554 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3555 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3556 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3557 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3558 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3559
3560 { "tx_64_byte_packets", GM_TXF_64B },
3561 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3562 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3563 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3564 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3565 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3566 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3567 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3568};
3569
cd28ab6a
SH		 3570static u32 sky2_get_rx_csum(struct net_device *dev)
3571{
3572 struct sky2_port *sky2 = netdev_priv(dev);
3573
0ea065e5 3574 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3575}
3576
3577static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3578{
3579 struct sky2_port *sky2 = netdev_priv(dev);
3580
0ea065e5
SH		 3581 if (data)
3582 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3583 else
3584 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3585
cd28ab6a
SH		 3586 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3587 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3588
3589 return 0;
3590}
3591
3592static u32 sky2_get_msglevel(struct net_device *netdev)
3593{
3594 struct sky2_port *sky2 = netdev_priv(netdev);
3595 return sky2->msg_enable;
3596}
3597
9a7ae0a9
SH		 3598static int sky2_nway_reset(struct net_device *dev)
3599{
3600 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3601
0ea065e5 3602 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3603 return -EINVAL;
3604
1b537565 3605 sky2_phy_reinit(sky2);
d1b139c0 3606 sky2_set_multicast(dev);
9a7ae0a9
SH		 3607
3608 return 0;
3609}
3610
793b883e 3611static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3612{
3613 struct sky2_hw *hw = sky2->hw;
3614 unsigned port = sky2->port;
3615 int i;
3616
3617 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3618 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3619 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3620 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3621
793b883e 3622 for (i = 2; i < count; i++)
cd28ab6a
SH		 3623 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3624}
3625
cd28ab6a
SH		 3626static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3627{
3628 struct sky2_port *sky2 = netdev_priv(netdev);
3629 sky2->msg_enable = value;
3630}
3631
b9f2c044 3632static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3633{
b9f2c044
JG		 3634 switch (sset) {
3635 case ETH_SS_STATS:
3636 return ARRAY_SIZE(sky2_stats);
3637 default:
3638 return -EOPNOTSUPP;
3639 }
cd28ab6a
SH		 3640}
3641
3642static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3643 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3644{
3645 struct sky2_port *sky2 = netdev_priv(dev);
3646
793b883e 3647 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3648}
3649
793b883e 3650static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3651{
3652 int i;
3653
3654 switch (stringset) {
3655 case ETH_SS_STATS:
3656 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3657 memcpy(data + i * ETH_GSTRING_LEN,
3658 sky2_stats[i].name, ETH_GSTRING_LEN);
3659 break;
3660 }
3661}
3662
cd28ab6a
SH		 3663static int sky2_set_mac_address(struct net_device *dev, void *p)
3664{
3665 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3666 struct sky2_hw *hw = sky2->hw;
3667 unsigned port = sky2->port;
3668 const struct sockaddr *addr = p;
cd28ab6a
SH		 3669
3670 if (!is_valid_ether_addr(addr->sa_data))
3671 return -EADDRNOTAVAIL;
3672
cd28ab6a 3673 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3674 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3675 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3676 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3677 dev->dev_addr, ETH_ALEN);
1b537565 3678
a8ab1ec0
SH		 3679 /* virtual address for data */
3680 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3681
3682 /* physical address: used for pause frames */
3683 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3684
3685 return 0;
cd28ab6a
SH		 3686}
3687
060b946c 3688static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
a052b52f
SH		 3689{
3690 u32 bit;
3691
3692 bit = ether_crc(ETH_ALEN, addr) & 63;
3693 filter[bit >> 3] |= 1 << (bit & 7);
3694}
3695
cd28ab6a
SH		 3696static void sky2_set_multicast(struct net_device *dev)
3697{
3698 struct sky2_port *sky2 = netdev_priv(dev);
3699 struct sky2_hw *hw = sky2->hw;
3700 unsigned port = sky2->port;
22bedad3 3701 struct netdev_hw_addr *ha;
cd28ab6a
SH		 3702 u16 reg;
3703 u8 filter[8];
a052b52f
SH		 3704 int rx_pause;
3705 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3706
a052b52f 3707 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3708 memset(filter, 0, sizeof(filter));
3709
3710 reg = gma_read16(hw, port, GM_RX_CTRL);
3711 reg |= GM_RXCR_UCF_ENA;
3712
d571b694 3713 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3714 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3715 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3716 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3717 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3718 reg &= ~GM_RXCR_MCF_ENA;
3719 else {
cd28ab6a
SH		 3720 reg |= GM_RXCR_MCF_ENA;
3721
a052b52f
SH		 3722 if (rx_pause)
3723 sky2_add_filter(filter, pause_mc_addr);
3724
22bedad3
JP		 3725 netdev_for_each_mc_addr(ha, dev)
3726 sky2_add_filter(filter, ha->addr);
cd28ab6a
SH		 3727 }
3728
cd28ab6a 3729 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3730 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3731 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3732 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3733 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3734 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3735 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3736 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3737
3738 gma_write16(hw, port, GM_RX_CTRL, reg);
3739}
3740
3741/* Can have one global because blinking is controlled by
3742 * ethtool and that is always under RTNL mutex
3743 */
a84d0a3d 3744static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3745{
a84d0a3d
SH		 3746 struct sky2_hw *hw = sky2->hw;
3747 unsigned port = sky2->port;
793b883e 3748
a84d0a3d
SH		 3749 spin_lock_bh(&sky2->phy_lock);
3750 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3751 hw->chip_id == CHIP_ID_YUKON_EX ||
3752 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3753 u16 pg;
793b883e
SH		 3754 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3755 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3756
a84d0a3d
SH		 3757 switch (mode) {
3758 case MO_LED_OFF:
3759 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3760 PHY_M_LEDC_LOS_CTRL(8) |
3761 PHY_M_LEDC_INIT_CTRL(8) |
3762 PHY_M_LEDC_STA1_CTRL(8) |
3763 PHY_M_LEDC_STA0_CTRL(8));
3764 break;
3765 case MO_LED_ON:
3766 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3767 PHY_M_LEDC_LOS_CTRL(9) |
3768 PHY_M_LEDC_INIT_CTRL(9) |
3769 PHY_M_LEDC_STA1_CTRL(9) |
3770 PHY_M_LEDC_STA0_CTRL(9));
3771 break;
3772 case MO_LED_BLINK:
3773 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3774 PHY_M_LEDC_LOS_CTRL(0xa) |
3775 PHY_M_LEDC_INIT_CTRL(0xa) |
3776 PHY_M_LEDC_STA1_CTRL(0xa) |
3777 PHY_M_LEDC_STA0_CTRL(0xa));
3778 break;
3779 case MO_LED_NORM:
3780 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3781 PHY_M_LEDC_LOS_CTRL(1) |
3782 PHY_M_LEDC_INIT_CTRL(8) |
3783 PHY_M_LEDC_STA1_CTRL(7) |
3784 PHY_M_LEDC_STA0_CTRL(7));
3785 }
793b883e 3786
a84d0a3d
SH		 3787 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3788 } else
7d2e3cb7 3789 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3790 PHY_M_LED_MO_DUP(mode) |
3791 PHY_M_LED_MO_10(mode) |
3792 PHY_M_LED_MO_100(mode) |
3793 PHY_M_LED_MO_1000(mode) |
3794 PHY_M_LED_MO_RX(mode) |
3795 PHY_M_LED_MO_TX(mode));
3796
3797 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3798}
3799
3800/* blink LED's for finding board */
3801static int sky2_phys_id(struct net_device *dev, u32 data)
3802{
3803 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3804 unsigned int i;
cd28ab6a 3805
a84d0a3d
SH		 3806 if (data == 0)
3807 data = UINT_MAX;
cd28ab6a 3808
a84d0a3d
SH		 3809 for (i = 0; i < data; i++) {
3810 sky2_led(sky2, MO_LED_ON);
3811 if (msleep_interruptible(500))
3812 break;
3813 sky2_led(sky2, MO_LED_OFF);
3814 if (msleep_interruptible(500))
3815 break;
793b883e 3816 }
a84d0a3d 3817 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3818
3819 return 0;
3820}
3821
3822static void sky2_get_pauseparam(struct net_device *dev,
3823 struct ethtool_pauseparam *ecmd)
3824{
3825 struct sky2_port *sky2 = netdev_priv(dev);
3826
16ad91e1
SH		 3827 switch (sky2->flow_mode) {
3828 case FC_NONE:
3829 ecmd->tx_pause = ecmd->rx_pause = 0;
3830 break;
3831 case FC_TX:
3832 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3833 break;
3834 case FC_RX:
3835 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3836 break;
3837 case FC_BOTH:
3838 ecmd->tx_pause = ecmd->rx_pause = 1;
3839 }
3840
0ea065e5
SH		 3841 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3842 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3843}
3844
3845static int sky2_set_pauseparam(struct net_device *dev,
3846 struct ethtool_pauseparam *ecmd)
3847{
3848 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3849
0ea065e5
SH		 3850 if (ecmd->autoneg == AUTONEG_ENABLE)
3851 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3852 else
3853 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3854
16ad91e1 3855 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3856
16ad91e1
SH		 3857 if (netif_running(dev))
3858 sky2_phy_reinit(sky2);
cd28ab6a 3859
2eaba1a2 3860 return 0;
cd28ab6a
SH		 3861}
3862
fb17358f
SH		 3863static int sky2_get_coalesce(struct net_device *dev,
3864 struct ethtool_coalesce *ecmd)
3865{
3866 struct sky2_port *sky2 = netdev_priv(dev);
3867 struct sky2_hw *hw = sky2->hw;
3868
3869 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3870 ecmd->tx_coalesce_usecs = 0;
3871 else {
3872 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3873 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3874 }
3875 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3876
3877 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3878 ecmd->rx_coalesce_usecs = 0;
3879 else {
3880 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3881 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3882 }
3883 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3884
3885 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3886 ecmd->rx_coalesce_usecs_irq = 0;
3887 else {
3888 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3889 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3890 }
3891
3892 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3893
3894 return 0;
3895}
3896
3897/* Note: this affect both ports */
3898static int sky2_set_coalesce(struct net_device *dev,
3899 struct ethtool_coalesce *ecmd)
3900{
3901 struct sky2_port *sky2 = netdev_priv(dev);
3902 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3903 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3904
77b3d6a2
SH		 3905 if (ecmd->tx_coalesce_usecs > tmax ||
3906 ecmd->rx_coalesce_usecs > tmax ||
3907 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3908 return -EINVAL;
3909
ee5f68fe 3910 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3911 return -EINVAL;
ff81fbbe 3912 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3913 return -EINVAL;
060b946c 3914 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
fb17358f
SH		 3915 return -EINVAL;
3916
3917 if (ecmd->tx_coalesce_usecs == 0)
3918 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3919 else {
3920 sky2_write32(hw, STAT_TX_TIMER_INI,
3921 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3922 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3923 }
3924 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3925
3926 if (ecmd->rx_coalesce_usecs == 0)
3927 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3928 else {
3929 sky2_write32(hw, STAT_LEV_TIMER_INI,
3930 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3931 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3932 }
3933 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3934
3935 if (ecmd->rx_coalesce_usecs_irq == 0)
3936 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3937 else {
d28d4870 3938 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3939 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3940 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3941 }
3942 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3943 return 0;
3944}
3945
793b883e
SH		 3946static void sky2_get_ringparam(struct net_device *dev,
3947 struct ethtool_ringparam *ering)
3948{
3949 struct sky2_port *sky2 = netdev_priv(dev);
3950
3951 ering->rx_max_pending = RX_MAX_PENDING;
3952 ering->rx_mini_max_pending = 0;
3953 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3954 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3955
3956 ering->rx_pending = sky2->rx_pending;
3957 ering->rx_mini_pending = 0;
3958 ering->rx_jumbo_pending = 0;
3959 ering->tx_pending = sky2->tx_pending;
3960}
3961
3962static int sky2_set_ringparam(struct net_device *dev,
3963 struct ethtool_ringparam *ering)
3964{
3965 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3966
3967 if (ering->rx_pending > RX_MAX_PENDING ||
3968 ering->rx_pending < 8 ||
ee5f68fe
SH		 3969 ering->tx_pending < TX_MIN_PENDING ||
3970 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3971 return -EINVAL;
3972
af18d8b8 3973 sky2_detach(dev);
793b883e
SH		 3974
3975 sky2->rx_pending = ering->rx_pending;
3976 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3977 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3978
af18d8b8 3979 return sky2_reattach(dev);
793b883e
SH		 3980}
3981
793b883e
SH		 3982static int sky2_get_regs_len(struct net_device *dev)
3983{
6e4cbb34 3984 return 0x4000;
793b883e
SH		 3985}
3986
c32bbff8
MM		 3987static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3988{
3989 /* This complicated switch statement is to make sure and
3990 * only access regions that are unreserved.
3991 * Some blocks are only valid on dual port cards.
3992 */
3993 switch (b) {
3994 /* second port */
3995 case 5: /* Tx Arbiter 2 */
3996 case 9: /* RX2 */
3997 case 14 ... 15: /* TX2 */
3998 case 17: case 19: /* Ram Buffer 2 */
3999 case 22 ... 23: /* Tx Ram Buffer 2 */
4000 case 25: /* Rx MAC Fifo 1 */
4001 case 27: /* Tx MAC Fifo 2 */
4002 case 31: /* GPHY 2 */
4003 case 40 ... 47: /* Pattern Ram 2 */
4004 case 52: case 54: /* TCP Segmentation 2 */
4005 case 112 ... 116: /* GMAC 2 */
4006 return hw->ports > 1;
4007
4008 case 0: /* Control */
4009 case 2: /* Mac address */
4010 case 4: /* Tx Arbiter 1 */
4011 case 7: /* PCI express reg */
4012 case 8: /* RX1 */
4013 case 12 ... 13: /* TX1 */
4014 case 16: case 18:/* Rx Ram Buffer 1 */
4015 case 20 ... 21: /* Tx Ram Buffer 1 */
4016 case 24: /* Rx MAC Fifo 1 */
4017 case 26: /* Tx MAC Fifo 1 */
4018 case 28 ... 29: /* Descriptor and status unit */
4019 case 30: /* GPHY 1*/
4020 case 32 ... 39: /* Pattern Ram 1 */
4021 case 48: case 50: /* TCP Segmentation 1 */
4022 case 56 ... 60: /* PCI space */
4023 case 80 ... 84: /* GMAC 1 */
4024 return 1;
4025
4026 default:
4027 return 0;
4028 }
4029}
4030
793b883e
SH		 4031/*
4032 * Returns copy of control register region
3ead5db7 4033 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 4034 */
4035static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4036 void *p)
4037{
4038 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 4039 const void __iomem *io = sky2->hw->regs;
295b54c4 4040 unsigned int b;
793b883e
SH		 4041
4042 regs->version = 1;
793b883e 4043
295b54c4 4044 for (b = 0; b < 128; b++) {
c32bbff8
MM		 4045 /* skip poisonous diagnostic ram region in block 3 */
4046 if (b == 3)
295b54c4 4047 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 4048 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 4049 memcpy_fromio(p, io, 128);
c32bbff8 4050 else
295b54c4 4051 memset(p, 0, 128);
3ead5db7 4052
295b54c4
SH		 4053 p += 128;
4054 io += 128;
4055 }
793b883e 4056}
cd28ab6a 4057
b628ed98
SH		 4058/* In order to do Jumbo packets on these chips, need to turn off the
4059 * transmit store/forward. Therefore checksum offload won't work.
4060 */
4061static int no_tx_offload(struct net_device *dev)
4062{
4063 const struct sky2_port *sky2 = netdev_priv(dev);
4064 const struct sky2_hw *hw = sky2->hw;
4065
69161611 4066 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 4067}
4068
4069static int sky2_set_tx_csum(struct net_device *dev, u32 data)
4070{
4071 if (data && no_tx_offload(dev))
4072 return -EINVAL;
4073
4074 return ethtool_op_set_tx_csum(dev, data);
4075}
4076
4077
4078static int sky2_set_tso(struct net_device *dev, u32 data)
4079{
4080 if (data && no_tx_offload(dev))
4081 return -EINVAL;
4082
4083 return ethtool_op_set_tso(dev, data);
4084}
4085
f4331a6d
SH		 4086static int sky2_get_eeprom_len(struct net_device *dev)
4087{
4088 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4089 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4090 u16 reg2;
4091
b32f40c4 4092 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4093 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4094}
4095
1413235c 4096static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4097{
1413235c 4098 unsigned long start = jiffies;
f4331a6d 4099
1413235c
SH		 4100 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4101 /* Can take up to 10.6 ms for write */
4102 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4103 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4104 return -ETIMEDOUT;
4105 }
4106 mdelay(1);
4107 }
167f53d0 4108
1413235c
SH		 4109 return 0;
4110}
167f53d0 4111
1413235c
SH		 4112static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4113 u16 offset, size_t length)
4114{
4115 int rc = 0;
4116
4117 while (length > 0) {
4118 u32 val;
4119
4120 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4121 rc = sky2_vpd_wait(hw, cap, 0);
4122 if (rc)
4123 break;
4124
4125 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4126
4127 memcpy(data, &val, min(sizeof(val), length));
4128 offset += sizeof(u32);
4129 data += sizeof(u32);
4130 length -= sizeof(u32);
4131 }
4132
4133 return rc;
f4331a6d
SH		 4134}
4135
1413235c
SH		 4136static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4137 u16 offset, unsigned int length)
f4331a6d 4138{
1413235c
SH		 4139 unsigned int i;
4140 int rc = 0;
4141
4142 for (i = 0; i < length; i += sizeof(u32)) {
4143 u32 val = *(u32 *)(data + i);
4144
4145 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4146 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4147
4148 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4149 if (rc)
4150 break;
4151 }
4152 return rc;
f4331a6d
SH		 4153}
4154
4155static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4156 u8 *data)
4157{
4158 struct sky2_port *sky2 = netdev_priv(dev);
4159 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4160
4161 if (!cap)
4162 return -EINVAL;
4163
4164 eeprom->magic = SKY2_EEPROM_MAGIC;
4165
1413235c 4166 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4167}
4168
4169static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4170 u8 *data)
4171{
4172 struct sky2_port *sky2 = netdev_priv(dev);
4173 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4174
4175 if (!cap)
4176 return -EINVAL;
4177
4178 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4179 return -EINVAL;
4180
1413235c
SH		 4181 /* Partial writes not supported */
4182 if ((eeprom->offset & 3) || (eeprom->len & 3))
4183 return -EINVAL;
f4331a6d 4184
1413235c 4185 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4186}
4187
bf73130d
SH		 4188static int sky2_set_flags(struct net_device *dev, u32 data)
4189{
4190 struct sky2_port *sky2 = netdev_priv(dev);
1437ce39
BH		 4191 u32 supported =
4192 (sky2->hw->flags & SKY2_HW_RSS_BROKEN) ? 0 : ETH_FLAG_RXHASH;
4193 int rc;
bf73130d 4194
1437ce39
BH		 4195 rc = ethtool_op_set_flags(dev, data, supported);
4196 if (rc)
4197 return rc;
bf73130d
SH		 4198
4199 rx_set_rss(dev);
4200
4201 return 0;
4202}
f4331a6d 4203
7282d491 4204static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4205 .get_settings = sky2_get_settings,
4206 .set_settings = sky2_set_settings,
4207 .get_drvinfo = sky2_get_drvinfo,
4208 .get_wol = sky2_get_wol,
4209 .set_wol = sky2_set_wol,
4210 .get_msglevel = sky2_get_msglevel,
4211 .set_msglevel = sky2_set_msglevel,
4212 .nway_reset = sky2_nway_reset,
4213 .get_regs_len = sky2_get_regs_len,
4214 .get_regs = sky2_get_regs,
4215 .get_link = ethtool_op_get_link,
4216 .get_eeprom_len = sky2_get_eeprom_len,
4217 .get_eeprom = sky2_get_eeprom,
4218 .set_eeprom = sky2_set_eeprom,
f4331a6d 4219 .set_sg = ethtool_op_set_sg,
f4331a6d 4220 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4221 .set_tso = sky2_set_tso,
4222 .get_rx_csum = sky2_get_rx_csum,
4223 .set_rx_csum = sky2_set_rx_csum,
4224 .get_strings = sky2_get_strings,
4225 .get_coalesce = sky2_get_coalesce,
4226 .set_coalesce = sky2_set_coalesce,
4227 .get_ringparam = sky2_get_ringparam,
4228 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4229 .get_pauseparam = sky2_get_pauseparam,
4230 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4231 .phys_id = sky2_phys_id,
b9f2c044 4232 .get_sset_count = sky2_get_sset_count,
cd28ab6a 4233 .get_ethtool_stats = sky2_get_ethtool_stats,
bf73130d 4234 .set_flags = sky2_set_flags,
cd28ab6a
SH		 4235};
4236
3cf26753
SH		 4237#ifdef CONFIG_SKY2_DEBUG
4238
4239static struct dentry *sky2_debug;
4240
e4c2abe2
SH		 4241
4242/*
4243 * Read and parse the first part of Vital Product Data
4244 */
4245#define VPD_SIZE 128
4246#define VPD_MAGIC 0x82
4247
4248static const struct vpd_tag {
4249 char tag[2];
4250 char *label;
4251} vpd_tags[] = {
4252 { "PN", "Part Number" },
4253 { "EC", "Engineering Level" },
4254 { "MN", "Manufacturer" },
4255 { "SN", "Serial Number" },
4256 { "YA", "Asset Tag" },
4257 { "VL", "First Error Log Message" },
4258 { "VF", "Second Error Log Message" },
4259 { "VB", "Boot Agent ROM Configuration" },
4260 { "VE", "EFI UNDI Configuration" },
4261};
4262
4263static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4264{
4265 size_t vpd_size;
4266 loff_t offs;
4267 u8 len;
4268 unsigned char *buf;
4269 u16 reg2;
4270
4271 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4272 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4273
4274 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4275 buf = kmalloc(vpd_size, GFP_KERNEL);
4276 if (!buf) {
4277 seq_puts(seq, "no memory!\n");
4278 return;
4279 }
4280
4281 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4282 seq_puts(seq, "VPD read failed\n");
4283 goto out;
4284 }
4285
4286 if (buf[0] != VPD_MAGIC) {
4287 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4288 goto out;
4289 }
4290 len = buf[1];
4291 if (len == 0 || len > vpd_size - 4) {
4292 seq_printf(seq, "Invalid id length: %d\n", len);
4293 goto out;
4294 }
4295
4296 seq_printf(seq, "%.*s\n", len, buf + 3);
4297 offs = len + 3;
4298
4299 while (offs < vpd_size - 4) {
4300 int i;
4301
4302 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4303 break;
4304 len = buf[offs + 2];
4305 if (offs + len + 3 >= vpd_size)
4306 break;
4307
4308 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4309 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4310 seq_printf(seq, " %s: %.*s\n",
4311 vpd_tags[i].label, len, buf + offs + 3);
4312 break;
4313 }
4314 }
4315 offs += len + 3;
4316 }
4317out:
4318 kfree(buf);
4319}
4320
3cf26753
SH		 4321static int sky2_debug_show(struct seq_file *seq, void *v)
4322{
4323 struct net_device *dev = seq->private;
4324 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4325 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4326 unsigned port = sky2->port;
4327 unsigned idx, last;
4328 int sop;
4329
e4c2abe2 4330 sky2_show_vpd(seq, hw);
3cf26753 4331
e4c2abe2 4332 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4333 sky2_read32(hw, B0_ISRC),
4334 sky2_read32(hw, B0_IMSK),
4335 sky2_read32(hw, B0_Y2_SP_ICR));
4336
e4c2abe2
SH		 4337 if (!netif_running(dev)) {
4338 seq_printf(seq, "network not running\n");
4339 return 0;
4340 }
4341
bea3348e 4342 napi_disable(&hw->napi);
3cf26753
SH		 4343 last = sky2_read16(hw, STAT_PUT_IDX);
4344
efe91932 4345 seq_printf(seq, "Status ring %u\n", hw->st_size);
3cf26753
SH		 4346 if (hw->st_idx == last)
4347 seq_puts(seq, "Status ring (empty)\n");
4348 else {
4349 seq_puts(seq, "Status ring\n");
efe91932 4350 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4351 idx = RING_NEXT(idx, hw->st_size)) {
3cf26753
SH		 4352 const struct sky2_status_le *le = hw->st_le + idx;
4353 seq_printf(seq, "[%d] %#x %d %#x\n",
4354 idx, le->opcode, le->length, le->status);
4355 }
4356 seq_puts(seq, "\n");
4357 }
4358
4359 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4360 sky2->tx_cons, sky2->tx_prod,
4361 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4362 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4363
4364 /* Dump contents of tx ring */
4365 sop = 1;
ee5f68fe
SH		 4366 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4367 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4368 const struct sky2_tx_le *le = sky2->tx_le + idx;
4369 u32 a = le32_to_cpu(le->addr);
4370
4371 if (sop)
4372 seq_printf(seq, "%u:", idx);
4373 sop = 0;
4374
060b946c 4375 switch (le->opcode & ~HW_OWNER) {
3cf26753
SH		 4376 case OP_ADDR64:
4377 seq_printf(seq, " %#x:", a);
4378 break;
4379 case OP_LRGLEN:
4380 seq_printf(seq, " mtu=%d", a);
4381 break;
4382 case OP_VLAN:
4383 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4384 break;
4385 case OP_TCPLISW:
4386 seq_printf(seq, " csum=%#x", a);
4387 break;
4388 case OP_LARGESEND:
4389 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4390 break;
4391 case OP_PACKET:
4392 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4393 break;
4394 case OP_BUFFER:
4395 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4396 break;
4397 default:
4398 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4399 a, le16_to_cpu(le->length));
4400 }
4401
4402 if (le->ctrl & EOP) {
4403 seq_putc(seq, '\n');
4404 sop = 1;
4405 }
4406 }
4407
4408 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4409 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4410 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4411 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4412
d1d08d12 4413 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4414 napi_enable(&hw->napi);
3cf26753
SH		 4415 return 0;
4416}
4417
4418static int sky2_debug_open(struct inode *inode, struct file *file)
4419{
4420 return single_open(file, sky2_debug_show, inode->i_private);
4421}
4422
4423static const struct file_operations sky2_debug_fops = {
4424 .owner = THIS_MODULE,
4425 .open = sky2_debug_open,
4426 .read = seq_read,
4427 .llseek = seq_lseek,
4428 .release = single_release,
4429};
4430
4431/*
4432 * Use network device events to create/remove/rename
4433 * debugfs file entries
4434 */
4435static int sky2_device_event(struct notifier_block *unused,
4436 unsigned long event, void *ptr)
4437{
4438 struct net_device *dev = ptr;
5b296bc9 4439 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4440
1436b301 4441 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4442 return NOTIFY_DONE;
3cf26753 4443
060b946c 4444 switch (event) {
5b296bc9
SH		 4445 case NETDEV_CHANGENAME:
4446 if (sky2->debugfs) {
4447 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4448 sky2_debug, dev->name);
4449 }
4450 break;
3cf26753 4451
5b296bc9
SH		 4452 case NETDEV_GOING_DOWN:
4453 if (sky2->debugfs) {
ada1db5c 4454 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4455 debugfs_remove(sky2->debugfs);
4456 sky2->debugfs = NULL;
3cf26753 4457 }
5b296bc9
SH		 4458 break;
4459
4460 case NETDEV_UP:
4461 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4462 sky2_debug, dev,
4463 &sky2_debug_fops);
4464 if (IS_ERR(sky2->debugfs))
4465 sky2->debugfs = NULL;
3cf26753
SH		 4466 }
4467
4468 return NOTIFY_DONE;
4469}
4470
4471static struct notifier_block sky2_notifier = {
4472 .notifier_call = sky2_device_event,
4473};
4474
4475
4476static __init void sky2_debug_init(void)
4477{
4478 struct dentry *ent;
4479
4480 ent = debugfs_create_dir("sky2", NULL);
4481 if (!ent || IS_ERR(ent))
4482 return;
4483
4484 sky2_debug = ent;
4485 register_netdevice_notifier(&sky2_notifier);
4486}
4487
4488static __exit void sky2_debug_cleanup(void)
4489{
4490 if (sky2_debug) {
4491 unregister_netdevice_notifier(&sky2_notifier);
4492 debugfs_remove(sky2_debug);
4493 sky2_debug = NULL;
4494 }
4495}
4496
4497#else
4498#define sky2_debug_init()
4499#define sky2_debug_cleanup()
4500#endif
4501
1436b301
SH		 4502/* Two copies of network device operations to handle special case of
4503 not allowing netpoll on second port */
4504static const struct net_device_ops sky2_netdev_ops[2] = {
4505 {
4506 .ndo_open = sky2_up,
4507 .ndo_stop = sky2_down,
00829823 4508 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4509 .ndo_do_ioctl = sky2_ioctl,
4510 .ndo_validate_addr = eth_validate_addr,
4511 .ndo_set_mac_address = sky2_set_mac_address,
4512 .ndo_set_multicast_list = sky2_set_multicast,
4513 .ndo_change_mtu = sky2_change_mtu,
4514 .ndo_tx_timeout = sky2_tx_timeout,
4515#ifdef SKY2_VLAN_TAG_USED
4516 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4517#endif
4518#ifdef CONFIG_NET_POLL_CONTROLLER
4519 .ndo_poll_controller = sky2_netpoll,
4520#endif
4521 },
4522 {
4523 .ndo_open = sky2_up,
4524 .ndo_stop = sky2_down,
00829823 4525 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4526 .ndo_do_ioctl = sky2_ioctl,
4527 .ndo_validate_addr = eth_validate_addr,
4528 .ndo_set_mac_address = sky2_set_mac_address,
4529 .ndo_set_multicast_list = sky2_set_multicast,
4530 .ndo_change_mtu = sky2_change_mtu,
4531 .ndo_tx_timeout = sky2_tx_timeout,
4532#ifdef SKY2_VLAN_TAG_USED
4533 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4534#endif
4535 },
4536};
3cf26753 4537
cd28ab6a
SH		 4538/* Initialize network device */
4539static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4540 unsigned port,
be63a21c 4541 int highmem, int wol)
cd28ab6a
SH		 4542{
4543 struct sky2_port *sky2;
4544 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4545
4546 if (!dev) {
898eb71c 4547 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4548 return NULL;
4549 }
4550
cd28ab6a 4551 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4552 dev->irq = hw->pdev->irq;
cd28ab6a 4553 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4554 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4555 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4556
4557 sky2 = netdev_priv(dev);
4558 sky2->netdev = dev;
4559 sky2->hw = hw;
4560 sky2->msg_enable = netif_msg_init(debug, default_msg);
4561
cd28ab6a 4562 /* Auto speed and flow control */
0ea065e5
SH		 4563 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4564 if (hw->chip_id != CHIP_ID_YUKON_XL)
4565 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4566
16ad91e1
SH		 4567 sky2->flow_mode = FC_BOTH;
4568
cd28ab6a
SH		 4569 sky2->duplex = -1;
4570 sky2->speed = -1;
4571 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4572 sky2->wol = wol;
75d070c5 4573
e07b1aa8 4574 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4575
793b883e 4576 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4577 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4578 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4579
4580 hw->dev[port] = dev;
4581
4582 sky2->port = port;
4583
4a50a876 4584 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4585 if (highmem)
4586 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4587
bf73130d
SH		 4588 /* Enable receive hashing unless hardware is known broken */
4589 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4590 dev->features |= NETIF_F_RXHASH;
4591
d1f13708 4592#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4593 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4594 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4595 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4596 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4597 }
d1f13708
SH		 4598#endif
4599
cd28ab6a 4600 /* read the mac address */
793b883e 4601 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4602 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4603
cd28ab6a
SH		 4604 return dev;
4605}
4606
28bd181a 4607static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4608{
4609 const struct sky2_port *sky2 = netdev_priv(dev);
4610
6c35abae 4611 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4612}
4613
fb2690a9 4614/* Handle software interrupt used during MSI test */
7d12e780 4615static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4616{
4617 struct sky2_hw *hw = dev_id;
4618 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4619
4620 if (status == 0)
4621 return IRQ_NONE;
4622
4623 if (status & Y2_IS_IRQ_SW) {
ea76e635 4624 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4625 wake_up(&hw->msi_wait);
4626 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4627 }
4628 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4629
4630 return IRQ_HANDLED;
4631}
4632
4633/* Test interrupt path by forcing a a software IRQ */
4634static int __devinit sky2_test_msi(struct sky2_hw *hw)
4635{
4636 struct pci_dev *pdev = hw->pdev;
4637 int err;
4638
060b946c 4639 init_waitqueue_head(&hw->msi_wait);
bb507fe1 4640
fb2690a9
SH		 4641 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4642
b0a20ded 4643 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4644 if (err) {
b02a9258 4645 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4646 return err;
4647 }
4648
fb2690a9 4649 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4650 sky2_read8(hw, B0_CTST);
fb2690a9 4651
ea76e635 4652 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4653
ea76e635 4654 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4655 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4656 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4657 "switching to INTx mode.\n");
fb2690a9
SH		 4658
4659 err = -EOPNOTSUPP;
4660 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4661 }
4662
4663 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4664 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4665
4666 free_irq(pdev->irq, hw);
4667
4668 return err;
4669}
4670
c7127a34
SH		 4671/* This driver supports yukon2 chipset only */
4672static const char *sky2_name(u8 chipid, char *buf, int sz)
4673{
4674 const char *name[] = {
4675 "XL", /* 0xb3 */
4676 "EC Ultra", /* 0xb4 */
4677 "Extreme", /* 0xb5 */
4678 "EC", /* 0xb6 */
4679 "FE", /* 0xb7 */
4680 "FE+", /* 0xb8 */
4681 "Supreme", /* 0xb9 */
0ce8b98d 4682 "UL 2", /* 0xba */
0f5aac70
SH		 4683 "Unknown", /* 0xbb */
4684 "Optima", /* 0xbc */
c7127a34
SH		 4685 };
4686
dae3a511 4687 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4688 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4689 else
4690 snprintf(buf, sz, "(chip %#x)", chipid);
4691 return buf;
4692}
4693
cd28ab6a
SH		 4694static int __devinit sky2_probe(struct pci_dev *pdev,
4695 const struct pci_device_id *ent)
4696{
7f60c64b 4697 struct net_device *dev;
cd28ab6a 4698 struct sky2_hw *hw;
be63a21c 4699 int err, using_dac = 0, wol_default;
3834507d 4700 u32 reg;
c7127a34 4701 char buf1[16];
cd28ab6a 4702
793b883e
SH		 4703 err = pci_enable_device(pdev);
4704 if (err) {
b02a9258 4705 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4706 goto err_out;
4707 }
4708
6cc90a5a
SH		 4709 /* Get configuration information
4710 * Note: only regular PCI config access once to test for HW issues
4711 * other PCI access through shared memory for speed and to
4712 * avoid MMCONFIG problems.
4713 */
4714 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4715 if (err) {
4716 dev_err(&pdev->dev, "PCI read config failed\n");
4717 goto err_out;
4718 }
4719
4720 if (~reg == 0) {
4721 dev_err(&pdev->dev, "PCI configuration read error\n");
4722 goto err_out;
4723 }
4724
793b883e
SH		 4725 err = pci_request_regions(pdev, DRV_NAME);
4726 if (err) {
b02a9258 4727 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4728 goto err_out_disable;
cd28ab6a
SH		 4729 }
4730
4731 pci_set_master(pdev);
4732
d1f3d4dd 4733 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4734 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4735 using_dac = 1;
6a35528a 4736 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4737 if (err < 0) {
b02a9258
SH		 4738 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4739 "for consistent allocations\n");
d1f3d4dd
SH		 4740 goto err_out_free_regions;
4741 }
d1f3d4dd 4742 } else {
284901a9 4743 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4744 if (err) {
b02a9258 4745 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4746 goto err_out_free_regions;
4747 }
4748 }
d1f3d4dd 4749
3834507d
SH		 4750
4751#ifdef __BIG_ENDIAN
4752 /* The sk98lin vendor driver uses hardware byte swapping but
4753 * this driver uses software swapping.
4754 */
4755 reg &= ~PCI_REV_DESC;
060b946c 4756 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3834507d
SH		 4757 if (err) {
4758 dev_err(&pdev->dev, "PCI write config failed\n");
4759 goto err_out_free_regions;
4760 }
4761#endif
4762
9d731d77 4763 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4764
cd28ab6a 4765 err = -ENOMEM;
66466797
SH		 4766
4767 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4768 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4769 if (!hw) {
b02a9258 4770 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4771 goto err_out_free_regions;
4772 }
4773
cd28ab6a 4774 hw->pdev = pdev;
66466797 4775 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4776
4777 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4778 if (!hw->regs) {
b02a9258 4779 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4780 goto err_out_free_hw;
4781 }
4782
e3173832 4783 err = sky2_init(hw);
cd28ab6a 4784 if (err)
793b883e 4785 goto err_out_iounmap;
cd28ab6a 4786
efe91932 4787 /* ring for status responses */
bf73130d 4788 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
efe91932 4789 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4790 &hw->st_dma);
4791 if (!hw->st_le)
4792 goto err_out_reset;
4793
c844d483
SH		 4794 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4795 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4796
e3173832
SH		 4797 sky2_reset(hw);
4798
be63a21c 4799 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4800 if (!dev) {
4801 err = -ENOMEM;
cd28ab6a 4802 goto err_out_free_pci;
7f60c64b 4803 }
cd28ab6a 4804
9fa1b1f3
SH		 4805 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4806 err = sky2_test_msi(hw);
4807 if (err == -EOPNOTSUPP)
4808 pci_disable_msi(pdev);
4809 else if (err)
4810 goto err_out_free_netdev;
4811 }
4812
793b883e
SH		 4813 err = register_netdev(dev);
4814 if (err) {
b02a9258 4815 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4816 goto err_out_free_netdev;
4817 }
4818
33cb7d33
BP		 4819 netif_carrier_off(dev);
4820
6de16237
SH		 4821 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4822
ea76e635
SH		 4823 err = request_irq(pdev->irq, sky2_intr,
4824 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4825 hw->irq_name, hw);
9fa1b1f3 4826 if (err) {
b02a9258 4827 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4828 goto err_out_unregister;
4829 }
4830 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4831 napi_enable(&hw->napi);
9fa1b1f3 4832
cd28ab6a
SH		 4833 sky2_show_addr(dev);
4834
7f60c64b 4835 if (hw->ports > 1) {
4836 struct net_device *dev1;
4837
ca519274 4838 err = -ENOMEM;
be63a21c 4839 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4840 if (dev1 && (err = register_netdev(dev1)) == 0)
4841 sky2_show_addr(dev1);
4842 else {
b02a9258
SH		 4843 dev_warn(&pdev->dev,
4844 "register of second port failed (%d)\n", err);
cd28ab6a 4845 hw->dev[1] = NULL;
ca519274
SH		 4846 hw->ports = 1;
4847 if (dev1)
4848 free_netdev(dev1);
4849 }
cd28ab6a
SH		 4850 }
4851
32c2c300 4852 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4853 INIT_WORK(&hw->restart_work, sky2_restart);
4854
793b883e 4855 pci_set_drvdata(pdev, hw);
1ae861e6 4856 pdev->d3_delay = 150;
793b883e 4857
cd28ab6a
SH		 4858 return 0;
4859
793b883e 4860err_out_unregister:
ea76e635 4861 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4862 pci_disable_msi(pdev);
793b883e 4863 unregister_netdev(dev);
cd28ab6a
SH		 4864err_out_free_netdev:
4865 free_netdev(dev);
cd28ab6a 4866err_out_free_pci:
efe91932 4867 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4868 hw->st_le, hw->st_dma);
4869err_out_reset:
793b883e 4870 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4871err_out_iounmap:
4872 iounmap(hw->regs);
4873err_out_free_hw:
4874 kfree(hw);
4875err_out_free_regions:
4876 pci_release_regions(pdev);
44a1d2e5 4877err_out_disable:
cd28ab6a 4878 pci_disable_device(pdev);
cd28ab6a 4879err_out:
549a68c3 4880 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4881 return err;
4882}
4883
4884static void __devexit sky2_remove(struct pci_dev *pdev)
4885{
793b883e 4886 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4887 int i;
cd28ab6a 4888
793b883e 4889 if (!hw)
cd28ab6a
SH		 4890 return;
4891
32c2c300 4892 del_timer_sync(&hw->watchdog_timer);
6de16237 4893 cancel_work_sync(&hw->restart_work);
d27ed387 4894
b877fe28 4895 for (i = hw->ports-1; i >= 0; --i)
6de16237 4896 unregister_netdev(hw->dev[i]);
81906791 4897
d27ed387 4898 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4899
ae306cca
SH		 4900 sky2_power_aux(hw);
4901
793b883e 4902 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4903 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4904
4905 free_irq(pdev->irq, hw);
ea76e635 4906 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4907 pci_disable_msi(pdev);
efe91932 4908 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4909 hw->st_le, hw->st_dma);
cd28ab6a
SH		 4910 pci_release_regions(pdev);
4911 pci_disable_device(pdev);
793b883e 4912
b877fe28 4913 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4914 free_netdev(hw->dev[i]);
4915
cd28ab6a
SH		 4916 iounmap(hw->regs);
4917 kfree(hw);
5afa0a9c 4918
cd28ab6a
SH		 4919 pci_set_drvdata(pdev, NULL);
4920}
4921
cd28ab6a
SH		 4922static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4923{
793b883e 4924 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4925 int i, wol = 0;
cd28ab6a 4926
549a68c3
SH		 4927 if (!hw)
4928 return 0;
4929
063a0b38
SH		 4930 del_timer_sync(&hw->watchdog_timer);
4931 cancel_work_sync(&hw->restart_work);
4932
19720737 4933 rtnl_lock();
3403aca2
MM		 4934
4935 sky2_all_down(hw);
f05267e7 4936 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4937 struct net_device *dev = hw->dev[i];
e3173832 4938 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4939
e3173832
SH		 4940 if (sky2->wol)
4941 sky2_wol_init(sky2);
4942
4943 wol |= sky2->wol;
cd28ab6a
SH		 4944 }
4945
5f8ae5c5 4946 device_set_wakeup_enable(&pdev->dev, wol != 0);
4947
ae306cca 4948 sky2_power_aux(hw);
19720737 4949 rtnl_unlock();
e3173832 4950
d374c1c1 4951 pci_save_state(pdev);
e3173832 4952 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4953 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4954
2ccc99b7 4955 return 0;
cd28ab6a
SH		 4956}
4957
5f8ae5c5 4958#ifdef CONFIG_PM
cd28ab6a
SH		 4959static int sky2_resume(struct pci_dev *pdev)
4960{
793b883e 4961 struct sky2_hw *hw = pci_get_drvdata(pdev);
3403aca2 4962 int err;
cd28ab6a 4963
549a68c3
SH		 4964 if (!hw)
4965 return 0;
4966
f71eb1a2
SH		 4967 err = pci_set_power_state(pdev, PCI_D0);
4968 if (err)
4969 goto out;
ae306cca
SH		 4970
4971 err = pci_restore_state(pdev);
4972 if (err)
4973 goto out;
4974
cd28ab6a 4975 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4976
4977 /* Re-enable all clocks */
a0db28b8 4978 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4979 if (err) {
4980 dev_err(&pdev->dev, "PCI write config failed\n");
4981 goto out;
4982 }
1ad5b4a5 4983
3403aca2 4984 rtnl_lock();
e3173832 4985 sky2_reset(hw);
3403aca2 4986 sky2_all_up(hw);
af18d8b8 4987 rtnl_unlock();
eb35cf60 4988
ae306cca 4989 return 0;
08c06d8a 4990out:
af18d8b8 4991
b02a9258 4992 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4993 pci_disable_device(pdev);
08c06d8a 4994 return err;
cd28ab6a
SH		 4995}
4996#endif
4997
e3173832
SH		 4998static void sky2_shutdown(struct pci_dev *pdev)
4999{
5f8ae5c5 5000 sky2_suspend(pdev, PMSG_SUSPEND);
e3173832
SH		 5001}
5002
cd28ab6a 5003static struct pci_driver sky2_driver = {
793b883e
SH		 5004 .name = DRV_NAME,
5005 .id_table = sky2_id_table,
5006 .probe = sky2_probe,
5007 .remove = __devexit_p(sky2_remove),
cd28ab6a 5008#ifdef CONFIG_PM
793b883e
SH		 5009 .suspend = sky2_suspend,
5010 .resume = sky2_resume,
cd28ab6a 5011#endif
e3173832 5012 .shutdown = sky2_shutdown,
cd28ab6a
SH		 5013};
5014
5015static int __init sky2_init_module(void)
5016{
ada1db5c 5017 pr_info("driver version " DRV_VERSION "\n");
c844d483 5018
3cf26753 5019 sky2_debug_init();
50241c4c 5020 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 5021}
5022
5023static void __exit sky2_cleanup_module(void)
5024{
5025 pci_unregister_driver(&sky2_driver);
3cf26753 5026 sky2_debug_cleanup();
cd28ab6a
SH		 5027}
5028
5029module_init(sky2_init_module);
5030module_exit(sky2_cleanup_module);
5031
5032MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 5033MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 5034MODULE_LICENSE("GPL");
5f4f9dc1 5035MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree