]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/qlcnic/qlcnic_hw.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
qlcnic: set mtu lower limit
[net-next-2.6.git] / drivers / net / qlcnic / qlcnic_hw.c
CommitLineData
af19b491
AKS		 1/*
2 * Copyright (C) 2009 - QLogic Corporation.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
22 *
23 */
24
25#include "qlcnic.h"
26
5a0e3ad6 27#include <linux/slab.h>
af19b491
AKS		 28#include <net/ip.h>
29
30#define MASK(n) ((1ULL<<(n))-1)
31#define OCM_WIN_P3P(addr) (addr & 0xffc0000)
32
33#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
34
35#define CRB_BLK(off) ((off >> 20) & 0x3f)
36#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
37#define CRB_WINDOW_2M (0x130060)
38#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
39#define CRB_INDIRECT_2M (0x1e0000UL)
40
41
42#ifndef readq
43static inline u64 readq(void __iomem *addr)
44{
45 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
46}
47#endif
48
49#ifndef writeq
50static inline void writeq(u64 val, void __iomem *addr)
51{
52 writel(((u32) (val)), (addr));
53 writel(((u32) (val >> 32)), (addr + 4));
54}
55#endif
56
af19b491
AKS		 57static const struct crb_128M_2M_block_map
58crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
59 {{{0, 0, 0, 0} } }, /* 0: PCI */
60 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
61 {1, 0x0110000, 0x0120000, 0x130000},
62 {1, 0x0120000, 0x0122000, 0x124000},
63 {1, 0x0130000, 0x0132000, 0x126000},
64 {1, 0x0140000, 0x0142000, 0x128000},
65 {1, 0x0150000, 0x0152000, 0x12a000},
66 {1, 0x0160000, 0x0170000, 0x110000},
67 {1, 0x0170000, 0x0172000, 0x12e000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {0, 0x0000000, 0x0000000, 0x000000},
72 {0, 0x0000000, 0x0000000, 0x000000},
73 {0, 0x0000000, 0x0000000, 0x000000},
74 {1, 0x01e0000, 0x01e0800, 0x122000},
75 {0, 0x0000000, 0x0000000, 0x000000} } },
76 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
77 {{{0, 0, 0, 0} } }, /* 3: */
78 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
79 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
80 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
81 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
82 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {1, 0x08f0000, 0x08f2000, 0x172000} } },
98 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {1, 0x09f0000, 0x09f2000, 0x176000} } },
114 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
130 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
146 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
147 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
148 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
149 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
150 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
151 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
152 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
153 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
154 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
155 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
156 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
157 {{{0, 0, 0, 0} } }, /* 23: */
158 {{{0, 0, 0, 0} } }, /* 24: */
159 {{{0, 0, 0, 0} } }, /* 25: */
160 {{{0, 0, 0, 0} } }, /* 26: */
161 {{{0, 0, 0, 0} } }, /* 27: */
162 {{{0, 0, 0, 0} } }, /* 28: */
163 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
164 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
165 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
166 {{{0} } }, /* 32: PCI */
167 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
168 {1, 0x2110000, 0x2120000, 0x130000},
169 {1, 0x2120000, 0x2122000, 0x124000},
170 {1, 0x2130000, 0x2132000, 0x126000},
171 {1, 0x2140000, 0x2142000, 0x128000},
172 {1, 0x2150000, 0x2152000, 0x12a000},
173 {1, 0x2160000, 0x2170000, 0x110000},
174 {1, 0x2170000, 0x2172000, 0x12e000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000} } },
183 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
184 {{{0} } }, /* 35: */
185 {{{0} } }, /* 36: */
186 {{{0} } }, /* 37: */
187 {{{0} } }, /* 38: */
188 {{{0} } }, /* 39: */
189 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
190 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
191 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
192 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
193 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
194 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
195 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
196 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
197 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
198 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
199 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
200 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
201 {{{0} } }, /* 52: */
202 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
203 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
204 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
205 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
206 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
207 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
208 {{{0} } }, /* 59: I2C0 */
209 {{{0} } }, /* 60: I2C1 */
210 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
211 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
212 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
213};
214
215/*
216 * top 12 bits of crb internal address (hub, agent)
217 */
218static const unsigned crb_hub_agt[64] = {
219 0,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
223 0,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
240 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
243 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
245 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
246 0,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
248 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
249 0,
250 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
251 0,
252 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
254 0,
255 0,
256 0,
257 0,
258 0,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
260 0,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
265 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
270 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
271 0,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
274 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
276 0,
277 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
278 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
279 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
280 0,
281 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
282 0,
283};
284
285/* PCI Windowing for DDR regions. */
286
287#define QLCNIC_PCIE_SEM_TIMEOUT 10000
288
289int
290qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
291{
292 int done = 0, timeout = 0;
293
294 while (!done) {
295 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
296 if (done == 1)
297 break;
65b5b420
AKS		 298 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
299 dev_err(&adapter->pdev->dev,
091754a1
SC		 300 "Failed to acquire sem=%d lock; holdby=%d\n",
301 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
af19b491 302 return -EIO;
65b5b420 303 }
af19b491
AKS		 304 msleep(1);
305 }
306
307 if (id_reg)
308 QLCWR32(adapter, id_reg, adapter->portnum);
309
310 return 0;
311}
312
313void
314qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
315{
316 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
317}
318
319static int
320qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
321 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
322{
323 u32 i, producer, consumer;
324 struct qlcnic_cmd_buffer *pbuf;
325 struct cmd_desc_type0 *cmd_desc;
326 struct qlcnic_host_tx_ring *tx_ring;
327
328 i = 0;
329
8a15ad1f 330 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
af19b491
AKS		 331 return -EIO;
332
333 tx_ring = adapter->tx_ring;
334 __netif_tx_lock_bh(tx_ring->txq);
335
336 producer = tx_ring->producer;
337 consumer = tx_ring->sw_consumer;
338
339 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
340 netif_tx_stop_queue(tx_ring->txq);
ef71ff83
RB		 341 smp_mb();
342 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
343 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
344 netif_tx_wake_queue(tx_ring->txq);
345 } else {
346 adapter->stats.xmit_off++;
347 __netif_tx_unlock_bh(tx_ring->txq);
348 return -EBUSY;
349 }
af19b491
AKS		 350 }
351
352 do {
353 cmd_desc = &cmd_desc_arr[i];
354
355 pbuf = &tx_ring->cmd_buf_arr[producer];
356 pbuf->skb = NULL;
357 pbuf->frag_count = 0;
358
359 memcpy(&tx_ring->desc_head[producer],
360 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
361
362 producer = get_next_index(producer, tx_ring->num_desc);
363 i++;
364
365 } while (i != nr_desc);
366
367 tx_ring->producer = producer;
368
369 qlcnic_update_cmd_producer(adapter, tx_ring);
370
371 __netif_tx_unlock_bh(tx_ring->txq);
372
373 return 0;
374}
375
376static int
377qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
7e56cac4 378 __le16 vlan_id, unsigned op)
af19b491
AKS		 379{
380 struct qlcnic_nic_req req;
381 struct qlcnic_mac_req *mac_req;
7e56cac4 382 struct qlcnic_vlan_req *vlan_req;
af19b491
AKS		 383 u64 word;
384
385 memset(&req, 0, sizeof(struct qlcnic_nic_req));
386 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
387
388 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
389 req.req_hdr = cpu_to_le64(word);
390
391 mac_req = (struct qlcnic_mac_req *)&req.words[0];
392 mac_req->op = op;
393 memcpy(mac_req->mac_addr, addr, 6);
394
7e56cac4
SC		 395 vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
396 vlan_req->vlan_id = vlan_id;
03c5d770 397
af19b491
AKS		 398 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
399}
400
9ab17b39 401static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
af19b491
AKS		 402{
403 struct list_head *head;
404 struct qlcnic_mac_list_s *cur;
405
406 /* look up if already exists */
9ab17b39 407 list_for_each(head, &adapter->mac_list) {
af19b491 408 cur = list_entry(head, struct qlcnic_mac_list_s, list);
9ab17b39 409 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
af19b491 410 return 0;
af19b491
AKS		 411 }
412
413 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
414 if (cur == NULL) {
415 dev_err(&adapter->netdev->dev,
416 "failed to add mac address filter\n");
417 return -ENOMEM;
418 }
419 memcpy(cur->mac_addr, addr, ETH_ALEN);
af19b491 420
42f65cba 421 if (qlcnic_sre_macaddr_change(adapter,
03c5d770 422 cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
42f65cba
AKS		 423 kfree(cur);
424 return -EIO;
425 }
426
427 list_add_tail(&cur->list, &adapter->mac_list);
428 return 0;
af19b491
AKS		 429}
430
431void qlcnic_set_multi(struct net_device *netdev)
432{
433 struct qlcnic_adapter *adapter = netdev_priv(netdev);
22bedad3 434 struct netdev_hw_addr *ha;
af19b491
AKS		 435 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
436 u32 mode = VPORT_MISS_MODE_DROP;
af19b491 437
8a15ad1f 438 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
a55cb185
AKS		 439 return;
440
9ab17b39
SC		 441 qlcnic_nic_add_mac(adapter, adapter->mac_addr);
442 qlcnic_nic_add_mac(adapter, bcast_addr);
af19b491
AKS		 443
444 if (netdev->flags & IFF_PROMISC) {
445 mode = VPORT_MISS_MODE_ACCEPT_ALL;
446 goto send_fw_cmd;
447 }
448
449 if ((netdev->flags & IFF_ALLMULTI) ||
4cd24eaf 450 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
af19b491
AKS		 451 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
452 goto send_fw_cmd;
453 }
454
4cd24eaf 455 if (!netdev_mc_empty(netdev)) {
22bedad3
JP		 456 netdev_for_each_mc_addr(ha, netdev) {
457 qlcnic_nic_add_mac(adapter, ha->addr);
af19b491
AKS		 458 }
459 }
460
461send_fw_cmd:
462 qlcnic_nic_set_promisc(adapter, mode);
af19b491
AKS		 463}
464
465int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
466{
467 struct qlcnic_nic_req req;
468 u64 word;
469
470 memset(&req, 0, sizeof(struct qlcnic_nic_req));
471
472 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
473
474 word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
475 ((u64)adapter->portnum << 16);
476 req.req_hdr = cpu_to_le64(word);
477
478 req.words[0] = cpu_to_le64(mode);
479
480 return qlcnic_send_cmd_descs(adapter,
481 (struct cmd_desc_type0 *)&req, 1);
482}
483
484void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
485{
486 struct qlcnic_mac_list_s *cur;
487 struct list_head *head = &adapter->mac_list;
488
489 while (!list_empty(head)) {
490 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
491 qlcnic_sre_macaddr_change(adapter,
03c5d770 492 cur->mac_addr, 0, QLCNIC_MAC_DEL);
af19b491
AKS		 493 list_del(&cur->list);
494 kfree(cur);
495 }
496}
497
b5e5492c
AKS		 498void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
499{
500 struct qlcnic_filter *tmp_fil;
501 struct hlist_node *tmp_hnode, *n;
502 struct hlist_head *head;
503 int i;
504
505 for (i = 0; i < adapter->fhash.fmax; i++) {
506 head = &(adapter->fhash.fhead[i]);
507
508 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode)
509 {
510 if (jiffies >
511 (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) {
512 qlcnic_sre_macaddr_change(adapter,
03c5d770
AKS		 513 tmp_fil->faddr, tmp_fil->vlan_id,
514 tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
515 QLCNIC_MAC_DEL);
b5e5492c
AKS		 516 spin_lock_bh(&adapter->mac_learn_lock);
517 adapter->fhash.fnum--;
518 hlist_del(&tmp_fil->fnode);
519 spin_unlock_bh(&adapter->mac_learn_lock);
520 kfree(tmp_fil);
521 }
522 }
523 }
524}
525
526void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
527{
528 struct qlcnic_filter *tmp_fil;
529 struct hlist_node *tmp_hnode, *n;
530 struct hlist_head *head;
531 int i;
532
533 for (i = 0; i < adapter->fhash.fmax; i++) {
534 head = &(adapter->fhash.fhead[i]);
535
536 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
03c5d770
AKS		 537 qlcnic_sre_macaddr_change(adapter, tmp_fil->faddr,
538 tmp_fil->vlan_id, tmp_fil->vlan_id ?
539 QLCNIC_MAC_VLAN_DEL : QLCNIC_MAC_DEL);
b5e5492c
AKS		 540 spin_lock_bh(&adapter->mac_learn_lock);
541 adapter->fhash.fnum--;
542 hlist_del(&tmp_fil->fnode);
543 spin_unlock_bh(&adapter->mac_learn_lock);
544 kfree(tmp_fil);
545 }
546 }
547}
548
af19b491
AKS		 549#define QLCNIC_CONFIG_INTR_COALESCE 3
550
551/*
552 * Send the interrupt coalescing parameter set by ethtool to the card.
553 */
554int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
555{
556 struct qlcnic_nic_req req;
557 u64 word[6];
558 int rv, i;
559
560 memset(&req, 0, sizeof(struct qlcnic_nic_req));
561
562 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
563
564 word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
565 req.req_hdr = cpu_to_le64(word[0]);
566
567 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
568 for (i = 0; i < 6; i++)
569 req.words[i] = cpu_to_le64(word[i]);
570
571 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
572 if (rv != 0)
573 dev_err(&adapter->netdev->dev,
574 "Could not send interrupt coalescing parameters\n");
575
576 return rv;
577}
578
579int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
580{
581 struct qlcnic_nic_req req;
582 u64 word;
583 int rv;
584
585 if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
586 return 0;
587
588 memset(&req, 0, sizeof(struct qlcnic_nic_req));
589
590 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
591
592 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
593 req.req_hdr = cpu_to_le64(word);
594
595 req.words[0] = cpu_to_le64(enable);
596
597 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
598 if (rv != 0)
599 dev_err(&adapter->netdev->dev,
600 "Could not send configure hw lro request\n");
601
602 adapter->flags ^= QLCNIC_LRO_ENABLED;
603
604 return rv;
605}
606
2e9d722d 607int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
af19b491
AKS		 608{
609 struct qlcnic_nic_req req;
610 u64 word;
611 int rv;
612
613 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
614 return 0;
615
616 memset(&req, 0, sizeof(struct qlcnic_nic_req));
617
618 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
619
620 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
621 ((u64)adapter->portnum << 16);
622 req.req_hdr = cpu_to_le64(word);
623
624 req.words[0] = cpu_to_le64(enable);
625
626 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
627 if (rv != 0)
628 dev_err(&adapter->netdev->dev,
629 "Could not send configure bridge mode request\n");
630
631 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
632
633 return rv;
634}
635
636
637#define RSS_HASHTYPE_IP_TCP 0x3
638
639int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
640{
641 struct qlcnic_nic_req req;
642 u64 word;
643 int i, rv;
644
645 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
646 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
647 0x255b0ec26d5a56daULL };
648
649
650 memset(&req, 0, sizeof(struct qlcnic_nic_req));
651 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
652
653 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
654 req.req_hdr = cpu_to_le64(word);
655
656 /*
657 * RSS request:
658 * bits 3-0: hash_method
659 * 5-4: hash_type_ipv4
660 * 7-6: hash_type_ipv6
661 * 8: enable
662 * 9: use indirection table
663 * 47-10: reserved
664 * 63-48: indirection table mask
665 */
666 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
667 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
668 ((u64)(enable & 0x1) << 8) |
669 ((0x7ULL) << 48);
670 req.words[0] = cpu_to_le64(word);
671 for (i = 0; i < 5; i++)
672 req.words[i+1] = cpu_to_le64(key[i]);
673
674 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
675 if (rv != 0)
676 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
677
678 return rv;
679}
680
b501595c 681int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd)
af19b491
AKS		 682{
683 struct qlcnic_nic_req req;
b501595c 684 struct qlcnic_ipaddr *ipa;
af19b491
AKS		 685 u64 word;
686 int rv;
687
688 memset(&req, 0, sizeof(struct qlcnic_nic_req));
689 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
690
691 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
692 req.req_hdr = cpu_to_le64(word);
693
694 req.words[0] = cpu_to_le64(cmd);
b501595c
SC		 695 ipa = (struct qlcnic_ipaddr *)&req.words[1];
696 ipa->ipv4 = ip;
af19b491
AKS		 697
698 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
699 if (rv != 0)
700 dev_err(&adapter->netdev->dev,
701 "could not notify %s IP 0x%x reuqest\n",
702 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
703
704 return rv;
705}
706
707int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
708{
709 struct qlcnic_nic_req req;
710 u64 word;
711 int rv;
712
713 memset(&req, 0, sizeof(struct qlcnic_nic_req));
714 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
715
716 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
717 req.req_hdr = cpu_to_le64(word);
718 req.words[0] = cpu_to_le64(enable | (enable << 8));
719
720 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
721 if (rv != 0)
722 dev_err(&adapter->netdev->dev,
723 "could not configure link notification\n");
724
725 return rv;
726}
727
728int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
729{
730 struct qlcnic_nic_req req;
731 u64 word;
732 int rv;
733
734 memset(&req, 0, sizeof(struct qlcnic_nic_req));
735 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
736
737 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
738 ((u64)adapter->portnum << 16) |
739 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
740
741 req.req_hdr = cpu_to_le64(word);
742
743 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
744 if (rv != 0)
745 dev_err(&adapter->netdev->dev,
746 "could not cleanup lro flows\n");
747
748 return rv;
749}
750
751/*
752 * qlcnic_change_mtu - Change the Maximum Transfer Unit
753 * @returns 0 on success, negative on failure
754 */
755
756int qlcnic_change_mtu(struct net_device *netdev, int mtu)
757{
758 struct qlcnic_adapter *adapter = netdev_priv(netdev);
759 int rc = 0;
760
0bd9e6a9
SV		 761 if (mtu < P3_MIN_MTU || mtu > P3_MAX_MTU) {
762 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
763 " not supported\n", P3_MAX_MTU, P3_MIN_MTU);
af19b491
AKS		 764 return -EINVAL;
765 }
766
767 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
768
769 if (!rc)
770 netdev->mtu = mtu;
771
772 return rc;
773}
774
af19b491
AKS		 775/*
776 * Changes the CRB window to the specified window.
777 */
778 /* Returns < 0 if off is not valid,
779 * 1 if window access is needed. 'off' is set to offset from
780 * CRB space in 128M pci map
781 * 0 if no window access is needed. 'off' is set to 2M addr
782 * In: 'off' is offset from base in 128M pci map
783 */
784static int
785qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
786 ulong off, void __iomem **addr)
787{
788 const struct crb_128M_2M_sub_block_map *m;
789
790 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
791 return -EINVAL;
792
793 off -= QLCNIC_PCI_CRBSPACE;
794
795 /*
796 * Try direct map
797 */
798 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
799
800 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
801 *addr = adapter->ahw.pci_base0 + m->start_2M +
802 (off - m->start_128M);
803 return 0;
804 }
805
806 /*
807 * Not in direct map, use crb window
808 */
809 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
810 return 1;
811}
812
813/*
814 * In: 'off' is offset from CRB space in 128M pci map
815 * Out: 'off' is 2M pci map addr
816 * side effect: lock crb window
817 */
4de57826 818static int
af19b491
AKS		 819qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
820{
821 u32 window;
822 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
823
824 off -= QLCNIC_PCI_CRBSPACE;
825
826 window = CRB_HI(off);
4de57826
AKS		 827 if (window == 0) {
828 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
829 return -EIO;
830 }
af19b491 831
af19b491
AKS		 832 writel(window, addr);
833 if (readl(addr) != window) {
834 if (printk_ratelimit())
835 dev_warn(&adapter->pdev->dev,
836 "failed to set CRB window to %d off 0x%lx\n",
837 window, off);
4de57826 838 return -EIO;
af19b491 839 }
4de57826 840 return 0;
af19b491
AKS		 841}
842
843int
844qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
845{
846 unsigned long flags;
847 int rv;
848 void __iomem *addr = NULL;
849
850 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
851
852 if (rv == 0) {
853 writel(data, addr);
854 return 0;
855 }
856
857 if (rv > 0) {
858 /* indirect access */
859 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
860 crb_win_lock(adapter);
4de57826
AKS		 861 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
862 if (!rv)
863 writel(data, addr);
af19b491
AKS		 864 crb_win_unlock(adapter);
865 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
4de57826 866 return rv;
af19b491
AKS		 867 }
868
869 dev_err(&adapter->pdev->dev,
870 "%s: invalid offset: 0x%016lx\n", __func__, off);
871 dump_stack();
872 return -EIO;
873}
874
875u32
876qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
877{
878 unsigned long flags;
879 int rv;
4de57826 880 u32 data = -1;
af19b491
AKS		 881 void __iomem *addr = NULL;
882
883 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
884
885 if (rv == 0)
886 return readl(addr);
887
888 if (rv > 0) {
889 /* indirect access */
890 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
891 crb_win_lock(adapter);
4de57826
AKS		 892 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
893 data = readl(addr);
af19b491
AKS		 894 crb_win_unlock(adapter);
895 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
896 return data;
897 }
898
899 dev_err(&adapter->pdev->dev,
900 "%s: invalid offset: 0x%016lx\n", __func__, off);
901 dump_stack();
902 return -1;
903}
904
905
906void __iomem *
907qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
908{
909 void __iomem *addr = NULL;
910
911 WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
912
913 return addr;
914}
915
916
917static int
918qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
919 u64 addr, u32 *start)
920{
921 u32 window;
af19b491
AKS		 922
923 window = OCM_WIN_P3P(addr);
924
925 writel(window, adapter->ahw.ocm_win_crb);
926 /* read back to flush */
927 readl(adapter->ahw.ocm_win_crb);
928
af19b491
AKS		 929 *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
930 return 0;
931}
932
933static int
934qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
935 u64 *data, int op)
936{
0c39aa48 937 void __iomem *addr;
af19b491
AKS		 938 int ret;
939 u32 start;
940
941 mutex_lock(&adapter->ahw.mem_lock);
942
943 ret = qlcnic_pci_set_window_2M(adapter, off, &start);
944 if (ret != 0)
945 goto unlock;
946
0c39aa48 947 addr = adapter->ahw.pci_base0 + start;
af19b491 948
af19b491
AKS		 949 if (op == 0) /* read */
950 *data = readq(addr);
951 else /* write */
952 writeq(*data, addr);
953
954unlock:
955 mutex_unlock(&adapter->ahw.mem_lock);
956
af19b491
AKS		 957 return ret;
958}
959
897e8c7c
DP		 960void
961qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
962{
963 void __iomem *addr = adapter->ahw.pci_base0 +
964 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
965
966 mutex_lock(&adapter->ahw.mem_lock);
967 *data = readq(addr);
968 mutex_unlock(&adapter->ahw.mem_lock);
969}
970
971void
972qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
973{
974 void __iomem *addr = adapter->ahw.pci_base0 +
975 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
976
977 mutex_lock(&adapter->ahw.mem_lock);
978 writeq(data, addr);
979 mutex_unlock(&adapter->ahw.mem_lock);
980}
981
af19b491
AKS		 982#define MAX_CTL_CHECK 1000
983
984int
985qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
986 u64 off, u64 data)
987{
988 int i, j, ret;
989 u32 temp, off8;
af19b491
AKS		 990 void __iomem *mem_crb;
991
992 /* Only 64-bit aligned access */
993 if (off & 7)
994 return -EIO;
995
996 /* P3 onward, test agent base for MIU and SIU is same */
997 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
b47acacd 998 QLCNIC_ADDR_QDR_NET_MAX)) {
af19b491
AKS		 999 mem_crb = qlcnic_get_ioaddr(adapter,
1000 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1001 goto correct;
1002 }
1003
1004 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1005 mem_crb = qlcnic_get_ioaddr(adapter,
1006 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1007 goto correct;
1008 }
1009
1010 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1011 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
1012
1013 return -EIO;
1014
1015correct:
b47acacd 1016 off8 = off & ~0xf;
af19b491
AKS		 1017
1018 mutex_lock(&adapter->ahw.mem_lock);
1019
1020 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1021 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1022
1023 i = 0;
b47acacd
DP		 1024 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1025 writel((TA_CTL_START | TA_CTL_ENABLE),
1026 (mem_crb + TEST_AGT_CTRL));
af19b491 1027
b47acacd
DP		 1028 for (j = 0; j < MAX_CTL_CHECK; j++) {
1029 temp = readl(mem_crb + TEST_AGT_CTRL);
1030 if ((temp & TA_CTL_BUSY) == 0)
1031 break;
1032 }
af19b491 1033
b47acacd
DP		 1034 if (j >= MAX_CTL_CHECK) {
1035 ret = -EIO;
1036 goto done;
af19b491
AKS		 1037 }
1038
b47acacd
DP		 1039 i = (off & 0xf) ? 0 : 2;
1040 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1041 mem_crb + MIU_TEST_AGT_WRDATA(i));
1042 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1043 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1044 i = (off & 0xf) ? 2 : 0;
1045
af19b491
AKS		 1046 writel(data & 0xffffffff,
1047 mem_crb + MIU_TEST_AGT_WRDATA(i));
1048 writel((data >> 32) & 0xffffffff,
1049 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1050
1051 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1052 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1053 (mem_crb + TEST_AGT_CTRL));
1054
1055 for (j = 0; j < MAX_CTL_CHECK; j++) {
1056 temp = readl(mem_crb + TEST_AGT_CTRL);
1057 if ((temp & TA_CTL_BUSY) == 0)
1058 break;
1059 }
1060
1061 if (j >= MAX_CTL_CHECK) {
1062 if (printk_ratelimit())
1063 dev_err(&adapter->pdev->dev,
1064 "failed to write through agent\n");
1065 ret = -EIO;
1066 } else
1067 ret = 0;
1068
1069done:
1070 mutex_unlock(&adapter->ahw.mem_lock);
1071
1072 return ret;
1073}
1074
1075int
1076qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1077 u64 off, u64 *data)
1078{
1079 int j, ret;
1080 u32 temp, off8;
b47acacd 1081 u64 val;
af19b491
AKS		 1082 void __iomem *mem_crb;
1083
1084 /* Only 64-bit aligned access */
1085 if (off & 7)
1086 return -EIO;
1087
1088 /* P3 onward, test agent base for MIU and SIU is same */
1089 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
b47acacd 1090 QLCNIC_ADDR_QDR_NET_MAX)) {
af19b491
AKS		 1091 mem_crb = qlcnic_get_ioaddr(adapter,
1092 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1093 goto correct;
1094 }
1095
1096 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1097 mem_crb = qlcnic_get_ioaddr(adapter,
1098 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1099 goto correct;
1100 }
1101
1102 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1103 return qlcnic_pci_mem_access_direct(adapter,
1104 off, data, 0);
1105 }
1106
1107 return -EIO;
1108
1109correct:
b47acacd 1110 off8 = off & ~0xf;
af19b491
AKS		 1111
1112 mutex_lock(&adapter->ahw.mem_lock);
1113
1114 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1115 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1116 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1117 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1118
1119 for (j = 0; j < MAX_CTL_CHECK; j++) {
1120 temp = readl(mem_crb + TEST_AGT_CTRL);
1121 if ((temp & TA_CTL_BUSY) == 0)
1122 break;
1123 }
1124
1125 if (j >= MAX_CTL_CHECK) {
1126 if (printk_ratelimit())
1127 dev_err(&adapter->pdev->dev,
1128 "failed to read through agent\n");
1129 ret = -EIO;
1130 } else {
1131 off8 = MIU_TEST_AGT_RDDATA_LO;
b47acacd 1132 if (off & 0xf)
af19b491
AKS		 1133 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1134
1135 temp = readl(mem_crb + off8 + 4);
1136 val = (u64)temp << 32;
1137 val |= readl(mem_crb + off8);
1138 *data = val;
1139 ret = 0;
1140 }
1141
1142 mutex_unlock(&adapter->ahw.mem_lock);
1143
1144 return ret;
1145}
1146
1147int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1148{
1149 int offset, board_type, magic;
1150 struct pci_dev *pdev = adapter->pdev;
1151
1152 offset = QLCNIC_FW_MAGIC_OFFSET;
1153 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1154 return -EIO;
1155
1156 if (magic != QLCNIC_BDINFO_MAGIC) {
1157 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1158 magic);
1159 return -EIO;
1160 }
1161
1162 offset = QLCNIC_BRDTYPE_OFFSET;
1163 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1164 return -EIO;
1165
1166 adapter->ahw.board_type = board_type;
1167
1168 if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1169 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1170 if ((gpio & 0x8000) == 0)
1171 board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1172 }
1173
1174 switch (board_type) {
1175 case QLCNIC_BRDTYPE_P3_HMEZ:
1176 case QLCNIC_BRDTYPE_P3_XG_LOM:
1177 case QLCNIC_BRDTYPE_P3_10G_CX4:
1178 case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1179 case QLCNIC_BRDTYPE_P3_IMEZ:
1180 case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1181 case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1182 case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1183 case QLCNIC_BRDTYPE_P3_10G_XFP:
1184 case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1185 adapter->ahw.port_type = QLCNIC_XGBE;
1186 break;
1187 case QLCNIC_BRDTYPE_P3_REF_QG:
1188 case QLCNIC_BRDTYPE_P3_4_GB:
1189 case QLCNIC_BRDTYPE_P3_4_GB_MM:
1190 adapter->ahw.port_type = QLCNIC_GBE;
1191 break;
1192 case QLCNIC_BRDTYPE_P3_10G_TP:
1193 adapter->ahw.port_type = (adapter->portnum < 2) ?
1194 QLCNIC_XGBE : QLCNIC_GBE;
1195 break;
1196 default:
1197 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1198 adapter->ahw.port_type = QLCNIC_XGBE;
1199 break;
1200 }
1201
1202 return 0;
1203}
1204
1205int
1206qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1207{
1208 u32 wol_cfg;
1209
1210 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1211 if (wol_cfg & (1UL << adapter->portnum)) {
1212 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1213 if (wol_cfg & (1 << adapter->portnum))
1214 return 1;
1215 }
1216
1217 return 0;
1218}
897d3596
SC		 1219
1220int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1221{
1222 struct qlcnic_nic_req req;
1223 int rv;
1224 u64 word;
1225
1226 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1227 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1228
1229 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1230 req.req_hdr = cpu_to_le64(word);
1231
1232 req.words[0] = cpu_to_le64((u64)rate << 32);
1233 req.words[1] = cpu_to_le64(state);
1234
1235 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1236 if (rv)
1237 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1238
1239 return rv;
1240}
cdaff185
AKS		 1241
1242static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1243{
1244 struct qlcnic_nic_req req;
1245 int rv;
1246 u64 word;
1247
1248 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1249 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1250
1251 word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1252 ((u64)adapter->portnum << 16);
1253 req.req_hdr = cpu_to_le64(word);
1254 req.words[0] = cpu_to_le64(flag);
1255
1256 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1257 if (rv)
1258 dev_err(&adapter->pdev->dev,
1259 "%sting loopback mode failed.\n",
1260 flag ? "Set" : "Reset");
1261 return rv;
1262}
1263
1264int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1265{
1266 if (qlcnic_set_fw_loopback(adapter, 1))
1267 return -EIO;
1268
1269 if (qlcnic_nic_set_promisc(adapter,
1270 VPORT_MISS_MODE_ACCEPT_ALL)) {
1271 qlcnic_set_fw_loopback(adapter, 0);
1272 return -EIO;
1273 }
1274
1275 msleep(1000);
1276 return 0;
1277}
1278
1279void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1280{
1281 int mode = VPORT_MISS_MODE_DROP;
1282 struct net_device *netdev = adapter->netdev;
1283
1284 qlcnic_set_fw_loopback(adapter, 0);
1285
1286 if (netdev->flags & IFF_PROMISC)
1287 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1288 else if (netdev->flags & IFF_ALLMULTI)
1289 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1290
1291 qlcnic_nic_set_promisc(adapter, mode);
8dec32cc 1292 msleep(1000);
cdaff185 1293}
Clone of davem's net-next-2.6 tree