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niu: always include of_device.h
[net-next-2.6.git] / drivers / net / niu.c
CommitLineData
a3138df9
DM		 1/* niu.c: Neptune ethernet driver.
2 *
be0c007a 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
a3138df9
DM		 4 */
5
f10a1f2e
JP		 6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
a3138df9
DM		 8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/dma-mapping.h>
12#include <linux/netdevice.h>
13#include <linux/ethtool.h>
14#include <linux/etherdevice.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/bitops.h>
18#include <linux/mii.h>
19#include <linux/if_ether.h>
20#include <linux/if_vlan.h>
21#include <linux/ip.h>
22#include <linux/in.h>
23#include <linux/ipv6.h>
24#include <linux/log2.h>
25#include <linux/jiffies.h>
26#include <linux/crc32.h>
ccffad25 27#include <linux/list.h>
5a0e3ad6 28#include <linux/slab.h>
a3138df9
DM		 29
30#include <linux/io.h>
a3138df9 31#include <linux/of_device.h>
a3138df9
DM		 32
33#include "niu.h"
34
35#define DRV_MODULE_NAME "niu"
3cfa856d
DM		 36#define DRV_MODULE_VERSION "1.1"
37#define DRV_MODULE_RELDATE "Apr 22, 2010"
a3138df9
DM		 38
39static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43MODULE_DESCRIPTION("NIU ethernet driver");
44MODULE_LICENSE("GPL");
45MODULE_VERSION(DRV_MODULE_VERSION);
46
a3138df9
DM		 47#ifndef readq
48static u64 readq(void __iomem *reg)
49{
e23a59e1 50 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
a3138df9
DM		 51}
52
53static void writeq(u64 val, void __iomem *reg)
54{
55 writel(val & 0xffffffff, reg);
56 writel(val >> 32, reg + 0x4UL);
57}
58#endif
59
a3aa1884 60static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
a3138df9
DM		 61 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
62 {}
63};
64
65MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
66
67#define NIU_TX_TIMEOUT (5 * HZ)
68
69#define nr64(reg) readq(np->regs + (reg))
70#define nw64(reg, val) writeq((val), np->regs + (reg))
71
72#define nr64_mac(reg) readq(np->mac_regs + (reg))
73#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
74
75#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
76#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
77
78#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
79#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
80
81#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
82#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
83
84#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
85
86static int niu_debug;
87static int debug = -1;
88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "NIU debug level");
90
a3138df9
DM		 91#define niu_lock_parent(np, flags) \
92 spin_lock_irqsave(&np->parent->lock, flags)
93#define niu_unlock_parent(np, flags) \
94 spin_unlock_irqrestore(&np->parent->lock, flags)
95
5fbd7e24
MW		 96static int serdes_init_10g_serdes(struct niu *np);
97
a3138df9
DM		 98static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
99 u64 bits, int limit, int delay)
100{
101 while (--limit >= 0) {
102 u64 val = nr64_mac(reg);
103
104 if (!(val & bits))
105 break;
106 udelay(delay);
107 }
108 if (limit < 0)
109 return -ENODEV;
110 return 0;
111}
112
113static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
114 u64 bits, int limit, int delay,
115 const char *reg_name)
116{
117 int err;
118
119 nw64_mac(reg, bits);
120 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
121 if (err)
f10a1f2e
JP		 122 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
123 (unsigned long long)bits, reg_name,
124 (unsigned long long)nr64_mac(reg));
a3138df9
DM		 125 return err;
126}
127
128#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
129({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
130 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
131})
132
133static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
134 u64 bits, int limit, int delay)
135{
136 while (--limit >= 0) {
137 u64 val = nr64_ipp(reg);
138
139 if (!(val & bits))
140 break;
141 udelay(delay);
142 }
143 if (limit < 0)
144 return -ENODEV;
145 return 0;
146}
147
148static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
149 u64 bits, int limit, int delay,
150 const char *reg_name)
151{
152 int err;
153 u64 val;
154
155 val = nr64_ipp(reg);
156 val |= bits;
157 nw64_ipp(reg, val);
158
159 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
160 if (err)
f10a1f2e
JP		 161 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
162 (unsigned long long)bits, reg_name,
163 (unsigned long long)nr64_ipp(reg));
a3138df9
DM		 164 return err;
165}
166
167#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
168({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
169 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
170})
171
172static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
173 u64 bits, int limit, int delay)
174{
175 while (--limit >= 0) {
176 u64 val = nr64(reg);
177
178 if (!(val & bits))
179 break;
180 udelay(delay);
181 }
182 if (limit < 0)
183 return -ENODEV;
184 return 0;
185}
186
187#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
188({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
190})
191
192static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
193 u64 bits, int limit, int delay,
194 const char *reg_name)
195{
196 int err;
197
198 nw64(reg, bits);
199 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
200 if (err)
f10a1f2e
JP		 201 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
202 (unsigned long long)bits, reg_name,
203 (unsigned long long)nr64(reg));
a3138df9
DM		 204 return err;
205}
206
207#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
208({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
210})
211
212static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
213{
214 u64 val = (u64) lp->timer;
215
216 if (on)
217 val |= LDG_IMGMT_ARM;
218
219 nw64(LDG_IMGMT(lp->ldg_num), val);
220}
221
222static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
223{
224 unsigned long mask_reg, bits;
225 u64 val;
226
227 if (ldn < 0 || ldn > LDN_MAX)
228 return -EINVAL;
229
230 if (ldn < 64) {
231 mask_reg = LD_IM0(ldn);
232 bits = LD_IM0_MASK;
233 } else {
234 mask_reg = LD_IM1(ldn - 64);
235 bits = LD_IM1_MASK;
236 }
237
238 val = nr64(mask_reg);
239 if (on)
240 val &= ~bits;
241 else
242 val |= bits;
243 nw64(mask_reg, val);
244
245 return 0;
246}
247
248static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
249{
250 struct niu_parent *parent = np->parent;
251 int i;
252
253 for (i = 0; i <= LDN_MAX; i++) {
254 int err;
255
256 if (parent->ldg_map[i] != lp->ldg_num)
257 continue;
258
259 err = niu_ldn_irq_enable(np, i, on);
260 if (err)
261 return err;
262 }
263 return 0;
264}
265
266static int niu_enable_interrupts(struct niu *np, int on)
267{
268 int i;
269
270 for (i = 0; i < np->num_ldg; i++) {
271 struct niu_ldg *lp = &np->ldg[i];
272 int err;
273
274 err = niu_enable_ldn_in_ldg(np, lp, on);
275 if (err)
276 return err;
277 }
278 for (i = 0; i < np->num_ldg; i++)
279 niu_ldg_rearm(np, &np->ldg[i], on);
280
281 return 0;
282}
283
284static u32 phy_encode(u32 type, int port)
285{
286 return (type << (port * 2));
287}
288
289static u32 phy_decode(u32 val, int port)
290{
291 return (val >> (port * 2)) & PORT_TYPE_MASK;
292}
293
294static int mdio_wait(struct niu *np)
295{
296 int limit = 1000;
297 u64 val;
298
299 while (--limit > 0) {
300 val = nr64(MIF_FRAME_OUTPUT);
301 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
302 return val & MIF_FRAME_OUTPUT_DATA;
303
304 udelay(10);
305 }
306
307 return -ENODEV;
308}
309
310static int mdio_read(struct niu *np, int port, int dev, int reg)
311{
312 int err;
313
314 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
315 err = mdio_wait(np);
316 if (err < 0)
317 return err;
318
319 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
320 return mdio_wait(np);
321}
322
323static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
324{
325 int err;
326
327 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
328 err = mdio_wait(np);
329 if (err < 0)
330 return err;
331
332 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
333 err = mdio_wait(np);
334 if (err < 0)
335 return err;
336
337 return 0;
338}
339
340static int mii_read(struct niu *np, int port, int reg)
341{
342 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
343 return mdio_wait(np);
344}
345
346static int mii_write(struct niu *np, int port, int reg, int data)
347{
348 int err;
349
350 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
351 err = mdio_wait(np);
352 if (err < 0)
353 return err;
354
355 return 0;
356}
357
358static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
359{
360 int err;
361
362 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
363 ESR2_TI_PLL_TX_CFG_L(channel),
364 val & 0xffff);
365 if (!err)
366 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
367 ESR2_TI_PLL_TX_CFG_H(channel),
368 val >> 16);
369 return err;
370}
371
372static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
373{
374 int err;
375
376 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
377 ESR2_TI_PLL_RX_CFG_L(channel),
378 val & 0xffff);
379 if (!err)
380 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
381 ESR2_TI_PLL_RX_CFG_H(channel),
382 val >> 16);
383 return err;
384}
385
386/* Mode is always 10G fiber. */
e3e081e1 387static int serdes_init_niu_10g_fiber(struct niu *np)
a3138df9
DM		 388{
389 struct niu_link_config *lp = &np->link_config;
390 u32 tx_cfg, rx_cfg;
391 unsigned long i;
392
393 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
394 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
395 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
396 PLL_RX_CFG_EQ_LP_ADAPTIVE);
397
398 if (lp->loopback_mode == LOOPBACK_PHY) {
399 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
400
401 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
403
404 tx_cfg |= PLL_TX_CFG_ENTEST;
405 rx_cfg |= PLL_RX_CFG_ENTEST;
406 }
407
408 /* Initialize all 4 lanes of the SERDES. */
409 for (i = 0; i < 4; i++) {
410 int err = esr2_set_tx_cfg(np, i, tx_cfg);
411 if (err)
412 return err;
413 }
414
415 for (i = 0; i < 4; i++) {
416 int err = esr2_set_rx_cfg(np, i, rx_cfg);
417 if (err)
418 return err;
419 }
420
421 return 0;
422}
423
e3e081e1
SB		 424static int serdes_init_niu_1g_serdes(struct niu *np)
425{
426 struct niu_link_config *lp = &np->link_config;
427 u16 pll_cfg, pll_sts;
428 int max_retry = 100;
51e0f058 429 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 430 u32 tx_cfg, rx_cfg;
431 unsigned long i;
432 int err;
433
434 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
435 PLL_TX_CFG_RATE_HALF);
436 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
437 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
438 PLL_RX_CFG_RATE_HALF);
439
440 if (np->port == 0)
441 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
442
443 if (lp->loopback_mode == LOOPBACK_PHY) {
444 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
445
446 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
447 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
448
449 tx_cfg |= PLL_TX_CFG_ENTEST;
450 rx_cfg |= PLL_RX_CFG_ENTEST;
451 }
452
453 /* Initialize PLL for 1G */
454 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
455
456 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
457 ESR2_TI_PLL_CFG_L, pll_cfg);
458 if (err) {
f10a1f2e
JP		 459 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
460 np->port, __func__);
e3e081e1
SB		 461 return err;
462 }
463
464 pll_sts = PLL_CFG_ENPLL;
465
466 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
467 ESR2_TI_PLL_STS_L, pll_sts);
468 if (err) {
f10a1f2e
JP		 469 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
470 np->port, __func__);
e3e081e1
SB		 471 return err;
472 }
473
474 udelay(200);
475
476 /* Initialize all 4 lanes of the SERDES. */
477 for (i = 0; i < 4; i++) {
478 err = esr2_set_tx_cfg(np, i, tx_cfg);
479 if (err)
480 return err;
481 }
482
483 for (i = 0; i < 4; i++) {
484 err = esr2_set_rx_cfg(np, i, rx_cfg);
485 if (err)
486 return err;
487 }
488
489 switch (np->port) {
490 case 0:
491 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
492 mask = val;
493 break;
494
495 case 1:
496 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
497 mask = val;
498 break;
499
500 default:
501 return -EINVAL;
502 }
503
504 while (max_retry--) {
505 sig = nr64(ESR_INT_SIGNALS);
506 if ((sig & mask) == val)
507 break;
508
509 mdelay(500);
510 }
511
512 if ((sig & mask) != val) {
f10a1f2e
JP		 513 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
514 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 515 return -ENODEV;
516 }
517
518 return 0;
519}
520
521static int serdes_init_niu_10g_serdes(struct niu *np)
522{
523 struct niu_link_config *lp = &np->link_config;
524 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
525 int max_retry = 100;
51e0f058 526 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 527 unsigned long i;
528 int err;
529
530 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
531 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
532 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
533 PLL_RX_CFG_EQ_LP_ADAPTIVE);
534
535 if (lp->loopback_mode == LOOPBACK_PHY) {
536 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
537
538 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
539 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
540
541 tx_cfg |= PLL_TX_CFG_ENTEST;
542 rx_cfg |= PLL_RX_CFG_ENTEST;
543 }
544
545 /* Initialize PLL for 10G */
546 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
547
548 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
549 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
550 if (err) {
f10a1f2e
JP		 551 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
552 np->port, __func__);
e3e081e1
SB		 553 return err;
554 }
555
556 pll_sts = PLL_CFG_ENPLL;
557
558 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
559 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
560 if (err) {
f10a1f2e
JP		 561 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
562 np->port, __func__);
e3e081e1
SB		 563 return err;
564 }
565
566 udelay(200);
567
568 /* Initialize all 4 lanes of the SERDES. */
569 for (i = 0; i < 4; i++) {
570 err = esr2_set_tx_cfg(np, i, tx_cfg);
571 if (err)
572 return err;
573 }
574
575 for (i = 0; i < 4; i++) {
576 err = esr2_set_rx_cfg(np, i, rx_cfg);
577 if (err)
578 return err;
579 }
580
581 /* check if serdes is ready */
582
583 switch (np->port) {
584 case 0:
585 mask = ESR_INT_SIGNALS_P0_BITS;
586 val = (ESR_INT_SRDY0_P0 |
587 ESR_INT_DET0_P0 |
588 ESR_INT_XSRDY_P0 |
589 ESR_INT_XDP_P0_CH3 |
590 ESR_INT_XDP_P0_CH2 |
591 ESR_INT_XDP_P0_CH1 |
592 ESR_INT_XDP_P0_CH0);
593 break;
594
595 case 1:
596 mask = ESR_INT_SIGNALS_P1_BITS;
597 val = (ESR_INT_SRDY0_P1 |
598 ESR_INT_DET0_P1 |
599 ESR_INT_XSRDY_P1 |
600 ESR_INT_XDP_P1_CH3 |
601 ESR_INT_XDP_P1_CH2 |
602 ESR_INT_XDP_P1_CH1 |
603 ESR_INT_XDP_P1_CH0);
604 break;
605
606 default:
607 return -EINVAL;
608 }
609
610 while (max_retry--) {
611 sig = nr64(ESR_INT_SIGNALS);
612 if ((sig & mask) == val)
613 break;
614
615 mdelay(500);
616 }
617
618 if ((sig & mask) != val) {
f10a1f2e
JP		 619 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
620 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 621
622 /* 10G failed, try initializing at 1G */
623 err = serdes_init_niu_1g_serdes(np);
624 if (!err) {
625 np->flags &= ~NIU_FLAGS_10G;
626 np->mac_xcvr = MAC_XCVR_PCS;
627 } else {
f10a1f2e
JP		 628 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
629 np->port);
e3e081e1
SB		 630 return -ENODEV;
631 }
632 }
633 return 0;
634}
635
a3138df9
DM		 636static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
637{
638 int err;
639
640 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
641 if (err >= 0) {
642 *val = (err & 0xffff);
643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
644 ESR_RXTX_CTRL_H(chan));
645 if (err >= 0)
646 *val |= ((err & 0xffff) << 16);
647 err = 0;
648 }
649 return err;
650}
651
652static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
653{
654 int err;
655
656 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
657 ESR_GLUE_CTRL0_L(chan));
658 if (err >= 0) {
659 *val = (err & 0xffff);
660 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
661 ESR_GLUE_CTRL0_H(chan));
662 if (err >= 0) {
663 *val |= ((err & 0xffff) << 16);
664 err = 0;
665 }
666 }
667 return err;
668}
669
670static int esr_read_reset(struct niu *np, u32 *val)
671{
672 int err;
673
674 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
675 ESR_RXTX_RESET_CTRL_L);
676 if (err >= 0) {
677 *val = (err & 0xffff);
678 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
679 ESR_RXTX_RESET_CTRL_H);
680 if (err >= 0) {
681 *val |= ((err & 0xffff) << 16);
682 err = 0;
683 }
684 }
685 return err;
686}
687
688static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
689{
690 int err;
691
692 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
693 ESR_RXTX_CTRL_L(chan), val & 0xffff);
694 if (!err)
695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696 ESR_RXTX_CTRL_H(chan), (val >> 16));
697 return err;
698}
699
700static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
701{
702 int err;
703
704 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
705 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
706 if (!err)
707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708 ESR_GLUE_CTRL0_H(chan), (val >> 16));
709 return err;
710}
711
712static int esr_reset(struct niu *np)
713{
f166400b 714 u32 uninitialized_var(reset);
a3138df9
DM		 715 int err;
716
717 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
718 ESR_RXTX_RESET_CTRL_L, 0x0000);
719 if (err)
720 return err;
721 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
722 ESR_RXTX_RESET_CTRL_H, 0xffff);
723 if (err)
724 return err;
725 udelay(200);
726
727 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
728 ESR_RXTX_RESET_CTRL_L, 0xffff);
729 if (err)
730 return err;
731 udelay(200);
732
733 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
734 ESR_RXTX_RESET_CTRL_H, 0x0000);
735 if (err)
736 return err;
737 udelay(200);
738
739 err = esr_read_reset(np, &reset);
740 if (err)
741 return err;
742 if (reset != 0) {
f10a1f2e
JP		 743 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
744 np->port, reset);
a3138df9
DM		 745 return -ENODEV;
746 }
747
748 return 0;
749}
750
751static int serdes_init_10g(struct niu *np)
752{
753 struct niu_link_config *lp = &np->link_config;
754 unsigned long ctrl_reg, test_cfg_reg, i;
755 u64 ctrl_val, test_cfg_val, sig, mask, val;
756 int err;
757
758 switch (np->port) {
759 case 0:
760 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
761 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
762 break;
763 case 1:
764 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
765 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
766 break;
767
768 default:
769 return -EINVAL;
770 }
771 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
772 ENET_SERDES_CTRL_SDET_1 |
773 ENET_SERDES_CTRL_SDET_2 |
774 ENET_SERDES_CTRL_SDET_3 |
775 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
776 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
777 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
779 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
780 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
783 test_cfg_val = 0;
784
785 if (lp->loopback_mode == LOOPBACK_PHY) {
786 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
787 ENET_SERDES_TEST_MD_0_SHIFT) |
788 (ENET_TEST_MD_PAD_LOOPBACK <<
789 ENET_SERDES_TEST_MD_1_SHIFT) |
790 (ENET_TEST_MD_PAD_LOOPBACK <<
791 ENET_SERDES_TEST_MD_2_SHIFT) |
792 (ENET_TEST_MD_PAD_LOOPBACK <<
793 ENET_SERDES_TEST_MD_3_SHIFT));
794 }
795
796 nw64(ctrl_reg, ctrl_val);
797 nw64(test_cfg_reg, test_cfg_val);
798
799 /* Initialize all 4 lanes of the SERDES. */
800 for (i = 0; i < 4; i++) {
801 u32 rxtx_ctrl, glue0;
802
803 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
804 if (err)
805 return err;
806 err = esr_read_glue0(np, i, &glue0);
807 if (err)
808 return err;
809
810 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
811 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
812 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
813
814 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
815 ESR_GLUE_CTRL0_THCNT |
816 ESR_GLUE_CTRL0_BLTIME);
817 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
818 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
819 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
820 (BLTIME_300_CYCLES <<
821 ESR_GLUE_CTRL0_BLTIME_SHIFT));
822
823 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
824 if (err)
825 return err;
826 err = esr_write_glue0(np, i, glue0);
827 if (err)
828 return err;
829 }
830
831 err = esr_reset(np);
832 if (err)
833 return err;
834
835 sig = nr64(ESR_INT_SIGNALS);
836 switch (np->port) {
837 case 0:
838 mask = ESR_INT_SIGNALS_P0_BITS;
839 val = (ESR_INT_SRDY0_P0 |
840 ESR_INT_DET0_P0 |
841 ESR_INT_XSRDY_P0 |
842 ESR_INT_XDP_P0_CH3 |
843 ESR_INT_XDP_P0_CH2 |
844 ESR_INT_XDP_P0_CH1 |
845 ESR_INT_XDP_P0_CH0);
846 break;
847
848 case 1:
849 mask = ESR_INT_SIGNALS_P1_BITS;
850 val = (ESR_INT_SRDY0_P1 |
851 ESR_INT_DET0_P1 |
852 ESR_INT_XSRDY_P1 |
853 ESR_INT_XDP_P1_CH3 |
854 ESR_INT_XDP_P1_CH2 |
855 ESR_INT_XDP_P1_CH1 |
856 ESR_INT_XDP_P1_CH0);
857 break;
858
859 default:
860 return -EINVAL;
861 }
862
863 if ((sig & mask) != val) {
a5d6ab56
MW		 864 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
865 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
866 return 0;
867 }
f10a1f2e
JP		 868 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
869 np->port, (int)(sig & mask), (int)val);
a3138df9
DM		 870 return -ENODEV;
871 }
a5d6ab56
MW		 872 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
873 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
a3138df9
DM		 874 return 0;
875}
876
877static int serdes_init_1g(struct niu *np)
878{
879 u64 val;
880
881 val = nr64(ENET_SERDES_1_PLL_CFG);
882 val &= ~ENET_SERDES_PLL_FBDIV2;
883 switch (np->port) {
884 case 0:
885 val |= ENET_SERDES_PLL_HRATE0;
886 break;
887 case 1:
888 val |= ENET_SERDES_PLL_HRATE1;
889 break;
890 case 2:
891 val |= ENET_SERDES_PLL_HRATE2;
892 break;
893 case 3:
894 val |= ENET_SERDES_PLL_HRATE3;
895 break;
896 default:
897 return -EINVAL;
898 }
899 nw64(ENET_SERDES_1_PLL_CFG, val);
900
901 return 0;
902}
903
5fbd7e24
MW		 904static int serdes_init_1g_serdes(struct niu *np)
905{
906 struct niu_link_config *lp = &np->link_config;
907 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
908 u64 ctrl_val, test_cfg_val, sig, mask, val;
909 int err;
910 u64 reset_val, val_rd;
911
912 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
913 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
914 ENET_SERDES_PLL_FBDIV0;
915 switch (np->port) {
916 case 0:
917 reset_val = ENET_SERDES_RESET_0;
918 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
919 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
920 pll_cfg = ENET_SERDES_0_PLL_CFG;
921 break;
922 case 1:
923 reset_val = ENET_SERDES_RESET_1;
924 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
925 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
926 pll_cfg = ENET_SERDES_1_PLL_CFG;
927 break;
928
929 default:
930 return -EINVAL;
931 }
932 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
933 ENET_SERDES_CTRL_SDET_1 |
934 ENET_SERDES_CTRL_SDET_2 |
935 ENET_SERDES_CTRL_SDET_3 |
936 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
937 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
938 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
940 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
941 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
944 test_cfg_val = 0;
945
946 if (lp->loopback_mode == LOOPBACK_PHY) {
947 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
948 ENET_SERDES_TEST_MD_0_SHIFT) |
949 (ENET_TEST_MD_PAD_LOOPBACK <<
950 ENET_SERDES_TEST_MD_1_SHIFT) |
951 (ENET_TEST_MD_PAD_LOOPBACK <<
952 ENET_SERDES_TEST_MD_2_SHIFT) |
953 (ENET_TEST_MD_PAD_LOOPBACK <<
954 ENET_SERDES_TEST_MD_3_SHIFT));
955 }
956
957 nw64(ENET_SERDES_RESET, reset_val);
958 mdelay(20);
959 val_rd = nr64(ENET_SERDES_RESET);
960 val_rd &= ~reset_val;
961 nw64(pll_cfg, val);
962 nw64(ctrl_reg, ctrl_val);
963 nw64(test_cfg_reg, test_cfg_val);
964 nw64(ENET_SERDES_RESET, val_rd);
965 mdelay(2000);
966
967 /* Initialize all 4 lanes of the SERDES. */
968 for (i = 0; i < 4; i++) {
969 u32 rxtx_ctrl, glue0;
970
971 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
972 if (err)
973 return err;
974 err = esr_read_glue0(np, i, &glue0);
975 if (err)
976 return err;
977
978 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
979 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
980 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
981
982 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
983 ESR_GLUE_CTRL0_THCNT |
984 ESR_GLUE_CTRL0_BLTIME);
985 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
986 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
987 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
988 (BLTIME_300_CYCLES <<
989 ESR_GLUE_CTRL0_BLTIME_SHIFT));
990
991 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
992 if (err)
993 return err;
994 err = esr_write_glue0(np, i, glue0);
995 if (err)
996 return err;
997 }
998
999
1000 sig = nr64(ESR_INT_SIGNALS);
1001 switch (np->port) {
1002 case 0:
1003 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1004 mask = val;
1005 break;
1006
1007 case 1:
1008 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1009 mask = val;
1010 break;
1011
1012 default:
1013 return -EINVAL;
1014 }
1015
1016 if ((sig & mask) != val) {
f10a1f2e
JP		 1017 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1018 np->port, (int)(sig & mask), (int)val);
5fbd7e24
MW		 1019 return -ENODEV;
1020 }
1021
1022 return 0;
1023}
1024
1025static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1026{
1027 struct niu_link_config *lp = &np->link_config;
1028 int link_up;
1029 u64 val;
1030 u16 current_speed;
1031 unsigned long flags;
1032 u8 current_duplex;
1033
1034 link_up = 0;
1035 current_speed = SPEED_INVALID;
1036 current_duplex = DUPLEX_INVALID;
1037
1038 spin_lock_irqsave(&np->lock, flags);
1039
1040 val = nr64_pcs(PCS_MII_STAT);
1041
1042 if (val & PCS_MII_STAT_LINK_STATUS) {
1043 link_up = 1;
1044 current_speed = SPEED_1000;
1045 current_duplex = DUPLEX_FULL;
1046 }
1047
1048 lp->active_speed = current_speed;
1049 lp->active_duplex = current_duplex;
1050 spin_unlock_irqrestore(&np->lock, flags);
1051
1052 *link_up_p = link_up;
1053 return 0;
1054}
1055
5fbd7e24
MW		 1056static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1057{
1058 unsigned long flags;
1059 struct niu_link_config *lp = &np->link_config;
1060 int link_up = 0;
1061 int link_ok = 1;
1062 u64 val, val2;
1063 u16 current_speed;
1064 u8 current_duplex;
1065
1066 if (!(np->flags & NIU_FLAGS_10G))
1067 return link_status_1g_serdes(np, link_up_p);
1068
1069 current_speed = SPEED_INVALID;
1070 current_duplex = DUPLEX_INVALID;
1071 spin_lock_irqsave(&np->lock, flags);
1072
1073 val = nr64_xpcs(XPCS_STATUS(0));
1074 val2 = nr64_mac(XMAC_INTER2);
1075 if (val2 & 0x01000000)
1076 link_ok = 0;
1077
1078 if ((val & 0x1000ULL) && link_ok) {
1079 link_up = 1;
1080 current_speed = SPEED_10000;
1081 current_duplex = DUPLEX_FULL;
1082 }
1083 lp->active_speed = current_speed;
1084 lp->active_duplex = current_duplex;
1085 spin_unlock_irqrestore(&np->lock, flags);
1086 *link_up_p = link_up;
1087 return 0;
1088}
1089
38bb045d
CB		 1090static int link_status_mii(struct niu *np, int *link_up_p)
1091{
1092 struct niu_link_config *lp = &np->link_config;
1093 int err;
1094 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1095 int supported, advertising, active_speed, active_duplex;
1096
1097 err = mii_read(np, np->phy_addr, MII_BMCR);
1098 if (unlikely(err < 0))
1099 return err;
1100 bmcr = err;
1101
1102 err = mii_read(np, np->phy_addr, MII_BMSR);
1103 if (unlikely(err < 0))
1104 return err;
1105 bmsr = err;
1106
1107 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1108 if (unlikely(err < 0))
1109 return err;
1110 advert = err;
1111
1112 err = mii_read(np, np->phy_addr, MII_LPA);
1113 if (unlikely(err < 0))
1114 return err;
1115 lpa = err;
1116
1117 if (likely(bmsr & BMSR_ESTATEN)) {
1118 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1119 if (unlikely(err < 0))
1120 return err;
1121 estatus = err;
1122
1123 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1124 if (unlikely(err < 0))
1125 return err;
1126 ctrl1000 = err;
1127
1128 err = mii_read(np, np->phy_addr, MII_STAT1000);
1129 if (unlikely(err < 0))
1130 return err;
1131 stat1000 = err;
1132 } else
1133 estatus = ctrl1000 = stat1000 = 0;
1134
1135 supported = 0;
1136 if (bmsr & BMSR_ANEGCAPABLE)
1137 supported |= SUPPORTED_Autoneg;
1138 if (bmsr & BMSR_10HALF)
1139 supported |= SUPPORTED_10baseT_Half;
1140 if (bmsr & BMSR_10FULL)
1141 supported |= SUPPORTED_10baseT_Full;
1142 if (bmsr & BMSR_100HALF)
1143 supported |= SUPPORTED_100baseT_Half;
1144 if (bmsr & BMSR_100FULL)
1145 supported |= SUPPORTED_100baseT_Full;
1146 if (estatus & ESTATUS_1000_THALF)
1147 supported |= SUPPORTED_1000baseT_Half;
1148 if (estatus & ESTATUS_1000_TFULL)
1149 supported |= SUPPORTED_1000baseT_Full;
1150 lp->supported = supported;
1151
1152 advertising = 0;
1153 if (advert & ADVERTISE_10HALF)
1154 advertising |= ADVERTISED_10baseT_Half;
1155 if (advert & ADVERTISE_10FULL)
1156 advertising |= ADVERTISED_10baseT_Full;
1157 if (advert & ADVERTISE_100HALF)
1158 advertising |= ADVERTISED_100baseT_Half;
1159 if (advert & ADVERTISE_100FULL)
1160 advertising |= ADVERTISED_100baseT_Full;
1161 if (ctrl1000 & ADVERTISE_1000HALF)
1162 advertising |= ADVERTISED_1000baseT_Half;
1163 if (ctrl1000 & ADVERTISE_1000FULL)
1164 advertising |= ADVERTISED_1000baseT_Full;
1165
1166 if (bmcr & BMCR_ANENABLE) {
1167 int neg, neg1000;
1168
1169 lp->active_autoneg = 1;
1170 advertising |= ADVERTISED_Autoneg;
1171
1172 neg = advert & lpa;
1173 neg1000 = (ctrl1000 << 2) & stat1000;
1174
1175 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1176 active_speed = SPEED_1000;
1177 else if (neg & LPA_100)
1178 active_speed = SPEED_100;
1179 else if (neg & (LPA_10HALF | LPA_10FULL))
1180 active_speed = SPEED_10;
1181 else
1182 active_speed = SPEED_INVALID;
1183
1184 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1185 active_duplex = DUPLEX_FULL;
1186 else if (active_speed != SPEED_INVALID)
1187 active_duplex = DUPLEX_HALF;
1188 else
1189 active_duplex = DUPLEX_INVALID;
1190 } else {
1191 lp->active_autoneg = 0;
1192
1193 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1194 active_speed = SPEED_1000;
1195 else if (bmcr & BMCR_SPEED100)
1196 active_speed = SPEED_100;
1197 else
1198 active_speed = SPEED_10;
1199
1200 if (bmcr & BMCR_FULLDPLX)
1201 active_duplex = DUPLEX_FULL;
1202 else
1203 active_duplex = DUPLEX_HALF;
1204 }
1205
1206 lp->active_advertising = advertising;
1207 lp->active_speed = active_speed;
1208 lp->active_duplex = active_duplex;
1209 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1210
1211 return 0;
1212}
1213
5fbd7e24
MW		 1214static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1215{
1216 struct niu_link_config *lp = &np->link_config;
1217 u16 current_speed, bmsr;
1218 unsigned long flags;
1219 u8 current_duplex;
1220 int err, link_up;
1221
1222 link_up = 0;
1223 current_speed = SPEED_INVALID;
1224 current_duplex = DUPLEX_INVALID;
1225
1226 spin_lock_irqsave(&np->lock, flags);
1227
1228 err = -EINVAL;
1229
1230 err = mii_read(np, np->phy_addr, MII_BMSR);
1231 if (err < 0)
1232 goto out;
1233
1234 bmsr = err;
1235 if (bmsr & BMSR_LSTATUS) {
1236 u16 adv, lpa, common, estat;
1237
1238 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1239 if (err < 0)
1240 goto out;
1241 adv = err;
1242
1243 err = mii_read(np, np->phy_addr, MII_LPA);
1244 if (err < 0)
1245 goto out;
1246 lpa = err;
1247
1248 common = adv & lpa;
1249
1250 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1251 if (err < 0)
1252 goto out;
1253 estat = err;
1254 link_up = 1;
1255 current_speed = SPEED_1000;
1256 current_duplex = DUPLEX_FULL;
1257
1258 }
1259 lp->active_speed = current_speed;
1260 lp->active_duplex = current_duplex;
1261 err = 0;
1262
1263out:
1264 spin_unlock_irqrestore(&np->lock, flags);
1265
1266 *link_up_p = link_up;
1267 return err;
1268}
1269
38bb045d
CB		 1270static int link_status_1g(struct niu *np, int *link_up_p)
1271{
1272 struct niu_link_config *lp = &np->link_config;
1273 unsigned long flags;
1274 int err;
1275
1276 spin_lock_irqsave(&np->lock, flags);
1277
1278 err = link_status_mii(np, link_up_p);
1279 lp->supported |= SUPPORTED_TP;
1280 lp->active_advertising |= ADVERTISED_TP;
1281
1282 spin_unlock_irqrestore(&np->lock, flags);
1283 return err;
1284}
1285
a3138df9
DM		 1286static int bcm8704_reset(struct niu *np)
1287{
1288 int err, limit;
1289
1290 err = mdio_read(np, np->phy_addr,
1291 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
9c5cd670 1292 if (err < 0 || err == 0xffff)
a3138df9
DM		 1293 return err;
1294 err |= BMCR_RESET;
1295 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1296 MII_BMCR, err);
1297 if (err)
1298 return err;
1299
1300 limit = 1000;
1301 while (--limit >= 0) {
1302 err = mdio_read(np, np->phy_addr,
1303 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1304 if (err < 0)
1305 return err;
1306 if (!(err & BMCR_RESET))
1307 break;
1308 }
1309 if (limit < 0) {
f10a1f2e
JP		 1310 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1311 np->port, (err & 0xffff));
a3138df9
DM		 1312 return -ENODEV;
1313 }
1314 return 0;
1315}
1316
1317/* When written, certain PHY registers need to be read back twice
1318 * in order for the bits to settle properly.
1319 */
1320static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1321{
1322 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1323 if (err < 0)
1324 return err;
1325 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1326 if (err < 0)
1327 return err;
1328 return 0;
1329}
1330
a5d6ab56
MW		 1331static int bcm8706_init_user_dev3(struct niu *np)
1332{
1333 int err;
1334
1335
1336 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1337 BCM8704_USER_OPT_DIGITAL_CTRL);
1338 if (err < 0)
1339 return err;
1340 err &= ~USER_ODIG_CTRL_GPIOS;
1341 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1342 err |= USER_ODIG_CTRL_RESV2;
1343 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1344 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1345 if (err)
1346 return err;
1347
1348 mdelay(1000);
1349
1350 return 0;
1351}
1352
a3138df9
DM		 1353static int bcm8704_init_user_dev3(struct niu *np)
1354{
1355 int err;
1356
1357 err = mdio_write(np, np->phy_addr,
1358 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1359 (USER_CONTROL_OPTXRST_LVL |
1360 USER_CONTROL_OPBIASFLT_LVL |
1361 USER_CONTROL_OBTMPFLT_LVL |
1362 USER_CONTROL_OPPRFLT_LVL |
1363 USER_CONTROL_OPTXFLT_LVL |
1364 USER_CONTROL_OPRXLOS_LVL |
1365 USER_CONTROL_OPRXFLT_LVL |
1366 USER_CONTROL_OPTXON_LVL |
1367 (0x3f << USER_CONTROL_RES1_SHIFT)));
1368 if (err)
1369 return err;
1370
1371 err = mdio_write(np, np->phy_addr,
1372 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1373 (USER_PMD_TX_CTL_XFP_CLKEN |
1374 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1375 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1376 USER_PMD_TX_CTL_TSCK_LPWREN));
1377 if (err)
1378 return err;
1379
1380 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1381 if (err)
1382 return err;
1383 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1384 if (err)
1385 return err;
1386
1387 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1388 BCM8704_USER_OPT_DIGITAL_CTRL);
1389 if (err < 0)
1390 return err;
1391 err &= ~USER_ODIG_CTRL_GPIOS;
1392 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1393 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1394 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1395 if (err)
1396 return err;
1397
1398 mdelay(1000);
1399
1400 return 0;
1401}
1402
b0de8e40
ML		 1403static int mrvl88x2011_act_led(struct niu *np, int val)
1404{
1405 int err;
1406
1407 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1408 MRVL88X2011_LED_8_TO_11_CTL);
1409 if (err < 0)
1410 return err;
1411
1412 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1413 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1414
1415 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1416 MRVL88X2011_LED_8_TO_11_CTL, err);
1417}
1418
1419static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1420{
1421 int err;
1422
1423 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1424 MRVL88X2011_LED_BLINK_CTL);
1425 if (err >= 0) {
1426 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1427 err |= (rate << 4);
1428
1429 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1430 MRVL88X2011_LED_BLINK_CTL, err);
1431 }
1432
1433 return err;
1434}
1435
1436static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1437{
1438 int err;
1439
1440 /* Set LED functions */
1441 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1442 if (err)
1443 return err;
1444
1445 /* led activity */
1446 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1447 if (err)
1448 return err;
1449
1450 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1451 MRVL88X2011_GENERAL_CTL);
1452 if (err < 0)
1453 return err;
1454
1455 err |= MRVL88X2011_ENA_XFPREFCLK;
1456
1457 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1458 MRVL88X2011_GENERAL_CTL, err);
1459 if (err < 0)
1460 return err;
1461
1462 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1463 MRVL88X2011_PMA_PMD_CTL_1);
1464 if (err < 0)
1465 return err;
1466
1467 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1468 err |= MRVL88X2011_LOOPBACK;
1469 else
1470 err &= ~MRVL88X2011_LOOPBACK;
1471
1472 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1473 MRVL88X2011_PMA_PMD_CTL_1, err);
1474 if (err < 0)
1475 return err;
1476
1477 /* Enable PMD */
1478 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1479 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1480}
1481
a5d6ab56
MW		 1482
1483static int xcvr_diag_bcm870x(struct niu *np)
a3138df9 1484{
a3138df9 1485 u16 analog_stat0, tx_alarm_status;
a5d6ab56 1486 int err = 0;
a3138df9
DM		 1487
1488#if 1
1489 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1490 MII_STAT1000);
1491 if (err < 0)
1492 return err;
f10a1f2e 1493 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
a3138df9
DM		 1494
1495 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1496 if (err < 0)
1497 return err;
f10a1f2e 1498 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
a3138df9
DM		 1499
1500 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1501 MII_NWAYTEST);
1502 if (err < 0)
1503 return err;
f10a1f2e 1504 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
a3138df9
DM		 1505#endif
1506
1507 /* XXX dig this out it might not be so useful XXX */
1508 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1509 BCM8704_USER_ANALOG_STATUS0);
1510 if (err < 0)
1511 return err;
1512 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1513 BCM8704_USER_ANALOG_STATUS0);
1514 if (err < 0)
1515 return err;
1516 analog_stat0 = err;
1517
1518 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1519 BCM8704_USER_TX_ALARM_STATUS);
1520 if (err < 0)
1521 return err;
1522 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1523 BCM8704_USER_TX_ALARM_STATUS);
1524 if (err < 0)
1525 return err;
1526 tx_alarm_status = err;
1527
1528 if (analog_stat0 != 0x03fc) {
1529 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
f10a1f2e
JP		 1530 pr_info("Port %u cable not connected or bad cable\n",
1531 np->port);
a3138df9 1532 } else if (analog_stat0 == 0x639c) {
f10a1f2e
JP		 1533 pr_info("Port %u optical module is bad or missing\n",
1534 np->port);
a3138df9
DM		 1535 }
1536 }
1537
1538 return 0;
1539}
1540
a5d6ab56
MW		 1541static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1542{
1543 struct niu_link_config *lp = &np->link_config;
1544 int err;
1545
1546 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1547 MII_BMCR);
1548 if (err < 0)
1549 return err;
1550
1551 err &= ~BMCR_LOOPBACK;
1552
1553 if (lp->loopback_mode == LOOPBACK_MAC)
1554 err |= BMCR_LOOPBACK;
1555
1556 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1557 MII_BMCR, err);
1558 if (err)
1559 return err;
1560
1561 return 0;
1562}
1563
1564static int xcvr_init_10g_bcm8706(struct niu *np)
1565{
1566 int err = 0;
1567 u64 val;
1568
1569 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1570 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1571 return err;
1572
1573 val = nr64_mac(XMAC_CONFIG);
1574 val &= ~XMAC_CONFIG_LED_POLARITY;
1575 val |= XMAC_CONFIG_FORCE_LED_ON;
1576 nw64_mac(XMAC_CONFIG, val);
1577
1578 val = nr64(MIF_CONFIG);
1579 val |= MIF_CONFIG_INDIRECT_MODE;
1580 nw64(MIF_CONFIG, val);
1581
1582 err = bcm8704_reset(np);
1583 if (err)
1584 return err;
1585
1586 err = xcvr_10g_set_lb_bcm870x(np);
1587 if (err)
1588 return err;
1589
1590 err = bcm8706_init_user_dev3(np);
1591 if (err)
1592 return err;
1593
1594 err = xcvr_diag_bcm870x(np);
1595 if (err)
1596 return err;
1597
1598 return 0;
1599}
1600
1601static int xcvr_init_10g_bcm8704(struct niu *np)
1602{
1603 int err;
1604
1605 err = bcm8704_reset(np);
1606 if (err)
1607 return err;
1608
1609 err = bcm8704_init_user_dev3(np);
1610 if (err)
1611 return err;
1612
1613 err = xcvr_10g_set_lb_bcm870x(np);
1614 if (err)
1615 return err;
1616
1617 err = xcvr_diag_bcm870x(np);
1618 if (err)
1619 return err;
1620
1621 return 0;
1622}
1623
b0de8e40
ML		 1624static int xcvr_init_10g(struct niu *np)
1625{
1626 int phy_id, err;
1627 u64 val;
1628
1629 val = nr64_mac(XMAC_CONFIG);
1630 val &= ~XMAC_CONFIG_LED_POLARITY;
1631 val |= XMAC_CONFIG_FORCE_LED_ON;
1632 nw64_mac(XMAC_CONFIG, val);
1633
1634 /* XXX shared resource, lock parent XXX */
1635 val = nr64(MIF_CONFIG);
1636 val |= MIF_CONFIG_INDIRECT_MODE;
1637 nw64(MIF_CONFIG, val);
1638
1639 phy_id = phy_decode(np->parent->port_phy, np->port);
1640 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1641
1642 /* handle different phy types */
1643 switch (phy_id & NIU_PHY_ID_MASK) {
1644 case NIU_PHY_ID_MRVL88X2011:
1645 err = xcvr_init_10g_mrvl88x2011(np);
1646 break;
1647
1648 default: /* bcom 8704 */
1649 err = xcvr_init_10g_bcm8704(np);
1650 break;
1651 }
1652
1653 return 0;
1654}
1655
a3138df9
DM		 1656static int mii_reset(struct niu *np)
1657{
1658 int limit, err;
1659
1660 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1661 if (err)
1662 return err;
1663
1664 limit = 1000;
1665 while (--limit >= 0) {
1666 udelay(500);
1667 err = mii_read(np, np->phy_addr, MII_BMCR);
1668 if (err < 0)
1669 return err;
1670 if (!(err & BMCR_RESET))
1671 break;
1672 }
1673 if (limit < 0) {
f10a1f2e
JP		 1674 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1675 np->port, err);
a3138df9
DM		 1676 return -ENODEV;
1677 }
1678
1679 return 0;
1680}
1681
5fbd7e24
MW		 1682static int xcvr_init_1g_rgmii(struct niu *np)
1683{
1684 int err;
1685 u64 val;
1686 u16 bmcr, bmsr, estat;
1687
1688 val = nr64(MIF_CONFIG);
1689 val &= ~MIF_CONFIG_INDIRECT_MODE;
1690 nw64(MIF_CONFIG, val);
1691
1692 err = mii_reset(np);
1693 if (err)
1694 return err;
1695
1696 err = mii_read(np, np->phy_addr, MII_BMSR);
1697 if (err < 0)
1698 return err;
1699 bmsr = err;
1700
1701 estat = 0;
1702 if (bmsr & BMSR_ESTATEN) {
1703 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1704 if (err < 0)
1705 return err;
1706 estat = err;
1707 }
1708
1709 bmcr = 0;
1710 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1711 if (err)
1712 return err;
1713
1714 if (bmsr & BMSR_ESTATEN) {
1715 u16 ctrl1000 = 0;
1716
1717 if (estat & ESTATUS_1000_TFULL)
1718 ctrl1000 |= ADVERTISE_1000FULL;
1719 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1720 if (err)
1721 return err;
1722 }
1723
1724 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1725
1726 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1727 if (err)
1728 return err;
1729
1730 err = mii_read(np, np->phy_addr, MII_BMCR);
1731 if (err < 0)
1732 return err;
1733 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1734
1735 err = mii_read(np, np->phy_addr, MII_BMSR);
1736 if (err < 0)
1737 return err;
1738
1739 return 0;
1740}
1741
a3138df9
DM		 1742static int mii_init_common(struct niu *np)
1743{
1744 struct niu_link_config *lp = &np->link_config;
1745 u16 bmcr, bmsr, adv, estat;
1746 int err;
1747
1748 err = mii_reset(np);
1749 if (err)
1750 return err;
1751
1752 err = mii_read(np, np->phy_addr, MII_BMSR);
1753 if (err < 0)
1754 return err;
1755 bmsr = err;
1756
1757 estat = 0;
1758 if (bmsr & BMSR_ESTATEN) {
1759 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1760 if (err < 0)
1761 return err;
1762 estat = err;
1763 }
1764
1765 bmcr = 0;
1766 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1767 if (err)
1768 return err;
1769
1770 if (lp->loopback_mode == LOOPBACK_MAC) {
1771 bmcr |= BMCR_LOOPBACK;
1772 if (lp->active_speed == SPEED_1000)
1773 bmcr |= BMCR_SPEED1000;
1774 if (lp->active_duplex == DUPLEX_FULL)
1775 bmcr |= BMCR_FULLDPLX;
1776 }
1777
1778 if (lp->loopback_mode == LOOPBACK_PHY) {
1779 u16 aux;
1780
1781 aux = (BCM5464R_AUX_CTL_EXT_LB |
1782 BCM5464R_AUX_CTL_WRITE_1);
1783 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1784 if (err)
1785 return err;
1786 }
1787
38bb045d
CB		 1788 if (lp->autoneg) {
1789 u16 ctrl1000;
1790
1791 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1792 if ((bmsr & BMSR_10HALF) &&
1793 (lp->advertising & ADVERTISED_10baseT_Half))
1794 adv |= ADVERTISE_10HALF;
1795 if ((bmsr & BMSR_10FULL) &&
1796 (lp->advertising & ADVERTISED_10baseT_Full))
1797 adv |= ADVERTISE_10FULL;
1798 if ((bmsr & BMSR_100HALF) &&
1799 (lp->advertising & ADVERTISED_100baseT_Half))
1800 adv |= ADVERTISE_100HALF;
1801 if ((bmsr & BMSR_100FULL) &&
1802 (lp->advertising & ADVERTISED_100baseT_Full))
1803 adv |= ADVERTISE_100FULL;
1804 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
a3138df9
DM		 1805 if (err)
1806 return err;
38bb045d
CB		 1807
1808 if (likely(bmsr & BMSR_ESTATEN)) {
1809 ctrl1000 = 0;
1810 if ((estat & ESTATUS_1000_THALF) &&
1811 (lp->advertising & ADVERTISED_1000baseT_Half))
1812 ctrl1000 |= ADVERTISE_1000HALF;
1813 if ((estat & ESTATUS_1000_TFULL) &&
1814 (lp->advertising & ADVERTISED_1000baseT_Full))
1815 ctrl1000 |= ADVERTISE_1000FULL;
1816 err = mii_write(np, np->phy_addr,
1817 MII_CTRL1000, ctrl1000);
1818 if (err)
1819 return err;
1820 }
1821
1822 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1823 } else {
1824 /* !lp->autoneg */
1825 int fulldpx;
1826
1827 if (lp->duplex == DUPLEX_FULL) {
1828 bmcr |= BMCR_FULLDPLX;
1829 fulldpx = 1;
1830 } else if (lp->duplex == DUPLEX_HALF)
1831 fulldpx = 0;
1832 else
1833 return -EINVAL;
1834
1835 if (lp->speed == SPEED_1000) {
1836 /* if X-full requested while not supported, or
1837 X-half requested while not supported... */
1838 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1839 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1840 return -EINVAL;
1841 bmcr |= BMCR_SPEED1000;
1842 } else if (lp->speed == SPEED_100) {
1843 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1844 (!fulldpx && !(bmsr & BMSR_100HALF)))
1845 return -EINVAL;
1846 bmcr |= BMCR_SPEED100;
1847 } else if (lp->speed == SPEED_10) {
1848 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1849 (!fulldpx && !(bmsr & BMSR_10HALF)))
1850 return -EINVAL;
1851 } else
1852 return -EINVAL;
a3138df9 1853 }
a3138df9
DM		 1854
1855 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1856 if (err)
1857 return err;
1858
38bb045d 1859#if 0
a3138df9
DM		 1860 err = mii_read(np, np->phy_addr, MII_BMCR);
1861 if (err < 0)
1862 return err;
38bb045d
CB		 1863 bmcr = err;
1864
a3138df9
DM		 1865 err = mii_read(np, np->phy_addr, MII_BMSR);
1866 if (err < 0)
1867 return err;
38bb045d
CB		 1868 bmsr = err;
1869
f10a1f2e 1870 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
a3138df9
DM		 1871 np->port, bmcr, bmsr);
1872#endif
1873
1874 return 0;
1875}
1876
1877static int xcvr_init_1g(struct niu *np)
1878{
1879 u64 val;
1880
1881 /* XXX shared resource, lock parent XXX */
1882 val = nr64(MIF_CONFIG);
1883 val &= ~MIF_CONFIG_INDIRECT_MODE;
1884 nw64(MIF_CONFIG, val);
1885
1886 return mii_init_common(np);
1887}
1888
1889static int niu_xcvr_init(struct niu *np)
1890{
1891 const struct niu_phy_ops *ops = np->phy_ops;
1892 int err;
1893
1894 err = 0;
1895 if (ops->xcvr_init)
1896 err = ops->xcvr_init(np);
1897
1898 return err;
1899}
1900
1901static int niu_serdes_init(struct niu *np)
1902{
1903 const struct niu_phy_ops *ops = np->phy_ops;
1904 int err;
1905
1906 err = 0;
1907 if (ops->serdes_init)
1908 err = ops->serdes_init(np);
1909
1910 return err;
1911}
1912
1913static void niu_init_xif(struct niu *);
0c3b091b 1914static void niu_handle_led(struct niu *, int status);
a3138df9
DM		 1915
1916static int niu_link_status_common(struct niu *np, int link_up)
1917{
1918 struct niu_link_config *lp = &np->link_config;
1919 struct net_device *dev = np->dev;
1920 unsigned long flags;
1921
1922 if (!netif_carrier_ok(dev) && link_up) {
f10a1f2e
JP		 1923 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1924 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1925 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1926 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1927 "10Mbit/sec",
1928 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
a3138df9
DM		 1929
1930 spin_lock_irqsave(&np->lock, flags);
1931 niu_init_xif(np);
0c3b091b 1932 niu_handle_led(np, 1);
a3138df9
DM		 1933 spin_unlock_irqrestore(&np->lock, flags);
1934
1935 netif_carrier_on(dev);
1936 } else if (netif_carrier_ok(dev) && !link_up) {
f10a1f2e 1937 netif_warn(np, link, dev, "Link is down\n");
0c3b091b
ML		 1938 spin_lock_irqsave(&np->lock, flags);
1939 niu_handle_led(np, 0);
1940 spin_unlock_irqrestore(&np->lock, flags);
a3138df9
DM		 1941 netif_carrier_off(dev);
1942 }
1943
1944 return 0;
1945}
1946
b0de8e40 1947static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
a3138df9 1948{
b0de8e40 1949 int err, link_up, pma_status, pcs_status;
a3138df9
DM		 1950
1951 link_up = 0;
1952
b0de8e40
ML		 1953 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1954 MRVL88X2011_10G_PMD_STATUS_2);
1955 if (err < 0)
1956 goto out;
a3138df9 1957
b0de8e40
ML		 1958 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1959 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1960 MRVL88X2011_PMA_PMD_STATUS_1);
1961 if (err < 0)
1962 goto out;
1963
1964 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1965
1966 /* Check PMC Register : 3.0001.2 == 1: read twice */
1967 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1968 MRVL88X2011_PMA_PMD_STATUS_1);
1969 if (err < 0)
1970 goto out;
1971
1972 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1973 MRVL88X2011_PMA_PMD_STATUS_1);
1974 if (err < 0)
1975 goto out;
1976
1977 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1978
1979 /* Check XGXS Register : 4.0018.[0-3,12] */
1980 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1981 MRVL88X2011_10G_XGXS_LANE_STAT);
1982 if (err < 0)
a3138df9
DM		 1983 goto out;
1984
b0de8e40
ML		 1985 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1986 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1987 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1988 0x800))
1989 link_up = (pma_status && pcs_status) ? 1 : 0;
1990
1991 np->link_config.active_speed = SPEED_10000;
1992 np->link_config.active_duplex = DUPLEX_FULL;
1993 err = 0;
1994out:
1995 mrvl88x2011_act_led(np, (link_up ?
1996 MRVL88X2011_LED_CTL_PCS_ACT :
1997 MRVL88X2011_LED_CTL_OFF));
1998
1999 *link_up_p = link_up;
2000 return err;
2001}
2002
a5d6ab56
MW		 2003static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2004{
2005 int err, link_up;
2006 link_up = 0;
2007
2008 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2009 BCM8704_PMD_RCV_SIGDET);
9c5cd670 2010 if (err < 0 || err == 0xffff)
a5d6ab56
MW		 2011 goto out;
2012 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2013 err = 0;
2014 goto out;
2015 }
2016
2017 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2018 BCM8704_PCS_10G_R_STATUS);
2019 if (err < 0)
2020 goto out;
2021
2022 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2023 err = 0;
2024 goto out;
2025 }
2026
2027 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2028 BCM8704_PHYXS_XGXS_LANE_STAT);
2029 if (err < 0)
2030 goto out;
2031 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2032 PHYXS_XGXS_LANE_STAT_MAGIC |
2033 PHYXS_XGXS_LANE_STAT_PATTEST |
2034 PHYXS_XGXS_LANE_STAT_LANE3 |
2035 PHYXS_XGXS_LANE_STAT_LANE2 |
2036 PHYXS_XGXS_LANE_STAT_LANE1 |
2037 PHYXS_XGXS_LANE_STAT_LANE0)) {
2038 err = 0;
2039 np->link_config.active_speed = SPEED_INVALID;
2040 np->link_config.active_duplex = DUPLEX_INVALID;
2041 goto out;
2042 }
2043
2044 link_up = 1;
2045 np->link_config.active_speed = SPEED_10000;
2046 np->link_config.active_duplex = DUPLEX_FULL;
2047 err = 0;
2048
2049out:
2050 *link_up_p = link_up;
a5d6ab56
MW		 2051 return err;
2052}
2053
b0de8e40
ML		 2054static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2055{
2056 int err, link_up;
2057
2058 link_up = 0;
2059
a3138df9
DM		 2060 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2061 BCM8704_PMD_RCV_SIGDET);
2062 if (err < 0)
2063 goto out;
2064 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2065 err = 0;
2066 goto out;
2067 }
2068
2069 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2070 BCM8704_PCS_10G_R_STATUS);
2071 if (err < 0)
2072 goto out;
2073 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2074 err = 0;
2075 goto out;
2076 }
2077
2078 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2079 BCM8704_PHYXS_XGXS_LANE_STAT);
2080 if (err < 0)
2081 goto out;
2082
2083 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2084 PHYXS_XGXS_LANE_STAT_MAGIC |
2085 PHYXS_XGXS_LANE_STAT_LANE3 |
2086 PHYXS_XGXS_LANE_STAT_LANE2 |
2087 PHYXS_XGXS_LANE_STAT_LANE1 |
2088 PHYXS_XGXS_LANE_STAT_LANE0)) {
2089 err = 0;
2090 goto out;
2091 }
2092
2093 link_up = 1;
2094 np->link_config.active_speed = SPEED_10000;
2095 np->link_config.active_duplex = DUPLEX_FULL;
2096 err = 0;
2097
2098out:
b0de8e40
ML		 2099 *link_up_p = link_up;
2100 return err;
2101}
2102
2103static int link_status_10g(struct niu *np, int *link_up_p)
2104{
2105 unsigned long flags;
2106 int err = -EINVAL;
2107
2108 spin_lock_irqsave(&np->lock, flags);
2109
2110 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2111 int phy_id;
2112
2113 phy_id = phy_decode(np->parent->port_phy, np->port);
2114 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2115
2116 /* handle different phy types */
2117 switch (phy_id & NIU_PHY_ID_MASK) {
2118 case NIU_PHY_ID_MRVL88X2011:
2119 err = link_status_10g_mrvl(np, link_up_p);
2120 break;
2121
2122 default: /* bcom 8704 */
2123 err = link_status_10g_bcom(np, link_up_p);
2124 break;
2125 }
2126 }
2127
a3138df9
DM		 2128 spin_unlock_irqrestore(&np->lock, flags);
2129
a3138df9
DM		 2130 return err;
2131}
2132
a5d6ab56
MW		 2133static int niu_10g_phy_present(struct niu *np)
2134{
2135 u64 sig, mask, val;
2136
2137 sig = nr64(ESR_INT_SIGNALS);
2138 switch (np->port) {
2139 case 0:
2140 mask = ESR_INT_SIGNALS_P0_BITS;
2141 val = (ESR_INT_SRDY0_P0 |
2142 ESR_INT_DET0_P0 |
2143 ESR_INT_XSRDY_P0 |
2144 ESR_INT_XDP_P0_CH3 |
2145 ESR_INT_XDP_P0_CH2 |
2146 ESR_INT_XDP_P0_CH1 |
2147 ESR_INT_XDP_P0_CH0);
2148 break;
2149
2150 case 1:
2151 mask = ESR_INT_SIGNALS_P1_BITS;
2152 val = (ESR_INT_SRDY0_P1 |
2153 ESR_INT_DET0_P1 |
2154 ESR_INT_XSRDY_P1 |
2155 ESR_INT_XDP_P1_CH3 |
2156 ESR_INT_XDP_P1_CH2 |
2157 ESR_INT_XDP_P1_CH1 |
2158 ESR_INT_XDP_P1_CH0);
2159 break;
2160
2161 default:
2162 return 0;
2163 }
2164
2165 if ((sig & mask) != val)
2166 return 0;
2167 return 1;
2168}
2169
2170static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2171{
2172 unsigned long flags;
2173 int err = 0;
2174 int phy_present;
2175 int phy_present_prev;
2176
2177 spin_lock_irqsave(&np->lock, flags);
2178
2179 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2180 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2181 1 : 0;
2182 phy_present = niu_10g_phy_present(np);
2183 if (phy_present != phy_present_prev) {
2184 /* state change */
2185 if (phy_present) {
9c5cd670 2186 /* A NEM was just plugged in */
a5d6ab56
MW		 2187 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2188 if (np->phy_ops->xcvr_init)
2189 err = np->phy_ops->xcvr_init(np);
2190 if (err) {
9c5cd670
TC		 2191 err = mdio_read(np, np->phy_addr,
2192 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2193 if (err == 0xffff) {
2194 /* No mdio, back-to-back XAUI */
2195 goto out;
2196 }
a5d6ab56
MW		 2197 /* debounce */
2198 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2199 }
2200 } else {
2201 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2202 *link_up_p = 0;
f10a1f2e
JP		 2203 netif_warn(np, link, np->dev,
2204 "Hotplug PHY Removed\n");
a5d6ab56
MW		 2205 }
2206 }
9c5cd670
TC		 2207out:
2208 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
a5d6ab56 2209 err = link_status_10g_bcm8706(np, link_up_p);
9c5cd670
TC		 2210 if (err == 0xffff) {
2211 /* No mdio, back-to-back XAUI: it is C10NEM */
2212 *link_up_p = 1;
2213 np->link_config.active_speed = SPEED_10000;
2214 np->link_config.active_duplex = DUPLEX_FULL;
2215 }
2216 }
a5d6ab56
MW		 2217 }
2218
2219 spin_unlock_irqrestore(&np->lock, flags);
2220
9c5cd670 2221 return 0;
a5d6ab56
MW		 2222}
2223
a3138df9
DM		 2224static int niu_link_status(struct niu *np, int *link_up_p)
2225{
2226 const struct niu_phy_ops *ops = np->phy_ops;
2227 int err;
2228
2229 err = 0;
2230 if (ops->link_status)
2231 err = ops->link_status(np, link_up_p);
2232
2233 return err;
2234}
2235
2236static void niu_timer(unsigned long __opaque)
2237{
2238 struct niu *np = (struct niu *) __opaque;
2239 unsigned long off;
2240 int err, link_up;
2241
2242 err = niu_link_status(np, &link_up);
2243 if (!err)
2244 niu_link_status_common(np, link_up);
2245
2246 if (netif_carrier_ok(np->dev))
2247 off = 5 * HZ;
2248 else
2249 off = 1 * HZ;
2250 np->timer.expires = jiffies + off;
2251
2252 add_timer(&np->timer);
2253}
2254
5fbd7e24
MW		 2255static const struct niu_phy_ops phy_ops_10g_serdes = {
2256 .serdes_init = serdes_init_10g_serdes,
2257 .link_status = link_status_10g_serdes,
2258};
2259
e3e081e1
SB		 2260static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2261 .serdes_init = serdes_init_niu_10g_serdes,
2262 .link_status = link_status_10g_serdes,
2263};
2264
2265static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2266 .serdes_init = serdes_init_niu_1g_serdes,
2267 .link_status = link_status_1g_serdes,
2268};
2269
5fbd7e24
MW		 2270static const struct niu_phy_ops phy_ops_1g_rgmii = {
2271 .xcvr_init = xcvr_init_1g_rgmii,
2272 .link_status = link_status_1g_rgmii,
2273};
2274
a3138df9 2275static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
e3e081e1 2276 .serdes_init = serdes_init_niu_10g_fiber,
a3138df9
DM		 2277 .xcvr_init = xcvr_init_10g,
2278 .link_status = link_status_10g,
2279};
2280
2281static const struct niu_phy_ops phy_ops_10g_fiber = {
2282 .serdes_init = serdes_init_10g,
2283 .xcvr_init = xcvr_init_10g,
2284 .link_status = link_status_10g,
2285};
2286
a5d6ab56
MW		 2287static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2288 .serdes_init = serdes_init_10g,
2289 .xcvr_init = xcvr_init_10g_bcm8706,
2290 .link_status = link_status_10g_hotplug,
2291};
2292
9c5cd670
TC		 2293static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2294 .serdes_init = serdes_init_niu_10g_fiber,
2295 .xcvr_init = xcvr_init_10g_bcm8706,
2296 .link_status = link_status_10g_hotplug,
2297};
2298
a3138df9
DM		 2299static const struct niu_phy_ops phy_ops_10g_copper = {
2300 .serdes_init = serdes_init_10g,
2301 .link_status = link_status_10g, /* XXX */
2302};
2303
2304static const struct niu_phy_ops phy_ops_1g_fiber = {
2305 .serdes_init = serdes_init_1g,
2306 .xcvr_init = xcvr_init_1g,
2307 .link_status = link_status_1g,
2308};
2309
2310static const struct niu_phy_ops phy_ops_1g_copper = {
2311 .xcvr_init = xcvr_init_1g,
2312 .link_status = link_status_1g,
2313};
2314
2315struct niu_phy_template {
2316 const struct niu_phy_ops *ops;
2317 u32 phy_addr_base;
2318};
2319
e3e081e1 2320static const struct niu_phy_template phy_template_niu_10g_fiber = {
a3138df9
DM		 2321 .ops = &phy_ops_10g_fiber_niu,
2322 .phy_addr_base = 16,
2323};
2324
e3e081e1
SB		 2325static const struct niu_phy_template phy_template_niu_10g_serdes = {
2326 .ops = &phy_ops_10g_serdes_niu,
2327 .phy_addr_base = 0,
2328};
2329
2330static const struct niu_phy_template phy_template_niu_1g_serdes = {
2331 .ops = &phy_ops_1g_serdes_niu,
2332 .phy_addr_base = 0,
2333};
2334
a3138df9
DM		 2335static const struct niu_phy_template phy_template_10g_fiber = {
2336 .ops = &phy_ops_10g_fiber,
2337 .phy_addr_base = 8,
2338};
2339
a5d6ab56
MW		 2340static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2341 .ops = &phy_ops_10g_fiber_hotplug,
2342 .phy_addr_base = 8,
2343};
2344
9c5cd670
TC		 2345static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2346 .ops = &phy_ops_niu_10g_hotplug,
2347 .phy_addr_base = 8,
2348};
2349
a3138df9
DM		 2350static const struct niu_phy_template phy_template_10g_copper = {
2351 .ops = &phy_ops_10g_copper,
2352 .phy_addr_base = 10,
2353};
2354
2355static const struct niu_phy_template phy_template_1g_fiber = {
2356 .ops = &phy_ops_1g_fiber,
2357 .phy_addr_base = 0,
2358};
2359
2360static const struct niu_phy_template phy_template_1g_copper = {
2361 .ops = &phy_ops_1g_copper,
2362 .phy_addr_base = 0,
2363};
2364
5fbd7e24
MW		 2365static const struct niu_phy_template phy_template_1g_rgmii = {
2366 .ops = &phy_ops_1g_rgmii,
2367 .phy_addr_base = 0,
2368};
2369
2370static const struct niu_phy_template phy_template_10g_serdes = {
2371 .ops = &phy_ops_10g_serdes,
2372 .phy_addr_base = 0,
2373};
2374
2375static int niu_atca_port_num[4] = {
2376 0, 0, 11, 10
2377};
2378
2379static int serdes_init_10g_serdes(struct niu *np)
2380{
2381 struct niu_link_config *lp = &np->link_config;
2382 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2383 u64 ctrl_val, test_cfg_val, sig, mask, val;
5fbd7e24
MW		 2384 u64 reset_val;
2385
2386 switch (np->port) {
2387 case 0:
2388 reset_val = ENET_SERDES_RESET_0;
2389 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2390 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2391 pll_cfg = ENET_SERDES_0_PLL_CFG;
2392 break;
2393 case 1:
2394 reset_val = ENET_SERDES_RESET_1;
2395 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2396 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2397 pll_cfg = ENET_SERDES_1_PLL_CFG;
2398 break;
2399
2400 default:
2401 return -EINVAL;
2402 }
2403 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2404 ENET_SERDES_CTRL_SDET_1 |
2405 ENET_SERDES_CTRL_SDET_2 |
2406 ENET_SERDES_CTRL_SDET_3 |
2407 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2408 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2409 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2410 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2411 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2412 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2413 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2414 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2415 test_cfg_val = 0;
2416
2417 if (lp->loopback_mode == LOOPBACK_PHY) {
2418 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2419 ENET_SERDES_TEST_MD_0_SHIFT) |
2420 (ENET_TEST_MD_PAD_LOOPBACK <<
2421 ENET_SERDES_TEST_MD_1_SHIFT) |
2422 (ENET_TEST_MD_PAD_LOOPBACK <<
2423 ENET_SERDES_TEST_MD_2_SHIFT) |
2424 (ENET_TEST_MD_PAD_LOOPBACK <<
2425 ENET_SERDES_TEST_MD_3_SHIFT));
2426 }
2427
2428 esr_reset(np);
2429 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2430 nw64(ctrl_reg, ctrl_val);
2431 nw64(test_cfg_reg, test_cfg_val);
2432
2433 /* Initialize all 4 lanes of the SERDES. */
2434 for (i = 0; i < 4; i++) {
2435 u32 rxtx_ctrl, glue0;
7c34eb89 2436 int err;
5fbd7e24
MW		 2437
2438 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2439 if (err)
2440 return err;
2441 err = esr_read_glue0(np, i, &glue0);
2442 if (err)
2443 return err;
2444
2445 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2446 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2447 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2448
2449 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2450 ESR_GLUE_CTRL0_THCNT |
2451 ESR_GLUE_CTRL0_BLTIME);
2452 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2453 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2454 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2455 (BLTIME_300_CYCLES <<
2456 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2457
2458 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2459 if (err)
2460 return err;
2461 err = esr_write_glue0(np, i, glue0);
2462 if (err)
2463 return err;
2464 }
2465
2466
2467 sig = nr64(ESR_INT_SIGNALS);
2468 switch (np->port) {
2469 case 0:
2470 mask = ESR_INT_SIGNALS_P0_BITS;
2471 val = (ESR_INT_SRDY0_P0 |
2472 ESR_INT_DET0_P0 |
2473 ESR_INT_XSRDY_P0 |
2474 ESR_INT_XDP_P0_CH3 |
2475 ESR_INT_XDP_P0_CH2 |
2476 ESR_INT_XDP_P0_CH1 |
2477 ESR_INT_XDP_P0_CH0);
2478 break;
2479
2480 case 1:
2481 mask = ESR_INT_SIGNALS_P1_BITS;
2482 val = (ESR_INT_SRDY0_P1 |
2483 ESR_INT_DET0_P1 |
2484 ESR_INT_XSRDY_P1 |
2485 ESR_INT_XDP_P1_CH3 |
2486 ESR_INT_XDP_P1_CH2 |
2487 ESR_INT_XDP_P1_CH1 |
2488 ESR_INT_XDP_P1_CH0);
2489 break;
2490
2491 default:
2492 return -EINVAL;
2493 }
2494
2495 if ((sig & mask) != val) {
2496 int err;
2497 err = serdes_init_1g_serdes(np);
2498 if (!err) {
2499 np->flags &= ~NIU_FLAGS_10G;
2500 np->mac_xcvr = MAC_XCVR_PCS;
2501 } else {
f10a1f2e
JP		 2502 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2503 np->port);
5fbd7e24
MW		 2504 return -ENODEV;
2505 }
2506 }
2507
2508 return 0;
2509}
2510
a3138df9
DM		 2511static int niu_determine_phy_disposition(struct niu *np)
2512{
2513 struct niu_parent *parent = np->parent;
2514 u8 plat_type = parent->plat_type;
2515 const struct niu_phy_template *tp;
2516 u32 phy_addr_off = 0;
2517
2518 if (plat_type == PLAT_TYPE_NIU) {
e3e081e1
SB		 2519 switch (np->flags &
2520 (NIU_FLAGS_10G |
2521 NIU_FLAGS_FIBER |
2522 NIU_FLAGS_XCVR_SERDES)) {
2523 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2524 /* 10G Serdes */
2525 tp = &phy_template_niu_10g_serdes;
2526 break;
2527 case NIU_FLAGS_XCVR_SERDES:
2528 /* 1G Serdes */
2529 tp = &phy_template_niu_1g_serdes;
2530 break;
2531 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2532 /* 10G Fiber */
2533 default:
9c5cd670
TC		 2534 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2535 tp = &phy_template_niu_10g_hotplug;
2536 if (np->port == 0)
2537 phy_addr_off = 8;
2538 if (np->port == 1)
2539 phy_addr_off = 12;
2540 } else {
2541 tp = &phy_template_niu_10g_fiber;
2542 phy_addr_off += np->port;
2543 }
e3e081e1
SB		 2544 break;
2545 }
a3138df9 2546 } else {
5fbd7e24
MW		 2547 switch (np->flags &
2548 (NIU_FLAGS_10G |
2549 NIU_FLAGS_FIBER |
2550 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 2551 case 0:
2552 /* 1G copper */
2553 tp = &phy_template_1g_copper;
2554 if (plat_type == PLAT_TYPE_VF_P0)
2555 phy_addr_off = 10;
2556 else if (plat_type == PLAT_TYPE_VF_P1)
2557 phy_addr_off = 26;
2558
2559 phy_addr_off += (np->port ^ 0x3);
2560 break;
2561
2562 case NIU_FLAGS_10G:
2563 /* 10G copper */
e0d8496a 2564 tp = &phy_template_10g_copper;
a3138df9
DM		 2565 break;
2566
2567 case NIU_FLAGS_FIBER:
2568 /* 1G fiber */
2569 tp = &phy_template_1g_fiber;
2570 break;
2571
2572 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2573 /* 10G fiber */
2574 tp = &phy_template_10g_fiber;
2575 if (plat_type == PLAT_TYPE_VF_P0 ||
2576 plat_type == PLAT_TYPE_VF_P1)
2577 phy_addr_off = 8;
2578 phy_addr_off += np->port;
a5d6ab56
MW		 2579 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2580 tp = &phy_template_10g_fiber_hotplug;
2581 if (np->port == 0)
2582 phy_addr_off = 8;
2583 if (np->port == 1)
2584 phy_addr_off = 12;
2585 }
a3138df9
DM		 2586 break;
2587
5fbd7e24
MW		 2588 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2589 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2590 case NIU_FLAGS_XCVR_SERDES:
2591 switch(np->port) {
2592 case 0:
2593 case 1:
2594 tp = &phy_template_10g_serdes;
2595 break;
2596 case 2:
2597 case 3:
2598 tp = &phy_template_1g_rgmii;
2599 break;
2600 default:
2601 return -EINVAL;
2602 break;
2603 }
2604 phy_addr_off = niu_atca_port_num[np->port];
2605 break;
2606
a3138df9
DM		 2607 default:
2608 return -EINVAL;
2609 }
2610 }
2611
2612 np->phy_ops = tp->ops;
2613 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2614
2615 return 0;
2616}
2617
2618static int niu_init_link(struct niu *np)
2619{
2620 struct niu_parent *parent = np->parent;
2621 int err, ignore;
2622
2623 if (parent->plat_type == PLAT_TYPE_NIU) {
2624 err = niu_xcvr_init(np);
2625 if (err)
2626 return err;
2627 msleep(200);
2628 }
2629 err = niu_serdes_init(np);
9c5cd670 2630 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2631 return err;
2632 msleep(200);
2633 err = niu_xcvr_init(np);
9c5cd670 2634 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2635 niu_link_status(np, &ignore);
2636 return 0;
2637}
2638
2639static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2640{
2641 u16 reg0 = addr[4] << 8 | addr[5];
2642 u16 reg1 = addr[2] << 8 | addr[3];
2643 u16 reg2 = addr[0] << 8 | addr[1];
2644
2645 if (np->flags & NIU_FLAGS_XMAC) {
2646 nw64_mac(XMAC_ADDR0, reg0);
2647 nw64_mac(XMAC_ADDR1, reg1);
2648 nw64_mac(XMAC_ADDR2, reg2);
2649 } else {
2650 nw64_mac(BMAC_ADDR0, reg0);
2651 nw64_mac(BMAC_ADDR1, reg1);
2652 nw64_mac(BMAC_ADDR2, reg2);
2653 }
2654}
2655
2656static int niu_num_alt_addr(struct niu *np)
2657{
2658 if (np->flags & NIU_FLAGS_XMAC)
2659 return XMAC_NUM_ALT_ADDR;
2660 else
2661 return BMAC_NUM_ALT_ADDR;
2662}
2663
2664static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2665{
2666 u16 reg0 = addr[4] << 8 | addr[5];
2667 u16 reg1 = addr[2] << 8 | addr[3];
2668 u16 reg2 = addr[0] << 8 | addr[1];
2669
2670 if (index >= niu_num_alt_addr(np))
2671 return -EINVAL;
2672
2673 if (np->flags & NIU_FLAGS_XMAC) {
2674 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2675 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2676 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2677 } else {
2678 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2679 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2680 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2681 }
2682
2683 return 0;
2684}
2685
2686static int niu_enable_alt_mac(struct niu *np, int index, int on)
2687{
2688 unsigned long reg;
2689 u64 val, mask;
2690
2691 if (index >= niu_num_alt_addr(np))
2692 return -EINVAL;
2693
fa907895 2694 if (np->flags & NIU_FLAGS_XMAC) {
a3138df9 2695 reg = XMAC_ADDR_CMPEN;
fa907895
MW		 2696 mask = 1 << index;
2697 } else {
a3138df9 2698 reg = BMAC_ADDR_CMPEN;
fa907895
MW		 2699 mask = 1 << (index + 1);
2700 }
a3138df9
DM		 2701
2702 val = nr64_mac(reg);
2703 if (on)
2704 val |= mask;
2705 else
2706 val &= ~mask;
2707 nw64_mac(reg, val);
2708
2709 return 0;
2710}
2711
2712static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2713 int num, int mac_pref)
2714{
2715 u64 val = nr64_mac(reg);
2716 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2717 val |= num;
2718 if (mac_pref)
2719 val |= HOST_INFO_MPR;
2720 nw64_mac(reg, val);
2721}
2722
2723static int __set_rdc_table_num(struct niu *np,
2724 int xmac_index, int bmac_index,
2725 int rdc_table_num, int mac_pref)
2726{
2727 unsigned long reg;
2728
2729 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2730 return -EINVAL;
2731 if (np->flags & NIU_FLAGS_XMAC)
2732 reg = XMAC_HOST_INFO(xmac_index);
2733 else
2734 reg = BMAC_HOST_INFO(bmac_index);
2735 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2736 return 0;
2737}
2738
2739static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2740 int mac_pref)
2741{
2742 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2743}
2744
2745static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2746 int mac_pref)
2747{
2748 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2749}
2750
2751static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2752 int table_num, int mac_pref)
2753{
2754 if (idx >= niu_num_alt_addr(np))
2755 return -EINVAL;
2756 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2757}
2758
2759static u64 vlan_entry_set_parity(u64 reg_val)
2760{
2761 u64 port01_mask;
2762 u64 port23_mask;
2763
2764 port01_mask = 0x00ff;
2765 port23_mask = 0xff00;
2766
2767 if (hweight64(reg_val & port01_mask) & 1)
2768 reg_val |= ENET_VLAN_TBL_PARITY0;
2769 else
2770 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2771
2772 if (hweight64(reg_val & port23_mask) & 1)
2773 reg_val |= ENET_VLAN_TBL_PARITY1;
2774 else
2775 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2776
2777 return reg_val;
2778}
2779
2780static void vlan_tbl_write(struct niu *np, unsigned long index,
2781 int port, int vpr, int rdc_table)
2782{
2783 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2784
2785 reg_val &= ~((ENET_VLAN_TBL_VPR |
2786 ENET_VLAN_TBL_VLANRDCTBLN) <<
2787 ENET_VLAN_TBL_SHIFT(port));
2788 if (vpr)
2789 reg_val |= (ENET_VLAN_TBL_VPR <<
2790 ENET_VLAN_TBL_SHIFT(port));
2791 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2792
2793 reg_val = vlan_entry_set_parity(reg_val);
2794
2795 nw64(ENET_VLAN_TBL(index), reg_val);
2796}
2797
2798static void vlan_tbl_clear(struct niu *np)
2799{
2800 int i;
2801
2802 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2803 nw64(ENET_VLAN_TBL(i), 0);
2804}
2805
2806static int tcam_wait_bit(struct niu *np, u64 bit)
2807{
2808 int limit = 1000;
2809
2810 while (--limit > 0) {
2811 if (nr64(TCAM_CTL) & bit)
2812 break;
2813 udelay(1);
2814 }
d2a928e4 2815 if (limit <= 0)
a3138df9
DM		 2816 return -ENODEV;
2817
2818 return 0;
2819}
2820
2821static int tcam_flush(struct niu *np, int index)
2822{
2823 nw64(TCAM_KEY_0, 0x00);
2824 nw64(TCAM_KEY_MASK_0, 0xff);
2825 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2826
2827 return tcam_wait_bit(np, TCAM_CTL_STAT);
2828}
2829
2830#if 0
2831static int tcam_read(struct niu *np, int index,
2832 u64 *key, u64 *mask)
2833{
2834 int err;
2835
2836 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2837 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2838 if (!err) {
2839 key[0] = nr64(TCAM_KEY_0);
2840 key[1] = nr64(TCAM_KEY_1);
2841 key[2] = nr64(TCAM_KEY_2);
2842 key[3] = nr64(TCAM_KEY_3);
2843 mask[0] = nr64(TCAM_KEY_MASK_0);
2844 mask[1] = nr64(TCAM_KEY_MASK_1);
2845 mask[2] = nr64(TCAM_KEY_MASK_2);
2846 mask[3] = nr64(TCAM_KEY_MASK_3);
2847 }
2848 return err;
2849}
2850#endif
2851
2852static int tcam_write(struct niu *np, int index,
2853 u64 *key, u64 *mask)
2854{
2855 nw64(TCAM_KEY_0, key[0]);
2856 nw64(TCAM_KEY_1, key[1]);
2857 nw64(TCAM_KEY_2, key[2]);
2858 nw64(TCAM_KEY_3, key[3]);
2859 nw64(TCAM_KEY_MASK_0, mask[0]);
2860 nw64(TCAM_KEY_MASK_1, mask[1]);
2861 nw64(TCAM_KEY_MASK_2, mask[2]);
2862 nw64(TCAM_KEY_MASK_3, mask[3]);
2863 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2864
2865 return tcam_wait_bit(np, TCAM_CTL_STAT);
2866}
2867
2868#if 0
2869static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2870{
2871 int err;
2872
2873 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2874 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2875 if (!err)
2876 *data = nr64(TCAM_KEY_1);
2877
2878 return err;
2879}
2880#endif
2881
2882static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2883{
2884 nw64(TCAM_KEY_1, assoc_data);
2885 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2886
2887 return tcam_wait_bit(np, TCAM_CTL_STAT);
2888}
2889
2890static void tcam_enable(struct niu *np, int on)
2891{
2892 u64 val = nr64(FFLP_CFG_1);
2893
2894 if (on)
2895 val &= ~FFLP_CFG_1_TCAM_DIS;
2896 else
2897 val |= FFLP_CFG_1_TCAM_DIS;
2898 nw64(FFLP_CFG_1, val);
2899}
2900
2901static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2902{
2903 u64 val = nr64(FFLP_CFG_1);
2904
2905 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2906 FFLP_CFG_1_CAMLAT |
2907 FFLP_CFG_1_CAMRATIO);
2908 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2909 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2910 nw64(FFLP_CFG_1, val);
2911
2912 val = nr64(FFLP_CFG_1);
2913 val |= FFLP_CFG_1_FFLPINITDONE;
2914 nw64(FFLP_CFG_1, val);
2915}
2916
2917static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2918 int on)
2919{
2920 unsigned long reg;
2921 u64 val;
2922
2923 if (class < CLASS_CODE_ETHERTYPE1 ||
2924 class > CLASS_CODE_ETHERTYPE2)
2925 return -EINVAL;
2926
2927 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2928 val = nr64(reg);
2929 if (on)
2930 val |= L2_CLS_VLD;
2931 else
2932 val &= ~L2_CLS_VLD;
2933 nw64(reg, val);
2934
2935 return 0;
2936}
2937
2938#if 0
2939static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2940 u64 ether_type)
2941{
2942 unsigned long reg;
2943 u64 val;
2944
2945 if (class < CLASS_CODE_ETHERTYPE1 ||
2946 class > CLASS_CODE_ETHERTYPE2 ||
2947 (ether_type & ~(u64)0xffff) != 0)
2948 return -EINVAL;
2949
2950 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2951 val = nr64(reg);
2952 val &= ~L2_CLS_ETYPE;
2953 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2954 nw64(reg, val);
2955
2956 return 0;
2957}
2958#endif
2959
2960static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2961 int on)
2962{
2963 unsigned long reg;
2964 u64 val;
2965
2966 if (class < CLASS_CODE_USER_PROG1 ||
2967 class > CLASS_CODE_USER_PROG4)
2968 return -EINVAL;
2969
2970 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2971 val = nr64(reg);
2972 if (on)
2973 val |= L3_CLS_VALID;
2974 else
2975 val &= ~L3_CLS_VALID;
2976 nw64(reg, val);
2977
2978 return 0;
2979}
2980
a3138df9
DM		 2981static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2982 int ipv6, u64 protocol_id,
2983 u64 tos_mask, u64 tos_val)
2984{
2985 unsigned long reg;
2986 u64 val;
2987
2988 if (class < CLASS_CODE_USER_PROG1 ||
2989 class > CLASS_CODE_USER_PROG4 ||
2990 (protocol_id & ~(u64)0xff) != 0 ||
2991 (tos_mask & ~(u64)0xff) != 0 ||
2992 (tos_val & ~(u64)0xff) != 0)
2993 return -EINVAL;
2994
2995 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2996 val = nr64(reg);
2997 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2998 L3_CLS_TOSMASK | L3_CLS_TOS);
2999 if (ipv6)
3000 val |= L3_CLS_IPVER;
3001 val |= (protocol_id << L3_CLS_PID_SHIFT);
3002 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3003 val |= (tos_val << L3_CLS_TOS_SHIFT);
3004 nw64(reg, val);
3005
3006 return 0;
3007}
a3138df9
DM		 3008
3009static int tcam_early_init(struct niu *np)
3010{
3011 unsigned long i;
3012 int err;
3013
3014 tcam_enable(np, 0);
3015 tcam_set_lat_and_ratio(np,
3016 DEFAULT_TCAM_LATENCY,
3017 DEFAULT_TCAM_ACCESS_RATIO);
3018 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3019 err = tcam_user_eth_class_enable(np, i, 0);
3020 if (err)
3021 return err;
3022 }
3023 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3024 err = tcam_user_ip_class_enable(np, i, 0);
3025 if (err)
3026 return err;
3027 }
3028
3029 return 0;
3030}
3031
3032static int tcam_flush_all(struct niu *np)
3033{
3034 unsigned long i;
3035
3036 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3037 int err = tcam_flush(np, i);
3038 if (err)
3039 return err;
3040 }
3041 return 0;
3042}
3043
3044static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3045{
3046 return ((u64)index | (num_entries == 1 ?
3047 HASH_TBL_ADDR_AUTOINC : 0));
3048}
3049
3050#if 0
3051static int hash_read(struct niu *np, unsigned long partition,
3052 unsigned long index, unsigned long num_entries,
3053 u64 *data)
3054{
3055 u64 val = hash_addr_regval(index, num_entries);
3056 unsigned long i;
3057
3058 if (partition >= FCRAM_NUM_PARTITIONS ||
3059 index + num_entries > FCRAM_SIZE)
3060 return -EINVAL;
3061
3062 nw64(HASH_TBL_ADDR(partition), val);
3063 for (i = 0; i < num_entries; i++)
3064 data[i] = nr64(HASH_TBL_DATA(partition));
3065
3066 return 0;
3067}
3068#endif
3069
3070static int hash_write(struct niu *np, unsigned long partition,
3071 unsigned long index, unsigned long num_entries,
3072 u64 *data)
3073{
3074 u64 val = hash_addr_regval(index, num_entries);
3075 unsigned long i;
3076
3077 if (partition >= FCRAM_NUM_PARTITIONS ||
3078 index + (num_entries * 8) > FCRAM_SIZE)
3079 return -EINVAL;
3080
3081 nw64(HASH_TBL_ADDR(partition), val);
3082 for (i = 0; i < num_entries; i++)
3083 nw64(HASH_TBL_DATA(partition), data[i]);
3084
3085 return 0;
3086}
3087
3088static void fflp_reset(struct niu *np)
3089{
3090 u64 val;
3091
3092 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3093 udelay(10);
3094 nw64(FFLP_CFG_1, 0);
3095
3096 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3097 nw64(FFLP_CFG_1, val);
3098}
3099
3100static void fflp_set_timings(struct niu *np)
3101{
3102 u64 val = nr64(FFLP_CFG_1);
3103
3104 val &= ~FFLP_CFG_1_FFLPINITDONE;
3105 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3106 nw64(FFLP_CFG_1, val);
3107
3108 val = nr64(FFLP_CFG_1);
3109 val |= FFLP_CFG_1_FFLPINITDONE;
3110 nw64(FFLP_CFG_1, val);
3111
3112 val = nr64(FCRAM_REF_TMR);
3113 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3114 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3115 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3116 nw64(FCRAM_REF_TMR, val);
3117}
3118
3119static int fflp_set_partition(struct niu *np, u64 partition,
3120 u64 mask, u64 base, int enable)
3121{
3122 unsigned long reg;
3123 u64 val;
3124
3125 if (partition >= FCRAM_NUM_PARTITIONS ||
3126 (mask & ~(u64)0x1f) != 0 ||
3127 (base & ~(u64)0x1f) != 0)
3128 return -EINVAL;
3129
3130 reg = FLW_PRT_SEL(partition);
3131
3132 val = nr64(reg);
3133 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3134 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3135 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3136 if (enable)
3137 val |= FLW_PRT_SEL_EXT;
3138 nw64(reg, val);
3139
3140 return 0;
3141}
3142
3143static int fflp_disable_all_partitions(struct niu *np)
3144{
3145 unsigned long i;
3146
3147 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3148 int err = fflp_set_partition(np, 0, 0, 0, 0);
3149 if (err)
3150 return err;
3151 }
3152 return 0;
3153}
3154
3155static void fflp_llcsnap_enable(struct niu *np, int on)
3156{
3157 u64 val = nr64(FFLP_CFG_1);
3158
3159 if (on)
3160 val |= FFLP_CFG_1_LLCSNAP;
3161 else
3162 val &= ~FFLP_CFG_1_LLCSNAP;
3163 nw64(FFLP_CFG_1, val);
3164}
3165
3166static void fflp_errors_enable(struct niu *np, int on)
3167{
3168 u64 val = nr64(FFLP_CFG_1);
3169
3170 if (on)
3171 val &= ~FFLP_CFG_1_ERRORDIS;
3172 else
3173 val |= FFLP_CFG_1_ERRORDIS;
3174 nw64(FFLP_CFG_1, val);
3175}
3176
3177static int fflp_hash_clear(struct niu *np)
3178{
3179 struct fcram_hash_ipv4 ent;
3180 unsigned long i;
3181
3182 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3183 memset(&ent, 0, sizeof(ent));
3184 ent.header = HASH_HEADER_EXT;
3185
3186 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3187 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3188 if (err)
3189 return err;
3190 }
3191 return 0;
3192}
3193
3194static int fflp_early_init(struct niu *np)
3195{
3196 struct niu_parent *parent;
3197 unsigned long flags;
3198 int err;
3199
3200 niu_lock_parent(np, flags);
3201
3202 parent = np->parent;
3203 err = 0;
3204 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
a3138df9
DM		 3205 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3206 fflp_reset(np);
3207 fflp_set_timings(np);
3208 err = fflp_disable_all_partitions(np);
3209 if (err) {
f10a1f2e
JP		 3210 netif_printk(np, probe, KERN_DEBUG, np->dev,
3211 "fflp_disable_all_partitions failed, err=%d\n",
3212 err);
a3138df9
DM		 3213 goto out;
3214 }
3215 }
3216
3217 err = tcam_early_init(np);
3218 if (err) {
f10a1f2e
JP		 3219 netif_printk(np, probe, KERN_DEBUG, np->dev,
3220 "tcam_early_init failed, err=%d\n", err);
a3138df9
DM		 3221 goto out;
3222 }
3223 fflp_llcsnap_enable(np, 1);
3224 fflp_errors_enable(np, 0);
3225 nw64(H1POLY, 0);
3226 nw64(H2POLY, 0);
3227
3228 err = tcam_flush_all(np);
3229 if (err) {
f10a1f2e
JP		 3230 netif_printk(np, probe, KERN_DEBUG, np->dev,
3231 "tcam_flush_all failed, err=%d\n", err);
a3138df9
DM		 3232 goto out;
3233 }
3234 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3235 err = fflp_hash_clear(np);
3236 if (err) {
f10a1f2e
JP		 3237 netif_printk(np, probe, KERN_DEBUG, np->dev,
3238 "fflp_hash_clear failed, err=%d\n",
3239 err);
a3138df9
DM		 3240 goto out;
3241 }
3242 }
3243
3244 vlan_tbl_clear(np);
3245
a3138df9
DM		 3246 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3247 }
3248out:
3249 niu_unlock_parent(np, flags);
3250 return err;
3251}
3252
3253static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3254{
3255 if (class_code < CLASS_CODE_USER_PROG1 ||
3256 class_code > CLASS_CODE_SCTP_IPV6)
3257 return -EINVAL;
3258
3259 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3260 return 0;
3261}
3262
3263static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3264{
3265 if (class_code < CLASS_CODE_USER_PROG1 ||
3266 class_code > CLASS_CODE_SCTP_IPV6)
3267 return -EINVAL;
3268
3269 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3270 return 0;
3271}
3272
2d96cf8c
SB		 3273/* Entries for the ports are interleaved in the TCAM */
3274static u16 tcam_get_index(struct niu *np, u16 idx)
3275{
3276 /* One entry reserved for IP fragment rule */
3277 if (idx >= (np->clas.tcam_sz - 1))
3278 idx = 0;
3279 return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3280}
3281
3282static u16 tcam_get_size(struct niu *np)
3283{
3284 /* One entry reserved for IP fragment rule */
3285 return np->clas.tcam_sz - 1;
3286}
3287
3288static u16 tcam_get_valid_entry_cnt(struct niu *np)
3289{
3290 /* One entry reserved for IP fragment rule */
3291 return np->clas.tcam_valid_entries - 1;
3292}
3293
a3138df9
DM		 3294static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3295 u32 offset, u32 size)
3296{
3297 int i = skb_shinfo(skb)->nr_frags;
3298 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3299
3300 frag->page = page;
3301 frag->page_offset = offset;
3302 frag->size = size;
3303
3304 skb->len += size;
3305 skb->data_len += size;
3306 skb->truesize += size;
3307
3308 skb_shinfo(skb)->nr_frags = i + 1;
3309}
3310
3311static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3312{
3313 a >>= PAGE_SHIFT;
3314 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3315
3316 return (a & (MAX_RBR_RING_SIZE - 1));
3317}
3318
3319static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3320 struct page ***link)
3321{
3322 unsigned int h = niu_hash_rxaddr(rp, addr);
3323 struct page *p, **pp;
3324
3325 addr &= PAGE_MASK;
3326 pp = &rp->rxhash[h];
3327 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3328 if (p->index == addr) {
3329 *link = pp;
3330 break;
3331 }
3332 }
3333
3334 return p;
3335}
3336
3337static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3338{
3339 unsigned int h = niu_hash_rxaddr(rp, base);
3340
3341 page->index = base;
3342 page->mapping = (struct address_space *) rp->rxhash[h];
3343 rp->rxhash[h] = page;
3344}
3345
3346static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3347 gfp_t mask, int start_index)
3348{
3349 struct page *page;
3350 u64 addr;
3351 int i;
3352
3353 page = alloc_page(mask);
3354 if (!page)
3355 return -ENOMEM;
3356
3357 addr = np->ops->map_page(np->device, page, 0,
3358 PAGE_SIZE, DMA_FROM_DEVICE);
3359
3360 niu_hash_page(rp, page, addr);
3361 if (rp->rbr_blocks_per_page > 1)
3362 atomic_add(rp->rbr_blocks_per_page - 1,
3363 &compound_head(page)->_count);
3364
3365 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3366 __le32 *rbr = &rp->rbr[start_index + i];
3367
3368 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3369 addr += rp->rbr_block_size;
3370 }
3371
3372 return 0;
3373}
3374
3375static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3376{
3377 int index = rp->rbr_index;
3378
3379 rp->rbr_pending++;
3380 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3381 int err = niu_rbr_add_page(np, rp, mask, index);
3382
3383 if (unlikely(err)) {
3384 rp->rbr_pending--;
3385 return;
3386 }
3387
3388 rp->rbr_index += rp->rbr_blocks_per_page;
3389 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3390 if (rp->rbr_index == rp->rbr_table_size)
3391 rp->rbr_index = 0;
3392
3393 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3394 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3395 rp->rbr_pending = 0;
3396 }
3397 }
3398}
3399
3400static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3401{
3402 unsigned int index = rp->rcr_index;
3403 int num_rcr = 0;
3404
3405 rp->rx_dropped++;
3406 while (1) {
3407 struct page *page, **link;
3408 u64 addr, val;
3409 u32 rcr_size;
3410
3411 num_rcr++;
3412
3413 val = le64_to_cpup(&rp->rcr[index]);
3414 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3415 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3416 page = niu_find_rxpage(rp, addr, &link);
3417
3418 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3419 RCR_ENTRY_PKTBUFSZ_SHIFT];
3420 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3421 *link = (struct page *) page->mapping;
3422 np->ops->unmap_page(np->device, page->index,
3423 PAGE_SIZE, DMA_FROM_DEVICE);
3424 page->index = 0;
3425 page->mapping = NULL;
3426 __free_page(page);
3427 rp->rbr_refill_pending++;
3428 }
3429
3430 index = NEXT_RCR(rp, index);
3431 if (!(val & RCR_ENTRY_MULTI))
3432 break;
3433
3434 }
3435 rp->rcr_index = index;
3436
3437 return num_rcr;
3438}
3439
4099e012
DM		 3440static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3441 struct rx_ring_info *rp)
a3138df9
DM		 3442{
3443 unsigned int index = rp->rcr_index;
3cfa856d 3444 struct rx_pkt_hdr1 *rh;
a3138df9
DM		 3445 struct sk_buff *skb;
3446 int len, num_rcr;
3447
3448 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3449 if (unlikely(!skb))
3450 return niu_rx_pkt_ignore(np, rp);
3451
3452 num_rcr = 0;
3453 while (1) {
3454 struct page *page, **link;
3455 u32 rcr_size, append_size;
3456 u64 addr, val, off;
3457
3458 num_rcr++;
3459
3460 val = le64_to_cpup(&rp->rcr[index]);
3461
3462 len = (val & RCR_ENTRY_L2_LEN) >>
3463 RCR_ENTRY_L2_LEN_SHIFT;
3464 len -= ETH_FCS_LEN;
3465
3466 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3467 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3468 page = niu_find_rxpage(rp, addr, &link);
3469
3470 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3471 RCR_ENTRY_PKTBUFSZ_SHIFT];
3472
3473 off = addr & ~PAGE_MASK;
3474 append_size = rcr_size;
3475 if (num_rcr == 1) {
3476 int ptype;
3477
a3138df9
DM		 3478 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3479 if ((ptype == RCR_PKT_TYPE_TCP ||
3480 ptype == RCR_PKT_TYPE_UDP) &&
3481 !(val & (RCR_ENTRY_NOPORT |
3482 RCR_ENTRY_ERROR)))
3483 skb->ip_summed = CHECKSUM_UNNECESSARY;
3484 else
3485 skb->ip_summed = CHECKSUM_NONE;
3cfa856d 3486 } else if (!(val & RCR_ENTRY_MULTI))
a3138df9
DM		 3487 append_size = len - skb->len;
3488
3489 niu_rx_skb_append(skb, page, off, append_size);
3490 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3491 *link = (struct page *) page->mapping;
3492 np->ops->unmap_page(np->device, page->index,
3493 PAGE_SIZE, DMA_FROM_DEVICE);
3494 page->index = 0;
3495 page->mapping = NULL;
3496 rp->rbr_refill_pending++;
3497 } else
3498 get_page(page);
3499
3500 index = NEXT_RCR(rp, index);
3501 if (!(val & RCR_ENTRY_MULTI))
3502 break;
3503
3504 }
3505 rp->rcr_index = index;
3506
3cfa856d
DM		 3507 len += sizeof(*rh);
3508 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3509 __pskb_pull_tail(skb, len);
3510
3511 rh = (struct rx_pkt_hdr1 *) skb->data;
3512 if (np->dev->features & NETIF_F_RXHASH)
3513 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3514 (u32)rh->hashval2_1 << 16 |
3515 (u32)rh->hashval1_1 << 8 |
3516 (u32)rh->hashval1_2 << 0);
3517 skb_pull(skb, sizeof(*rh));
a3138df9
DM		 3518
3519 rp->rx_packets++;
3520 rp->rx_bytes += skb->len;
3521
3522 skb->protocol = eth_type_trans(skb, np->dev);
0c8dfc83 3523 skb_record_rx_queue(skb, rp->rx_channel);
4099e012 3524 napi_gro_receive(napi, skb);
a3138df9
DM		 3525
3526 return num_rcr;
3527}
3528
3529static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3530{
3531 int blocks_per_page = rp->rbr_blocks_per_page;
3532 int err, index = rp->rbr_index;
3533
3534 err = 0;
3535 while (index < (rp->rbr_table_size - blocks_per_page)) {
3536 err = niu_rbr_add_page(np, rp, mask, index);
3537 if (err)
3538 break;
3539
3540 index += blocks_per_page;
3541 }
3542
3543 rp->rbr_index = index;
3544 return err;
3545}
3546
3547static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3548{
3549 int i;
3550
3551 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3552 struct page *page;
3553
3554 page = rp->rxhash[i];
3555 while (page) {
3556 struct page *next = (struct page *) page->mapping;
3557 u64 base = page->index;
3558
3559 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3560 DMA_FROM_DEVICE);
3561 page->index = 0;
3562 page->mapping = NULL;
3563
3564 __free_page(page);
3565
3566 page = next;
3567 }
3568 }
3569
3570 for (i = 0; i < rp->rbr_table_size; i++)
3571 rp->rbr[i] = cpu_to_le32(0);
3572 rp->rbr_index = 0;
3573}
3574
3575static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3576{
3577 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3578 struct sk_buff *skb = tb->skb;
3579 struct tx_pkt_hdr *tp;
3580 u64 tx_flags;
3581 int i, len;
3582
3583 tp = (struct tx_pkt_hdr *) skb->data;
3584 tx_flags = le64_to_cpup(&tp->flags);
3585
3586 rp->tx_packets++;
3587 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3588 ((tx_flags & TXHDR_PAD) / 2));
3589
3590 len = skb_headlen(skb);
3591 np->ops->unmap_single(np->device, tb->mapping,
3592 len, DMA_TO_DEVICE);
3593
3594 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3595 rp->mark_pending--;
3596
3597 tb->skb = NULL;
3598 do {
3599 idx = NEXT_TX(rp, idx);
3600 len -= MAX_TX_DESC_LEN;
3601 } while (len > 0);
3602
3603 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3604 tb = &rp->tx_buffs[idx];
3605 BUG_ON(tb->skb != NULL);
3606 np->ops->unmap_page(np->device, tb->mapping,
3607 skb_shinfo(skb)->frags[i].size,
3608 DMA_TO_DEVICE);
3609 idx = NEXT_TX(rp, idx);
3610 }
3611
3612 dev_kfree_skb(skb);
3613
3614 return idx;
3615}
3616
3617#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3618
3619static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3620{
b4c21639 3621 struct netdev_queue *txq;
a3138df9 3622 u16 pkt_cnt, tmp;
b4c21639 3623 int cons, index;
a3138df9
DM		 3624 u64 cs;
3625
b4c21639
DM		 3626 index = (rp - np->tx_rings);
3627 txq = netdev_get_tx_queue(np->dev, index);
3628
a3138df9
DM		 3629 cs = rp->tx_cs;
3630 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3631 goto out;
3632
3633 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3634 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3635 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3636
3637 rp->last_pkt_cnt = tmp;
3638
3639 cons = rp->cons;
3640
f10a1f2e
JP		 3641 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3642 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
a3138df9
DM		 3643
3644 while (pkt_cnt--)
3645 cons = release_tx_packet(np, rp, cons);
3646
3647 rp->cons = cons;
3648 smp_mb();
3649
3650out:
b4c21639 3651 if (unlikely(netif_tx_queue_stopped(txq) &&
a3138df9 3652 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
b4c21639
DM		 3653 __netif_tx_lock(txq, smp_processor_id());
3654 if (netif_tx_queue_stopped(txq) &&
a3138df9 3655 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
b4c21639
DM		 3656 netif_tx_wake_queue(txq);
3657 __netif_tx_unlock(txq);
a3138df9
DM		 3658 }
3659}
3660
b8a606b8
JDB		 3661static inline void niu_sync_rx_discard_stats(struct niu *np,
3662 struct rx_ring_info *rp,
3663 const int limit)
3664{
3665 /* This elaborate scheme is needed for reading the RX discard
3666 * counters, as they are only 16-bit and can overflow quickly,
3667 * and because the overflow indication bit is not usable as
3668 * the counter value does not wrap, but remains at max value
3669 * 0xFFFF.
3670 *
3671 * In theory and in practice counters can be lost in between
3672 * reading nr64() and clearing the counter nw64(). For this
3673 * reason, the number of counter clearings nw64() is
3674 * limited/reduced though the limit parameter.
3675 */
3676 int rx_channel = rp->rx_channel;
3677 u32 misc, wred;
3678
3679 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3680 * following discard events: IPP (Input Port Process),
3681 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3682 * Block Ring) prefetch buffer is empty.
3683 */
3684 misc = nr64(RXMISC(rx_channel));
3685 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3686 nw64(RXMISC(rx_channel), 0);
3687 rp->rx_errors += misc & RXMISC_COUNT;
3688
3689 if (unlikely(misc & RXMISC_OFLOW))
f10a1f2e
JP		 3690 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3691 rx_channel);
d231776f 3692
f10a1f2e
JP		 3693 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3694 "rx-%d: MISC drop=%u over=%u\n",
3695 rx_channel, misc, misc-limit);
b8a606b8
JDB		 3696 }
3697
3698 /* WRED (Weighted Random Early Discard) by hardware */
3699 wred = nr64(RED_DIS_CNT(rx_channel));
3700 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3701 nw64(RED_DIS_CNT(rx_channel), 0);
3702 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3703
3704 if (unlikely(wred & RED_DIS_CNT_OFLOW))
f10a1f2e 3705 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
d231776f 3706
f10a1f2e
JP		 3707 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3708 "rx-%d: WRED drop=%u over=%u\n",
3709 rx_channel, wred, wred-limit);
b8a606b8
JDB		 3710 }
3711}
3712
4099e012
DM		 3713static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3714 struct rx_ring_info *rp, int budget)
a3138df9
DM		 3715{
3716 int qlen, rcr_done = 0, work_done = 0;
3717 struct rxdma_mailbox *mbox = rp->mbox;
3718 u64 stat;
3719
3720#if 1
3721 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3722 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3723#else
3724 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3725 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3726#endif
3727 mbox->rx_dma_ctl_stat = 0;
3728 mbox->rcrstat_a = 0;
3729
f10a1f2e
JP		 3730 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3731 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3732 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
a3138df9
DM		 3733
3734 rcr_done = work_done = 0;
3735 qlen = min(qlen, budget);
3736 while (work_done < qlen) {
4099e012 3737 rcr_done += niu_process_rx_pkt(napi, np, rp);
a3138df9
DM		 3738 work_done++;
3739 }
3740
3741 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3742 unsigned int i;
3743
3744 for (i = 0; i < rp->rbr_refill_pending; i++)
3745 niu_rbr_refill(np, rp, GFP_ATOMIC);
3746 rp->rbr_refill_pending = 0;
3747 }
3748
3749 stat = (RX_DMA_CTL_STAT_MEX |
3750 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3751 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3752
3753 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3754
e98def1f
JDB		 3755 /* Only sync discards stats when qlen indicate potential for drops */
3756 if (qlen > 10)
3757 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
b8a606b8 3758
a3138df9
DM		 3759 return work_done;
3760}
3761
3762static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3763{
3764 u64 v0 = lp->v0;
3765 u32 tx_vec = (v0 >> 32);
3766 u32 rx_vec = (v0 & 0xffffffff);
3767 int i, work_done = 0;
3768
f10a1f2e
JP		 3769 netif_printk(np, intr, KERN_DEBUG, np->dev,
3770 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
a3138df9
DM		 3771
3772 for (i = 0; i < np->num_tx_rings; i++) {
3773 struct tx_ring_info *rp = &np->tx_rings[i];
3774 if (tx_vec & (1 << rp->tx_channel))
3775 niu_tx_work(np, rp);
3776 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3777 }
3778
3779 for (i = 0; i < np->num_rx_rings; i++) {
3780 struct rx_ring_info *rp = &np->rx_rings[i];
3781
3782 if (rx_vec & (1 << rp->rx_channel)) {
3783 int this_work_done;
3784
4099e012 3785 this_work_done = niu_rx_work(&lp->napi, np, rp,
a3138df9
DM		 3786 budget);
3787
3788 budget -= this_work_done;
3789 work_done += this_work_done;
3790 }
3791 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3792 }
3793
3794 return work_done;
3795}
3796
3797static int niu_poll(struct napi_struct *napi, int budget)
3798{
3799 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3800 struct niu *np = lp->np;
3801 int work_done;
3802
3803 work_done = niu_poll_core(np, lp, budget);
3804
3805 if (work_done < budget) {
288379f0 3806 napi_complete(napi);
a3138df9
DM		 3807 niu_ldg_rearm(np, lp, 1);
3808 }
3809 return work_done;
3810}
3811
3812static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3813 u64 stat)
3814{
f10a1f2e 3815 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
a3138df9
DM		 3816
3817 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
f10a1f2e 3818 pr_cont("RBR_TMOUT ");
a3138df9 3819 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
f10a1f2e 3820 pr_cont("RSP_CNT ");
a3138df9 3821 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
f10a1f2e 3822 pr_cont("BYTE_EN_BUS ");
a3138df9 3823 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
f10a1f2e 3824 pr_cont("RSP_DAT ");
a3138df9 3825 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
f10a1f2e 3826 pr_cont("RCR_ACK ");
a3138df9 3827 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
f10a1f2e 3828 pr_cont("RCR_SHA_PAR ");
a3138df9 3829 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
f10a1f2e 3830 pr_cont("RBR_PRE_PAR ");
a3138df9 3831 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
f10a1f2e 3832 pr_cont("CONFIG ");
a3138df9 3833 if (stat & RX_DMA_CTL_STAT_RCRINCON)
f10a1f2e 3834 pr_cont("RCRINCON ");
a3138df9 3835 if (stat & RX_DMA_CTL_STAT_RCRFULL)
f10a1f2e 3836 pr_cont("RCRFULL ");
a3138df9 3837 if (stat & RX_DMA_CTL_STAT_RBRFULL)
f10a1f2e 3838 pr_cont("RBRFULL ");
a3138df9 3839 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
f10a1f2e 3840 pr_cont("RBRLOGPAGE ");
a3138df9 3841 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
f10a1f2e 3842 pr_cont("CFIGLOGPAGE ");
a3138df9 3843 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
f10a1f2e 3844 pr_cont("DC_FIDO ");
a3138df9 3845
f10a1f2e 3846 pr_cont(")\n");
a3138df9
DM		 3847}
3848
3849static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3850{
3851 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3852 int err = 0;
3853
a3138df9
DM		 3854
3855 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3856 RX_DMA_CTL_STAT_PORT_FATAL))
3857 err = -EINVAL;
3858
406f353c 3859 if (err) {
f10a1f2e
JP		 3860 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3861 rp->rx_channel,
3862 (unsigned long long) stat);
406f353c
MW		 3863
3864 niu_log_rxchan_errors(np, rp, stat);
3865 }
3866
a3138df9
DM		 3867 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3868 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3869
3870 return err;
3871}
3872
3873static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3874 u64 cs)
3875{
f10a1f2e 3876 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
a3138df9
DM		 3877
3878 if (cs & TX_CS_MBOX_ERR)
f10a1f2e 3879 pr_cont("MBOX ");
a3138df9 3880 if (cs & TX_CS_PKT_SIZE_ERR)
f10a1f2e 3881 pr_cont("PKT_SIZE ");
a3138df9 3882 if (cs & TX_CS_TX_RING_OFLOW)
f10a1f2e 3883 pr_cont("TX_RING_OFLOW ");
a3138df9 3884 if (cs & TX_CS_PREF_BUF_PAR_ERR)
f10a1f2e 3885 pr_cont("PREF_BUF_PAR ");
a3138df9 3886 if (cs & TX_CS_NACK_PREF)
f10a1f2e 3887 pr_cont("NACK_PREF ");
a3138df9 3888 if (cs & TX_CS_NACK_PKT_RD)
f10a1f2e 3889 pr_cont("NACK_PKT_RD ");
a3138df9 3890 if (cs & TX_CS_CONF_PART_ERR)
f10a1f2e 3891 pr_cont("CONF_PART ");
a3138df9 3892 if (cs & TX_CS_PKT_PRT_ERR)
f10a1f2e 3893 pr_cont("PKT_PTR ");
a3138df9 3894
f10a1f2e 3895 pr_cont(")\n");
a3138df9
DM		 3896}
3897
3898static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3899{
3900 u64 cs, logh, logl;
3901
3902 cs = nr64(TX_CS(rp->tx_channel));
3903 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3904 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3905
f10a1f2e
JP		 3906 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3907 rp->tx_channel,
3908 (unsigned long long)cs,
3909 (unsigned long long)logh,
3910 (unsigned long long)logl);
a3138df9
DM		 3911
3912 niu_log_txchan_errors(np, rp, cs);
3913
3914 return -ENODEV;
3915}
3916
3917static int niu_mif_interrupt(struct niu *np)
3918{
3919 u64 mif_status = nr64(MIF_STATUS);
3920 int phy_mdint = 0;
3921
3922 if (np->flags & NIU_FLAGS_XMAC) {
3923 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3924
3925 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3926 phy_mdint = 1;
3927 }
3928
f10a1f2e
JP		 3929 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3930 (unsigned long long)mif_status, phy_mdint);
a3138df9
DM		 3931
3932 return -ENODEV;
3933}
3934
3935static void niu_xmac_interrupt(struct niu *np)
3936{
3937 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3938 u64 val;
3939
3940 val = nr64_mac(XTXMAC_STATUS);
3941 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3942 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3943 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3944 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3945 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3946 mp->tx_fifo_errors++;
3947 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3948 mp->tx_overflow_errors++;
3949 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3950 mp->tx_max_pkt_size_errors++;
3951 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3952 mp->tx_underflow_errors++;
3953
3954 val = nr64_mac(XRXMAC_STATUS);
3955 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3956 mp->rx_local_faults++;
3957 if (val & XRXMAC_STATUS_RFLT_DET)
3958 mp->rx_remote_faults++;
3959 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3960 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3961 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3962 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3963 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3964 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3965 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3966 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3967 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3968 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3969 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3970 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3971 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3972 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3973 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3974 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3975 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3976 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3977 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3978 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3979 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3980 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3981 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3982 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3983 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3984 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
176edd52 3985 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
a3138df9
DM		 3986 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3987 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3988 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3989 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3990 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3991 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3992 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3993 if (val & XRXMAC_STATUS_RXUFLOW)
3994 mp->rx_underflows++;
3995 if (val & XRXMAC_STATUS_RXOFLOW)
3996 mp->rx_overflows++;
3997
3998 val = nr64_mac(XMAC_FC_STAT);
3999 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4000 mp->pause_off_state++;
4001 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4002 mp->pause_on_state++;
4003 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4004 mp->pause_received++;
4005}
4006
4007static void niu_bmac_interrupt(struct niu *np)
4008{
4009 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4010 u64 val;
4011
4012 val = nr64_mac(BTXMAC_STATUS);
4013 if (val & BTXMAC_STATUS_UNDERRUN)
4014 mp->tx_underflow_errors++;
4015 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4016 mp->tx_max_pkt_size_errors++;
4017 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4018 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4019 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4020 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4021
4022 val = nr64_mac(BRXMAC_STATUS);
4023 if (val & BRXMAC_STATUS_OVERFLOW)
4024 mp->rx_overflows++;
4025 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4026 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4027 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4028 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4029 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4030 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4031 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4032 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4033
4034 val = nr64_mac(BMAC_CTRL_STATUS);
4035 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4036 mp->pause_off_state++;
4037 if (val & BMAC_CTRL_STATUS_PAUSE)
4038 mp->pause_on_state++;
4039 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4040 mp->pause_received++;
4041}
4042
4043static int niu_mac_interrupt(struct niu *np)
4044{
4045 if (np->flags & NIU_FLAGS_XMAC)
4046 niu_xmac_interrupt(np);
4047 else
4048 niu_bmac_interrupt(np);
4049
4050 return 0;
4051}
4052
4053static void niu_log_device_error(struct niu *np, u64 stat)
4054{
f10a1f2e 4055 netdev_err(np->dev, "Core device errors ( ");
a3138df9
DM		 4056
4057 if (stat & SYS_ERR_MASK_META2)
f10a1f2e 4058 pr_cont("META2 ");
a3138df9 4059 if (stat & SYS_ERR_MASK_META1)
f10a1f2e 4060 pr_cont("META1 ");
a3138df9 4061 if (stat & SYS_ERR_MASK_PEU)
f10a1f2e 4062 pr_cont("PEU ");
a3138df9 4063 if (stat & SYS_ERR_MASK_TXC)
f10a1f2e 4064 pr_cont("TXC ");
a3138df9 4065 if (stat & SYS_ERR_MASK_RDMC)
f10a1f2e 4066 pr_cont("RDMC ");
a3138df9 4067 if (stat & SYS_ERR_MASK_TDMC)
f10a1f2e 4068 pr_cont("TDMC ");
a3138df9 4069 if (stat & SYS_ERR_MASK_ZCP)
f10a1f2e 4070 pr_cont("ZCP ");
a3138df9 4071 if (stat & SYS_ERR_MASK_FFLP)
f10a1f2e 4072 pr_cont("FFLP ");
a3138df9 4073 if (stat & SYS_ERR_MASK_IPP)
f10a1f2e 4074 pr_cont("IPP ");
a3138df9 4075 if (stat & SYS_ERR_MASK_MAC)
f10a1f2e 4076 pr_cont("MAC ");
a3138df9 4077 if (stat & SYS_ERR_MASK_SMX)
f10a1f2e 4078 pr_cont("SMX ");
a3138df9 4079
f10a1f2e 4080 pr_cont(")\n");
a3138df9
DM		 4081}
4082
4083static int niu_device_error(struct niu *np)
4084{
4085 u64 stat = nr64(SYS_ERR_STAT);
4086
f10a1f2e
JP		 4087 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4088 (unsigned long long)stat);
a3138df9
DM		 4089
4090 niu_log_device_error(np, stat);
4091
4092 return -ENODEV;
4093}
4094
406f353c
MW		 4095static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4096 u64 v0, u64 v1, u64 v2)
a3138df9 4097{
406f353c 4098
a3138df9
DM		 4099 int i, err = 0;
4100
406f353c
MW		 4101 lp->v0 = v0;
4102 lp->v1 = v1;
4103 lp->v2 = v2;
4104
a3138df9
DM		 4105 if (v1 & 0x00000000ffffffffULL) {
4106 u32 rx_vec = (v1 & 0xffffffff);
4107
4108 for (i = 0; i < np->num_rx_rings; i++) {
4109 struct rx_ring_info *rp = &np->rx_rings[i];
4110
4111 if (rx_vec & (1 << rp->rx_channel)) {
4112 int r = niu_rx_error(np, rp);
406f353c 4113 if (r) {
a3138df9 4114 err = r;
406f353c
MW		 4115 } else {
4116 if (!v0)
4117 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4118 RX_DMA_CTL_STAT_MEX);
4119 }
a3138df9
DM		 4120 }
4121 }
4122 }
4123 if (v1 & 0x7fffffff00000000ULL) {
4124 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4125
4126 for (i = 0; i < np->num_tx_rings; i++) {
4127 struct tx_ring_info *rp = &np->tx_rings[i];
4128
4129 if (tx_vec & (1 << rp->tx_channel)) {
4130 int r = niu_tx_error(np, rp);
4131 if (r)
4132 err = r;
4133 }
4134 }
4135 }
4136 if ((v0 | v1) & 0x8000000000000000ULL) {
4137 int r = niu_mif_interrupt(np);
4138 if (r)
4139 err = r;
4140 }
4141 if (v2) {
4142 if (v2 & 0x01ef) {
4143 int r = niu_mac_interrupt(np);
4144 if (r)
4145 err = r;
4146 }
4147 if (v2 & 0x0210) {
4148 int r = niu_device_error(np);
4149 if (r)
4150 err = r;
4151 }
4152 }
4153
4154 if (err)
4155 niu_enable_interrupts(np, 0);
4156
406f353c 4157 return err;
a3138df9
DM		 4158}
4159
4160static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4161 int ldn)
4162{
4163 struct rxdma_mailbox *mbox = rp->mbox;
4164 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4165
4166 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4167 RX_DMA_CTL_STAT_RCRTO);
4168 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4169
f10a1f2e
JP		 4170 netif_printk(np, intr, KERN_DEBUG, np->dev,
4171 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
a3138df9
DM		 4172}
4173
4174static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4175 int ldn)
4176{
4177 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4178
f10a1f2e
JP		 4179 netif_printk(np, intr, KERN_DEBUG, np->dev,
4180 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
a3138df9
DM		 4181}
4182
4183static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4184{
4185 struct niu_parent *parent = np->parent;
4186 u32 rx_vec, tx_vec;
4187 int i;
4188
4189 tx_vec = (v0 >> 32);
4190 rx_vec = (v0 & 0xffffffff);
4191
4192 for (i = 0; i < np->num_rx_rings; i++) {
4193 struct rx_ring_info *rp = &np->rx_rings[i];
4194 int ldn = LDN_RXDMA(rp->rx_channel);
4195
4196 if (parent->ldg_map[ldn] != ldg)
4197 continue;
4198
4199 nw64(LD_IM0(ldn), LD_IM0_MASK);
4200 if (rx_vec & (1 << rp->rx_channel))
4201 niu_rxchan_intr(np, rp, ldn);
4202 }
4203
4204 for (i = 0; i < np->num_tx_rings; i++) {
4205 struct tx_ring_info *rp = &np->tx_rings[i];
4206 int ldn = LDN_TXDMA(rp->tx_channel);
4207
4208 if (parent->ldg_map[ldn] != ldg)
4209 continue;
4210
4211 nw64(LD_IM0(ldn), LD_IM0_MASK);
4212 if (tx_vec & (1 << rp->tx_channel))
4213 niu_txchan_intr(np, rp, ldn);
4214 }
4215}
4216
4217static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4218 u64 v0, u64 v1, u64 v2)
4219{
288379f0 4220 if (likely(napi_schedule_prep(&lp->napi))) {
a3138df9
DM		 4221 lp->v0 = v0;
4222 lp->v1 = v1;
4223 lp->v2 = v2;
4224 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
288379f0 4225 __napi_schedule(&lp->napi);
a3138df9
DM		 4226 }
4227}
4228
4229static irqreturn_t niu_interrupt(int irq, void *dev_id)
4230{
4231 struct niu_ldg *lp = dev_id;
4232 struct niu *np = lp->np;
4233 int ldg = lp->ldg_num;
4234 unsigned long flags;
4235 u64 v0, v1, v2;
4236
4237 if (netif_msg_intr(np))
f10a1f2e
JP		 4238 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4239 __func__, lp, ldg);
a3138df9
DM		 4240
4241 spin_lock_irqsave(&np->lock, flags);
4242
4243 v0 = nr64(LDSV0(ldg));
4244 v1 = nr64(LDSV1(ldg));
4245 v2 = nr64(LDSV2(ldg));
4246
4247 if (netif_msg_intr(np))
02b1bae5 4248 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
a3138df9
DM		 4249 (unsigned long long) v0,
4250 (unsigned long long) v1,
4251 (unsigned long long) v2);
4252
4253 if (unlikely(!v0 && !v1 && !v2)) {
4254 spin_unlock_irqrestore(&np->lock, flags);
4255 return IRQ_NONE;
4256 }
4257
4258 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
406f353c 4259 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
a3138df9
DM		 4260 if (err)
4261 goto out;
4262 }
4263 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4264 niu_schedule_napi(np, lp, v0, v1, v2);
4265 else
4266 niu_ldg_rearm(np, lp, 1);
4267out:
4268 spin_unlock_irqrestore(&np->lock, flags);
4269
4270 return IRQ_HANDLED;
4271}
4272
4273static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4274{
4275 if (rp->mbox) {
4276 np->ops->free_coherent(np->device,
4277 sizeof(struct rxdma_mailbox),
4278 rp->mbox, rp->mbox_dma);
4279 rp->mbox = NULL;
4280 }
4281 if (rp->rcr) {
4282 np->ops->free_coherent(np->device,
4283 MAX_RCR_RING_SIZE * sizeof(__le64),
4284 rp->rcr, rp->rcr_dma);
4285 rp->rcr = NULL;
4286 rp->rcr_table_size = 0;
4287 rp->rcr_index = 0;
4288 }
4289 if (rp->rbr) {
4290 niu_rbr_free(np, rp);
4291
4292 np->ops->free_coherent(np->device,
4293 MAX_RBR_RING_SIZE * sizeof(__le32),
4294 rp->rbr, rp->rbr_dma);
4295 rp->rbr = NULL;
4296 rp->rbr_table_size = 0;
4297 rp->rbr_index = 0;
4298 }
4299 kfree(rp->rxhash);
4300 rp->rxhash = NULL;
4301}
4302
4303static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4304{
4305 if (rp->mbox) {
4306 np->ops->free_coherent(np->device,
4307 sizeof(struct txdma_mailbox),
4308 rp->mbox, rp->mbox_dma);
4309 rp->mbox = NULL;
4310 }
4311 if (rp->descr) {
4312 int i;
4313
4314 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4315 if (rp->tx_buffs[i].skb)
4316 (void) release_tx_packet(np, rp, i);
4317 }
4318
4319 np->ops->free_coherent(np->device,
4320 MAX_TX_RING_SIZE * sizeof(__le64),
4321 rp->descr, rp->descr_dma);
4322 rp->descr = NULL;
4323 rp->pending = 0;
4324 rp->prod = 0;
4325 rp->cons = 0;
4326 rp->wrap_bit = 0;
4327 }
4328}
4329
4330static void niu_free_channels(struct niu *np)
4331{
4332 int i;
4333
4334 if (np->rx_rings) {
4335 for (i = 0; i < np->num_rx_rings; i++) {
4336 struct rx_ring_info *rp = &np->rx_rings[i];
4337
4338 niu_free_rx_ring_info(np, rp);
4339 }
4340 kfree(np->rx_rings);
4341 np->rx_rings = NULL;
4342 np->num_rx_rings = 0;
4343 }
4344
4345 if (np->tx_rings) {
4346 for (i = 0; i < np->num_tx_rings; i++) {
4347 struct tx_ring_info *rp = &np->tx_rings[i];
4348
4349 niu_free_tx_ring_info(np, rp);
4350 }
4351 kfree(np->tx_rings);
4352 np->tx_rings = NULL;
4353 np->num_tx_rings = 0;
4354 }
4355}
4356
4357static int niu_alloc_rx_ring_info(struct niu *np,
4358 struct rx_ring_info *rp)
4359{
4360 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4361
4362 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4363 GFP_KERNEL);
4364 if (!rp->rxhash)
4365 return -ENOMEM;
4366
4367 rp->mbox = np->ops->alloc_coherent(np->device,
4368 sizeof(struct rxdma_mailbox),
4369 &rp->mbox_dma, GFP_KERNEL);
4370 if (!rp->mbox)
4371 return -ENOMEM;
4372 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4373 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4374 rp->mbox);
a3138df9
DM		 4375 return -EINVAL;
4376 }
4377
4378 rp->rcr = np->ops->alloc_coherent(np->device,
4379 MAX_RCR_RING_SIZE * sizeof(__le64),
4380 &rp->rcr_dma, GFP_KERNEL);
4381 if (!rp->rcr)
4382 return -ENOMEM;
4383 if ((unsigned long)rp->rcr & (64UL - 1)) {
f10a1f2e
JP		 4384 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4385 rp->rcr);
a3138df9
DM		 4386 return -EINVAL;
4387 }
4388 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4389 rp->rcr_index = 0;
4390
4391 rp->rbr = np->ops->alloc_coherent(np->device,
4392 MAX_RBR_RING_SIZE * sizeof(__le32),
4393 &rp->rbr_dma, GFP_KERNEL);
4394 if (!rp->rbr)
4395 return -ENOMEM;
4396 if ((unsigned long)rp->rbr & (64UL - 1)) {
f10a1f2e
JP		 4397 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4398 rp->rbr);
a3138df9
DM		 4399 return -EINVAL;
4400 }
4401 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4402 rp->rbr_index = 0;
4403 rp->rbr_pending = 0;
4404
4405 return 0;
4406}
4407
4408static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4409{
4410 int mtu = np->dev->mtu;
4411
4412 /* These values are recommended by the HW designers for fair
4413 * utilization of DRR amongst the rings.
4414 */
4415 rp->max_burst = mtu + 32;
4416 if (rp->max_burst > 4096)
4417 rp->max_burst = 4096;
4418}
4419
4420static int niu_alloc_tx_ring_info(struct niu *np,
4421 struct tx_ring_info *rp)
4422{
4423 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4424
4425 rp->mbox = np->ops->alloc_coherent(np->device,
4426 sizeof(struct txdma_mailbox),
4427 &rp->mbox_dma, GFP_KERNEL);
4428 if (!rp->mbox)
4429 return -ENOMEM;
4430 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4431 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4432 rp->mbox);
a3138df9
DM		 4433 return -EINVAL;
4434 }
4435
4436 rp->descr = np->ops->alloc_coherent(np->device,
4437 MAX_TX_RING_SIZE * sizeof(__le64),
4438 &rp->descr_dma, GFP_KERNEL);
4439 if (!rp->descr)
4440 return -ENOMEM;
4441 if ((unsigned long)rp->descr & (64UL - 1)) {
f10a1f2e
JP		 4442 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4443 rp->descr);
a3138df9
DM		 4444 return -EINVAL;
4445 }
4446
4447 rp->pending = MAX_TX_RING_SIZE;
4448 rp->prod = 0;
4449 rp->cons = 0;
4450 rp->wrap_bit = 0;
4451
4452 /* XXX make these configurable... XXX */
4453 rp->mark_freq = rp->pending / 4;
4454
4455 niu_set_max_burst(np, rp);
4456
4457 return 0;
4458}
4459
4460static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4461{
81429973 4462 u16 bss;
a3138df9 4463
81429973 4464 bss = min(PAGE_SHIFT, 15);
a3138df9 4465
81429973
OJ		 4466 rp->rbr_block_size = 1 << bss;
4467 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
a3138df9
DM		 4468
4469 rp->rbr_sizes[0] = 256;
4470 rp->rbr_sizes[1] = 1024;
4471 if (np->dev->mtu > ETH_DATA_LEN) {
4472 switch (PAGE_SIZE) {
4473 case 4 * 1024:
4474 rp->rbr_sizes[2] = 4096;
4475 break;
4476
4477 default:
4478 rp->rbr_sizes[2] = 8192;
4479 break;
4480 }
4481 } else {
4482 rp->rbr_sizes[2] = 2048;
4483 }
4484 rp->rbr_sizes[3] = rp->rbr_block_size;
4485}
4486
4487static int niu_alloc_channels(struct niu *np)
4488{
4489 struct niu_parent *parent = np->parent;
4490 int first_rx_channel, first_tx_channel;
4491 int i, port, err;
4492
4493 port = np->port;
4494 first_rx_channel = first_tx_channel = 0;
4495 for (i = 0; i < port; i++) {
4496 first_rx_channel += parent->rxchan_per_port[i];
4497 first_tx_channel += parent->txchan_per_port[i];
4498 }
4499
4500 np->num_rx_rings = parent->rxchan_per_port[port];
4501 np->num_tx_rings = parent->txchan_per_port[port];
4502
b4c21639
DM		 4503 np->dev->real_num_tx_queues = np->num_tx_rings;
4504
a3138df9
DM		 4505 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4506 GFP_KERNEL);
4507 err = -ENOMEM;
4508 if (!np->rx_rings)
4509 goto out_err;
4510
4511 for (i = 0; i < np->num_rx_rings; i++) {
4512 struct rx_ring_info *rp = &np->rx_rings[i];
4513
4514 rp->np = np;
4515 rp->rx_channel = first_rx_channel + i;
4516
4517 err = niu_alloc_rx_ring_info(np, rp);
4518 if (err)
4519 goto out_err;
4520
4521 niu_size_rbr(np, rp);
4522
4523 /* XXX better defaults, configurable, etc... XXX */
4524 rp->nonsyn_window = 64;
4525 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4526 rp->syn_window = 64;
4527 rp->syn_threshold = rp->rcr_table_size - 64;
4528 rp->rcr_pkt_threshold = 16;
4529 rp->rcr_timeout = 8;
4530 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4531 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4532 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4533
4534 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4535 if (err)
4536 return err;
4537 }
4538
4539 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4540 GFP_KERNEL);
4541 err = -ENOMEM;
4542 if (!np->tx_rings)
4543 goto out_err;
4544
4545 for (i = 0; i < np->num_tx_rings; i++) {
4546 struct tx_ring_info *rp = &np->tx_rings[i];
4547
4548 rp->np = np;
4549 rp->tx_channel = first_tx_channel + i;
4550
4551 err = niu_alloc_tx_ring_info(np, rp);
4552 if (err)
4553 goto out_err;
4554 }
4555
4556 return 0;
4557
4558out_err:
4559 niu_free_channels(np);
4560 return err;
4561}
4562
4563static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4564{
4565 int limit = 1000;
4566
4567 while (--limit > 0) {
4568 u64 val = nr64(TX_CS(channel));
4569 if (val & TX_CS_SNG_STATE)
4570 return 0;
4571 }
4572 return -ENODEV;
4573}
4574
4575static int niu_tx_channel_stop(struct niu *np, int channel)
4576{
4577 u64 val = nr64(TX_CS(channel));
4578
4579 val |= TX_CS_STOP_N_GO;
4580 nw64(TX_CS(channel), val);
4581
4582 return niu_tx_cs_sng_poll(np, channel);
4583}
4584
4585static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4586{
4587 int limit = 1000;
4588
4589 while (--limit > 0) {
4590 u64 val = nr64(TX_CS(channel));
4591 if (!(val & TX_CS_RST))
4592 return 0;
4593 }
4594 return -ENODEV;
4595}
4596
4597static int niu_tx_channel_reset(struct niu *np, int channel)
4598{
4599 u64 val = nr64(TX_CS(channel));
4600 int err;
4601
4602 val |= TX_CS_RST;
4603 nw64(TX_CS(channel), val);
4604
4605 err = niu_tx_cs_reset_poll(np, channel);
4606 if (!err)
4607 nw64(TX_RING_KICK(channel), 0);
4608
4609 return err;
4610}
4611
4612static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4613{
4614 u64 val;
4615
4616 nw64(TX_LOG_MASK1(channel), 0);
4617 nw64(TX_LOG_VAL1(channel), 0);
4618 nw64(TX_LOG_MASK2(channel), 0);
4619 nw64(TX_LOG_VAL2(channel), 0);
4620 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4621 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4622 nw64(TX_LOG_PAGE_HDL(channel), 0);
4623
4624 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4625 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4626 nw64(TX_LOG_PAGE_VLD(channel), val);
4627
4628 /* XXX TXDMA 32bit mode? XXX */
4629
4630 return 0;
4631}
4632
4633static void niu_txc_enable_port(struct niu *np, int on)
4634{
4635 unsigned long flags;
4636 u64 val, mask;
4637
4638 niu_lock_parent(np, flags);
4639 val = nr64(TXC_CONTROL);
4640 mask = (u64)1 << np->port;
4641 if (on) {
4642 val |= TXC_CONTROL_ENABLE | mask;
4643 } else {
4644 val &= ~mask;
4645 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4646 val &= ~TXC_CONTROL_ENABLE;
4647 }
4648 nw64(TXC_CONTROL, val);
4649 niu_unlock_parent(np, flags);
4650}
4651
4652static void niu_txc_set_imask(struct niu *np, u64 imask)
4653{
4654 unsigned long flags;
4655 u64 val;
4656
4657 niu_lock_parent(np, flags);
4658 val = nr64(TXC_INT_MASK);
4659 val &= ~TXC_INT_MASK_VAL(np->port);
4660 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4661 niu_unlock_parent(np, flags);
4662}
4663
4664static void niu_txc_port_dma_enable(struct niu *np, int on)
4665{
4666 u64 val = 0;
4667
4668 if (on) {
4669 int i;
4670
4671 for (i = 0; i < np->num_tx_rings; i++)
4672 val |= (1 << np->tx_rings[i].tx_channel);
4673 }
4674 nw64(TXC_PORT_DMA(np->port), val);
4675}
4676
4677static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4678{
4679 int err, channel = rp->tx_channel;
4680 u64 val, ring_len;
4681
4682 err = niu_tx_channel_stop(np, channel);
4683 if (err)
4684 return err;
4685
4686 err = niu_tx_channel_reset(np, channel);
4687 if (err)
4688 return err;
4689
4690 err = niu_tx_channel_lpage_init(np, channel);
4691 if (err)
4692 return err;
4693
4694 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4695 nw64(TX_ENT_MSK(channel), 0);
4696
4697 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4698 TX_RNG_CFIG_STADDR)) {
f10a1f2e
JP		 4699 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4700 channel, (unsigned long long)rp->descr_dma);
a3138df9
DM		 4701 return -EINVAL;
4702 }
4703
4704 /* The length field in TX_RNG_CFIG is measured in 64-byte
4705 * blocks. rp->pending is the number of TX descriptors in
4706 * our ring, 8 bytes each, thus we divide by 8 bytes more
4707 * to get the proper value the chip wants.
4708 */
4709 ring_len = (rp->pending / 8);
4710
4711 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4712 rp->descr_dma);
4713 nw64(TX_RNG_CFIG(channel), val);
4714
4715 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4716 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
f10a1f2e
JP		 4717 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4718 channel, (unsigned long long)rp->mbox_dma);
a3138df9
DM		 4719 return -EINVAL;
4720 }
4721 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4722 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4723
4724 nw64(TX_CS(channel), 0);
4725
4726 rp->last_pkt_cnt = 0;
4727
4728 return 0;
4729}
4730
4731static void niu_init_rdc_groups(struct niu *np)
4732{
4733 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4734 int i, first_table_num = tp->first_table_num;
4735
4736 for (i = 0; i < tp->num_tables; i++) {
4737 struct rdc_table *tbl = &tp->tables[i];
4738 int this_table = first_table_num + i;
4739 int slot;
4740
4741 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4742 nw64(RDC_TBL(this_table, slot),
4743 tbl->rxdma_channel[slot]);
4744 }
4745
4746 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4747}
4748
4749static void niu_init_drr_weight(struct niu *np)
4750{
4751 int type = phy_decode(np->parent->port_phy, np->port);
4752 u64 val;
4753
4754 switch (type) {
4755 case PORT_TYPE_10G:
4756 val = PT_DRR_WEIGHT_DEFAULT_10G;
4757 break;
4758
4759 case PORT_TYPE_1G:
4760 default:
4761 val = PT_DRR_WEIGHT_DEFAULT_1G;
4762 break;
4763 }
4764 nw64(PT_DRR_WT(np->port), val);
4765}
4766
4767static int niu_init_hostinfo(struct niu *np)
4768{
4769 struct niu_parent *parent = np->parent;
4770 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4771 int i, err, num_alt = niu_num_alt_addr(np);
4772 int first_rdc_table = tp->first_table_num;
4773
4774 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4775 if (err)
4776 return err;
4777
4778 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4779 if (err)
4780 return err;
4781
4782 for (i = 0; i < num_alt; i++) {
4783 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4784 if (err)
4785 return err;
4786 }
4787
4788 return 0;
4789}
4790
4791static int niu_rx_channel_reset(struct niu *np, int channel)
4792{
4793 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4794 RXDMA_CFIG1_RST, 1000, 10,
4795 "RXDMA_CFIG1");
4796}
4797
4798static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4799{
4800 u64 val;
4801
4802 nw64(RX_LOG_MASK1(channel), 0);
4803 nw64(RX_LOG_VAL1(channel), 0);
4804 nw64(RX_LOG_MASK2(channel), 0);
4805 nw64(RX_LOG_VAL2(channel), 0);
4806 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4807 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4808 nw64(RX_LOG_PAGE_HDL(channel), 0);
4809
4810 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4811 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4812 nw64(RX_LOG_PAGE_VLD(channel), val);
4813
4814 return 0;
4815}
4816
4817static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4818{
4819 u64 val;
4820
4821 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4822 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4823 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4824 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4825 nw64(RDC_RED_PARA(rp->rx_channel), val);
4826}
4827
4828static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4829{
4830 u64 val = 0;
4831
efb6c736 4832 *ret = 0;
a3138df9
DM		 4833 switch (rp->rbr_block_size) {
4834 case 4 * 1024:
4835 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4836 break;
4837 case 8 * 1024:
4838 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4839 break;
4840 case 16 * 1024:
4841 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4842 break;
4843 case 32 * 1024:
4844 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4845 break;
4846 default:
4847 return -EINVAL;
4848 }
4849 val |= RBR_CFIG_B_VLD2;
4850 switch (rp->rbr_sizes[2]) {
4851 case 2 * 1024:
4852 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4853 break;
4854 case 4 * 1024:
4855 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4856 break;
4857 case 8 * 1024:
4858 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4859 break;
4860 case 16 * 1024:
4861 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4862 break;
4863
4864 default:
4865 return -EINVAL;
4866 }
4867 val |= RBR_CFIG_B_VLD1;
4868 switch (rp->rbr_sizes[1]) {
4869 case 1 * 1024:
4870 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4871 break;
4872 case 2 * 1024:
4873 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4874 break;
4875 case 4 * 1024:
4876 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4877 break;
4878 case 8 * 1024:
4879 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4880 break;
4881
4882 default:
4883 return -EINVAL;
4884 }
4885 val |= RBR_CFIG_B_VLD0;
4886 switch (rp->rbr_sizes[0]) {
4887 case 256:
4888 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4889 break;
4890 case 512:
4891 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4892 break;
4893 case 1 * 1024:
4894 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4895 break;
4896 case 2 * 1024:
4897 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4898 break;
4899
4900 default:
4901 return -EINVAL;
4902 }
4903
4904 *ret = val;
4905 return 0;
4906}
4907
4908static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4909{
4910 u64 val = nr64(RXDMA_CFIG1(channel));
4911 int limit;
4912
4913 if (on)
4914 val |= RXDMA_CFIG1_EN;
4915 else
4916 val &= ~RXDMA_CFIG1_EN;
4917 nw64(RXDMA_CFIG1(channel), val);
4918
4919 limit = 1000;
4920 while (--limit > 0) {
4921 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4922 break;
4923 udelay(10);
4924 }
4925 if (limit <= 0)
4926 return -ENODEV;
4927 return 0;
4928}
4929
4930static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4931{
4932 int err, channel = rp->rx_channel;
4933 u64 val;
4934
4935 err = niu_rx_channel_reset(np, channel);
4936 if (err)
4937 return err;
4938
4939 err = niu_rx_channel_lpage_init(np, channel);
4940 if (err)
4941 return err;
4942
4943 niu_rx_channel_wred_init(np, rp);
4944
4945 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4946 nw64(RX_DMA_CTL_STAT(channel),
4947 (RX_DMA_CTL_STAT_MEX |
4948 RX_DMA_CTL_STAT_RCRTHRES |
4949 RX_DMA_CTL_STAT_RCRTO |
4950 RX_DMA_CTL_STAT_RBR_EMPTY));
4951 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
3cfa856d
DM		 4952 nw64(RXDMA_CFIG2(channel),
4953 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4954 RXDMA_CFIG2_FULL_HDR));
a3138df9
DM		 4955 nw64(RBR_CFIG_A(channel),
4956 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4957 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4958 err = niu_compute_rbr_cfig_b(rp, &val);
4959 if (err)
4960 return err;
4961 nw64(RBR_CFIG_B(channel), val);
4962 nw64(RCRCFIG_A(channel),
4963 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4964 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4965 nw64(RCRCFIG_B(channel),
4966 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4967 RCRCFIG_B_ENTOUT |
4968 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4969
4970 err = niu_enable_rx_channel(np, channel, 1);
4971 if (err)
4972 return err;
4973
4974 nw64(RBR_KICK(channel), rp->rbr_index);
4975
4976 val = nr64(RX_DMA_CTL_STAT(channel));
4977 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4978 nw64(RX_DMA_CTL_STAT(channel), val);
4979
4980 return 0;
4981}
4982
4983static int niu_init_rx_channels(struct niu *np)
4984{
4985 unsigned long flags;
4986 u64 seed = jiffies_64;
4987 int err, i;
4988
4989 niu_lock_parent(np, flags);
4990 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4991 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4992 niu_unlock_parent(np, flags);
4993
4994 /* XXX RXDMA 32bit mode? XXX */
4995
4996 niu_init_rdc_groups(np);
4997 niu_init_drr_weight(np);
4998
4999 err = niu_init_hostinfo(np);
5000 if (err)
5001 return err;
5002
5003 for (i = 0; i < np->num_rx_rings; i++) {
5004 struct rx_ring_info *rp = &np->rx_rings[i];
5005
5006 err = niu_init_one_rx_channel(np, rp);
5007 if (err)
5008 return err;
5009 }
5010
5011 return 0;
5012}
5013
5014static int niu_set_ip_frag_rule(struct niu *np)
5015{
5016 struct niu_parent *parent = np->parent;
5017 struct niu_classifier *cp = &np->clas;
5018 struct niu_tcam_entry *tp;
5019 int index, err;
5020
2d96cf8c 5021 index = cp->tcam_top;
a3138df9
DM		 5022 tp = &parent->tcam[index];
5023
5024 /* Note that the noport bit is the same in both ipv4 and
5025 * ipv6 format TCAM entries.
5026 */
5027 memset(tp, 0, sizeof(*tp));
5028 tp->key[1] = TCAM_V4KEY1_NOPORT;
5029 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5030 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5031 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5032 err = tcam_write(np, index, tp->key, tp->key_mask);
5033 if (err)
5034 return err;
5035 err = tcam_assoc_write(np, index, tp->assoc_data);
5036 if (err)
5037 return err;
2d96cf8c
SB		 5038 tp->valid = 1;
5039 cp->tcam_valid_entries++;
a3138df9
DM		 5040
5041 return 0;
5042}
5043
5044static int niu_init_classifier_hw(struct niu *np)
5045{
5046 struct niu_parent *parent = np->parent;
5047 struct niu_classifier *cp = &np->clas;
5048 int i, err;
5049
5050 nw64(H1POLY, cp->h1_init);
5051 nw64(H2POLY, cp->h2_init);
5052
5053 err = niu_init_hostinfo(np);
5054 if (err)
5055 return err;
5056
5057 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5058 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5059
5060 vlan_tbl_write(np, i, np->port,
5061 vp->vlan_pref, vp->rdc_num);
5062 }
5063
5064 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5065 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5066
5067 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5068 ap->rdc_num, ap->mac_pref);
5069 if (err)
5070 return err;
5071 }
5072
5073 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5074 int index = i - CLASS_CODE_USER_PROG1;
5075
5076 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5077 if (err)
5078 return err;
5079 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5080 if (err)
5081 return err;
5082 }
5083
5084 err = niu_set_ip_frag_rule(np);
5085 if (err)
5086 return err;
5087
5088 tcam_enable(np, 1);
5089
5090 return 0;
5091}
5092
5093static int niu_zcp_write(struct niu *np, int index, u64 *data)
5094{
5095 nw64(ZCP_RAM_DATA0, data[0]);
5096 nw64(ZCP_RAM_DATA1, data[1]);
5097 nw64(ZCP_RAM_DATA2, data[2]);
5098 nw64(ZCP_RAM_DATA3, data[3]);
5099 nw64(ZCP_RAM_DATA4, data[4]);
5100 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5101 nw64(ZCP_RAM_ACC,
5102 (ZCP_RAM_ACC_WRITE |
5103 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5104 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5105
5106 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5107 1000, 100);
5108}
5109
5110static int niu_zcp_read(struct niu *np, int index, u64 *data)
5111{
5112 int err;
5113
5114 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5115 1000, 100);
5116 if (err) {
f10a1f2e
JP		 5117 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5118 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5119 return err;
5120 }
5121
5122 nw64(ZCP_RAM_ACC,
5123 (ZCP_RAM_ACC_READ |
5124 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5125 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5126
5127 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5128 1000, 100);
5129 if (err) {
f10a1f2e
JP		 5130 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5131 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5132 return err;
5133 }
5134
5135 data[0] = nr64(ZCP_RAM_DATA0);
5136 data[1] = nr64(ZCP_RAM_DATA1);
5137 data[2] = nr64(ZCP_RAM_DATA2);
5138 data[3] = nr64(ZCP_RAM_DATA3);
5139 data[4] = nr64(ZCP_RAM_DATA4);
5140
5141 return 0;
5142}
5143
5144static void niu_zcp_cfifo_reset(struct niu *np)
5145{
5146 u64 val = nr64(RESET_CFIFO);
5147
5148 val |= RESET_CFIFO_RST(np->port);
5149 nw64(RESET_CFIFO, val);
5150 udelay(10);
5151
5152 val &= ~RESET_CFIFO_RST(np->port);
5153 nw64(RESET_CFIFO, val);
5154}
5155
5156static int niu_init_zcp(struct niu *np)
5157{
5158 u64 data[5], rbuf[5];
5159 int i, max, err;
5160
5161 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5162 if (np->port == 0 || np->port == 1)
5163 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5164 else
5165 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5166 } else
5167 max = NIU_CFIFO_ENTRIES;
5168
5169 data[0] = 0;
5170 data[1] = 0;
5171 data[2] = 0;
5172 data[3] = 0;
5173 data[4] = 0;
5174
5175 for (i = 0; i < max; i++) {
5176 err = niu_zcp_write(np, i, data);
5177 if (err)
5178 return err;
5179 err = niu_zcp_read(np, i, rbuf);
5180 if (err)
5181 return err;
5182 }
5183
5184 niu_zcp_cfifo_reset(np);
5185 nw64(CFIFO_ECC(np->port), 0);
5186 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5187 (void) nr64(ZCP_INT_STAT);
5188 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5189
5190 return 0;
5191}
5192
5193static void niu_ipp_write(struct niu *np, int index, u64 *data)
5194{
5195 u64 val = nr64_ipp(IPP_CFIG);
5196
5197 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5198 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5199 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5200 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5201 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5202 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5203 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5204 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5205}
5206
5207static void niu_ipp_read(struct niu *np, int index, u64 *data)
5208{
5209 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5210 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5211 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5212 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5213 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5214 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5215}
5216
5217static int niu_ipp_reset(struct niu *np)
5218{
5219 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5220 1000, 100, "IPP_CFIG");
5221}
5222
5223static int niu_init_ipp(struct niu *np)
5224{
5225 u64 data[5], rbuf[5], val;
5226 int i, max, err;
5227
5228 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5229 if (np->port == 0 || np->port == 1)
5230 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5231 else
5232 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5233 } else
5234 max = NIU_DFIFO_ENTRIES;
5235
5236 data[0] = 0;
5237 data[1] = 0;
5238 data[2] = 0;
5239 data[3] = 0;
5240 data[4] = 0;
5241
5242 for (i = 0; i < max; i++) {
5243 niu_ipp_write(np, i, data);
5244 niu_ipp_read(np, i, rbuf);
5245 }
5246
5247 (void) nr64_ipp(IPP_INT_STAT);
5248 (void) nr64_ipp(IPP_INT_STAT);
5249
5250 err = niu_ipp_reset(np);
5251 if (err)
5252 return err;
5253
5254 (void) nr64_ipp(IPP_PKT_DIS);
5255 (void) nr64_ipp(IPP_BAD_CS_CNT);
5256 (void) nr64_ipp(IPP_ECC);
5257
5258 (void) nr64_ipp(IPP_INT_STAT);
5259
5260 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5261
5262 val = nr64_ipp(IPP_CFIG);
5263 val &= ~IPP_CFIG_IP_MAX_PKT;
5264 val |= (IPP_CFIG_IPP_ENABLE |
5265 IPP_CFIG_DFIFO_ECC_EN |
5266 IPP_CFIG_DROP_BAD_CRC |
5267 IPP_CFIG_CKSUM_EN |
5268 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5269 nw64_ipp(IPP_CFIG, val);
5270
5271 return 0;
5272}
5273
0c3b091b 5274static void niu_handle_led(struct niu *np, int status)
a3138df9 5275{
a3138df9 5276 u64 val;
a3138df9
DM		 5277 val = nr64_mac(XMAC_CONFIG);
5278
5279 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5280 (np->flags & NIU_FLAGS_FIBER) != 0) {
0c3b091b 5281 if (status) {
a3138df9
DM		 5282 val |= XMAC_CONFIG_LED_POLARITY;
5283 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5284 } else {
5285 val |= XMAC_CONFIG_FORCE_LED_ON;
5286 val &= ~XMAC_CONFIG_LED_POLARITY;
5287 }
5288 }
5289
0c3b091b
ML		 5290 nw64_mac(XMAC_CONFIG, val);
5291}
5292
5293static void niu_init_xif_xmac(struct niu *np)
5294{
5295 struct niu_link_config *lp = &np->link_config;
5296 u64 val;
5297
5fbd7e24
MW		 5298 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5299 val = nr64(MIF_CONFIG);
5300 val |= MIF_CONFIG_ATCA_GE;
5301 nw64(MIF_CONFIG, val);
5302 }
5303
0c3b091b 5304 val = nr64_mac(XMAC_CONFIG);
a3138df9
DM		 5305 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5306
5307 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5308
5309 if (lp->loopback_mode == LOOPBACK_MAC) {
5310 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5311 val |= XMAC_CONFIG_LOOPBACK;
5312 } else {
5313 val &= ~XMAC_CONFIG_LOOPBACK;
5314 }
5315
5316 if (np->flags & NIU_FLAGS_10G) {
5317 val &= ~XMAC_CONFIG_LFS_DISABLE;
5318 } else {
5319 val |= XMAC_CONFIG_LFS_DISABLE;
5fbd7e24
MW		 5320 if (!(np->flags & NIU_FLAGS_FIBER) &&
5321 !(np->flags & NIU_FLAGS_XCVR_SERDES))
a3138df9
DM		 5322 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5323 else
5324 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5325 }
5326
5327 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5328
5329 if (lp->active_speed == SPEED_100)
5330 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5331 else
5332 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5333
5334 nw64_mac(XMAC_CONFIG, val);
5335
5336 val = nr64_mac(XMAC_CONFIG);
5337 val &= ~XMAC_CONFIG_MODE_MASK;
5338 if (np->flags & NIU_FLAGS_10G) {
5339 val |= XMAC_CONFIG_MODE_XGMII;
5340 } else {
38bb045d 5341 if (lp->active_speed == SPEED_1000)
a3138df9 5342 val |= XMAC_CONFIG_MODE_GMII;
38bb045d
CB		 5343 else
5344 val |= XMAC_CONFIG_MODE_MII;
a3138df9
DM		 5345 }
5346
5347 nw64_mac(XMAC_CONFIG, val);
5348}
5349
5350static void niu_init_xif_bmac(struct niu *np)
5351{
5352 struct niu_link_config *lp = &np->link_config;
5353 u64 val;
5354
5355 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5356
5357 if (lp->loopback_mode == LOOPBACK_MAC)
5358 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5359 else
5360 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5361
5362 if (lp->active_speed == SPEED_1000)
5363 val |= BMAC_XIF_CONFIG_GMII_MODE;
5364 else
5365 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5366
5367 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5368 BMAC_XIF_CONFIG_LED_POLARITY);
5369
5370 if (!(np->flags & NIU_FLAGS_10G) &&
5371 !(np->flags & NIU_FLAGS_FIBER) &&
5372 lp->active_speed == SPEED_100)
5373 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5374 else
5375 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5376
5377 nw64_mac(BMAC_XIF_CONFIG, val);
5378}
5379
5380static void niu_init_xif(struct niu *np)
5381{
5382 if (np->flags & NIU_FLAGS_XMAC)
5383 niu_init_xif_xmac(np);
5384 else
5385 niu_init_xif_bmac(np);
5386}
5387
5388static void niu_pcs_mii_reset(struct niu *np)
5389{
5fbd7e24 5390 int limit = 1000;
a3138df9
DM		 5391 u64 val = nr64_pcs(PCS_MII_CTL);
5392 val |= PCS_MII_CTL_RST;
5393 nw64_pcs(PCS_MII_CTL, val);
5fbd7e24
MW		 5394 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5395 udelay(100);
5396 val = nr64_pcs(PCS_MII_CTL);
5397 }
a3138df9
DM		 5398}
5399
5400static void niu_xpcs_reset(struct niu *np)
5401{
5fbd7e24 5402 int limit = 1000;
a3138df9
DM		 5403 u64 val = nr64_xpcs(XPCS_CONTROL1);
5404 val |= XPCS_CONTROL1_RESET;
5405 nw64_xpcs(XPCS_CONTROL1, val);
5fbd7e24
MW		 5406 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5407 udelay(100);
5408 val = nr64_xpcs(XPCS_CONTROL1);
5409 }
a3138df9
DM		 5410}
5411
5412static int niu_init_pcs(struct niu *np)
5413{
5414 struct niu_link_config *lp = &np->link_config;
5415 u64 val;
5416
5fbd7e24
MW		 5417 switch (np->flags & (NIU_FLAGS_10G |
5418 NIU_FLAGS_FIBER |
5419 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 5420 case NIU_FLAGS_FIBER:
5421 /* 1G fiber */
5422 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5423 nw64_pcs(PCS_DPATH_MODE, 0);
5424 niu_pcs_mii_reset(np);
5425 break;
5426
5427 case NIU_FLAGS_10G:
5428 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5fbd7e24
MW		 5429 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5430 /* 10G SERDES */
a3138df9
DM		 5431 if (!(np->flags & NIU_FLAGS_XMAC))
5432 return -EINVAL;
5433
5434 /* 10G copper or fiber */
5435 val = nr64_mac(XMAC_CONFIG);
5436 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5437 nw64_mac(XMAC_CONFIG, val);
5438
5439 niu_xpcs_reset(np);
5440
5441 val = nr64_xpcs(XPCS_CONTROL1);
5442 if (lp->loopback_mode == LOOPBACK_PHY)
5443 val |= XPCS_CONTROL1_LOOPBACK;
5444 else
5445 val &= ~XPCS_CONTROL1_LOOPBACK;
5446 nw64_xpcs(XPCS_CONTROL1, val);
5447
5448 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5449 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5450 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5451 break;
5452
5fbd7e24
MW		 5453
5454 case NIU_FLAGS_XCVR_SERDES:
5455 /* 1G SERDES */
5456 niu_pcs_mii_reset(np);
5457 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5458 nw64_pcs(PCS_DPATH_MODE, 0);
5459 break;
5460
a3138df9
DM		 5461 case 0:
5462 /* 1G copper */
5fbd7e24
MW		 5463 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5464 /* 1G RGMII FIBER */
a3138df9
DM		 5465 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5466 niu_pcs_mii_reset(np);
5467 break;
5468
5469 default:
5470 return -EINVAL;
5471 }
5472
5473 return 0;
5474}
5475
5476static int niu_reset_tx_xmac(struct niu *np)
5477{
5478 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5479 (XTXMAC_SW_RST_REG_RS |
5480 XTXMAC_SW_RST_SOFT_RST),
5481 1000, 100, "XTXMAC_SW_RST");
5482}
5483
5484static int niu_reset_tx_bmac(struct niu *np)
5485{
5486 int limit;
5487
5488 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5489 limit = 1000;
5490 while (--limit >= 0) {
5491 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5492 break;
5493 udelay(100);
5494 }
5495 if (limit < 0) {
f10a1f2e 5496 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5497 np->port,
5498 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5499 return -ENODEV;
5500 }
5501
5502 return 0;
5503}
5504
5505static int niu_reset_tx_mac(struct niu *np)
5506{
5507 if (np->flags & NIU_FLAGS_XMAC)
5508 return niu_reset_tx_xmac(np);
5509 else
5510 return niu_reset_tx_bmac(np);
5511}
5512
5513static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5514{
5515 u64 val;
5516
5517 val = nr64_mac(XMAC_MIN);
5518 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5519 XMAC_MIN_RX_MIN_PKT_SIZE);
5520 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5521 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5522 nw64_mac(XMAC_MIN, val);
5523
5524 nw64_mac(XMAC_MAX, max);
5525
5526 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5527
5528 val = nr64_mac(XMAC_IPG);
5529 if (np->flags & NIU_FLAGS_10G) {
5530 val &= ~XMAC_IPG_IPG_XGMII;
5531 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5532 } else {
5533 val &= ~XMAC_IPG_IPG_MII_GMII;
5534 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5535 }
5536 nw64_mac(XMAC_IPG, val);
5537
5538 val = nr64_mac(XMAC_CONFIG);
5539 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5540 XMAC_CONFIG_STRETCH_MODE |
5541 XMAC_CONFIG_VAR_MIN_IPG_EN |
5542 XMAC_CONFIG_TX_ENABLE);
5543 nw64_mac(XMAC_CONFIG, val);
5544
5545 nw64_mac(TXMAC_FRM_CNT, 0);
5546 nw64_mac(TXMAC_BYTE_CNT, 0);
5547}
5548
5549static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5550{
5551 u64 val;
5552
5553 nw64_mac(BMAC_MIN_FRAME, min);
5554 nw64_mac(BMAC_MAX_FRAME, max);
5555
5556 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5557 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5558 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5559
5560 val = nr64_mac(BTXMAC_CONFIG);
5561 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5562 BTXMAC_CONFIG_ENABLE);
5563 nw64_mac(BTXMAC_CONFIG, val);
5564}
5565
5566static void niu_init_tx_mac(struct niu *np)
5567{
5568 u64 min, max;
5569
5570 min = 64;
5571 if (np->dev->mtu > ETH_DATA_LEN)
5572 max = 9216;
5573 else
5574 max = 1522;
5575
5576 /* The XMAC_MIN register only accepts values for TX min which
5577 * have the low 3 bits cleared.
5578 */
8c87df45 5579 BUG_ON(min & 0x7);
a3138df9
DM		 5580
5581 if (np->flags & NIU_FLAGS_XMAC)
5582 niu_init_tx_xmac(np, min, max);
5583 else
5584 niu_init_tx_bmac(np, min, max);
5585}
5586
5587static int niu_reset_rx_xmac(struct niu *np)
5588{
5589 int limit;
5590
5591 nw64_mac(XRXMAC_SW_RST,
5592 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5593 limit = 1000;
5594 while (--limit >= 0) {
5595 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5596 XRXMAC_SW_RST_SOFT_RST)))
f10a1f2e 5597 break;
a3138df9
DM		 5598 udelay(100);
5599 }
5600 if (limit < 0) {
f10a1f2e 5601 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5602 np->port,
5603 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5604 return -ENODEV;
5605 }
5606
5607 return 0;
5608}
5609
5610static int niu_reset_rx_bmac(struct niu *np)
5611{
5612 int limit;
5613
5614 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5615 limit = 1000;
5616 while (--limit >= 0) {
5617 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5618 break;
5619 udelay(100);
5620 }
5621 if (limit < 0) {
f10a1f2e 5622 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5623 np->port,
5624 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5625 return -ENODEV;
5626 }
5627
5628 return 0;
5629}
5630
5631static int niu_reset_rx_mac(struct niu *np)
5632{
5633 if (np->flags & NIU_FLAGS_XMAC)
5634 return niu_reset_rx_xmac(np);
5635 else
5636 return niu_reset_rx_bmac(np);
5637}
5638
5639static void niu_init_rx_xmac(struct niu *np)
5640{
5641 struct niu_parent *parent = np->parent;
5642 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5643 int first_rdc_table = tp->first_table_num;
5644 unsigned long i;
5645 u64 val;
5646
5647 nw64_mac(XMAC_ADD_FILT0, 0);
5648 nw64_mac(XMAC_ADD_FILT1, 0);
5649 nw64_mac(XMAC_ADD_FILT2, 0);
5650 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5651 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5652 for (i = 0; i < MAC_NUM_HASH; i++)
5653 nw64_mac(XMAC_HASH_TBL(i), 0);
5654 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5655 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5656 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5657
5658 val = nr64_mac(XMAC_CONFIG);
5659 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5660 XMAC_CONFIG_PROMISCUOUS |
5661 XMAC_CONFIG_PROMISC_GROUP |
5662 XMAC_CONFIG_ERR_CHK_DIS |
5663 XMAC_CONFIG_RX_CRC_CHK_DIS |
5664 XMAC_CONFIG_RESERVED_MULTICAST |
5665 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5666 XMAC_CONFIG_ADDR_FILTER_EN |
5667 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5668 XMAC_CONFIG_STRIP_CRC |
5669 XMAC_CONFIG_PASS_FLOW_CTRL |
5670 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5671 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5672 nw64_mac(XMAC_CONFIG, val);
5673
5674 nw64_mac(RXMAC_BT_CNT, 0);
5675 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5676 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5677 nw64_mac(RXMAC_FRAG_CNT, 0);
5678 nw64_mac(RXMAC_HIST_CNT1, 0);
5679 nw64_mac(RXMAC_HIST_CNT2, 0);
5680 nw64_mac(RXMAC_HIST_CNT3, 0);
5681 nw64_mac(RXMAC_HIST_CNT4, 0);
5682 nw64_mac(RXMAC_HIST_CNT5, 0);
5683 nw64_mac(RXMAC_HIST_CNT6, 0);
5684 nw64_mac(RXMAC_HIST_CNT7, 0);
5685 nw64_mac(RXMAC_MPSZER_CNT, 0);
5686 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5687 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5688 nw64_mac(LINK_FAULT_CNT, 0);
5689}
5690
5691static void niu_init_rx_bmac(struct niu *np)
5692{
5693 struct niu_parent *parent = np->parent;
5694 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5695 int first_rdc_table = tp->first_table_num;
5696 unsigned long i;
5697 u64 val;
5698
5699 nw64_mac(BMAC_ADD_FILT0, 0);
5700 nw64_mac(BMAC_ADD_FILT1, 0);
5701 nw64_mac(BMAC_ADD_FILT2, 0);
5702 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5703 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5704 for (i = 0; i < MAC_NUM_HASH; i++)
5705 nw64_mac(BMAC_HASH_TBL(i), 0);
5706 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5707 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5708 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5709
5710 val = nr64_mac(BRXMAC_CONFIG);
5711 val &= ~(BRXMAC_CONFIG_ENABLE |
5712 BRXMAC_CONFIG_STRIP_PAD |
5713 BRXMAC_CONFIG_STRIP_FCS |
5714 BRXMAC_CONFIG_PROMISC |
5715 BRXMAC_CONFIG_PROMISC_GRP |
5716 BRXMAC_CONFIG_ADDR_FILT_EN |
5717 BRXMAC_CONFIG_DISCARD_DIS);
5718 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5719 nw64_mac(BRXMAC_CONFIG, val);
5720
5721 val = nr64_mac(BMAC_ADDR_CMPEN);
5722 val |= BMAC_ADDR_CMPEN_EN0;
5723 nw64_mac(BMAC_ADDR_CMPEN, val);
5724}
5725
5726static void niu_init_rx_mac(struct niu *np)
5727{
5728 niu_set_primary_mac(np, np->dev->dev_addr);
5729
5730 if (np->flags & NIU_FLAGS_XMAC)
5731 niu_init_rx_xmac(np);
5732 else
5733 niu_init_rx_bmac(np);
5734}
5735
5736static void niu_enable_tx_xmac(struct niu *np, int on)
5737{
5738 u64 val = nr64_mac(XMAC_CONFIG);
5739
5740 if (on)
5741 val |= XMAC_CONFIG_TX_ENABLE;
5742 else
5743 val &= ~XMAC_CONFIG_TX_ENABLE;
5744 nw64_mac(XMAC_CONFIG, val);
5745}
5746
5747static void niu_enable_tx_bmac(struct niu *np, int on)
5748{
5749 u64 val = nr64_mac(BTXMAC_CONFIG);
5750
5751 if (on)
5752 val |= BTXMAC_CONFIG_ENABLE;
5753 else
5754 val &= ~BTXMAC_CONFIG_ENABLE;
5755 nw64_mac(BTXMAC_CONFIG, val);
5756}
5757
5758static void niu_enable_tx_mac(struct niu *np, int on)
5759{
5760 if (np->flags & NIU_FLAGS_XMAC)
5761 niu_enable_tx_xmac(np, on);
5762 else
5763 niu_enable_tx_bmac(np, on);
5764}
5765
5766static void niu_enable_rx_xmac(struct niu *np, int on)
5767{
5768 u64 val = nr64_mac(XMAC_CONFIG);
5769
5770 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5771 XMAC_CONFIG_PROMISCUOUS);
5772
5773 if (np->flags & NIU_FLAGS_MCAST)
5774 val |= XMAC_CONFIG_HASH_FILTER_EN;
5775 if (np->flags & NIU_FLAGS_PROMISC)
5776 val |= XMAC_CONFIG_PROMISCUOUS;
5777
5778 if (on)
5779 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5780 else
5781 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5782 nw64_mac(XMAC_CONFIG, val);
5783}
5784
5785static void niu_enable_rx_bmac(struct niu *np, int on)
5786{
5787 u64 val = nr64_mac(BRXMAC_CONFIG);
5788
5789 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5790 BRXMAC_CONFIG_PROMISC);
5791
5792 if (np->flags & NIU_FLAGS_MCAST)
5793 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5794 if (np->flags & NIU_FLAGS_PROMISC)
5795 val |= BRXMAC_CONFIG_PROMISC;
5796
5797 if (on)
5798 val |= BRXMAC_CONFIG_ENABLE;
5799 else
5800 val &= ~BRXMAC_CONFIG_ENABLE;
5801 nw64_mac(BRXMAC_CONFIG, val);
5802}
5803
5804static void niu_enable_rx_mac(struct niu *np, int on)
5805{
5806 if (np->flags & NIU_FLAGS_XMAC)
5807 niu_enable_rx_xmac(np, on);
5808 else
5809 niu_enable_rx_bmac(np, on);
5810}
5811
5812static int niu_init_mac(struct niu *np)
5813{
5814 int err;
5815
5816 niu_init_xif(np);
5817 err = niu_init_pcs(np);
5818 if (err)
5819 return err;
5820
5821 err = niu_reset_tx_mac(np);
5822 if (err)
5823 return err;
5824 niu_init_tx_mac(np);
5825 err = niu_reset_rx_mac(np);
5826 if (err)
5827 return err;
5828 niu_init_rx_mac(np);
5829
5830 /* This looks hookey but the RX MAC reset we just did will
5831 * undo some of the state we setup in niu_init_tx_mac() so we
5832 * have to call it again. In particular, the RX MAC reset will
5833 * set the XMAC_MAX register back to it's default value.
5834 */
5835 niu_init_tx_mac(np);
5836 niu_enable_tx_mac(np, 1);
5837
5838 niu_enable_rx_mac(np, 1);
5839
5840 return 0;
5841}
5842
5843static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5844{
5845 (void) niu_tx_channel_stop(np, rp->tx_channel);
5846}
5847
5848static void niu_stop_tx_channels(struct niu *np)
5849{
5850 int i;
5851
5852 for (i = 0; i < np->num_tx_rings; i++) {
5853 struct tx_ring_info *rp = &np->tx_rings[i];
5854
5855 niu_stop_one_tx_channel(np, rp);
5856 }
5857}
5858
5859static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5860{
5861 (void) niu_tx_channel_reset(np, rp->tx_channel);
5862}
5863
5864static void niu_reset_tx_channels(struct niu *np)
5865{
5866 int i;
5867
5868 for (i = 0; i < np->num_tx_rings; i++) {
5869 struct tx_ring_info *rp = &np->tx_rings[i];
5870
5871 niu_reset_one_tx_channel(np, rp);
5872 }
5873}
5874
5875static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5876{
5877 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5878}
5879
5880static void niu_stop_rx_channels(struct niu *np)
5881{
5882 int i;
5883
5884 for (i = 0; i < np->num_rx_rings; i++) {
5885 struct rx_ring_info *rp = &np->rx_rings[i];
5886
5887 niu_stop_one_rx_channel(np, rp);
5888 }
5889}
5890
5891static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5892{
5893 int channel = rp->rx_channel;
5894
5895 (void) niu_rx_channel_reset(np, channel);
5896 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5897 nw64(RX_DMA_CTL_STAT(channel), 0);
5898 (void) niu_enable_rx_channel(np, channel, 0);
5899}
5900
5901static void niu_reset_rx_channels(struct niu *np)
5902{
5903 int i;
5904
5905 for (i = 0; i < np->num_rx_rings; i++) {
5906 struct rx_ring_info *rp = &np->rx_rings[i];
5907
5908 niu_reset_one_rx_channel(np, rp);
5909 }
5910}
5911
5912static void niu_disable_ipp(struct niu *np)
5913{
5914 u64 rd, wr, val;
5915 int limit;
5916
5917 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5918 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5919 limit = 100;
5920 while (--limit >= 0 && (rd != wr)) {
5921 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5922 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5923 }
5924 if (limit < 0 &&
5925 (rd != 0 && wr != 1)) {
f10a1f2e
JP		 5926 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5927 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5928 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
a3138df9
DM		 5929 }
5930
5931 val = nr64_ipp(IPP_CFIG);
5932 val &= ~(IPP_CFIG_IPP_ENABLE |
5933 IPP_CFIG_DFIFO_ECC_EN |
5934 IPP_CFIG_DROP_BAD_CRC |
5935 IPP_CFIG_CKSUM_EN);
5936 nw64_ipp(IPP_CFIG, val);
5937
5938 (void) niu_ipp_reset(np);
5939}
5940
5941static int niu_init_hw(struct niu *np)
5942{
5943 int i, err;
5944
f10a1f2e 5945 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
a3138df9
DM		 5946 niu_txc_enable_port(np, 1);
5947 niu_txc_port_dma_enable(np, 1);
5948 niu_txc_set_imask(np, 0);
5949
f10a1f2e 5950 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
a3138df9
DM		 5951 for (i = 0; i < np->num_tx_rings; i++) {
5952 struct tx_ring_info *rp = &np->tx_rings[i];
5953
5954 err = niu_init_one_tx_channel(np, rp);
5955 if (err)
5956 return err;
5957 }
5958
f10a1f2e 5959 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
a3138df9
DM		 5960 err = niu_init_rx_channels(np);
5961 if (err)
5962 goto out_uninit_tx_channels;
5963
f10a1f2e 5964 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
a3138df9
DM		 5965 err = niu_init_classifier_hw(np);
5966 if (err)
5967 goto out_uninit_rx_channels;
5968
f10a1f2e 5969 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
a3138df9
DM		 5970 err = niu_init_zcp(np);
5971 if (err)
5972 goto out_uninit_rx_channels;
5973
f10a1f2e 5974 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
a3138df9
DM		 5975 err = niu_init_ipp(np);
5976 if (err)
5977 goto out_uninit_rx_channels;
5978
f10a1f2e 5979 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
a3138df9
DM		 5980 err = niu_init_mac(np);
5981 if (err)
5982 goto out_uninit_ipp;
5983
5984 return 0;
5985
5986out_uninit_ipp:
f10a1f2e 5987 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
a3138df9
DM		 5988 niu_disable_ipp(np);
5989
5990out_uninit_rx_channels:
f10a1f2e 5991 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
a3138df9
DM		 5992 niu_stop_rx_channels(np);
5993 niu_reset_rx_channels(np);
5994
5995out_uninit_tx_channels:
f10a1f2e 5996 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
a3138df9
DM		 5997 niu_stop_tx_channels(np);
5998 niu_reset_tx_channels(np);
5999
6000 return err;
6001}
6002
6003static void niu_stop_hw(struct niu *np)
6004{
f10a1f2e 6005 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
a3138df9
DM		 6006 niu_enable_interrupts(np, 0);
6007
f10a1f2e 6008 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
a3138df9
DM		 6009 niu_enable_rx_mac(np, 0);
6010
f10a1f2e 6011 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
a3138df9
DM		 6012 niu_disable_ipp(np);
6013
f10a1f2e 6014 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
a3138df9
DM		 6015 niu_stop_tx_channels(np);
6016
f10a1f2e 6017 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
a3138df9
DM		 6018 niu_stop_rx_channels(np);
6019
f10a1f2e 6020 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
a3138df9
DM		 6021 niu_reset_tx_channels(np);
6022
f10a1f2e 6023 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
a3138df9
DM		 6024 niu_reset_rx_channels(np);
6025}
6026
70340d72
RO		 6027static void niu_set_irq_name(struct niu *np)
6028{
6029 int port = np->port;
6030 int i, j = 1;
6031
6032 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6033
6034 if (port == 0) {
6035 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6036 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6037 j = 3;
6038 }
6039
6040 for (i = 0; i < np->num_ldg - j; i++) {
6041 if (i < np->num_rx_rings)
6042 sprintf(np->irq_name[i+j], "%s-rx-%d",
6043 np->dev->name, i);
6044 else if (i < np->num_tx_rings + np->num_rx_rings)
6045 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6046 i - np->num_rx_rings);
6047 }
6048}
6049
a3138df9
DM		 6050static int niu_request_irq(struct niu *np)
6051{
6052 int i, j, err;
6053
70340d72
RO		 6054 niu_set_irq_name(np);
6055
a3138df9
DM		 6056 err = 0;
6057 for (i = 0; i < np->num_ldg; i++) {
6058 struct niu_ldg *lp = &np->ldg[i];
6059
6060 err = request_irq(lp->irq, niu_interrupt,
6061 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
70340d72 6062 np->irq_name[i], lp);
a3138df9
DM		 6063 if (err)
6064 goto out_free_irqs;
6065
6066 }
6067
6068 return 0;
6069
6070out_free_irqs:
6071 for (j = 0; j < i; j++) {
6072 struct niu_ldg *lp = &np->ldg[j];
6073
6074 free_irq(lp->irq, lp);
6075 }
6076 return err;
6077}
6078
6079static void niu_free_irq(struct niu *np)
6080{
6081 int i;
6082
6083 for (i = 0; i < np->num_ldg; i++) {
6084 struct niu_ldg *lp = &np->ldg[i];
6085
6086 free_irq(lp->irq, lp);
6087 }
6088}
6089
6090static void niu_enable_napi(struct niu *np)
6091{
6092 int i;
6093
6094 for (i = 0; i < np->num_ldg; i++)
6095 napi_enable(&np->ldg[i].napi);
6096}
6097
6098static void niu_disable_napi(struct niu *np)
6099{
6100 int i;
6101
6102 for (i = 0; i < np->num_ldg; i++)
6103 napi_disable(&np->ldg[i].napi);
6104}
6105
6106static int niu_open(struct net_device *dev)
6107{
6108 struct niu *np = netdev_priv(dev);
6109 int err;
6110
6111 netif_carrier_off(dev);
6112
6113 err = niu_alloc_channels(np);
6114 if (err)
6115 goto out_err;
6116
6117 err = niu_enable_interrupts(np, 0);
6118 if (err)
6119 goto out_free_channels;
6120
6121 err = niu_request_irq(np);
6122 if (err)
6123 goto out_free_channels;
6124
6125 niu_enable_napi(np);
6126
6127 spin_lock_irq(&np->lock);
6128
6129 err = niu_init_hw(np);
6130 if (!err) {
6131 init_timer(&np->timer);
6132 np->timer.expires = jiffies + HZ;
6133 np->timer.data = (unsigned long) np;
6134 np->timer.function = niu_timer;
6135
6136 err = niu_enable_interrupts(np, 1);
6137 if (err)
6138 niu_stop_hw(np);
6139 }
6140
6141 spin_unlock_irq(&np->lock);
6142
6143 if (err) {
6144 niu_disable_napi(np);
6145 goto out_free_irq;
6146 }
6147
b4c21639 6148 netif_tx_start_all_queues(dev);
a3138df9
DM		 6149
6150 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6151 netif_carrier_on(dev);
6152
6153 add_timer(&np->timer);
6154
6155 return 0;
6156
6157out_free_irq:
6158 niu_free_irq(np);
6159
6160out_free_channels:
6161 niu_free_channels(np);
6162
6163out_err:
6164 return err;
6165}
6166
6167static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6168{
6169 cancel_work_sync(&np->reset_task);
6170
6171 niu_disable_napi(np);
b4c21639 6172 netif_tx_stop_all_queues(dev);
a3138df9
DM		 6173
6174 del_timer_sync(&np->timer);
6175
6176 spin_lock_irq(&np->lock);
6177
6178 niu_stop_hw(np);
6179
6180 spin_unlock_irq(&np->lock);
6181}
6182
6183static int niu_close(struct net_device *dev)
6184{
6185 struct niu *np = netdev_priv(dev);
6186
6187 niu_full_shutdown(np, dev);
6188
6189 niu_free_irq(np);
6190
6191 niu_free_channels(np);
6192
0c3b091b
ML		 6193 niu_handle_led(np, 0);
6194
a3138df9
DM		 6195 return 0;
6196}
6197
6198static void niu_sync_xmac_stats(struct niu *np)
6199{
6200 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6201
6202 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6203 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6204
6205 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6206 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6207 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6208 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6209 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6210 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6211 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6212 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6213 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6214 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6215 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6216 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6217 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6218 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6219 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6220 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6221}
6222
6223static void niu_sync_bmac_stats(struct niu *np)
6224{
6225 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6226
6227 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6228 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6229
6230 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6231 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6232 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6233 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6234}
6235
6236static void niu_sync_mac_stats(struct niu *np)
6237{
6238 if (np->flags & NIU_FLAGS_XMAC)
6239 niu_sync_xmac_stats(np);
6240 else
6241 niu_sync_bmac_stats(np);
6242}
6243
6244static void niu_get_rx_stats(struct niu *np)
6245{
6246 unsigned long pkts, dropped, errors, bytes;
6247 int i;
6248
6249 pkts = dropped = errors = bytes = 0;
6250 for (i = 0; i < np->num_rx_rings; i++) {
6251 struct rx_ring_info *rp = &np->rx_rings[i];
6252
b8a606b8
JDB		 6253 niu_sync_rx_discard_stats(np, rp, 0);
6254
a3138df9
DM		 6255 pkts += rp->rx_packets;
6256 bytes += rp->rx_bytes;
6257 dropped += rp->rx_dropped;
6258 errors += rp->rx_errors;
6259 }
9fd42876
IJ		 6260 np->dev->stats.rx_packets = pkts;
6261 np->dev->stats.rx_bytes = bytes;
6262 np->dev->stats.rx_dropped = dropped;
6263 np->dev->stats.rx_errors = errors;
a3138df9
DM		 6264}
6265
6266static void niu_get_tx_stats(struct niu *np)
6267{
6268 unsigned long pkts, errors, bytes;
6269 int i;
6270
6271 pkts = errors = bytes = 0;
6272 for (i = 0; i < np->num_tx_rings; i++) {
6273 struct tx_ring_info *rp = &np->tx_rings[i];
6274
6275 pkts += rp->tx_packets;
6276 bytes += rp->tx_bytes;
6277 errors += rp->tx_errors;
6278 }
9fd42876
IJ		 6279 np->dev->stats.tx_packets = pkts;
6280 np->dev->stats.tx_bytes = bytes;
6281 np->dev->stats.tx_errors = errors;
a3138df9
DM		 6282}
6283
6284static struct net_device_stats *niu_get_stats(struct net_device *dev)
6285{
6286 struct niu *np = netdev_priv(dev);
6287
6288 niu_get_rx_stats(np);
6289 niu_get_tx_stats(np);
6290
9fd42876 6291 return &dev->stats;
a3138df9
DM		 6292}
6293
6294static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6295{
6296 int i;
6297
6298 for (i = 0; i < 16; i++)
6299 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6300}
6301
6302static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6303{
6304 int i;
6305
6306 for (i = 0; i < 16; i++)
6307 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6308}
6309
6310static void niu_load_hash(struct niu *np, u16 *hash)
6311{
6312 if (np->flags & NIU_FLAGS_XMAC)
6313 niu_load_hash_xmac(np, hash);
6314 else
6315 niu_load_hash_bmac(np, hash);
6316}
6317
6318static void niu_set_rx_mode(struct net_device *dev)
6319{
6320 struct niu *np = netdev_priv(dev);
6321 int i, alt_cnt, err;
ccffad25 6322 struct netdev_hw_addr *ha;
a3138df9
DM		 6323 unsigned long flags;
6324 u16 hash[16] = { 0, };
6325
6326 spin_lock_irqsave(&np->lock, flags);
6327 niu_enable_rx_mac(np, 0);
6328
6329 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6330 if (dev->flags & IFF_PROMISC)
6331 np->flags |= NIU_FLAGS_PROMISC;
4cd24eaf 6332 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
a3138df9
DM		 6333 np->flags |= NIU_FLAGS_MCAST;
6334
32e7bfc4 6335 alt_cnt = netdev_uc_count(dev);
a3138df9
DM		 6336 if (alt_cnt > niu_num_alt_addr(np)) {
6337 alt_cnt = 0;
6338 np->flags |= NIU_FLAGS_PROMISC;
6339 }
6340
6341 if (alt_cnt) {
6342 int index = 0;
6343
32e7bfc4 6344 netdev_for_each_uc_addr(ha, dev) {
ccffad25 6345 err = niu_set_alt_mac(np, index, ha->addr);
a3138df9 6346 if (err)
f10a1f2e
JP		 6347 netdev_warn(dev, "Error %d adding alt mac %d\n",
6348 err, index);
a3138df9
DM		 6349 err = niu_enable_alt_mac(np, index, 1);
6350 if (err)
f10a1f2e
JP		 6351 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6352 err, index);
a3138df9
DM		 6353
6354 index++;
6355 }
6356 } else {
3b5bcede
MW		 6357 int alt_start;
6358 if (np->flags & NIU_FLAGS_XMAC)
6359 alt_start = 0;
6360 else
6361 alt_start = 1;
6362 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
a3138df9
DM		 6363 err = niu_enable_alt_mac(np, i, 0);
6364 if (err)
f10a1f2e
JP		 6365 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6366 err, i);
a3138df9
DM		 6367 }
6368 }
6369 if (dev->flags & IFF_ALLMULTI) {
6370 for (i = 0; i < 16; i++)
6371 hash[i] = 0xffff;
4cd24eaf 6372 } else if (!netdev_mc_empty(dev)) {
22bedad3
JP		 6373 netdev_for_each_mc_addr(ha, dev) {
6374 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
a3138df9
DM		 6375
6376 crc >>= 24;
6377 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6378 }
6379 }
6380
6381 if (np->flags & NIU_FLAGS_MCAST)
6382 niu_load_hash(np, hash);
6383
6384 niu_enable_rx_mac(np, 1);
6385 spin_unlock_irqrestore(&np->lock, flags);
6386}
6387
6388static int niu_set_mac_addr(struct net_device *dev, void *p)
6389{
6390 struct niu *np = netdev_priv(dev);
6391 struct sockaddr *addr = p;
6392 unsigned long flags;
6393
6394 if (!is_valid_ether_addr(addr->sa_data))
6395 return -EINVAL;
6396
6397 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6398
6399 if (!netif_running(dev))
6400 return 0;
6401
6402 spin_lock_irqsave(&np->lock, flags);
6403 niu_enable_rx_mac(np, 0);
6404 niu_set_primary_mac(np, dev->dev_addr);
6405 niu_enable_rx_mac(np, 1);
6406 spin_unlock_irqrestore(&np->lock, flags);
6407
6408 return 0;
6409}
6410
6411static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6412{
6413 return -EOPNOTSUPP;
6414}
6415
6416static void niu_netif_stop(struct niu *np)
6417{
6418 np->dev->trans_start = jiffies; /* prevent tx timeout */
6419
6420 niu_disable_napi(np);
6421
6422 netif_tx_disable(np->dev);
6423}
6424
6425static void niu_netif_start(struct niu *np)
6426{
6427 /* NOTE: unconditional netif_wake_queue is only appropriate
6428 * so long as all callers are assured to have free tx slots
6429 * (such as after niu_init_hw).
6430 */
b4c21639 6431 netif_tx_wake_all_queues(np->dev);
a3138df9
DM		 6432
6433 niu_enable_napi(np);
6434
6435 niu_enable_interrupts(np, 1);
6436}
6437
cff502a3
SB		 6438static void niu_reset_buffers(struct niu *np)
6439{
6440 int i, j, k, err;
6441
6442 if (np->rx_rings) {
6443 for (i = 0; i < np->num_rx_rings; i++) {
6444 struct rx_ring_info *rp = &np->rx_rings[i];
6445
6446 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6447 struct page *page;
6448
6449 page = rp->rxhash[j];
6450 while (page) {
6451 struct page *next =
6452 (struct page *) page->mapping;
6453 u64 base = page->index;
6454 base = base >> RBR_DESCR_ADDR_SHIFT;
6455 rp->rbr[k++] = cpu_to_le32(base);
6456 page = next;
6457 }
6458 }
6459 for (; k < MAX_RBR_RING_SIZE; k++) {
6460 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6461 if (unlikely(err))
6462 break;
6463 }
6464
6465 rp->rbr_index = rp->rbr_table_size - 1;
6466 rp->rcr_index = 0;
6467 rp->rbr_pending = 0;
6468 rp->rbr_refill_pending = 0;
6469 }
6470 }
6471 if (np->tx_rings) {
6472 for (i = 0; i < np->num_tx_rings; i++) {
6473 struct tx_ring_info *rp = &np->tx_rings[i];
6474
6475 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6476 if (rp->tx_buffs[j].skb)
6477 (void) release_tx_packet(np, rp, j);
6478 }
6479
6480 rp->pending = MAX_TX_RING_SIZE;
6481 rp->prod = 0;
6482 rp->cons = 0;
6483 rp->wrap_bit = 0;
6484 }
6485 }
6486}
6487
a3138df9
DM		 6488static void niu_reset_task(struct work_struct *work)
6489{
6490 struct niu *np = container_of(work, struct niu, reset_task);
6491 unsigned long flags;
6492 int err;
6493
6494 spin_lock_irqsave(&np->lock, flags);
6495 if (!netif_running(np->dev)) {
6496 spin_unlock_irqrestore(&np->lock, flags);
6497 return;
6498 }
6499
6500 spin_unlock_irqrestore(&np->lock, flags);
6501
6502 del_timer_sync(&np->timer);
6503
6504 niu_netif_stop(np);
6505
6506 spin_lock_irqsave(&np->lock, flags);
6507
6508 niu_stop_hw(np);
6509
cff502a3
SB		 6510 spin_unlock_irqrestore(&np->lock, flags);
6511
6512 niu_reset_buffers(np);
6513
6514 spin_lock_irqsave(&np->lock, flags);
6515
a3138df9
DM		 6516 err = niu_init_hw(np);
6517 if (!err) {
6518 np->timer.expires = jiffies + HZ;
6519 add_timer(&np->timer);
6520 niu_netif_start(np);
6521 }
6522
6523 spin_unlock_irqrestore(&np->lock, flags);
6524}
6525
6526static void niu_tx_timeout(struct net_device *dev)
6527{
6528 struct niu *np = netdev_priv(dev);
6529
f10a1f2e 6530 dev_err(np->device, "%s: Transmit timed out, resetting\n",
a3138df9
DM		 6531 dev->name);
6532
6533 schedule_work(&np->reset_task);
6534}
6535
6536static void niu_set_txd(struct tx_ring_info *rp, int index,
6537 u64 mapping, u64 len, u64 mark,
6538 u64 n_frags)
6539{
6540 __le64 *desc = &rp->descr[index];
6541
6542 *desc = cpu_to_le64(mark |
6543 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6544 (len << TX_DESC_TR_LEN_SHIFT) |
6545 (mapping & TX_DESC_SAD));
6546}
6547
6548static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6549 u64 pad_bytes, u64 len)
6550{
6551 u16 eth_proto, eth_proto_inner;
6552 u64 csum_bits, l3off, ihl, ret;
6553 u8 ip_proto;
6554 int ipv6;
6555
6556 eth_proto = be16_to_cpu(ehdr->h_proto);
6557 eth_proto_inner = eth_proto;
6558 if (eth_proto == ETH_P_8021Q) {
6559 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6560 __be16 val = vp->h_vlan_encapsulated_proto;
6561
6562 eth_proto_inner = be16_to_cpu(val);
6563 }
6564
6565 ipv6 = ihl = 0;
6566 switch (skb->protocol) {
09640e63 6567 case cpu_to_be16(ETH_P_IP):
a3138df9
DM		 6568 ip_proto = ip_hdr(skb)->protocol;
6569 ihl = ip_hdr(skb)->ihl;
6570 break;
09640e63 6571 case cpu_to_be16(ETH_P_IPV6):
a3138df9
DM		 6572 ip_proto = ipv6_hdr(skb)->nexthdr;
6573 ihl = (40 >> 2);
6574 ipv6 = 1;
6575 break;
6576 default:
6577 ip_proto = ihl = 0;
6578 break;
6579 }
6580
6581 csum_bits = TXHDR_CSUM_NONE;
6582 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6583 u64 start, stuff;
6584
6585 csum_bits = (ip_proto == IPPROTO_TCP ?
6586 TXHDR_CSUM_TCP :
6587 (ip_proto == IPPROTO_UDP ?
6588 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6589
6590 start = skb_transport_offset(skb) -
6591 (pad_bytes + sizeof(struct tx_pkt_hdr));
6592 stuff = start + skb->csum_offset;
6593
6594 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6595 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6596 }
6597
6598 l3off = skb_network_offset(skb) -
6599 (pad_bytes + sizeof(struct tx_pkt_hdr));
6600
6601 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6602 (len << TXHDR_LEN_SHIFT) |
6603 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6604 (ihl << TXHDR_IHL_SHIFT) |
6605 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6606 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6607 (ipv6 ? TXHDR_IP_VER : 0) |
6608 csum_bits);
6609
6610 return ret;
6611}
6612
61357325
SH		 6613static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6614 struct net_device *dev)
a3138df9
DM		 6615{
6616 struct niu *np = netdev_priv(dev);
6617 unsigned long align, headroom;
b4c21639 6618 struct netdev_queue *txq;
a3138df9
DM		 6619 struct tx_ring_info *rp;
6620 struct tx_pkt_hdr *tp;
6621 unsigned int len, nfg;
6622 struct ethhdr *ehdr;
6623 int prod, i, tlen;
6624 u64 mapping, mrk;
6625
b4c21639
DM		 6626 i = skb_get_queue_mapping(skb);
6627 rp = &np->tx_rings[i];
6628 txq = netdev_get_tx_queue(dev, i);
a3138df9
DM		 6629
6630 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
b4c21639 6631 netif_tx_stop_queue(txq);
f10a1f2e 6632 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
a3138df9
DM		 6633 rp->tx_errors++;
6634 return NETDEV_TX_BUSY;
6635 }
6636
6637 if (skb->len < ETH_ZLEN) {
6638 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6639
6640 if (skb_pad(skb, pad_bytes))
6641 goto out;
6642 skb_put(skb, pad_bytes);
6643 }
6644
6645 len = sizeof(struct tx_pkt_hdr) + 15;
6646 if (skb_headroom(skb) < len) {
6647 struct sk_buff *skb_new;
6648
6649 skb_new = skb_realloc_headroom(skb, len);
6650 if (!skb_new) {
6651 rp->tx_errors++;
6652 goto out_drop;
6653 }
6654 kfree_skb(skb);
6655 skb = skb_new;
3ebebccf
DM		 6656 } else
6657 skb_orphan(skb);
a3138df9
DM		 6658
6659 align = ((unsigned long) skb->data & (16 - 1));
6660 headroom = align + sizeof(struct tx_pkt_hdr);
6661
6662 ehdr = (struct ethhdr *) skb->data;
6663 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6664
6665 len = skb->len - sizeof(struct tx_pkt_hdr);
6666 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6667 tp->resv = 0;
6668
6669 len = skb_headlen(skb);
6670 mapping = np->ops->map_single(np->device, skb->data,
6671 len, DMA_TO_DEVICE);
6672
6673 prod = rp->prod;
6674
6675 rp->tx_buffs[prod].skb = skb;
6676 rp->tx_buffs[prod].mapping = mapping;
6677
6678 mrk = TX_DESC_SOP;
6679 if (++rp->mark_counter == rp->mark_freq) {
6680 rp->mark_counter = 0;
6681 mrk |= TX_DESC_MARK;
6682 rp->mark_pending++;
6683 }
6684
6685 tlen = len;
6686 nfg = skb_shinfo(skb)->nr_frags;
6687 while (tlen > 0) {
6688 tlen -= MAX_TX_DESC_LEN;
6689 nfg++;
6690 }
6691
6692 while (len > 0) {
6693 unsigned int this_len = len;
6694
6695 if (this_len > MAX_TX_DESC_LEN)
6696 this_len = MAX_TX_DESC_LEN;
6697
6698 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6699 mrk = nfg = 0;
6700
6701 prod = NEXT_TX(rp, prod);
6702 mapping += this_len;
6703 len -= this_len;
6704 }
6705
6706 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6707 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6708
6709 len = frag->size;
6710 mapping = np->ops->map_page(np->device, frag->page,
6711 frag->page_offset, len,
6712 DMA_TO_DEVICE);
6713
6714 rp->tx_buffs[prod].skb = NULL;
6715 rp->tx_buffs[prod].mapping = mapping;
6716
6717 niu_set_txd(rp, prod, mapping, len, 0, 0);
6718
6719 prod = NEXT_TX(rp, prod);
6720 }
6721
6722 if (prod < rp->prod)
6723 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6724 rp->prod = prod;
6725
6726 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6727
6728 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
b4c21639 6729 netif_tx_stop_queue(txq);
a3138df9 6730 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
b4c21639 6731 netif_tx_wake_queue(txq);
a3138df9
DM		 6732 }
6733
a3138df9
DM		 6734out:
6735 return NETDEV_TX_OK;
6736
6737out_drop:
6738 rp->tx_errors++;
6739 kfree_skb(skb);
6740 goto out;
6741}
6742
6743static int niu_change_mtu(struct net_device *dev, int new_mtu)
6744{
6745 struct niu *np = netdev_priv(dev);
6746 int err, orig_jumbo, new_jumbo;
6747
6748 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6749 return -EINVAL;
6750
6751 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6752 new_jumbo = (new_mtu > ETH_DATA_LEN);
6753
6754 dev->mtu = new_mtu;
6755
6756 if (!netif_running(dev) ||
6757 (orig_jumbo == new_jumbo))
6758 return 0;
6759
6760 niu_full_shutdown(np, dev);
6761
6762 niu_free_channels(np);
6763
6764 niu_enable_napi(np);
6765
6766 err = niu_alloc_channels(np);
6767 if (err)
6768 return err;
6769
6770 spin_lock_irq(&np->lock);
6771
6772 err = niu_init_hw(np);
6773 if (!err) {
6774 init_timer(&np->timer);
6775 np->timer.expires = jiffies + HZ;
6776 np->timer.data = (unsigned long) np;
6777 np->timer.function = niu_timer;
6778
6779 err = niu_enable_interrupts(np, 1);
6780 if (err)
6781 niu_stop_hw(np);
6782 }
6783
6784 spin_unlock_irq(&np->lock);
6785
6786 if (!err) {
b4c21639 6787 netif_tx_start_all_queues(dev);
a3138df9
DM		 6788 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6789 netif_carrier_on(dev);
6790
6791 add_timer(&np->timer);
6792 }
6793
6794 return err;
6795}
6796
6797static void niu_get_drvinfo(struct net_device *dev,
6798 struct ethtool_drvinfo *info)
6799{
6800 struct niu *np = netdev_priv(dev);
6801 struct niu_vpd *vpd = &np->vpd;
6802
6803 strcpy(info->driver, DRV_MODULE_NAME);
6804 strcpy(info->version, DRV_MODULE_VERSION);
6805 sprintf(info->fw_version, "%d.%d",
6806 vpd->fcode_major, vpd->fcode_minor);
6807 if (np->parent->plat_type != PLAT_TYPE_NIU)
6808 strcpy(info->bus_info, pci_name(np->pdev));
6809}
6810
6811static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6812{
6813 struct niu *np = netdev_priv(dev);
6814 struct niu_link_config *lp;
6815
6816 lp = &np->link_config;
6817
6818 memset(cmd, 0, sizeof(*cmd));
6819 cmd->phy_address = np->phy_addr;
6820 cmd->supported = lp->supported;
38bb045d
CB		 6821 cmd->advertising = lp->active_advertising;
6822 cmd->autoneg = lp->active_autoneg;
a3138df9
DM		 6823 cmd->speed = lp->active_speed;
6824 cmd->duplex = lp->active_duplex;
38bb045d
CB		 6825 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6826 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6827 XCVR_EXTERNAL : XCVR_INTERNAL;
a3138df9
DM		 6828
6829 return 0;
6830}
6831
6832static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6833{
38bb045d
CB		 6834 struct niu *np = netdev_priv(dev);
6835 struct niu_link_config *lp = &np->link_config;
6836
6837 lp->advertising = cmd->advertising;
6838 lp->speed = cmd->speed;
6839 lp->duplex = cmd->duplex;
6840 lp->autoneg = cmd->autoneg;
6841 return niu_init_link(np);
a3138df9
DM		 6842}
6843
6844static u32 niu_get_msglevel(struct net_device *dev)
6845{
6846 struct niu *np = netdev_priv(dev);
6847 return np->msg_enable;
6848}
6849
6850static void niu_set_msglevel(struct net_device *dev, u32 value)
6851{
6852 struct niu *np = netdev_priv(dev);
6853 np->msg_enable = value;
6854}
6855
38bb045d
CB		 6856static int niu_nway_reset(struct net_device *dev)
6857{
6858 struct niu *np = netdev_priv(dev);
6859
6860 if (np->link_config.autoneg)
6861 return niu_init_link(np);
6862
6863 return 0;
6864}
6865
a3138df9
DM		 6866static int niu_get_eeprom_len(struct net_device *dev)
6867{
6868 struct niu *np = netdev_priv(dev);
6869
6870 return np->eeprom_len;
6871}
6872
6873static int niu_get_eeprom(struct net_device *dev,
6874 struct ethtool_eeprom *eeprom, u8 *data)
6875{
6876 struct niu *np = netdev_priv(dev);
6877 u32 offset, len, val;
6878
6879 offset = eeprom->offset;
6880 len = eeprom->len;
6881
6882 if (offset + len < offset)
6883 return -EINVAL;
6884 if (offset >= np->eeprom_len)
6885 return -EINVAL;
6886 if (offset + len > np->eeprom_len)
6887 len = eeprom->len = np->eeprom_len - offset;
6888
6889 if (offset & 3) {
6890 u32 b_offset, b_count;
6891
6892 b_offset = offset & 3;
6893 b_count = 4 - b_offset;
6894 if (b_count > len)
6895 b_count = len;
6896
6897 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6898 memcpy(data, ((char *)&val) + b_offset, b_count);
6899 data += b_count;
6900 len -= b_count;
6901 offset += b_count;
6902 }
6903 while (len >= 4) {
6904 val = nr64(ESPC_NCR(offset / 4));
6905 memcpy(data, &val, 4);
6906 data += 4;
6907 len -= 4;
6908 offset += 4;
6909 }
6910 if (len) {
6911 val = nr64(ESPC_NCR(offset / 4));
6912 memcpy(data, &val, len);
6913 }
6914 return 0;
6915}
6916
2d96cf8c
SB		 6917static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6918{
6919 switch (flow_type) {
6920 case TCP_V4_FLOW:
6921 case TCP_V6_FLOW:
6922 *pid = IPPROTO_TCP;
6923 break;
6924 case UDP_V4_FLOW:
6925 case UDP_V6_FLOW:
6926 *pid = IPPROTO_UDP;
6927 break;
6928 case SCTP_V4_FLOW:
6929 case SCTP_V6_FLOW:
6930 *pid = IPPROTO_SCTP;
6931 break;
6932 case AH_V4_FLOW:
6933 case AH_V6_FLOW:
6934 *pid = IPPROTO_AH;
6935 break;
6936 case ESP_V4_FLOW:
6937 case ESP_V6_FLOW:
6938 *pid = IPPROTO_ESP;
6939 break;
6940 default:
6941 *pid = 0;
6942 break;
6943 }
6944}
6945
6946static int niu_class_to_ethflow(u64 class, int *flow_type)
6947{
6948 switch (class) {
6949 case CLASS_CODE_TCP_IPV4:
6950 *flow_type = TCP_V4_FLOW;
6951 break;
6952 case CLASS_CODE_UDP_IPV4:
6953 *flow_type = UDP_V4_FLOW;
6954 break;
6955 case CLASS_CODE_AH_ESP_IPV4:
6956 *flow_type = AH_V4_FLOW;
6957 break;
6958 case CLASS_CODE_SCTP_IPV4:
6959 *flow_type = SCTP_V4_FLOW;
6960 break;
6961 case CLASS_CODE_TCP_IPV6:
6962 *flow_type = TCP_V6_FLOW;
6963 break;
6964 case CLASS_CODE_UDP_IPV6:
6965 *flow_type = UDP_V6_FLOW;
6966 break;
6967 case CLASS_CODE_AH_ESP_IPV6:
6968 *flow_type = AH_V6_FLOW;
6969 break;
6970 case CLASS_CODE_SCTP_IPV6:
6971 *flow_type = SCTP_V6_FLOW;
6972 break;
6973 case CLASS_CODE_USER_PROG1:
6974 case CLASS_CODE_USER_PROG2:
6975 case CLASS_CODE_USER_PROG3:
6976 case CLASS_CODE_USER_PROG4:
6977 *flow_type = IP_USER_FLOW;
6978 break;
6979 default:
6980 return 0;
6981 }
6982
6983 return 1;
6984}
6985
b4653e99
SB		 6986static int niu_ethflow_to_class(int flow_type, u64 *class)
6987{
6988 switch (flow_type) {
6989 case TCP_V4_FLOW:
6990 *class = CLASS_CODE_TCP_IPV4;
6991 break;
6992 case UDP_V4_FLOW:
6993 *class = CLASS_CODE_UDP_IPV4;
6994 break;
2d96cf8c
SB		 6995 case AH_V4_FLOW:
6996 case ESP_V4_FLOW:
b4653e99
SB		 6997 *class = CLASS_CODE_AH_ESP_IPV4;
6998 break;
6999 case SCTP_V4_FLOW:
7000 *class = CLASS_CODE_SCTP_IPV4;
7001 break;
7002 case TCP_V6_FLOW:
7003 *class = CLASS_CODE_TCP_IPV6;
7004 break;
7005 case UDP_V6_FLOW:
7006 *class = CLASS_CODE_UDP_IPV6;
7007 break;
2d96cf8c
SB		 7008 case AH_V6_FLOW:
7009 case ESP_V6_FLOW:
b4653e99
SB		 7010 *class = CLASS_CODE_AH_ESP_IPV6;
7011 break;
7012 case SCTP_V6_FLOW:
7013 *class = CLASS_CODE_SCTP_IPV6;
7014 break;
7015 default:
38c080ff 7016 return 0;
b4653e99
SB		 7017 }
7018
7019 return 1;
7020}
7021
7022static u64 niu_flowkey_to_ethflow(u64 flow_key)
7023{
7024 u64 ethflow = 0;
7025
b4653e99
SB		 7026 if (flow_key & FLOW_KEY_L2DA)
7027 ethflow |= RXH_L2DA;
7028 if (flow_key & FLOW_KEY_VLAN)
7029 ethflow |= RXH_VLAN;
7030 if (flow_key & FLOW_KEY_IPSA)
7031 ethflow |= RXH_IP_SRC;
7032 if (flow_key & FLOW_KEY_IPDA)
7033 ethflow |= RXH_IP_DST;
7034 if (flow_key & FLOW_KEY_PROTO)
7035 ethflow |= RXH_L3_PROTO;
7036 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7037 ethflow |= RXH_L4_B_0_1;
7038 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7039 ethflow |= RXH_L4_B_2_3;
7040
7041 return ethflow;
7042
7043}
7044
7045static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7046{
7047 u64 key = 0;
7048
b4653e99
SB		 7049 if (ethflow & RXH_L2DA)
7050 key |= FLOW_KEY_L2DA;
7051 if (ethflow & RXH_VLAN)
7052 key |= FLOW_KEY_VLAN;
7053 if (ethflow & RXH_IP_SRC)
7054 key |= FLOW_KEY_IPSA;
7055 if (ethflow & RXH_IP_DST)
7056 key |= FLOW_KEY_IPDA;
7057 if (ethflow & RXH_L3_PROTO)
7058 key |= FLOW_KEY_PROTO;
7059 if (ethflow & RXH_L4_B_0_1)
7060 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7061 if (ethflow & RXH_L4_B_2_3)
7062 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7063
7064 *flow_key = key;
7065
7066 return 1;
7067
7068}
7069
2d96cf8c 7070static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
b4653e99 7071{
b4653e99
SB		 7072 u64 class;
7073
2d96cf8c 7074 nfc->data = 0;
b4653e99 7075
2d96cf8c 7076 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7077 return -EINVAL;
7078
7079 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7080 TCAM_KEY_DISC)
2d96cf8c 7081 nfc->data = RXH_DISCARD;
b4653e99 7082 else
2d96cf8c 7083 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
b4653e99
SB		 7084 CLASS_CODE_USER_PROG1]);
7085 return 0;
7086}
7087
2d96cf8c
SB		 7088static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7089 struct ethtool_rx_flow_spec *fsp)
7090{
7091
7092 fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7093 TCAM_V4KEY3_SADDR_SHIFT;
7094 fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7095 TCAM_V4KEY3_DADDR_SHIFT;
7096 fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7097 TCAM_V4KEY3_SADDR_SHIFT;
7098 fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7099 TCAM_V4KEY3_DADDR_SHIFT;
7100
7101 fsp->h_u.tcp_ip4_spec.ip4src =
7102 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7103 fsp->m_u.tcp_ip4_spec.ip4src =
7104 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7105 fsp->h_u.tcp_ip4_spec.ip4dst =
7106 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7107 fsp->m_u.tcp_ip4_spec.ip4dst =
7108 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7109
7110 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7111 TCAM_V4KEY2_TOS_SHIFT;
7112 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7113 TCAM_V4KEY2_TOS_SHIFT;
7114
7115 switch (fsp->flow_type) {
7116 case TCP_V4_FLOW:
7117 case UDP_V4_FLOW:
7118 case SCTP_V4_FLOW:
7119 fsp->h_u.tcp_ip4_spec.psrc =
7120 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7121 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7122 fsp->h_u.tcp_ip4_spec.pdst =
7123 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7124 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7125 fsp->m_u.tcp_ip4_spec.psrc =
7126 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7127 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7128 fsp->m_u.tcp_ip4_spec.pdst =
7129 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7130 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7131
7132 fsp->h_u.tcp_ip4_spec.psrc =
7133 cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7134 fsp->h_u.tcp_ip4_spec.pdst =
7135 cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7136 fsp->m_u.tcp_ip4_spec.psrc =
7137 cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7138 fsp->m_u.tcp_ip4_spec.pdst =
7139 cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7140 break;
7141 case AH_V4_FLOW:
7142 case ESP_V4_FLOW:
7143 fsp->h_u.ah_ip4_spec.spi =
7144 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7145 TCAM_V4KEY2_PORT_SPI_SHIFT;
7146 fsp->m_u.ah_ip4_spec.spi =
7147 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7148 TCAM_V4KEY2_PORT_SPI_SHIFT;
7149
7150 fsp->h_u.ah_ip4_spec.spi =
7151 cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7152 fsp->m_u.ah_ip4_spec.spi =
7153 cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7154 break;
7155 case IP_USER_FLOW:
7156 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7157 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7158 TCAM_V4KEY2_PORT_SPI_SHIFT;
7159 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7160 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7161 TCAM_V4KEY2_PORT_SPI_SHIFT;
7162
7163 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7164 cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7165 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7166 cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7167
7168 fsp->h_u.usr_ip4_spec.proto =
7169 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7170 TCAM_V4KEY2_PROTO_SHIFT;
7171 fsp->m_u.usr_ip4_spec.proto =
7172 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7173 TCAM_V4KEY2_PROTO_SHIFT;
7174
7175 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7176 break;
7177 default:
7178 break;
7179 }
7180}
7181
7182static int niu_get_ethtool_tcam_entry(struct niu *np,
7183 struct ethtool_rxnfc *nfc)
7184{
7185 struct niu_parent *parent = np->parent;
7186 struct niu_tcam_entry *tp;
7187 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7188 u16 idx;
7189 u64 class;
7190 int ret = 0;
7191
7192 idx = tcam_get_index(np, (u16)nfc->fs.location);
7193
7194 tp = &parent->tcam[idx];
7195 if (!tp->valid) {
f10a1f2e
JP		 7196 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7197 parent->index, (u16)nfc->fs.location, idx);
2d96cf8c
SB		 7198 return -EINVAL;
7199 }
7200
7201 /* fill the flow spec entry */
7202 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7203 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7204 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7205
7206 if (ret < 0) {
f10a1f2e
JP		 7207 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7208 parent->index);
2d96cf8c
SB		 7209 ret = -EINVAL;
7210 goto out;
7211 }
7212
7213 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7214 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7215 TCAM_V4KEY2_PROTO_SHIFT;
7216 if (proto == IPPROTO_ESP) {
7217 if (fsp->flow_type == AH_V4_FLOW)
7218 fsp->flow_type = ESP_V4_FLOW;
7219 else
7220 fsp->flow_type = ESP_V6_FLOW;
7221 }
7222 }
7223
7224 switch (fsp->flow_type) {
7225 case TCP_V4_FLOW:
7226 case UDP_V4_FLOW:
7227 case SCTP_V4_FLOW:
7228 case AH_V4_FLOW:
7229 case ESP_V4_FLOW:
7230 niu_get_ip4fs_from_tcam_key(tp, fsp);
7231 break;
7232 case TCP_V6_FLOW:
7233 case UDP_V6_FLOW:
7234 case SCTP_V6_FLOW:
7235 case AH_V6_FLOW:
7236 case ESP_V6_FLOW:
7237 /* Not yet implemented */
7238 ret = -EINVAL;
7239 break;
7240 case IP_USER_FLOW:
7241 niu_get_ip4fs_from_tcam_key(tp, fsp);
7242 break;
7243 default:
7244 ret = -EINVAL;
7245 break;
7246 }
7247
7248 if (ret < 0)
7249 goto out;
7250
7251 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7252 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7253 else
7254 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7255 TCAM_ASSOCDATA_OFFSET_SHIFT;
7256
7257 /* put the tcam size here */
7258 nfc->data = tcam_get_size(np);
7259out:
7260 return ret;
7261}
7262
7263static int niu_get_ethtool_tcam_all(struct niu *np,
7264 struct ethtool_rxnfc *nfc,
7265 u32 *rule_locs)
7266{
7267 struct niu_parent *parent = np->parent;
7268 struct niu_tcam_entry *tp;
7269 int i, idx, cnt;
7270 u16 n_entries;
7271 unsigned long flags;
7272
7273
7274 /* put the tcam size here */
7275 nfc->data = tcam_get_size(np);
7276
7277 niu_lock_parent(np, flags);
7278 n_entries = nfc->rule_cnt;
7279 for (cnt = 0, i = 0; i < nfc->data; i++) {
7280 idx = tcam_get_index(np, i);
7281 tp = &parent->tcam[idx];
7282 if (!tp->valid)
7283 continue;
7284 rule_locs[cnt] = i;
7285 cnt++;
7286 }
7287 niu_unlock_parent(np, flags);
7288
7289 if (n_entries != cnt) {
7290 /* print warning, this should not happen */
f10a1f2e
JP		 7291 netdev_info(np->dev, "niu%d: In %s(): n_entries[%d] != cnt[%d]!!!\n",
7292 np->parent->index, __func__, n_entries, cnt);
2d96cf8c
SB		 7293 }
7294
7295 return 0;
7296}
7297
7298static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7299 void *rule_locs)
b4653e99
SB		 7300{
7301 struct niu *np = netdev_priv(dev);
2d96cf8c
SB		 7302 int ret = 0;
7303
7304 switch (cmd->cmd) {
7305 case ETHTOOL_GRXFH:
7306 ret = niu_get_hash_opts(np, cmd);
7307 break;
7308 case ETHTOOL_GRXRINGS:
7309 cmd->data = np->num_rx_rings;
7310 break;
7311 case ETHTOOL_GRXCLSRLCNT:
7312 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7313 break;
7314 case ETHTOOL_GRXCLSRULE:
7315 ret = niu_get_ethtool_tcam_entry(np, cmd);
7316 break;
7317 case ETHTOOL_GRXCLSRLALL:
7318 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7319 break;
7320 default:
7321 ret = -EINVAL;
7322 break;
7323 }
7324
7325 return ret;
7326}
7327
7328static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7329{
b4653e99
SB		 7330 u64 class;
7331 u64 flow_key = 0;
7332 unsigned long flags;
7333
2d96cf8c 7334 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7335 return -EINVAL;
7336
7337 if (class < CLASS_CODE_USER_PROG1 ||
7338 class > CLASS_CODE_SCTP_IPV6)
7339 return -EINVAL;
7340
2d96cf8c 7341 if (nfc->data & RXH_DISCARD) {
b4653e99
SB		 7342 niu_lock_parent(np, flags);
7343 flow_key = np->parent->tcam_key[class -
7344 CLASS_CODE_USER_PROG1];
7345 flow_key |= TCAM_KEY_DISC;
7346 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7347 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7348 niu_unlock_parent(np, flags);
7349 return 0;
7350 } else {
7351 /* Discard was set before, but is not set now */
7352 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7353 TCAM_KEY_DISC) {
7354 niu_lock_parent(np, flags);
7355 flow_key = np->parent->tcam_key[class -
7356 CLASS_CODE_USER_PROG1];
7357 flow_key &= ~TCAM_KEY_DISC;
7358 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7359 flow_key);
7360 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7361 flow_key;
7362 niu_unlock_parent(np, flags);
7363 }
7364 }
7365
2d96cf8c 7366 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
b4653e99
SB		 7367 return -EINVAL;
7368
7369 niu_lock_parent(np, flags);
7370 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7371 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7372 niu_unlock_parent(np, flags);
7373
7374 return 0;
7375}
7376
2d96cf8c
SB		 7377static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7378 struct niu_tcam_entry *tp,
7379 int l2_rdc_tab, u64 class)
7380{
7381 u8 pid = 0;
7382 u32 sip, dip, sipm, dipm, spi, spim;
7383 u16 sport, dport, spm, dpm;
7384
7385 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7386 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7387 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7388 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7389
7390 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7391 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7392 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7393 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7394
7395 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7396 tp->key[3] |= dip;
7397
7398 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7399 tp->key_mask[3] |= dipm;
7400
7401 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7402 TCAM_V4KEY2_TOS_SHIFT);
7403 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7404 TCAM_V4KEY2_TOS_SHIFT);
7405 switch (fsp->flow_type) {
7406 case TCP_V4_FLOW:
7407 case UDP_V4_FLOW:
7408 case SCTP_V4_FLOW:
7409 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7410 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7411 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7412 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7413
7414 tp->key[2] |= (((u64)sport << 16) | dport);
7415 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7416 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7417 break;
7418 case AH_V4_FLOW:
7419 case ESP_V4_FLOW:
7420 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7421 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7422
7423 tp->key[2] |= spi;
7424 tp->key_mask[2] |= spim;
7425 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7426 break;
7427 case IP_USER_FLOW:
7428 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7429 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7430
7431 tp->key[2] |= spi;
7432 tp->key_mask[2] |= spim;
7433 pid = fsp->h_u.usr_ip4_spec.proto;
7434 break;
7435 default:
7436 break;
7437 }
7438
7439 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7440 if (pid) {
7441 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7442 }
7443}
7444
7445static int niu_add_ethtool_tcam_entry(struct niu *np,
7446 struct ethtool_rxnfc *nfc)
7447{
7448 struct niu_parent *parent = np->parent;
7449 struct niu_tcam_entry *tp;
7450 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7451 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7452 int l2_rdc_table = rdc_table->first_table_num;
7453 u16 idx;
7454 u64 class;
7455 unsigned long flags;
7456 int err, ret;
7457
7458 ret = 0;
7459
7460 idx = nfc->fs.location;
7461 if (idx >= tcam_get_size(np))
7462 return -EINVAL;
7463
7464 if (fsp->flow_type == IP_USER_FLOW) {
7465 int i;
7466 int add_usr_cls = 0;
7467 int ipv6 = 0;
7468 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7469 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7470
7471 niu_lock_parent(np, flags);
7472
7473 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7474 if (parent->l3_cls[i]) {
7475 if (uspec->proto == parent->l3_cls_pid[i]) {
7476 class = parent->l3_cls[i];
7477 parent->l3_cls_refcnt[i]++;
7478 add_usr_cls = 1;
7479 break;
7480 }
7481 } else {
7482 /* Program new user IP class */
7483 switch (i) {
7484 case 0:
7485 class = CLASS_CODE_USER_PROG1;
7486 break;
7487 case 1:
7488 class = CLASS_CODE_USER_PROG2;
7489 break;
7490 case 2:
7491 class = CLASS_CODE_USER_PROG3;
7492 break;
7493 case 3:
7494 class = CLASS_CODE_USER_PROG4;
7495 break;
7496 default:
7497 break;
7498 }
7499 if (uspec->ip_ver == ETH_RX_NFC_IP6)
7500 ipv6 = 1;
7501 ret = tcam_user_ip_class_set(np, class, ipv6,
7502 uspec->proto,
7503 uspec->tos,
7504 umask->tos);
7505 if (ret)
7506 goto out;
7507
7508 ret = tcam_user_ip_class_enable(np, class, 1);
7509 if (ret)
7510 goto out;
7511 parent->l3_cls[i] = class;
7512 parent->l3_cls_pid[i] = uspec->proto;
7513 parent->l3_cls_refcnt[i]++;
7514 add_usr_cls = 1;
7515 break;
7516 }
7517 }
7518 if (!add_usr_cls) {
f10a1f2e
JP		 7519 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7520 parent->index, __func__, uspec->proto);
2d96cf8c
SB		 7521 ret = -EINVAL;
7522 goto out;
7523 }
7524 niu_unlock_parent(np, flags);
7525 } else {
7526 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7527 return -EINVAL;
7528 }
7529 }
7530
7531 niu_lock_parent(np, flags);
7532
7533 idx = tcam_get_index(np, idx);
7534 tp = &parent->tcam[idx];
7535
7536 memset(tp, 0, sizeof(*tp));
7537
7538 /* fill in the tcam key and mask */
7539 switch (fsp->flow_type) {
7540 case TCP_V4_FLOW:
7541 case UDP_V4_FLOW:
7542 case SCTP_V4_FLOW:
7543 case AH_V4_FLOW:
7544 case ESP_V4_FLOW:
7545 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7546 break;
7547 case TCP_V6_FLOW:
7548 case UDP_V6_FLOW:
7549 case SCTP_V6_FLOW:
7550 case AH_V6_FLOW:
7551 case ESP_V6_FLOW:
7552 /* Not yet implemented */
f10a1f2e
JP		 7553 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7554 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7555 ret = -EINVAL;
7556 goto out;
7557 case IP_USER_FLOW:
7558 if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
7559 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
7560 class);
7561 } else {
7562 /* Not yet implemented */
f10a1f2e
JP		 7563 netdev_info(np->dev, "niu%d: In %s(): usr flow for IPv6 not implemented\n",
7564 parent->index, __func__);
2d96cf8c
SB		 7565 ret = -EINVAL;
7566 goto out;
7567 }
7568 break;
7569 default:
f10a1f2e
JP		 7570 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7571 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7572 ret = -EINVAL;
7573 goto out;
7574 }
7575
7576 /* fill in the assoc data */
7577 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7578 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7579 } else {
7580 if (fsp->ring_cookie >= np->num_rx_rings) {
f10a1f2e
JP		 7581 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7582 parent->index, __func__,
7583 (long long)fsp->ring_cookie);
2d96cf8c
SB		 7584 ret = -EINVAL;
7585 goto out;
7586 }
7587 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7588 (fsp->ring_cookie <<
7589 TCAM_ASSOCDATA_OFFSET_SHIFT));
7590 }
7591
7592 err = tcam_write(np, idx, tp->key, tp->key_mask);
7593 if (err) {
7594 ret = -EINVAL;
7595 goto out;
7596 }
7597 err = tcam_assoc_write(np, idx, tp->assoc_data);
7598 if (err) {
7599 ret = -EINVAL;
7600 goto out;
7601 }
7602
7603 /* validate the entry */
7604 tp->valid = 1;
7605 np->clas.tcam_valid_entries++;
7606out:
7607 niu_unlock_parent(np, flags);
7608
7609 return ret;
7610}
7611
7612static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7613{
7614 struct niu_parent *parent = np->parent;
7615 struct niu_tcam_entry *tp;
7616 u16 idx;
7617 unsigned long flags;
7618 u64 class;
7619 int ret = 0;
7620
7621 if (loc >= tcam_get_size(np))
7622 return -EINVAL;
7623
7624 niu_lock_parent(np, flags);
7625
7626 idx = tcam_get_index(np, loc);
7627 tp = &parent->tcam[idx];
7628
7629 /* if the entry is of a user defined class, then update*/
7630 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7631 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7632
7633 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7634 int i;
7635 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7636 if (parent->l3_cls[i] == class) {
7637 parent->l3_cls_refcnt[i]--;
7638 if (!parent->l3_cls_refcnt[i]) {
7639 /* disable class */
7640 ret = tcam_user_ip_class_enable(np,
7641 class,
7642 0);
7643 if (ret)
7644 goto out;
7645 parent->l3_cls[i] = 0;
7646 parent->l3_cls_pid[i] = 0;
7647 }
7648 break;
7649 }
7650 }
7651 if (i == NIU_L3_PROG_CLS) {
f10a1f2e
JP		 7652 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7653 parent->index, __func__,
7654 (unsigned long long)class);
2d96cf8c
SB		 7655 ret = -EINVAL;
7656 goto out;
7657 }
7658 }
7659
7660 ret = tcam_flush(np, idx);
7661 if (ret)
7662 goto out;
7663
7664 /* invalidate the entry */
7665 tp->valid = 0;
7666 np->clas.tcam_valid_entries--;
7667out:
7668 niu_unlock_parent(np, flags);
7669
7670 return ret;
7671}
7672
7673static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7674{
7675 struct niu *np = netdev_priv(dev);
7676 int ret = 0;
7677
7678 switch (cmd->cmd) {
7679 case ETHTOOL_SRXFH:
7680 ret = niu_set_hash_opts(np, cmd);
7681 break;
7682 case ETHTOOL_SRXCLSRLINS:
7683 ret = niu_add_ethtool_tcam_entry(np, cmd);
7684 break;
7685 case ETHTOOL_SRXCLSRLDEL:
7686 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7687 break;
7688 default:
7689 ret = -EINVAL;
7690 break;
7691 }
7692
7693 return ret;
7694}
7695
a3138df9
DM		 7696static const struct {
7697 const char string[ETH_GSTRING_LEN];
7698} niu_xmac_stat_keys[] = {
7699 { "tx_frames" },
7700 { "tx_bytes" },
7701 { "tx_fifo_errors" },
7702 { "tx_overflow_errors" },
7703 { "tx_max_pkt_size_errors" },
7704 { "tx_underflow_errors" },
7705 { "rx_local_faults" },
7706 { "rx_remote_faults" },
7707 { "rx_link_faults" },
7708 { "rx_align_errors" },
7709 { "rx_frags" },
7710 { "rx_mcasts" },
7711 { "rx_bcasts" },
7712 { "rx_hist_cnt1" },
7713 { "rx_hist_cnt2" },
7714 { "rx_hist_cnt3" },
7715 { "rx_hist_cnt4" },
7716 { "rx_hist_cnt5" },
7717 { "rx_hist_cnt6" },
7718 { "rx_hist_cnt7" },
7719 { "rx_octets" },
7720 { "rx_code_violations" },
7721 { "rx_len_errors" },
7722 { "rx_crc_errors" },
7723 { "rx_underflows" },
7724 { "rx_overflows" },
7725 { "pause_off_state" },
7726 { "pause_on_state" },
7727 { "pause_received" },
7728};
7729
7730#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7731
7732static const struct {
7733 const char string[ETH_GSTRING_LEN];
7734} niu_bmac_stat_keys[] = {
7735 { "tx_underflow_errors" },
7736 { "tx_max_pkt_size_errors" },
7737 { "tx_bytes" },
7738 { "tx_frames" },
7739 { "rx_overflows" },
7740 { "rx_frames" },
7741 { "rx_align_errors" },
7742 { "rx_crc_errors" },
7743 { "rx_len_errors" },
7744 { "pause_off_state" },
7745 { "pause_on_state" },
7746 { "pause_received" },
7747};
7748
7749#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7750
7751static const struct {
7752 const char string[ETH_GSTRING_LEN];
7753} niu_rxchan_stat_keys[] = {
7754 { "rx_channel" },
7755 { "rx_packets" },
7756 { "rx_bytes" },
7757 { "rx_dropped" },
7758 { "rx_errors" },
7759};
7760
7761#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7762
7763static const struct {
7764 const char string[ETH_GSTRING_LEN];
7765} niu_txchan_stat_keys[] = {
7766 { "tx_channel" },
7767 { "tx_packets" },
7768 { "tx_bytes" },
7769 { "tx_errors" },
7770};
7771
7772#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7773
7774static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7775{
7776 struct niu *np = netdev_priv(dev);
7777 int i;
7778
7779 if (stringset != ETH_SS_STATS)
7780 return;
7781
7782 if (np->flags & NIU_FLAGS_XMAC) {
7783 memcpy(data, niu_xmac_stat_keys,
7784 sizeof(niu_xmac_stat_keys));
7785 data += sizeof(niu_xmac_stat_keys);
7786 } else {
7787 memcpy(data, niu_bmac_stat_keys,
7788 sizeof(niu_bmac_stat_keys));
7789 data += sizeof(niu_bmac_stat_keys);
7790 }
7791 for (i = 0; i < np->num_rx_rings; i++) {
7792 memcpy(data, niu_rxchan_stat_keys,
7793 sizeof(niu_rxchan_stat_keys));
7794 data += sizeof(niu_rxchan_stat_keys);
7795 }
7796 for (i = 0; i < np->num_tx_rings; i++) {
7797 memcpy(data, niu_txchan_stat_keys,
7798 sizeof(niu_txchan_stat_keys));
7799 data += sizeof(niu_txchan_stat_keys);
7800 }
7801}
7802
15f0a394 7803static int niu_get_sset_count(struct net_device *dev, int stringset)
a3138df9
DM		 7804{
7805 struct niu *np = netdev_priv(dev);
7806
15f0a394
BH		 7807 if (stringset != ETH_SS_STATS)
7808 return -EINVAL;
7809
a3138df9
DM		 7810 return ((np->flags & NIU_FLAGS_XMAC ?
7811 NUM_XMAC_STAT_KEYS :
7812 NUM_BMAC_STAT_KEYS) +
7813 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7814 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7815}
7816
7817static void niu_get_ethtool_stats(struct net_device *dev,
7818 struct ethtool_stats *stats, u64 *data)
7819{
7820 struct niu *np = netdev_priv(dev);
7821 int i;
7822
7823 niu_sync_mac_stats(np);
7824 if (np->flags & NIU_FLAGS_XMAC) {
7825 memcpy(data, &np->mac_stats.xmac,
7826 sizeof(struct niu_xmac_stats));
7827 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7828 } else {
7829 memcpy(data, &np->mac_stats.bmac,
7830 sizeof(struct niu_bmac_stats));
7831 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7832 }
7833 for (i = 0; i < np->num_rx_rings; i++) {
7834 struct rx_ring_info *rp = &np->rx_rings[i];
7835
b8a606b8
JDB		 7836 niu_sync_rx_discard_stats(np, rp, 0);
7837
a3138df9
DM		 7838 data[0] = rp->rx_channel;
7839 data[1] = rp->rx_packets;
7840 data[2] = rp->rx_bytes;
7841 data[3] = rp->rx_dropped;
7842 data[4] = rp->rx_errors;
7843 data += 5;
7844 }
7845 for (i = 0; i < np->num_tx_rings; i++) {
7846 struct tx_ring_info *rp = &np->tx_rings[i];
7847
7848 data[0] = rp->tx_channel;
7849 data[1] = rp->tx_packets;
7850 data[2] = rp->tx_bytes;
7851 data[3] = rp->tx_errors;
7852 data += 4;
7853 }
7854}
7855
7856static u64 niu_led_state_save(struct niu *np)
7857{
7858 if (np->flags & NIU_FLAGS_XMAC)
7859 return nr64_mac(XMAC_CONFIG);
7860 else
7861 return nr64_mac(BMAC_XIF_CONFIG);
7862}
7863
7864static void niu_led_state_restore(struct niu *np, u64 val)
7865{
7866 if (np->flags & NIU_FLAGS_XMAC)
7867 nw64_mac(XMAC_CONFIG, val);
7868 else
7869 nw64_mac(BMAC_XIF_CONFIG, val);
7870}
7871
7872static void niu_force_led(struct niu *np, int on)
7873{
7874 u64 val, reg, bit;
7875
7876 if (np->flags & NIU_FLAGS_XMAC) {
7877 reg = XMAC_CONFIG;
7878 bit = XMAC_CONFIG_FORCE_LED_ON;
7879 } else {
7880 reg = BMAC_XIF_CONFIG;
7881 bit = BMAC_XIF_CONFIG_LINK_LED;
7882 }
7883
7884 val = nr64_mac(reg);
7885 if (on)
7886 val |= bit;
7887 else
7888 val &= ~bit;
7889 nw64_mac(reg, val);
7890}
7891
7892static int niu_phys_id(struct net_device *dev, u32 data)
7893{
7894 struct niu *np = netdev_priv(dev);
7895 u64 orig_led_state;
7896 int i;
7897
7898 if (!netif_running(dev))
7899 return -EAGAIN;
7900
7901 if (data == 0)
7902 data = 2;
7903
7904 orig_led_state = niu_led_state_save(np);
7905 for (i = 0; i < (data * 2); i++) {
7906 int on = ((i % 2) == 0);
7907
7908 niu_force_led(np, on);
7909
7910 if (msleep_interruptible(500))
7911 break;
7912 }
7913 niu_led_state_restore(np, orig_led_state);
7914
7915 return 0;
7916}
7917
3cfa856d
DM		 7918static int niu_set_flags(struct net_device *dev, u32 data)
7919{
7920 if (data & (ETH_FLAG_LRO | ETH_FLAG_NTUPLE))
7921 return -EOPNOTSUPP;
7922
7923 if (data & ETH_FLAG_RXHASH)
7924 dev->features |= NETIF_F_RXHASH;
7925 else
7926 dev->features &= ~NETIF_F_RXHASH;
7927 return 0;
7928}
7929
a3138df9
DM		 7930static const struct ethtool_ops niu_ethtool_ops = {
7931 .get_drvinfo = niu_get_drvinfo,
7932 .get_link = ethtool_op_get_link,
7933 .get_msglevel = niu_get_msglevel,
7934 .set_msglevel = niu_set_msglevel,
38bb045d 7935 .nway_reset = niu_nway_reset,
a3138df9
DM		 7936 .get_eeprom_len = niu_get_eeprom_len,
7937 .get_eeprom = niu_get_eeprom,
7938 .get_settings = niu_get_settings,
7939 .set_settings = niu_set_settings,
7940 .get_strings = niu_get_strings,
15f0a394 7941 .get_sset_count = niu_get_sset_count,
a3138df9
DM		 7942 .get_ethtool_stats = niu_get_ethtool_stats,
7943 .phys_id = niu_phys_id,
2d96cf8c
SB		 7944 .get_rxnfc = niu_get_nfc,
7945 .set_rxnfc = niu_set_nfc,
3cfa856d
DM		 7946 .set_flags = niu_set_flags,
7947 .get_flags = ethtool_op_get_flags,
a3138df9
DM		 7948};
7949
7950static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7951 int ldg, int ldn)
7952{
7953 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7954 return -EINVAL;
7955 if (ldn < 0 || ldn > LDN_MAX)
7956 return -EINVAL;
7957
7958 parent->ldg_map[ldn] = ldg;
7959
7960 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7961 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7962 * the firmware, and we're not supposed to change them.
7963 * Validate the mapping, because if it's wrong we probably
7964 * won't get any interrupts and that's painful to debug.
7965 */
7966 if (nr64(LDG_NUM(ldn)) != ldg) {
f10a1f2e 7967 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
a3138df9
DM		 7968 np->port, ldn, ldg,
7969 (unsigned long long) nr64(LDG_NUM(ldn)));
7970 return -EINVAL;
7971 }
7972 } else
7973 nw64(LDG_NUM(ldn), ldg);
7974
7975 return 0;
7976}
7977
7978static int niu_set_ldg_timer_res(struct niu *np, int res)
7979{
7980 if (res < 0 || res > LDG_TIMER_RES_VAL)
7981 return -EINVAL;
7982
7983
7984 nw64(LDG_TIMER_RES, res);
7985
7986 return 0;
7987}
7988
7989static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7990{
7991 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7992 (func < 0 || func > 3) ||
7993 (vector < 0 || vector > 0x1f))
7994 return -EINVAL;
7995
7996 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7997
7998 return 0;
7999}
8000
8001static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
8002{
8003 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
8004 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
8005 int limit;
8006
8007 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
8008 return -EINVAL;
8009
8010 frame = frame_base;
8011 nw64(ESPC_PIO_STAT, frame);
8012 limit = 64;
8013 do {
8014 udelay(5);
8015 frame = nr64(ESPC_PIO_STAT);
8016 if (frame & ESPC_PIO_STAT_READ_END)
8017 break;
8018 } while (limit--);
8019 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8020 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8021 (unsigned long long) frame);
8022 return -ENODEV;
8023 }
8024
8025 frame = frame_base;
8026 nw64(ESPC_PIO_STAT, frame);
8027 limit = 64;
8028 do {
8029 udelay(5);
8030 frame = nr64(ESPC_PIO_STAT);
8031 if (frame & ESPC_PIO_STAT_READ_END)
8032 break;
8033 } while (limit--);
8034 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8035 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8036 (unsigned long long) frame);
8037 return -ENODEV;
8038 }
8039
8040 frame = nr64(ESPC_PIO_STAT);
8041 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8042}
8043
8044static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8045{
8046 int err = niu_pci_eeprom_read(np, off);
8047 u16 val;
8048
8049 if (err < 0)
8050 return err;
8051 val = (err << 8);
8052 err = niu_pci_eeprom_read(np, off + 1);
8053 if (err < 0)
8054 return err;
8055 val |= (err & 0xff);
8056
8057 return val;
8058}
8059
8060static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8061{
8062 int err = niu_pci_eeprom_read(np, off);
8063 u16 val;
8064
8065 if (err < 0)
8066 return err;
8067
8068 val = (err & 0xff);
8069 err = niu_pci_eeprom_read(np, off + 1);
8070 if (err < 0)
8071 return err;
8072
8073 val |= (err & 0xff) << 8;
8074
8075 return val;
8076}
8077
8078static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8079 u32 off,
8080 char *namebuf,
8081 int namebuf_len)
8082{
8083 int i;
8084
8085 for (i = 0; i < namebuf_len; i++) {
8086 int err = niu_pci_eeprom_read(np, off + i);
8087 if (err < 0)
8088 return err;
8089 *namebuf++ = err;
8090 if (!err)
8091 break;
8092 }
8093 if (i >= namebuf_len)
8094 return -EINVAL;
8095
8096 return i + 1;
8097}
8098
8099static void __devinit niu_vpd_parse_version(struct niu *np)
8100{
8101 struct niu_vpd *vpd = &np->vpd;
8102 int len = strlen(vpd->version) + 1;
8103 const char *s = vpd->version;
8104 int i;
8105
8106 for (i = 0; i < len - 5; i++) {
9ea2bdab 8107 if (!strncmp(s + i, "FCode ", 6))
a3138df9
DM		 8108 break;
8109 }
8110 if (i >= len - 5)
8111 return;
8112
8113 s += i + 5;
8114 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8115
f10a1f2e
JP		 8116 netif_printk(np, probe, KERN_DEBUG, np->dev,
8117 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8118 vpd->fcode_major, vpd->fcode_minor);
a3138df9
DM		 8119 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8120 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8121 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8122 np->flags |= NIU_FLAGS_VPD_VALID;
8123}
8124
8125/* ESPC_PIO_EN_ENABLE must be set */
8126static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8127 u32 start, u32 end)
8128{
8129 unsigned int found_mask = 0;
8130#define FOUND_MASK_MODEL 0x00000001
8131#define FOUND_MASK_BMODEL 0x00000002
8132#define FOUND_MASK_VERS 0x00000004
8133#define FOUND_MASK_MAC 0x00000008
8134#define FOUND_MASK_NMAC 0x00000010
8135#define FOUND_MASK_PHY 0x00000020
8136#define FOUND_MASK_ALL 0x0000003f
8137
f10a1f2e
JP		 8138 netif_printk(np, probe, KERN_DEBUG, np->dev,
8139 "VPD_SCAN: start[%x] end[%x]\n", start, end);
a3138df9
DM		 8140 while (start < end) {
8141 int len, err, instance, type, prop_len;
8142 char namebuf[64];
8143 u8 *prop_buf;
8144 int max_len;
8145
8146 if (found_mask == FOUND_MASK_ALL) {
8147 niu_vpd_parse_version(np);
8148 return 1;
8149 }
8150
8151 err = niu_pci_eeprom_read(np, start + 2);
8152 if (err < 0)
8153 return err;
8154 len = err;
8155 start += 3;
8156
8157 instance = niu_pci_eeprom_read(np, start);
8158 type = niu_pci_eeprom_read(np, start + 3);
8159 prop_len = niu_pci_eeprom_read(np, start + 4);
8160 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8161 if (err < 0)
8162 return err;
8163
8164 prop_buf = NULL;
8165 max_len = 0;
8166 if (!strcmp(namebuf, "model")) {
8167 prop_buf = np->vpd.model;
8168 max_len = NIU_VPD_MODEL_MAX;
8169 found_mask |= FOUND_MASK_MODEL;
8170 } else if (!strcmp(namebuf, "board-model")) {
8171 prop_buf = np->vpd.board_model;
8172 max_len = NIU_VPD_BD_MODEL_MAX;
8173 found_mask |= FOUND_MASK_BMODEL;
8174 } else if (!strcmp(namebuf, "version")) {
8175 prop_buf = np->vpd.version;
8176 max_len = NIU_VPD_VERSION_MAX;
8177 found_mask |= FOUND_MASK_VERS;
8178 } else if (!strcmp(namebuf, "local-mac-address")) {
8179 prop_buf = np->vpd.local_mac;
8180 max_len = ETH_ALEN;
8181 found_mask |= FOUND_MASK_MAC;
8182 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8183 prop_buf = &np->vpd.mac_num;
8184 max_len = 1;
8185 found_mask |= FOUND_MASK_NMAC;
8186 } else if (!strcmp(namebuf, "phy-type")) {
8187 prop_buf = np->vpd.phy_type;
8188 max_len = NIU_VPD_PHY_TYPE_MAX;
8189 found_mask |= FOUND_MASK_PHY;
8190 }
8191
8192 if (max_len && prop_len > max_len) {
f10a1f2e 8193 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
a3138df9
DM		 8194 return -EINVAL;
8195 }
8196
8197 if (prop_buf) {
8198 u32 off = start + 5 + err;
8199 int i;
8200
f10a1f2e
JP		 8201 netif_printk(np, probe, KERN_DEBUG, np->dev,
8202 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8203 namebuf, prop_len);
a3138df9
DM		 8204 for (i = 0; i < prop_len; i++)
8205 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8206 }
8207
8208 start += len;
8209 }
8210
8211 return 0;
8212}
8213
8214/* ESPC_PIO_EN_ENABLE must be set */
8215static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8216{
8217 u32 offset;
8218 int err;
8219
8220 err = niu_pci_eeprom_read16_swp(np, start + 1);
8221 if (err < 0)
8222 return;
8223
8224 offset = err + 3;
8225
8226 while (start + offset < ESPC_EEPROM_SIZE) {
8227 u32 here = start + offset;
8228 u32 end;
8229
8230 err = niu_pci_eeprom_read(np, here);
8231 if (err != 0x90)
8232 return;
8233
8234 err = niu_pci_eeprom_read16_swp(np, here + 1);
8235 if (err < 0)
8236 return;
8237
8238 here = start + offset + 3;
8239 end = start + offset + err;
8240
8241 offset += err;
8242
8243 err = niu_pci_vpd_scan_props(np, here, end);
8244 if (err < 0 || err == 1)
8245 return;
8246 }
8247}
8248
8249/* ESPC_PIO_EN_ENABLE must be set */
8250static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8251{
8252 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8253 int err;
8254
8255 while (start < end) {
8256 ret = start;
8257
8258 /* ROM header signature? */
8259 err = niu_pci_eeprom_read16(np, start + 0);
8260 if (err != 0x55aa)
8261 return 0;
8262
8263 /* Apply offset to PCI data structure. */
8264 err = niu_pci_eeprom_read16(np, start + 23);
8265 if (err < 0)
8266 return 0;
8267 start += err;
8268
8269 /* Check for "PCIR" signature. */
8270 err = niu_pci_eeprom_read16(np, start + 0);
8271 if (err != 0x5043)
8272 return 0;
8273 err = niu_pci_eeprom_read16(np, start + 2);
8274 if (err != 0x4952)
8275 return 0;
8276
8277 /* Check for OBP image type. */
8278 err = niu_pci_eeprom_read(np, start + 20);
8279 if (err < 0)
8280 return 0;
8281 if (err != 0x01) {
8282 err = niu_pci_eeprom_read(np, ret + 2);
8283 if (err < 0)
8284 return 0;
8285
8286 start = ret + (err * 512);
8287 continue;
8288 }
8289
8290 err = niu_pci_eeprom_read16_swp(np, start + 8);
8291 if (err < 0)
8292 return err;
8293 ret += err;
8294
8295 err = niu_pci_eeprom_read(np, ret + 0);
8296 if (err != 0x82)
8297 return 0;
8298
8299 return ret;
8300 }
8301
8302 return 0;
8303}
8304
8305static int __devinit niu_phy_type_prop_decode(struct niu *np,
8306 const char *phy_prop)
8307{
8308 if (!strcmp(phy_prop, "mif")) {
8309 /* 1G copper, MII */
8310 np->flags &= ~(NIU_FLAGS_FIBER |
8311 NIU_FLAGS_10G);
8312 np->mac_xcvr = MAC_XCVR_MII;
8313 } else if (!strcmp(phy_prop, "xgf")) {
8314 /* 10G fiber, XPCS */
8315 np->flags |= (NIU_FLAGS_10G |
8316 NIU_FLAGS_FIBER);
8317 np->mac_xcvr = MAC_XCVR_XPCS;
8318 } else if (!strcmp(phy_prop, "pcs")) {
8319 /* 1G fiber, PCS */
8320 np->flags &= ~NIU_FLAGS_10G;
8321 np->flags |= NIU_FLAGS_FIBER;
8322 np->mac_xcvr = MAC_XCVR_PCS;
8323 } else if (!strcmp(phy_prop, "xgc")) {
8324 /* 10G copper, XPCS */
8325 np->flags |= NIU_FLAGS_10G;
8326 np->flags &= ~NIU_FLAGS_FIBER;
8327 np->mac_xcvr = MAC_XCVR_XPCS;
e3e081e1
SB		 8328 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8329 /* 10G Serdes or 1G Serdes, default to 10G */
8330 np->flags |= NIU_FLAGS_10G;
8331 np->flags &= ~NIU_FLAGS_FIBER;
8332 np->flags |= NIU_FLAGS_XCVR_SERDES;
8333 np->mac_xcvr = MAC_XCVR_XPCS;
a3138df9
DM		 8334 } else {
8335 return -EINVAL;
8336 }
8337 return 0;
8338}
8339
7f7c4072
MW		 8340static int niu_pci_vpd_get_nports(struct niu *np)
8341{
8342 int ports = 0;
8343
f9af8574
MW		 8344 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8345 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8346 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8347 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8348 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7f7c4072 8349 ports = 4;
f9af8574
MW		 8350 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8351 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8352 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8353 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7f7c4072
MW		 8354 ports = 2;
8355 }
8356
8357 return ports;
8358}
8359
a3138df9
DM		 8360static void __devinit niu_pci_vpd_validate(struct niu *np)
8361{
8362 struct net_device *dev = np->dev;
8363 struct niu_vpd *vpd = &np->vpd;
8364 u8 val8;
8365
8366 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
f10a1f2e 8367 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
a3138df9
DM		 8368
8369 np->flags &= ~NIU_FLAGS_VPD_VALID;
8370 return;
8371 }
8372
f9af8574
MW		 8373 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8374 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8375 np->flags |= NIU_FLAGS_10G;
8376 np->flags &= ~NIU_FLAGS_FIBER;
8377 np->flags |= NIU_FLAGS_XCVR_SERDES;
8378 np->mac_xcvr = MAC_XCVR_PCS;
8379 if (np->port > 1) {
8380 np->flags |= NIU_FLAGS_FIBER;
8381 np->flags &= ~NIU_FLAGS_10G;
8382 }
8383 if (np->flags & NIU_FLAGS_10G)
f10a1f2e 8384 np->mac_xcvr = MAC_XCVR_XPCS;
f9af8574 8385 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8386 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8387 NIU_FLAGS_HOTPLUG_PHY);
5fbd7e24 8388 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e 8389 dev_err(np->device, "Illegal phy string [%s]\n",
a3138df9 8390 np->vpd.phy_type);
f10a1f2e 8391 dev_err(np->device, "Falling back to SPROM\n");
a3138df9
DM		 8392 np->flags &= ~NIU_FLAGS_VPD_VALID;
8393 return;
8394 }
8395
8396 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8397
8398 val8 = dev->perm_addr[5];
8399 dev->perm_addr[5] += np->port;
8400 if (dev->perm_addr[5] < val8)
8401 dev->perm_addr[4]++;
8402
8403 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8404}
8405
8406static int __devinit niu_pci_probe_sprom(struct niu *np)
8407{
8408 struct net_device *dev = np->dev;
8409 int len, i;
8410 u64 val, sum;
8411 u8 val8;
8412
8413 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8414 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8415 len = val / 4;
8416
8417 np->eeprom_len = len;
8418
f10a1f2e
JP		 8419 netif_printk(np, probe, KERN_DEBUG, np->dev,
8420 "SPROM: Image size %llu\n", (unsigned long long)val);
a3138df9
DM		 8421
8422 sum = 0;
8423 for (i = 0; i < len; i++) {
8424 val = nr64(ESPC_NCR(i));
8425 sum += (val >> 0) & 0xff;
8426 sum += (val >> 8) & 0xff;
8427 sum += (val >> 16) & 0xff;
8428 sum += (val >> 24) & 0xff;
8429 }
f10a1f2e
JP		 8430 netif_printk(np, probe, KERN_DEBUG, np->dev,
8431 "SPROM: Checksum %x\n", (int)(sum & 0xff));
a3138df9 8432 if ((sum & 0xff) != 0xab) {
f10a1f2e 8433 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
a3138df9
DM		 8434 return -EINVAL;
8435 }
8436
8437 val = nr64(ESPC_PHY_TYPE);
8438 switch (np->port) {
8439 case 0:
a9d41192 8440 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
a3138df9
DM		 8441 ESPC_PHY_TYPE_PORT0_SHIFT;
8442 break;
8443 case 1:
a9d41192 8444 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
a3138df9
DM		 8445 ESPC_PHY_TYPE_PORT1_SHIFT;
8446 break;
8447 case 2:
a9d41192 8448 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
a3138df9
DM		 8449 ESPC_PHY_TYPE_PORT2_SHIFT;
8450 break;
8451 case 3:
a9d41192 8452 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
a3138df9
DM		 8453 ESPC_PHY_TYPE_PORT3_SHIFT;
8454 break;
8455 default:
f10a1f2e 8456 dev_err(np->device, "Bogus port number %u\n",
a3138df9
DM		 8457 np->port);
8458 return -EINVAL;
8459 }
f10a1f2e
JP		 8460 netif_printk(np, probe, KERN_DEBUG, np->dev,
8461 "SPROM: PHY type %x\n", val8);
a3138df9 8462
a9d41192 8463 switch (val8) {
a3138df9
DM		 8464 case ESPC_PHY_TYPE_1G_COPPER:
8465 /* 1G copper, MII */
8466 np->flags &= ~(NIU_FLAGS_FIBER |
8467 NIU_FLAGS_10G);
8468 np->mac_xcvr = MAC_XCVR_MII;
8469 break;
8470
8471 case ESPC_PHY_TYPE_1G_FIBER:
8472 /* 1G fiber, PCS */
8473 np->flags &= ~NIU_FLAGS_10G;
8474 np->flags |= NIU_FLAGS_FIBER;
8475 np->mac_xcvr = MAC_XCVR_PCS;
8476 break;
8477
8478 case ESPC_PHY_TYPE_10G_COPPER:
8479 /* 10G copper, XPCS */
8480 np->flags |= NIU_FLAGS_10G;
8481 np->flags &= ~NIU_FLAGS_FIBER;
8482 np->mac_xcvr = MAC_XCVR_XPCS;
8483 break;
8484
8485 case ESPC_PHY_TYPE_10G_FIBER:
8486 /* 10G fiber, XPCS */
8487 np->flags |= (NIU_FLAGS_10G |
8488 NIU_FLAGS_FIBER);
8489 np->mac_xcvr = MAC_XCVR_XPCS;
8490 break;
8491
8492 default:
f10a1f2e 8493 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
a3138df9
DM		 8494 return -EINVAL;
8495 }
8496
8497 val = nr64(ESPC_MAC_ADDR0);
f10a1f2e
JP		 8498 netif_printk(np, probe, KERN_DEBUG, np->dev,
8499 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8500 dev->perm_addr[0] = (val >> 0) & 0xff;
8501 dev->perm_addr[1] = (val >> 8) & 0xff;
8502 dev->perm_addr[2] = (val >> 16) & 0xff;
8503 dev->perm_addr[3] = (val >> 24) & 0xff;
8504
8505 val = nr64(ESPC_MAC_ADDR1);
f10a1f2e
JP		 8506 netif_printk(np, probe, KERN_DEBUG, np->dev,
8507 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8508 dev->perm_addr[4] = (val >> 0) & 0xff;
8509 dev->perm_addr[5] = (val >> 8) & 0xff;
8510
8511 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 8512 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8513 dev->perm_addr);
a3138df9
DM		 8514 return -EINVAL;
8515 }
8516
8517 val8 = dev->perm_addr[5];
8518 dev->perm_addr[5] += np->port;
8519 if (dev->perm_addr[5] < val8)
8520 dev->perm_addr[4]++;
8521
8522 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8523
8524 val = nr64(ESPC_MOD_STR_LEN);
f10a1f2e
JP		 8525 netif_printk(np, probe, KERN_DEBUG, np->dev,
8526 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8527 if (val >= 8 * 4)
a3138df9
DM		 8528 return -EINVAL;
8529
8530 for (i = 0; i < val; i += 4) {
8531 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8532
8533 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8534 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8535 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8536 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8537 }
8538 np->vpd.model[val] = '\0';
8539
8540 val = nr64(ESPC_BD_MOD_STR_LEN);
f10a1f2e
JP		 8541 netif_printk(np, probe, KERN_DEBUG, np->dev,
8542 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8543 if (val >= 4 * 4)
a3138df9
DM		 8544 return -EINVAL;
8545
8546 for (i = 0; i < val; i += 4) {
8547 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8548
8549 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8550 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8551 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8552 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8553 }
8554 np->vpd.board_model[val] = '\0';
8555
8556 np->vpd.mac_num =
8557 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
f10a1f2e
JP		 8558 netif_printk(np, probe, KERN_DEBUG, np->dev,
8559 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
a3138df9
DM		 8560
8561 return 0;
8562}
8563
8564static int __devinit niu_get_and_validate_port(struct niu *np)
8565{
8566 struct niu_parent *parent = np->parent;
8567
8568 if (np->port <= 1)
8569 np->flags |= NIU_FLAGS_XMAC;
8570
8571 if (!parent->num_ports) {
8572 if (parent->plat_type == PLAT_TYPE_NIU) {
8573 parent->num_ports = 2;
8574 } else {
7f7c4072
MW		 8575 parent->num_ports = niu_pci_vpd_get_nports(np);
8576 if (!parent->num_ports) {
8577 /* Fall back to SPROM as last resort.
8578 * This will fail on most cards.
8579 */
8580 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8581 ESPC_NUM_PORTS_MACS_VAL;
8582
be0c007a
DM		 8583 /* All of the current probing methods fail on
8584 * Maramba on-board parts.
8585 */
7f7c4072 8586 if (!parent->num_ports)
be0c007a 8587 parent->num_ports = 4;
7f7c4072 8588 }
a3138df9
DM		 8589 }
8590 }
8591
a3138df9
DM		 8592 if (np->port >= parent->num_ports)
8593 return -ENODEV;
8594
8595 return 0;
8596}
8597
8598static int __devinit phy_record(struct niu_parent *parent,
8599 struct phy_probe_info *p,
8600 int dev_id_1, int dev_id_2, u8 phy_port,
8601 int type)
8602{
8603 u32 id = (dev_id_1 << 16) | dev_id_2;
8604 u8 idx;
8605
8606 if (dev_id_1 < 0 || dev_id_2 < 0)
8607 return 0;
8608 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
b0de8e40 8609 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
a5d6ab56
MW		 8610 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8611 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
a3138df9
DM		 8612 return 0;
8613 } else {
8614 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8615 return 0;
8616 }
8617
8618 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8619 parent->index, id,
f10a1f2e
JP		 8620 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8621 type == PHY_TYPE_PCS ? "PCS" : "MII",
a3138df9
DM		 8622 phy_port);
8623
8624 if (p->cur[type] >= NIU_MAX_PORTS) {
f10a1f2e 8625 pr_err("Too many PHY ports\n");
a3138df9
DM		 8626 return -EINVAL;
8627 }
8628 idx = p->cur[type];
8629 p->phy_id[type][idx] = id;
8630 p->phy_port[type][idx] = phy_port;
8631 p->cur[type] = idx + 1;
8632 return 0;
8633}
8634
8635static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8636{
8637 int i;
8638
8639 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8640 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8641 return 1;
8642 }
8643 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8644 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8645 return 1;
8646 }
8647
8648 return 0;
8649}
8650
8651static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8652{
8653 int port, cnt;
8654
8655 cnt = 0;
8656 *lowest = 32;
8657 for (port = 8; port < 32; port++) {
8658 if (port_has_10g(p, port)) {
8659 if (!cnt)
8660 *lowest = port;
8661 cnt++;
8662 }
8663 }
8664
8665 return cnt;
8666}
8667
8668static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8669{
8670 *lowest = 32;
8671 if (p->cur[PHY_TYPE_MII])
8672 *lowest = p->phy_port[PHY_TYPE_MII][0];
8673
8674 return p->cur[PHY_TYPE_MII];
8675}
8676
8677static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8678{
8679 int num_ports = parent->num_ports;
8680 int i;
8681
8682 for (i = 0; i < num_ports; i++) {
8683 parent->rxchan_per_port[i] = (16 / num_ports);
8684 parent->txchan_per_port[i] = (16 / num_ports);
8685
f10a1f2e 8686 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8687 parent->index, i,
8688 parent->rxchan_per_port[i],
8689 parent->txchan_per_port[i]);
8690 }
8691}
8692
8693static void __devinit niu_divide_channels(struct niu_parent *parent,
8694 int num_10g, int num_1g)
8695{
8696 int num_ports = parent->num_ports;
8697 int rx_chans_per_10g, rx_chans_per_1g;
8698 int tx_chans_per_10g, tx_chans_per_1g;
8699 int i, tot_rx, tot_tx;
8700
8701 if (!num_10g || !num_1g) {
8702 rx_chans_per_10g = rx_chans_per_1g =
8703 (NIU_NUM_RXCHAN / num_ports);
8704 tx_chans_per_10g = tx_chans_per_1g =
8705 (NIU_NUM_TXCHAN / num_ports);
8706 } else {
8707 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8708 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8709 (rx_chans_per_1g * num_1g)) /
8710 num_10g;
8711
8712 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8713 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8714 (tx_chans_per_1g * num_1g)) /
8715 num_10g;
8716 }
8717
8718 tot_rx = tot_tx = 0;
8719 for (i = 0; i < num_ports; i++) {
8720 int type = phy_decode(parent->port_phy, i);
8721
8722 if (type == PORT_TYPE_10G) {
8723 parent->rxchan_per_port[i] = rx_chans_per_10g;
8724 parent->txchan_per_port[i] = tx_chans_per_10g;
8725 } else {
8726 parent->rxchan_per_port[i] = rx_chans_per_1g;
8727 parent->txchan_per_port[i] = tx_chans_per_1g;
8728 }
f10a1f2e 8729 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8730 parent->index, i,
8731 parent->rxchan_per_port[i],
8732 parent->txchan_per_port[i]);
8733 tot_rx += parent->rxchan_per_port[i];
8734 tot_tx += parent->txchan_per_port[i];
8735 }
8736
8737 if (tot_rx > NIU_NUM_RXCHAN) {
f10a1f2e 8738 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
a3138df9
DM		 8739 parent->index, tot_rx);
8740 for (i = 0; i < num_ports; i++)
8741 parent->rxchan_per_port[i] = 1;
8742 }
8743 if (tot_tx > NIU_NUM_TXCHAN) {
f10a1f2e 8744 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
a3138df9
DM		 8745 parent->index, tot_tx);
8746 for (i = 0; i < num_ports; i++)
8747 parent->txchan_per_port[i] = 1;
8748 }
8749 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
f10a1f2e
JP		 8750 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8751 parent->index, tot_rx, tot_tx);
a3138df9
DM		 8752 }
8753}
8754
8755static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8756 int num_10g, int num_1g)
8757{
8758 int i, num_ports = parent->num_ports;
8759 int rdc_group, rdc_groups_per_port;
8760 int rdc_channel_base;
8761
8762 rdc_group = 0;
8763 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8764
8765 rdc_channel_base = 0;
8766
8767 for (i = 0; i < num_ports; i++) {
8768 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8769 int grp, num_channels = parent->rxchan_per_port[i];
8770 int this_channel_offset;
8771
8772 tp->first_table_num = rdc_group;
8773 tp->num_tables = rdc_groups_per_port;
8774 this_channel_offset = 0;
8775 for (grp = 0; grp < tp->num_tables; grp++) {
8776 struct rdc_table *rt = &tp->tables[grp];
8777 int slot;
8778
f10a1f2e 8779 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
a3138df9
DM		 8780 parent->index, i, tp->first_table_num + grp);
8781 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8782 rt->rxdma_channel[slot] =
8783 rdc_channel_base + this_channel_offset;
8784
f10a1f2e 8785 pr_cont("%d ", rt->rxdma_channel[slot]);
a3138df9
DM		 8786
8787 if (++this_channel_offset == num_channels)
8788 this_channel_offset = 0;
8789 }
f10a1f2e 8790 pr_cont("]\n");
a3138df9
DM		 8791 }
8792
8793 parent->rdc_default[i] = rdc_channel_base;
8794
8795 rdc_channel_base += num_channels;
8796 rdc_group += rdc_groups_per_port;
8797 }
8798}
8799
8800static int __devinit fill_phy_probe_info(struct niu *np,
8801 struct niu_parent *parent,
8802 struct phy_probe_info *info)
8803{
8804 unsigned long flags;
8805 int port, err;
8806
8807 memset(info, 0, sizeof(*info));
8808
8809 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8810 niu_lock_parent(np, flags);
8811 err = 0;
8812 for (port = 8; port < 32; port++) {
8813 int dev_id_1, dev_id_2;
8814
8815 dev_id_1 = mdio_read(np, port,
8816 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8817 dev_id_2 = mdio_read(np, port,
8818 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8819 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8820 PHY_TYPE_PMA_PMD);
8821 if (err)
8822 break;
8823 dev_id_1 = mdio_read(np, port,
8824 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8825 dev_id_2 = mdio_read(np, port,
8826 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8827 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8828 PHY_TYPE_PCS);
8829 if (err)
8830 break;
8831 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8832 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8833 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8834 PHY_TYPE_MII);
8835 if (err)
8836 break;
8837 }
8838 niu_unlock_parent(np, flags);
8839
8840 return err;
8841}
8842
8843static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8844{
8845 struct phy_probe_info *info = &parent->phy_probe_info;
8846 int lowest_10g, lowest_1g;
8847 int num_10g, num_1g;
8848 u32 val;
8849 int err;
8850
e3e081e1
SB		 8851 num_10g = num_1g = 0;
8852
f9af8574
MW		 8853 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8854 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8855 num_10g = 0;
8856 num_1g = 2;
8857 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8858 parent->num_ports = 4;
8859 val = (phy_encode(PORT_TYPE_1G, 0) |
8860 phy_encode(PORT_TYPE_1G, 1) |
a3138df9
DM		 8861 phy_encode(PORT_TYPE_1G, 2) |
8862 phy_encode(PORT_TYPE_1G, 3));
f9af8574 8863 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8864 num_10g = 2;
8865 num_1g = 0;
8866 parent->num_ports = 2;
8867 val = (phy_encode(PORT_TYPE_10G, 0) |
8868 phy_encode(PORT_TYPE_10G, 1));
e3e081e1
SB		 8869 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8870 (parent->plat_type == PLAT_TYPE_NIU)) {
8871 /* this is the Monza case */
8872 if (np->flags & NIU_FLAGS_10G) {
8873 val = (phy_encode(PORT_TYPE_10G, 0) |
8874 phy_encode(PORT_TYPE_10G, 1));
8875 } else {
8876 val = (phy_encode(PORT_TYPE_1G, 0) |
8877 phy_encode(PORT_TYPE_1G, 1));
8878 }
5fbd7e24
MW		 8879 } else {
8880 err = fill_phy_probe_info(np, parent, info);
8881 if (err)
8882 return err;
a3138df9 8883
5fbd7e24
MW		 8884 num_10g = count_10g_ports(info, &lowest_10g);
8885 num_1g = count_1g_ports(info, &lowest_1g);
a3138df9 8886
5fbd7e24
MW		 8887 switch ((num_10g << 4) | num_1g) {
8888 case 0x24:
8889 if (lowest_1g == 10)
8890 parent->plat_type = PLAT_TYPE_VF_P0;
8891 else if (lowest_1g == 26)
8892 parent->plat_type = PLAT_TYPE_VF_P1;
8893 else
8894 goto unknown_vg_1g_port;
a3138df9 8895
5fbd7e24
MW		 8896 /* fallthru */
8897 case 0x22:
a3138df9 8898 val = (phy_encode(PORT_TYPE_10G, 0) |
a3138df9
DM		 8899 phy_encode(PORT_TYPE_10G, 1) |
8900 phy_encode(PORT_TYPE_1G, 2) |
8901 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24 8902 break;
a3138df9 8903
5fbd7e24
MW		 8904 case 0x20:
8905 val = (phy_encode(PORT_TYPE_10G, 0) |
8906 phy_encode(PORT_TYPE_10G, 1));
8907 break;
a3138df9 8908
5fbd7e24
MW		 8909 case 0x10:
8910 val = phy_encode(PORT_TYPE_10G, np->port);
8911 break;
a3138df9 8912
5fbd7e24
MW		 8913 case 0x14:
8914 if (lowest_1g == 10)
8915 parent->plat_type = PLAT_TYPE_VF_P0;
8916 else if (lowest_1g == 26)
8917 parent->plat_type = PLAT_TYPE_VF_P1;
8918 else
8919 goto unknown_vg_1g_port;
8920
8921 /* fallthru */
8922 case 0x13:
8923 if ((lowest_10g & 0x7) == 0)
8924 val = (phy_encode(PORT_TYPE_10G, 0) |
8925 phy_encode(PORT_TYPE_1G, 1) |
8926 phy_encode(PORT_TYPE_1G, 2) |
8927 phy_encode(PORT_TYPE_1G, 3));
8928 else
8929 val = (phy_encode(PORT_TYPE_1G, 0) |
8930 phy_encode(PORT_TYPE_10G, 1) |
8931 phy_encode(PORT_TYPE_1G, 2) |
8932 phy_encode(PORT_TYPE_1G, 3));
8933 break;
8934
8935 case 0x04:
8936 if (lowest_1g == 10)
8937 parent->plat_type = PLAT_TYPE_VF_P0;
8938 else if (lowest_1g == 26)
8939 parent->plat_type = PLAT_TYPE_VF_P1;
8940 else
8941 goto unknown_vg_1g_port;
8942
8943 val = (phy_encode(PORT_TYPE_1G, 0) |
8944 phy_encode(PORT_TYPE_1G, 1) |
8945 phy_encode(PORT_TYPE_1G, 2) |
8946 phy_encode(PORT_TYPE_1G, 3));
8947 break;
8948
8949 default:
f10a1f2e 8950 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
5fbd7e24
MW		 8951 num_10g, num_1g);
8952 return -EINVAL;
8953 }
a3138df9
DM		 8954 }
8955
8956 parent->port_phy = val;
8957
8958 if (parent->plat_type == PLAT_TYPE_NIU)
8959 niu_n2_divide_channels(parent);
8960 else
8961 niu_divide_channels(parent, num_10g, num_1g);
8962
8963 niu_divide_rdc_groups(parent, num_10g, num_1g);
8964
8965 return 0;
8966
8967unknown_vg_1g_port:
f10a1f2e 8968 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
a3138df9
DM		 8969 return -EINVAL;
8970}
8971
8972static int __devinit niu_probe_ports(struct niu *np)
8973{
8974 struct niu_parent *parent = np->parent;
8975 int err, i;
8976
a3138df9
DM		 8977 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8978 err = walk_phys(np, parent);
8979 if (err)
8980 return err;
8981
8982 niu_set_ldg_timer_res(np, 2);
8983 for (i = 0; i <= LDN_MAX; i++)
8984 niu_ldn_irq_enable(np, i, 0);
8985 }
8986
8987 if (parent->port_phy == PORT_PHY_INVALID)
8988 return -EINVAL;
8989
8990 return 0;
8991}
8992
8993static int __devinit niu_classifier_swstate_init(struct niu *np)
8994{
8995 struct niu_classifier *cp = &np->clas;
8996
2d96cf8c
SB		 8997 cp->tcam_top = (u16) np->port;
8998 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
a3138df9
DM		 8999 cp->h1_init = 0xffffffff;
9000 cp->h2_init = 0xffff;
9001
9002 return fflp_early_init(np);
9003}
9004
9005static void __devinit niu_link_config_init(struct niu *np)
9006{
9007 struct niu_link_config *lp = &np->link_config;
9008
9009 lp->advertising = (ADVERTISED_10baseT_Half |
9010 ADVERTISED_10baseT_Full |
9011 ADVERTISED_100baseT_Half |
9012 ADVERTISED_100baseT_Full |
9013 ADVERTISED_1000baseT_Half |
9014 ADVERTISED_1000baseT_Full |
9015 ADVERTISED_10000baseT_Full |
9016 ADVERTISED_Autoneg);
9017 lp->speed = lp->active_speed = SPEED_INVALID;
38bb045d
CB		 9018 lp->duplex = DUPLEX_FULL;
9019 lp->active_duplex = DUPLEX_INVALID;
9020 lp->autoneg = 1;
a3138df9
DM		 9021#if 0
9022 lp->loopback_mode = LOOPBACK_MAC;
9023 lp->active_speed = SPEED_10000;
9024 lp->active_duplex = DUPLEX_FULL;
9025#else
9026 lp->loopback_mode = LOOPBACK_DISABLED;
9027#endif
9028}
9029
9030static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9031{
9032 switch (np->port) {
9033 case 0:
9034 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9035 np->ipp_off = 0x00000;
9036 np->pcs_off = 0x04000;
9037 np->xpcs_off = 0x02000;
9038 break;
9039
9040 case 1:
9041 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9042 np->ipp_off = 0x08000;
9043 np->pcs_off = 0x0a000;
9044 np->xpcs_off = 0x08000;
9045 break;
9046
9047 case 2:
9048 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9049 np->ipp_off = 0x04000;
9050 np->pcs_off = 0x0e000;
9051 np->xpcs_off = ~0UL;
9052 break;
9053
9054 case 3:
9055 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9056 np->ipp_off = 0x0c000;
9057 np->pcs_off = 0x12000;
9058 np->xpcs_off = ~0UL;
9059 break;
9060
9061 default:
f10a1f2e 9062 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
a3138df9
DM		 9063 return -EINVAL;
9064 }
9065
9066 return 0;
9067}
9068
9069static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9070{
9071 struct msix_entry msi_vec[NIU_NUM_LDG];
9072 struct niu_parent *parent = np->parent;
9073 struct pci_dev *pdev = np->pdev;
9074 int i, num_irqs, err;
9075 u8 first_ldg;
9076
9077 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9078 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9079 ldg_num_map[i] = first_ldg + i;
9080
9081 num_irqs = (parent->rxchan_per_port[np->port] +
9082 parent->txchan_per_port[np->port] +
9083 (np->port == 0 ? 3 : 1));
9084 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9085
9086retry:
9087 for (i = 0; i < num_irqs; i++) {
9088 msi_vec[i].vector = 0;
9089 msi_vec[i].entry = i;
9090 }
9091
9092 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9093 if (err < 0) {
9094 np->flags &= ~NIU_FLAGS_MSIX;
9095 return;
9096 }
9097 if (err > 0) {
9098 num_irqs = err;
9099 goto retry;
9100 }
9101
9102 np->flags |= NIU_FLAGS_MSIX;
9103 for (i = 0; i < num_irqs; i++)
9104 np->ldg[i].irq = msi_vec[i].vector;
9105 np->num_ldg = num_irqs;
9106}
9107
9108static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9109{
9110#ifdef CONFIG_SPARC64
9111 struct of_device *op = np->op;
9112 const u32 *int_prop;
9113 int i;
9114
61c7a080 9115 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
a3138df9
DM		 9116 if (!int_prop)
9117 return -ENODEV;
9118
1636f8ac 9119 for (i = 0; i < op->archdata.num_irqs; i++) {
a3138df9 9120 ldg_num_map[i] = int_prop[i];
1636f8ac 9121 np->ldg[i].irq = op->archdata.irqs[i];
a3138df9
DM		 9122 }
9123
1636f8ac 9124 np->num_ldg = op->archdata.num_irqs;
a3138df9
DM		 9125
9126 return 0;
9127#else
9128 return -EINVAL;
9129#endif
9130}
9131
9132static int __devinit niu_ldg_init(struct niu *np)
9133{
9134 struct niu_parent *parent = np->parent;
9135 u8 ldg_num_map[NIU_NUM_LDG];
9136 int first_chan, num_chan;
9137 int i, err, ldg_rotor;
9138 u8 port;
9139
9140 np->num_ldg = 1;
9141 np->ldg[0].irq = np->dev->irq;
9142 if (parent->plat_type == PLAT_TYPE_NIU) {
9143 err = niu_n2_irq_init(np, ldg_num_map);
9144 if (err)
9145 return err;
9146 } else
9147 niu_try_msix(np, ldg_num_map);
9148
9149 port = np->port;
9150 for (i = 0; i < np->num_ldg; i++) {
9151 struct niu_ldg *lp = &np->ldg[i];
9152
9153 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9154
9155 lp->np = np;
9156 lp->ldg_num = ldg_num_map[i];
9157 lp->timer = 2; /* XXX */
9158
9159 /* On N2 NIU the firmware has setup the SID mappings so they go
9160 * to the correct values that will route the LDG to the proper
9161 * interrupt in the NCU interrupt table.
9162 */
9163 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9164 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9165 if (err)
9166 return err;
9167 }
9168 }
9169
9170 /* We adopt the LDG assignment ordering used by the N2 NIU
9171 * 'interrupt' properties because that simplifies a lot of
9172 * things. This ordering is:
9173 *
9174 * MAC
9175 * MIF (if port zero)
9176 * SYSERR (if port zero)
9177 * RX channels
9178 * TX channels
9179 */
9180
9181 ldg_rotor = 0;
9182
9183 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9184 LDN_MAC(port));
9185 if (err)
9186 return err;
9187
9188 ldg_rotor++;
9189 if (ldg_rotor == np->num_ldg)
9190 ldg_rotor = 0;
9191
9192 if (port == 0) {
9193 err = niu_ldg_assign_ldn(np, parent,
9194 ldg_num_map[ldg_rotor],
9195 LDN_MIF);
9196 if (err)
9197 return err;
9198
9199 ldg_rotor++;
9200 if (ldg_rotor == np->num_ldg)
9201 ldg_rotor = 0;
9202
9203 err = niu_ldg_assign_ldn(np, parent,
9204 ldg_num_map[ldg_rotor],
9205 LDN_DEVICE_ERROR);
9206 if (err)
9207 return err;
9208
9209 ldg_rotor++;
9210 if (ldg_rotor == np->num_ldg)
9211 ldg_rotor = 0;
9212
9213 }
9214
9215 first_chan = 0;
9216 for (i = 0; i < port; i++)
9217 first_chan += parent->rxchan_per_port[port];
9218 num_chan = parent->rxchan_per_port[port];
9219
9220 for (i = first_chan; i < (first_chan + num_chan); i++) {
9221 err = niu_ldg_assign_ldn(np, parent,
9222 ldg_num_map[ldg_rotor],
9223 LDN_RXDMA(i));
9224 if (err)
9225 return err;
9226 ldg_rotor++;
9227 if (ldg_rotor == np->num_ldg)
9228 ldg_rotor = 0;
9229 }
9230
9231 first_chan = 0;
9232 for (i = 0; i < port; i++)
9233 first_chan += parent->txchan_per_port[port];
9234 num_chan = parent->txchan_per_port[port];
9235 for (i = first_chan; i < (first_chan + num_chan); i++) {
9236 err = niu_ldg_assign_ldn(np, parent,
9237 ldg_num_map[ldg_rotor],
9238 LDN_TXDMA(i));
9239 if (err)
9240 return err;
9241 ldg_rotor++;
9242 if (ldg_rotor == np->num_ldg)
9243 ldg_rotor = 0;
9244 }
9245
9246 return 0;
9247}
9248
9249static void __devexit niu_ldg_free(struct niu *np)
9250{
9251 if (np->flags & NIU_FLAGS_MSIX)
9252 pci_disable_msix(np->pdev);
9253}
9254
9255static int __devinit niu_get_of_props(struct niu *np)
9256{
9257#ifdef CONFIG_SPARC64
9258 struct net_device *dev = np->dev;
9259 struct device_node *dp;
9260 const char *phy_type;
9261 const u8 *mac_addr;
f9af8574 9262 const char *model;
a3138df9
DM		 9263 int prop_len;
9264
9265 if (np->parent->plat_type == PLAT_TYPE_NIU)
61c7a080 9266 dp = np->op->dev.of_node;
a3138df9
DM		 9267 else
9268 dp = pci_device_to_OF_node(np->pdev);
9269
9270 phy_type = of_get_property(dp, "phy-type", &prop_len);
9271 if (!phy_type) {
f10a1f2e
JP		 9272 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9273 dp->full_name);
a3138df9
DM		 9274 return -EINVAL;
9275 }
9276
9277 if (!strcmp(phy_type, "none"))
9278 return -ENODEV;
9279
9280 strcpy(np->vpd.phy_type, phy_type);
9281
9282 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e
JP		 9283 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9284 dp->full_name, np->vpd.phy_type);
a3138df9
DM		 9285 return -EINVAL;
9286 }
9287
9288 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9289 if (!mac_addr) {
f10a1f2e
JP		 9290 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9291 dp->full_name);
a3138df9
DM		 9292 return -EINVAL;
9293 }
9294 if (prop_len != dev->addr_len) {
f10a1f2e
JP		 9295 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9296 dp->full_name, prop_len);
a3138df9
DM		 9297 }
9298 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9299 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 9300 netdev_err(dev, "%s: OF MAC address is invalid\n",
9301 dp->full_name);
9302 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
a3138df9
DM		 9303 return -EINVAL;
9304 }
9305
9306 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
f9af8574
MW		 9307
9308 model = of_get_property(dp, "model", &prop_len);
9309
9310 if (model)
9311 strcpy(np->vpd.model, model);
a3138df9 9312
9c5cd670
TC		 9313 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9314 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9315 NIU_FLAGS_HOTPLUG_PHY);
9316 }
9317
a3138df9
DM		 9318 return 0;
9319#else
9320 return -EINVAL;
9321#endif
9322}
9323
9324static int __devinit niu_get_invariants(struct niu *np)
9325{
9326 int err, have_props;
9327 u32 offset;
9328
9329 err = niu_get_of_props(np);
9330 if (err == -ENODEV)
9331 return err;
9332
9333 have_props = !err;
9334
a3138df9
DM		 9335 err = niu_init_mac_ipp_pcs_base(np);
9336 if (err)
9337 return err;
9338
7f7c4072
MW		 9339 if (have_props) {
9340 err = niu_get_and_validate_port(np);
9341 if (err)
9342 return err;
9343
9344 } else {
a3138df9
DM		 9345 if (np->parent->plat_type == PLAT_TYPE_NIU)
9346 return -EINVAL;
9347
9348 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9349 offset = niu_pci_vpd_offset(np);
f10a1f2e
JP		 9350 netif_printk(np, probe, KERN_DEBUG, np->dev,
9351 "%s() VPD offset [%08x]\n", __func__, offset);
a3138df9
DM		 9352 if (offset)
9353 niu_pci_vpd_fetch(np, offset);
9354 nw64(ESPC_PIO_EN, 0);
9355
7f7c4072 9356 if (np->flags & NIU_FLAGS_VPD_VALID) {
a3138df9 9357 niu_pci_vpd_validate(np);
7f7c4072
MW		 9358 err = niu_get_and_validate_port(np);
9359 if (err)
9360 return err;
9361 }
a3138df9
DM		 9362
9363 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7f7c4072
MW		 9364 err = niu_get_and_validate_port(np);
9365 if (err)
9366 return err;
a3138df9
DM		 9367 err = niu_pci_probe_sprom(np);
9368 if (err)
9369 return err;
9370 }
9371 }
9372
9373 err = niu_probe_ports(np);
9374 if (err)
9375 return err;
9376
9377 niu_ldg_init(np);
9378
9379 niu_classifier_swstate_init(np);
9380 niu_link_config_init(np);
9381
9382 err = niu_determine_phy_disposition(np);
9383 if (!err)
9384 err = niu_init_link(np);
9385
9386 return err;
9387}
9388
9389static LIST_HEAD(niu_parent_list);
9390static DEFINE_MUTEX(niu_parent_lock);
9391static int niu_parent_index;
9392
9393static ssize_t show_port_phy(struct device *dev,
9394 struct device_attribute *attr, char *buf)
9395{
9396 struct platform_device *plat_dev = to_platform_device(dev);
9397 struct niu_parent *p = plat_dev->dev.platform_data;
9398 u32 port_phy = p->port_phy;
9399 char *orig_buf = buf;
9400 int i;
9401
9402 if (port_phy == PORT_PHY_UNKNOWN ||
9403 port_phy == PORT_PHY_INVALID)
9404 return 0;
9405
9406 for (i = 0; i < p->num_ports; i++) {
9407 const char *type_str;
9408 int type;
9409
9410 type = phy_decode(port_phy, i);
9411 if (type == PORT_TYPE_10G)
9412 type_str = "10G";
9413 else
9414 type_str = "1G";
9415 buf += sprintf(buf,
9416 (i == 0) ? "%s" : " %s",
9417 type_str);
9418 }
9419 buf += sprintf(buf, "\n");
9420 return buf - orig_buf;
9421}
9422
9423static ssize_t show_plat_type(struct device *dev,
9424 struct device_attribute *attr, char *buf)
9425{
9426 struct platform_device *plat_dev = to_platform_device(dev);
9427 struct niu_parent *p = plat_dev->dev.platform_data;
9428 const char *type_str;
9429
9430 switch (p->plat_type) {
9431 case PLAT_TYPE_ATLAS:
9432 type_str = "atlas";
9433 break;
9434 case PLAT_TYPE_NIU:
9435 type_str = "niu";
9436 break;
9437 case PLAT_TYPE_VF_P0:
9438 type_str = "vf_p0";
9439 break;
9440 case PLAT_TYPE_VF_P1:
9441 type_str = "vf_p1";
9442 break;
9443 default:
9444 type_str = "unknown";
9445 break;
9446 }
9447
9448 return sprintf(buf, "%s\n", type_str);
9449}
9450
9451static ssize_t __show_chan_per_port(struct device *dev,
9452 struct device_attribute *attr, char *buf,
9453 int rx)
9454{
9455 struct platform_device *plat_dev = to_platform_device(dev);
9456 struct niu_parent *p = plat_dev->dev.platform_data;
9457 char *orig_buf = buf;
9458 u8 *arr;
9459 int i;
9460
9461 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9462
9463 for (i = 0; i < p->num_ports; i++) {
9464 buf += sprintf(buf,
9465 (i == 0) ? "%d" : " %d",
9466 arr[i]);
9467 }
9468 buf += sprintf(buf, "\n");
9469
9470 return buf - orig_buf;
9471}
9472
9473static ssize_t show_rxchan_per_port(struct device *dev,
9474 struct device_attribute *attr, char *buf)
9475{
9476 return __show_chan_per_port(dev, attr, buf, 1);
9477}
9478
9479static ssize_t show_txchan_per_port(struct device *dev,
9480 struct device_attribute *attr, char *buf)
9481{
9482 return __show_chan_per_port(dev, attr, buf, 1);
9483}
9484
9485static ssize_t show_num_ports(struct device *dev,
9486 struct device_attribute *attr, char *buf)
9487{
9488 struct platform_device *plat_dev = to_platform_device(dev);
9489 struct niu_parent *p = plat_dev->dev.platform_data;
9490
9491 return sprintf(buf, "%d\n", p->num_ports);
9492}
9493
9494static struct device_attribute niu_parent_attributes[] = {
9495 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9496 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9497 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9498 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9499 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9500 {}
9501};
9502
9503static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9504 union niu_parent_id *id,
9505 u8 ptype)
9506{
9507 struct platform_device *plat_dev;
9508 struct niu_parent *p;
9509 int i;
9510
a3138df9
DM		 9511 plat_dev = platform_device_register_simple("niu", niu_parent_index,
9512 NULL, 0);
58f3e0a8 9513 if (IS_ERR(plat_dev))
a3138df9
DM		 9514 return NULL;
9515
9516 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9517 int err = device_create_file(&plat_dev->dev,
9518 &niu_parent_attributes[i]);
9519 if (err)
9520 goto fail_unregister;
9521 }
9522
9523 p = kzalloc(sizeof(*p), GFP_KERNEL);
9524 if (!p)
9525 goto fail_unregister;
9526
9527 p->index = niu_parent_index++;
9528
9529 plat_dev->dev.platform_data = p;
9530 p->plat_dev = plat_dev;
9531
9532 memcpy(&p->id, id, sizeof(*id));
9533 p->plat_type = ptype;
9534 INIT_LIST_HEAD(&p->list);
9535 atomic_set(&p->refcnt, 0);
9536 list_add(&p->list, &niu_parent_list);
9537 spin_lock_init(&p->lock);
9538
9539 p->rxdma_clock_divider = 7500;
9540
9541 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9542 if (p->plat_type == PLAT_TYPE_NIU)
9543 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9544
9545 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9546 int index = i - CLASS_CODE_USER_PROG1;
9547
9548 p->tcam_key[index] = TCAM_KEY_TSEL;
9549 p->flow_key[index] = (FLOW_KEY_IPSA |
9550 FLOW_KEY_IPDA |
9551 FLOW_KEY_PROTO |
9552 (FLOW_KEY_L4_BYTE12 <<
9553 FLOW_KEY_L4_0_SHIFT) |
9554 (FLOW_KEY_L4_BYTE12 <<
9555 FLOW_KEY_L4_1_SHIFT));
9556 }
9557
9558 for (i = 0; i < LDN_MAX + 1; i++)
9559 p->ldg_map[i] = LDG_INVALID;
9560
9561 return p;
9562
9563fail_unregister:
9564 platform_device_unregister(plat_dev);
9565 return NULL;
9566}
9567
9568static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9569 union niu_parent_id *id,
9570 u8 ptype)
9571{
9572 struct niu_parent *p, *tmp;
9573 int port = np->port;
9574
a3138df9
DM		 9575 mutex_lock(&niu_parent_lock);
9576 p = NULL;
9577 list_for_each_entry(tmp, &niu_parent_list, list) {
9578 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9579 p = tmp;
9580 break;
9581 }
9582 }
9583 if (!p)
9584 p = niu_new_parent(np, id, ptype);
9585
9586 if (p) {
9587 char port_name[6];
9588 int err;
9589
9590 sprintf(port_name, "port%d", port);
9591 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9592 &np->device->kobj,
9593 port_name);
9594 if (!err) {
9595 p->ports[port] = np;
9596 atomic_inc(&p->refcnt);
9597 }
9598 }
9599 mutex_unlock(&niu_parent_lock);
9600
9601 return p;
9602}
9603
9604static void niu_put_parent(struct niu *np)
9605{
9606 struct niu_parent *p = np->parent;
9607 u8 port = np->port;
9608 char port_name[6];
9609
9610 BUG_ON(!p || p->ports[port] != np);
9611
f10a1f2e
JP		 9612 netif_printk(np, probe, KERN_DEBUG, np->dev,
9613 "%s() port[%u]\n", __func__, port);
a3138df9
DM		 9614
9615 sprintf(port_name, "port%d", port);
9616
9617 mutex_lock(&niu_parent_lock);
9618
9619 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9620
9621 p->ports[port] = NULL;
9622 np->parent = NULL;
9623
9624 if (atomic_dec_and_test(&p->refcnt)) {
9625 list_del(&p->list);
9626 platform_device_unregister(p->plat_dev);
9627 }
9628
9629 mutex_unlock(&niu_parent_lock);
9630}
9631
9632static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9633 u64 *handle, gfp_t flag)
9634{
9635 dma_addr_t dh;
9636 void *ret;
9637
9638 ret = dma_alloc_coherent(dev, size, &dh, flag);
9639 if (ret)
9640 *handle = dh;
9641 return ret;
9642}
9643
9644static void niu_pci_free_coherent(struct device *dev, size_t size,
9645 void *cpu_addr, u64 handle)
9646{
9647 dma_free_coherent(dev, size, cpu_addr, handle);
9648}
9649
9650static u64 niu_pci_map_page(struct device *dev, struct page *page,
9651 unsigned long offset, size_t size,
9652 enum dma_data_direction direction)
9653{
9654 return dma_map_page(dev, page, offset, size, direction);
9655}
9656
9657static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9658 size_t size, enum dma_data_direction direction)
9659{
a08b32df 9660 dma_unmap_page(dev, dma_address, size, direction);
a3138df9
DM		 9661}
9662
9663static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9664 size_t size,
9665 enum dma_data_direction direction)
9666{
9667 return dma_map_single(dev, cpu_addr, size, direction);
9668}
9669
9670static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9671 size_t size,
9672 enum dma_data_direction direction)
9673{
9674 dma_unmap_single(dev, dma_address, size, direction);
9675}
9676
9677static const struct niu_ops niu_pci_ops = {
9678 .alloc_coherent = niu_pci_alloc_coherent,
9679 .free_coherent = niu_pci_free_coherent,
9680 .map_page = niu_pci_map_page,
9681 .unmap_page = niu_pci_unmap_page,
9682 .map_single = niu_pci_map_single,
9683 .unmap_single = niu_pci_unmap_single,
9684};
9685
9686static void __devinit niu_driver_version(void)
9687{
9688 static int niu_version_printed;
9689
9690 if (niu_version_printed++ == 0)
9691 pr_info("%s", version);
9692}
9693
9694static struct net_device * __devinit niu_alloc_and_init(
9695 struct device *gen_dev, struct pci_dev *pdev,
9696 struct of_device *op, const struct niu_ops *ops,
9697 u8 port)
9698{
b4c21639 9699 struct net_device *dev;
a3138df9
DM		 9700 struct niu *np;
9701
b4c21639 9702 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
a3138df9 9703 if (!dev) {
f10a1f2e 9704 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
a3138df9
DM		 9705 return NULL;
9706 }
9707
9708 SET_NETDEV_DEV(dev, gen_dev);
9709
9710 np = netdev_priv(dev);
9711 np->dev = dev;
9712 np->pdev = pdev;
9713 np->op = op;
9714 np->device = gen_dev;
9715 np->ops = ops;
9716
9717 np->msg_enable = niu_debug;
9718
9719 spin_lock_init(&np->lock);
9720 INIT_WORK(&np->reset_task, niu_reset_task);
9721
9722 np->port = port;
9723
9724 return dev;
9725}
9726
2c9171d4
SH		 9727static const struct net_device_ops niu_netdev_ops = {
9728 .ndo_open = niu_open,
9729 .ndo_stop = niu_close,
00829823 9730 .ndo_start_xmit = niu_start_xmit,
2c9171d4
SH		 9731 .ndo_get_stats = niu_get_stats,
9732 .ndo_set_multicast_list = niu_set_rx_mode,
9733 .ndo_validate_addr = eth_validate_addr,
9734 .ndo_set_mac_address = niu_set_mac_addr,
9735 .ndo_do_ioctl = niu_ioctl,
9736 .ndo_tx_timeout = niu_tx_timeout,
9737 .ndo_change_mtu = niu_change_mtu,
9738};
9739
a3138df9
DM		 9740static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9741{
2c9171d4 9742 dev->netdev_ops = &niu_netdev_ops;
a3138df9
DM		 9743 dev->ethtool_ops = &niu_ethtool_ops;
9744 dev->watchdog_timeo = NIU_TX_TIMEOUT;
a3138df9
DM		 9745}
9746
9747static void __devinit niu_device_announce(struct niu *np)
9748{
9749 struct net_device *dev = np->dev;
a3138df9 9750
e174961c 9751 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
a3138df9 9752
5fbd7e24
MW		 9753 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9754 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9755 dev->name,
9756 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9757 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9758 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9759 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9760 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9761 np->vpd.phy_type);
9762 } else {
9763 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9764 dev->name,
9765 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9766 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
e3e081e1
SB		 9767 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9768 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9769 "COPPER")),
5fbd7e24
MW		 9770 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9771 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9772 np->vpd.phy_type);
9773 }
a3138df9
DM		 9774}
9775
3cfa856d
DM		 9776static void __devinit niu_set_basic_features(struct net_device *dev)
9777{
9778 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM |
9779 NETIF_F_GRO | NETIF_F_RXHASH);
9780}
9781
a3138df9
DM		 9782static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9783 const struct pci_device_id *ent)
9784{
a3138df9
DM		 9785 union niu_parent_id parent_id;
9786 struct net_device *dev;
9787 struct niu *np;
9788 int err, pos;
9789 u64 dma_mask;
9790 u16 val16;
9791
9792 niu_driver_version();
9793
9794 err = pci_enable_device(pdev);
9795 if (err) {
f10a1f2e 9796 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
a3138df9
DM		 9797 return err;
9798 }
9799
9800 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9801 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
f10a1f2e 9802 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
a3138df9
DM		 9803 err = -ENODEV;
9804 goto err_out_disable_pdev;
9805 }
9806
9807 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9808 if (err) {
f10a1f2e 9809 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
a3138df9
DM		 9810 goto err_out_disable_pdev;
9811 }
9812
9813 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9814 if (pos <= 0) {
f10a1f2e 9815 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
a3138df9
DM		 9816 goto err_out_free_res;
9817 }
9818
9819 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9820 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9821 if (!dev) {
9822 err = -ENOMEM;
9823 goto err_out_free_res;
9824 }
9825 np = netdev_priv(dev);
9826
9827 memset(&parent_id, 0, sizeof(parent_id));
9828 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9829 parent_id.pci.bus = pdev->bus->number;
9830 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9831
9832 np->parent = niu_get_parent(np, &parent_id,
9833 PLAT_TYPE_ATLAS);
9834 if (!np->parent) {
9835 err = -ENOMEM;
9836 goto err_out_free_dev;
9837 }
9838
9839 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9840 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9841 val16 |= (PCI_EXP_DEVCTL_CERE |
9842 PCI_EXP_DEVCTL_NFERE |
9843 PCI_EXP_DEVCTL_FERE |
9844 PCI_EXP_DEVCTL_URRE |
9845 PCI_EXP_DEVCTL_RELAX_EN);
9846 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9847
8cbd9623 9848 dma_mask = DMA_BIT_MASK(44);
a3138df9
DM		 9849 err = pci_set_dma_mask(pdev, dma_mask);
9850 if (!err) {
9851 dev->features |= NETIF_F_HIGHDMA;
9852 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9853 if (err) {
f10a1f2e 9854 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
a3138df9
DM		 9855 goto err_out_release_parent;
9856 }
9857 }
284901a9
YH		 9858 if (err || dma_mask == DMA_BIT_MASK(32)) {
9859 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
a3138df9 9860 if (err) {
f10a1f2e 9861 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
a3138df9
DM		 9862 goto err_out_release_parent;
9863 }
9864 }
9865
3cfa856d 9866 niu_set_basic_features(dev);
a3138df9 9867
19ecb6ba 9868 np->regs = pci_ioremap_bar(pdev, 0);
a3138df9 9869 if (!np->regs) {
f10a1f2e 9870 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 9871 err = -ENOMEM;
9872 goto err_out_release_parent;
9873 }
9874
9875 pci_set_master(pdev);
9876 pci_save_state(pdev);
9877
9878 dev->irq = pdev->irq;
9879
9880 niu_assign_netdev_ops(dev);
9881
9882 err = niu_get_invariants(np);
9883 if (err) {
9884 if (err != -ENODEV)
f10a1f2e 9885 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 9886 goto err_out_iounmap;
9887 }
9888
9889 err = register_netdev(dev);
9890 if (err) {
f10a1f2e 9891 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 9892 goto err_out_iounmap;
9893 }
9894
9895 pci_set_drvdata(pdev, dev);
9896
9897 niu_device_announce(np);
9898
9899 return 0;
9900
9901err_out_iounmap:
9902 if (np->regs) {
9903 iounmap(np->regs);
9904 np->regs = NULL;
9905 }
9906
9907err_out_release_parent:
9908 niu_put_parent(np);
9909
9910err_out_free_dev:
9911 free_netdev(dev);
9912
9913err_out_free_res:
9914 pci_release_regions(pdev);
9915
9916err_out_disable_pdev:
9917 pci_disable_device(pdev);
9918 pci_set_drvdata(pdev, NULL);
9919
9920 return err;
9921}
9922
9923static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9924{
9925 struct net_device *dev = pci_get_drvdata(pdev);
9926
9927 if (dev) {
9928 struct niu *np = netdev_priv(dev);
9929
9930 unregister_netdev(dev);
9931 if (np->regs) {
9932 iounmap(np->regs);
9933 np->regs = NULL;
9934 }
9935
9936 niu_ldg_free(np);
9937
9938 niu_put_parent(np);
9939
9940 free_netdev(dev);
9941 pci_release_regions(pdev);
9942 pci_disable_device(pdev);
9943 pci_set_drvdata(pdev, NULL);
9944 }
9945}
9946
9947static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9948{
9949 struct net_device *dev = pci_get_drvdata(pdev);
9950 struct niu *np = netdev_priv(dev);
9951 unsigned long flags;
9952
9953 if (!netif_running(dev))
9954 return 0;
9955
9956 flush_scheduled_work();
9957 niu_netif_stop(np);
9958
9959 del_timer_sync(&np->timer);
9960
9961 spin_lock_irqsave(&np->lock, flags);
9962 niu_enable_interrupts(np, 0);
9963 spin_unlock_irqrestore(&np->lock, flags);
9964
9965 netif_device_detach(dev);
9966
9967 spin_lock_irqsave(&np->lock, flags);
9968 niu_stop_hw(np);
9969 spin_unlock_irqrestore(&np->lock, flags);
9970
9971 pci_save_state(pdev);
9972
9973 return 0;
9974}
9975
9976static int niu_resume(struct pci_dev *pdev)
9977{
9978 struct net_device *dev = pci_get_drvdata(pdev);
9979 struct niu *np = netdev_priv(dev);
9980 unsigned long flags;
9981 int err;
9982
9983 if (!netif_running(dev))
9984 return 0;
9985
9986 pci_restore_state(pdev);
9987
9988 netif_device_attach(dev);
9989
9990 spin_lock_irqsave(&np->lock, flags);
9991
9992 err = niu_init_hw(np);
9993 if (!err) {
9994 np->timer.expires = jiffies + HZ;
9995 add_timer(&np->timer);
9996 niu_netif_start(np);
9997 }
9998
9999 spin_unlock_irqrestore(&np->lock, flags);
10000
10001 return err;
10002}
10003
10004static struct pci_driver niu_pci_driver = {
10005 .name = DRV_MODULE_NAME,
10006 .id_table = niu_pci_tbl,
10007 .probe = niu_pci_init_one,
10008 .remove = __devexit_p(niu_pci_remove_one),
10009 .suspend = niu_suspend,
10010 .resume = niu_resume,
10011};
10012
10013#ifdef CONFIG_SPARC64
10014static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
10015 u64 *dma_addr, gfp_t flag)
10016{
10017 unsigned long order = get_order(size);
10018 unsigned long page = __get_free_pages(flag, order);
10019
10020 if (page == 0UL)
10021 return NULL;
10022 memset((char *)page, 0, PAGE_SIZE << order);
10023 *dma_addr = __pa(page);
10024
10025 return (void *) page;
10026}
10027
10028static void niu_phys_free_coherent(struct device *dev, size_t size,
10029 void *cpu_addr, u64 handle)
10030{
10031 unsigned long order = get_order(size);
10032
10033 free_pages((unsigned long) cpu_addr, order);
10034}
10035
10036static u64 niu_phys_map_page(struct device *dev, struct page *page,
10037 unsigned long offset, size_t size,
10038 enum dma_data_direction direction)
10039{
10040 return page_to_phys(page) + offset;
10041}
10042
10043static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10044 size_t size, enum dma_data_direction direction)
10045{
10046 /* Nothing to do. */
10047}
10048
10049static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10050 size_t size,
10051 enum dma_data_direction direction)
10052{
10053 return __pa(cpu_addr);
10054}
10055
10056static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10057 size_t size,
10058 enum dma_data_direction direction)
10059{
10060 /* Nothing to do. */
10061}
10062
10063static const struct niu_ops niu_phys_ops = {
10064 .alloc_coherent = niu_phys_alloc_coherent,
10065 .free_coherent = niu_phys_free_coherent,
10066 .map_page = niu_phys_map_page,
10067 .unmap_page = niu_phys_unmap_page,
10068 .map_single = niu_phys_map_single,
10069 .unmap_single = niu_phys_unmap_single,
10070};
10071
a3138df9
DM		 10072static int __devinit niu_of_probe(struct of_device *op,
10073 const struct of_device_id *match)
10074{
10075 union niu_parent_id parent_id;
10076 struct net_device *dev;
10077 struct niu *np;
10078 const u32 *reg;
10079 int err;
10080
10081 niu_driver_version();
10082
61c7a080 10083 reg = of_get_property(op->dev.of_node, "reg", NULL);
a3138df9 10084 if (!reg) {
f10a1f2e 10085 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
61c7a080 10086 op->dev.of_node->full_name);
a3138df9
DM		 10087 return -ENODEV;
10088 }
10089
10090 dev = niu_alloc_and_init(&op->dev, NULL, op,
10091 &niu_phys_ops, reg[0] & 0x1);
10092 if (!dev) {
10093 err = -ENOMEM;
10094 goto err_out;
10095 }
10096 np = netdev_priv(dev);
10097
10098 memset(&parent_id, 0, sizeof(parent_id));
61c7a080 10099 parent_id.of = of_get_parent(op->dev.of_node);
a3138df9
DM		 10100
10101 np->parent = niu_get_parent(np, &parent_id,
10102 PLAT_TYPE_NIU);
10103 if (!np->parent) {
10104 err = -ENOMEM;
10105 goto err_out_free_dev;
10106 }
10107
3cfa856d 10108 niu_set_basic_features(dev);
a3138df9
DM		 10109
10110 np->regs = of_ioremap(&op->resource[1], 0,
6f0e0135 10111 resource_size(&op->resource[1]),
a3138df9
DM		 10112 "niu regs");
10113 if (!np->regs) {
f10a1f2e 10114 dev_err(&op->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 10115 err = -ENOMEM;
10116 goto err_out_release_parent;
10117 }
10118
10119 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
6f0e0135 10120 resource_size(&op->resource[2]),
a3138df9
DM		 10121 "niu vregs-1");
10122 if (!np->vir_regs_1) {
f10a1f2e 10123 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
a3138df9
DM		 10124 err = -ENOMEM;
10125 goto err_out_iounmap;
10126 }
10127
10128 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
6f0e0135 10129 resource_size(&op->resource[3]),
a3138df9
DM		 10130 "niu vregs-2");
10131 if (!np->vir_regs_2) {
f10a1f2e 10132 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
a3138df9
DM		 10133 err = -ENOMEM;
10134 goto err_out_iounmap;
10135 }
10136
10137 niu_assign_netdev_ops(dev);
10138
10139 err = niu_get_invariants(np);
10140 if (err) {
10141 if (err != -ENODEV)
f10a1f2e 10142 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 10143 goto err_out_iounmap;
10144 }
10145
10146 err = register_netdev(dev);
10147 if (err) {
f10a1f2e 10148 dev_err(&op->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 10149 goto err_out_iounmap;
10150 }
10151
10152 dev_set_drvdata(&op->dev, dev);
10153
10154 niu_device_announce(np);
10155
10156 return 0;
10157
10158err_out_iounmap:
10159 if (np->vir_regs_1) {
10160 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10161 resource_size(&op->resource[2]));
a3138df9
DM		 10162 np->vir_regs_1 = NULL;
10163 }
10164
10165 if (np->vir_regs_2) {
10166 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10167 resource_size(&op->resource[3]));
a3138df9
DM		 10168 np->vir_regs_2 = NULL;
10169 }
10170
10171 if (np->regs) {
10172 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10173 resource_size(&op->resource[1]));
a3138df9
DM		 10174 np->regs = NULL;
10175 }
10176
10177err_out_release_parent:
10178 niu_put_parent(np);
10179
10180err_out_free_dev:
10181 free_netdev(dev);
10182
10183err_out:
10184 return err;
10185}
10186
10187static int __devexit niu_of_remove(struct of_device *op)
10188{
10189 struct net_device *dev = dev_get_drvdata(&op->dev);
10190
10191 if (dev) {
10192 struct niu *np = netdev_priv(dev);
10193
10194 unregister_netdev(dev);
10195
10196 if (np->vir_regs_1) {
10197 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10198 resource_size(&op->resource[2]));
a3138df9
DM		 10199 np->vir_regs_1 = NULL;
10200 }
10201
10202 if (np->vir_regs_2) {
10203 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10204 resource_size(&op->resource[3]));
a3138df9
DM		 10205 np->vir_regs_2 = NULL;
10206 }
10207
10208 if (np->regs) {
10209 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10210 resource_size(&op->resource[1]));
a3138df9
DM		 10211 np->regs = NULL;
10212 }
10213
10214 niu_ldg_free(np);
10215
10216 niu_put_parent(np);
10217
10218 free_netdev(dev);
10219 dev_set_drvdata(&op->dev, NULL);
10220 }
10221 return 0;
10222}
10223
fd098316 10224static const struct of_device_id niu_match[] = {
a3138df9
DM		 10225 {
10226 .name = "network",
10227 .compatible = "SUNW,niusl",
10228 },
10229 {},
10230};
10231MODULE_DEVICE_TABLE(of, niu_match);
10232
10233static struct of_platform_driver niu_of_driver = {
4018294b
GL		 10234 .driver = {
10235 .name = "niu",
10236 .owner = THIS_MODULE,
10237 .of_match_table = niu_match,
10238 },
a3138df9
DM		 10239 .probe = niu_of_probe,
10240 .remove = __devexit_p(niu_of_remove),
10241};
10242
10243#endif /* CONFIG_SPARC64 */
10244
10245static int __init niu_init(void)
10246{
10247 int err = 0;
10248
81429973 10249 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
a3138df9
DM		 10250
10251 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10252
10253#ifdef CONFIG_SPARC64
10254 err = of_register_driver(&niu_of_driver, &of_bus_type);
10255#endif
10256
10257 if (!err) {
10258 err = pci_register_driver(&niu_pci_driver);
10259#ifdef CONFIG_SPARC64
10260 if (err)
10261 of_unregister_driver(&niu_of_driver);
10262#endif
10263 }
10264
10265 return err;
10266}
10267
10268static void __exit niu_exit(void)
10269{
10270 pci_unregister_driver(&niu_pci_driver);
10271#ifdef CONFIG_SPARC64
10272 of_unregister_driver(&niu_of_driver);
10273#endif
10274}
10275
10276module_init(niu_init);
10277module_exit(niu_exit);
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