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[net-next-2.6.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
e3fd5534 4 * Copyright (C) 2005 - 2009 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
78ca90ea
JP		 41#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42
0da34b6d
BG		 43#include <linux/tcp.h>
44#include <linux/netdevice.h>
45#include <linux/skbuff.h>
46#include <linux/string.h>
47#include <linux/module.h>
48#include <linux/pci.h>
b10c0668 49#include <linux/dma-mapping.h>
0da34b6d
BG		 50#include <linux/etherdevice.h>
51#include <linux/if_ether.h>
52#include <linux/if_vlan.h>
1e6e9342 53#include <linux/inet_lro.h>
981813d8 54#include <linux/dca.h>
0da34b6d
BG		 55#include <linux/ip.h>
56#include <linux/inet.h>
57#include <linux/in.h>
58#include <linux/ethtool.h>
59#include <linux/firmware.h>
60#include <linux/delay.h>
0da34b6d
BG		 61#include <linux/timer.h>
62#include <linux/vmalloc.h>
63#include <linux/crc32.h>
64#include <linux/moduleparam.h>
65#include <linux/io.h>
199126a2 66#include <linux/log2.h>
0da34b6d 67#include <net/checksum.h>
1e6e9342
AG		 68#include <net/ip.h>
69#include <net/tcp.h>
0da34b6d
BG		 70#include <asm/byteorder.h>
71#include <asm/io.h>
0da34b6d
BG		 72#include <asm/processor.h>
73#ifdef CONFIG_MTRR
74#include <asm/mtrr.h>
75#endif
76
77#include "myri10ge_mcp.h"
78#include "myri10ge_mcp_gen_header.h"
79
2a3f2790 80#define MYRI10GE_VERSION_STR "1.5.2-1.459"
0da34b6d
BG		 81
82MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
83MODULE_AUTHOR("Maintainer: help@myri.com");
84MODULE_VERSION(MYRI10GE_VERSION_STR);
85MODULE_LICENSE("Dual BSD/GPL");
86
87#define MYRI10GE_MAX_ETHER_MTU 9014
88
89#define MYRI10GE_ETH_STOPPED 0
90#define MYRI10GE_ETH_STOPPING 1
91#define MYRI10GE_ETH_STARTING 2
92#define MYRI10GE_ETH_RUNNING 3
93#define MYRI10GE_ETH_OPEN_FAILED 4
94
95#define MYRI10GE_EEPROM_STRINGS_SIZE 256
96#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 97#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
98#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 99
40f6cff5 100#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 101#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
102
dd50f336
BG		 103#define MYRI10GE_ALLOC_ORDER 0
104#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
105#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
106
236bb5e6
BG		 107#define MYRI10GE_MAX_SLICES 32
108
0da34b6d 109struct myri10ge_rx_buffer_state {
dd50f336
BG		 110 struct page *page;
111 int page_offset;
0da34b6d
BG		 112 DECLARE_PCI_UNMAP_ADDR(bus)
113 DECLARE_PCI_UNMAP_LEN(len)
114};
115
116struct myri10ge_tx_buffer_state {
117 struct sk_buff *skb;
118 int last;
119 DECLARE_PCI_UNMAP_ADDR(bus)
120 DECLARE_PCI_UNMAP_LEN(len)
121};
122
123struct myri10ge_cmd {
124 u32 data0;
125 u32 data1;
126 u32 data2;
127};
128
129struct myri10ge_rx_buf {
130 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 131 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
132 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 133 struct page *page;
134 dma_addr_t bus;
135 int page_offset;
0da34b6d 136 int cnt;
dd50f336 137 int fill_cnt;
0da34b6d
BG		 138 int alloc_fail;
139 int mask; /* number of rx slots -1 */
dd50f336 140 int watchdog_needed;
0da34b6d
BG		 141};
142
143struct myri10ge_tx_buf {
144 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 145 __be32 __iomem *send_go; /* "go" doorbell ptr */
146 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 147 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
148 char *req_bytes;
149 struct myri10ge_tx_buffer_state *info;
150 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 151 int req ____cacheline_aligned; /* transmit slots submitted */
152 int pkt_start; /* packets started */
b53bef84
BG		 153 int stop_queue;
154 int linearized;
0da34b6d
BG		 155 int done ____cacheline_aligned; /* transmit slots completed */
156 int pkt_done; /* packets completed */
b53bef84 157 int wake_queue;
236bb5e6 158 int queue_active;
0da34b6d
BG		 159};
160
161struct myri10ge_rx_done {
162 struct mcp_slot *entry;
163 dma_addr_t bus;
164 int cnt;
165 int idx;
1e6e9342
AG		 166 struct net_lro_mgr lro_mgr;
167 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 168};
169
b53bef84
BG		 170struct myri10ge_slice_netstats {
171 unsigned long rx_packets;
172 unsigned long tx_packets;
173 unsigned long rx_bytes;
174 unsigned long tx_bytes;
175 unsigned long rx_dropped;
176 unsigned long tx_dropped;
177};
178
179struct myri10ge_slice_state {
0da34b6d
BG		 180 struct myri10ge_tx_buf tx; /* transmit ring */
181 struct myri10ge_rx_buf rx_small;
182 struct myri10ge_rx_buf rx_big;
183 struct myri10ge_rx_done rx_done;
b53bef84
BG		 184 struct net_device *dev;
185 struct napi_struct napi;
186 struct myri10ge_priv *mgp;
187 struct myri10ge_slice_netstats stats;
188 __be32 __iomem *irq_claim;
189 struct mcp_irq_data *fw_stats;
190 dma_addr_t fw_stats_bus;
191 int watchdog_tx_done;
192 int watchdog_tx_req;
d0234215 193 int watchdog_rx_done;
5dd2d332 194#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 195 int cached_dca_tag;
196 int cpu;
197 __be32 __iomem *dca_tag;
198#endif
0dcffac1 199 char irq_desc[32];
b53bef84
BG		 200};
201
202struct myri10ge_priv {
0dcffac1 203 struct myri10ge_slice_state *ss;
b53bef84 204 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 205 int num_slices;
b53bef84
BG		 206 int running; /* running? */
207 int csum_flag; /* rx_csums? */
0da34b6d 208 int small_bytes;
dd50f336 209 int big_bytes;
fa0a90d9 210 int max_intr_slots;
0da34b6d 211 struct net_device *dev;
b53bef84 212 spinlock_t stats_lock;
0da34b6d
BG		 213 u8 __iomem *sram;
214 int sram_size;
215 unsigned long board_span;
216 unsigned long iomem_base;
40f6cff5 217 __be32 __iomem *irq_deassert;
0da34b6d
BG		 218 char *mac_addr_string;
219 struct mcp_cmd_response *cmd;
220 dma_addr_t cmd_bus;
0da34b6d
BG		 221 struct pci_dev *pdev;
222 int msi_enabled;
0dcffac1
BG		 223 int msix_enabled;
224 struct msix_entry *msix_vectors;
5dd2d332 225#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 226 int dca_enabled;
227#endif
66341fff 228 u32 link_state;
0da34b6d
BG		 229 unsigned int rdma_tags_available;
230 int intr_coal_delay;
40f6cff5 231 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 232 int mtrr;
276e26c3 233 int wc_enabled;
0da34b6d
BG		 234 int down_cnt;
235 wait_queue_head_t down_wq;
236 struct work_struct watchdog_work;
237 struct timer_list watchdog_timer;
0da34b6d 238 int watchdog_resets;
b53bef84 239 int watchdog_pause;
0da34b6d
BG		 240 int pause;
241 char *fw_name;
242 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 243 char *product_code_string;
0da34b6d 244 char fw_version[128];
9dc6f0e7
BG		 245 int fw_ver_major;
246 int fw_ver_minor;
247 int fw_ver_tiny;
248 int adopted_rx_filter_bug;
0da34b6d
BG		 249 u8 mac_addr[6]; /* eeprom mac address */
250 unsigned long serial_number;
251 int vendor_specific_offset;
85a7ea1b 252 int fw_multicast_support;
4f93fde0
BG		 253 unsigned long features;
254 u32 max_tso6;
0da34b6d
BG		 255 u32 read_dma;
256 u32 write_dma;
257 u32 read_write_dma;
c58ac5ca
BG		 258 u32 link_changes;
259 u32 msg_enable;
2d90b0aa 260 unsigned int board_number;
d0234215 261 int rebooted;
0da34b6d
BG		 262};
263
264static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
265static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 266static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
267static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
b9721d5a
BH		 268MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
269MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
270MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
271MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
0da34b6d
BG		 272
273static char *myri10ge_fw_name = NULL;
274module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 275MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 276
2d90b0aa
BG		 277#define MYRI10GE_MAX_BOARDS 8
278static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 279 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 280module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
281 0444);
282MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
283
0da34b6d
BG		 284static int myri10ge_ecrc_enable = 1;
285module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 286MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 287
0da34b6d
BG		 288static int myri10ge_small_bytes = -1; /* -1 == auto */
289module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 290MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 291
292static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 293module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 294MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 295
f761fae1 296static int myri10ge_intr_coal_delay = 75;
0da34b6d 297module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 298MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 299
300static int myri10ge_flow_control = 1;
301module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 302MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 303
304static int myri10ge_deassert_wait = 1;
305module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
306MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 307 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 308
309static int myri10ge_force_firmware = 0;
310module_param(myri10ge_force_firmware, int, S_IRUGO);
311MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 312 "Force firmware to assume aligned completions");
0da34b6d 313
0da34b6d
BG		 314static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
315module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 316MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 317
318static int myri10ge_napi_weight = 64;
319module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 320MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 321
322static int myri10ge_watchdog_timeout = 1;
323module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 324MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 325
326static int myri10ge_max_irq_loops = 1048576;
327module_param(myri10ge_max_irq_loops, int, S_IRUGO);
328MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 329 "Set stuck legacy IRQ detection threshold");
0da34b6d 330
c58ac5ca
BG		 331#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
332
333static int myri10ge_debug = -1; /* defaults above */
334module_param(myri10ge_debug, int, 0);
335MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
336
1e6e9342
AG		 337static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
338module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 339MODULE_PARM_DESC(myri10ge_lro_max_pkts,
340 "Number of LRO packets to be aggregated");
1e6e9342 341
dd50f336
BG		 342static int myri10ge_fill_thresh = 256;
343module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 344MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 345
f181137f
BG		 346static int myri10ge_reset_recover = 1;
347
0dcffac1
BG		 348static int myri10ge_max_slices = 1;
349module_param(myri10ge_max_slices, int, S_IRUGO);
350MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
351
4b860abf 352static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
0dcffac1
BG		 353module_param(myri10ge_rss_hash, int, S_IRUGO);
354MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
355
981813d8
BG		 356static int myri10ge_dca = 1;
357module_param(myri10ge_dca, int, S_IRUGO);
358MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
359
0da34b6d
BG		 360#define MYRI10GE_FW_OFFSET 1024*1024
361#define MYRI10GE_HIGHPART_TO_U32(X) \
362(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
363#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
364
365#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
366
2f76216f 367static void myri10ge_set_multicast_list(struct net_device *dev);
61357325
SH		 368static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
369 struct net_device *dev);
2f76216f 370
6250223e 371static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 372{
6250223e 373 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 374}
375
59081825
BG		 376static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
377
0da34b6d
BG		 378static int
379myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
380 struct myri10ge_cmd *data, int atomic)
381{
382 struct mcp_cmd *buf;
383 char buf_bytes[sizeof(*buf) + 8];
384 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 385 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 386 u32 dma_low, dma_high, result, value;
387 int sleep_total = 0;
388
389 /* ensure buf is aligned to 8 bytes */
390 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
391
392 buf->data0 = htonl(data->data0);
393 buf->data1 = htonl(data->data1);
394 buf->data2 = htonl(data->data2);
395 buf->cmd = htonl(cmd);
396 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
397 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
398
399 buf->response_addr.low = htonl(dma_low);
400 buf->response_addr.high = htonl(dma_high);
40f6cff5 401 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 402 mb();
403 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
404
405 /* wait up to 15ms. Longest command is the DMA benchmark,
406 * which is capped at 5ms, but runs from a timeout handler
407 * that runs every 7.8ms. So a 15ms timeout leaves us with
408 * a 2.2ms margin
409 */
410 if (atomic) {
411 /* if atomic is set, do not sleep,
412 * and try to get the completion quickly
413 * (1ms will be enough for those commands) */
414 for (sleep_total = 0;
8e95a202
JP		 415 sleep_total < 1000 &&
416 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 417 sleep_total += 10) {
0da34b6d 418 udelay(10);
bd2db0cf
BG		 419 mb();
420 }
0da34b6d
BG		 421 } else {
422 /* use msleep for most command */
423 for (sleep_total = 0;
8e95a202
JP		 424 sleep_total < 15 &&
425 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 426 sleep_total++)
427 msleep(1);
428 }
429
430 result = ntohl(response->result);
431 value = ntohl(response->data);
432 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
433 if (result == 0) {
434 data->data0 = value;
435 return 0;
85a7ea1b
BG		 436 } else if (result == MXGEFW_CMD_UNKNOWN) {
437 return -ENOSYS;
5443e9ea
BG		 438 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
439 return -E2BIG;
236bb5e6
BG		 440 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
441 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
442 (data->
443 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
444 0) {
445 return -ERANGE;
0da34b6d
BG		 446 } else {
447 dev_err(&mgp->pdev->dev,
448 "command %d failed, result = %d\n",
449 cmd, result);
450 return -ENXIO;
451 }
452 }
453
454 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
455 cmd, result);
456 return -EAGAIN;
457}
458
459/*
460 * The eeprom strings on the lanaiX have the format
461 * SN=x\0
462 * MAC=x:x:x:x:x:x\0
463 * PT:ddd mmm xx xx:xx:xx xx\0
464 * PV:ddd mmm xx xx:xx:xx xx\0
465 */
466static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
467{
468 char *ptr, *limit;
469 int i;
470
471 ptr = mgp->eeprom_strings;
472 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
473
474 while (*ptr != '\0' && ptr < limit) {
475 if (memcmp(ptr, "MAC=", 4) == 0) {
476 ptr += 4;
477 mgp->mac_addr_string = ptr;
478 for (i = 0; i < 6; i++) {
479 if ((ptr + 2) > limit)
480 goto abort;
481 mgp->mac_addr[i] =
482 simple_strtoul(ptr, &ptr, 16);
483 ptr += 1;
484 }
485 }
c0bf8801
BG		 486 if (memcmp(ptr, "PC=", 3) == 0) {
487 ptr += 3;
488 mgp->product_code_string = ptr;
489 }
0da34b6d
BG		 490 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
491 ptr += 3;
492 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
493 }
494 while (ptr < limit && *ptr++) ;
495 }
496
497 return 0;
498
499abort:
500 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
501 return -ENXIO;
502}
503
504/*
505 * Enable or disable periodic RDMAs from the host to make certain
506 * chipsets resend dropped PCIe messages
507 */
508
509static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
510{
511 char __iomem *submit;
f8fd57c1 512 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 513 u32 dma_low, dma_high;
514 int i;
515
516 /* clear confirmation addr */
517 mgp->cmd->data = 0;
518 mb();
519
520 /* send a rdma command to the PCIe engine, and wait for the
521 * response in the confirmation address. The firmware should
522 * write a -1 there to indicate it is alive and well
523 */
524 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
525 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
526
527 buf[0] = htonl(dma_high); /* confirm addr MSW */
528 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 529 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 530 buf[3] = htonl(dma_high); /* dummy addr MSW */
531 buf[4] = htonl(dma_low); /* dummy addr LSW */
532 buf[5] = htonl(enable); /* enable? */
533
e700f9f4 534 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 535
536 myri10ge_pio_copy(submit, &buf, sizeof(buf));
537 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
538 msleep(1);
539 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
540 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
541 (enable ? "enable" : "disable"));
542}
543
544static int
545myri10ge_validate_firmware(struct myri10ge_priv *mgp,
546 struct mcp_gen_header *hdr)
547{
548 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 549
550 /* check firmware type */
551 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
552 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
553 return -EINVAL;
554 }
555
556 /* save firmware version for ethtool */
557 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
558
9dc6f0e7
BG		 559 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
560 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 561
8e95a202
JP		 562 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
563 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 564 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
565 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
566 MXGEFW_VERSION_MINOR);
567 return -EINVAL;
568 }
569 return 0;
570}
571
572static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
573{
574 unsigned crc, reread_crc;
575 const struct firmware *fw;
576 struct device *dev = &mgp->pdev->dev;
b0d31d6b 577 unsigned char *fw_readback;
0da34b6d
BG		 578 struct mcp_gen_header *hdr;
579 size_t hdr_offset;
580 int status;
e454358a 581 unsigned i;
0da34b6d
BG		 582
583 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
584 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
585 mgp->fw_name);
586 status = -EINVAL;
587 goto abort_with_nothing;
588 }
589
590 /* check size */
591
592 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
593 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
594 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
595 status = -EINVAL;
596 goto abort_with_fw;
597 }
598
599 /* check id */
40f6cff5 600 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 601 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
602 dev_err(dev, "Bad firmware file\n");
603 status = -EINVAL;
604 goto abort_with_fw;
605 }
606 hdr = (void *)(fw->data + hdr_offset);
607
608 status = myri10ge_validate_firmware(mgp, hdr);
609 if (status != 0)
610 goto abort_with_fw;
611
612 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 613 for (i = 0; i < fw->size; i += 256) {
614 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
615 fw->data + i,
616 min(256U, (unsigned)(fw->size - i)));
617 mb();
618 readb(mgp->sram);
b10c0668 619 }
b0d31d6b
DW		 620 fw_readback = vmalloc(fw->size);
621 if (!fw_readback) {
622 status = -ENOMEM;
623 goto abort_with_fw;
624 }
0da34b6d 625 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 626 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
627 reread_crc = crc32(~0, fw_readback, fw->size);
628 vfree(fw_readback);
0da34b6d
BG		 629 if (crc != reread_crc) {
630 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
631 (unsigned)fw->size, reread_crc, crc);
632 status = -EIO;
633 goto abort_with_fw;
634 }
635 *size = (u32) fw->size;
636
637abort_with_fw:
638 release_firmware(fw);
639
640abort_with_nothing:
641 return status;
642}
643
644static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
645{
646 struct mcp_gen_header *hdr;
647 struct device *dev = &mgp->pdev->dev;
648 const size_t bytes = sizeof(struct mcp_gen_header);
649 size_t hdr_offset;
650 int status;
651
652 /* find running firmware header */
66341fff 653 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 654
655 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
656 dev_err(dev, "Running firmware has bad header offset (%d)\n",
657 (int)hdr_offset);
658 return -EIO;
659 }
660
661 /* copy header of running firmware from SRAM to host memory to
662 * validate firmware */
663 hdr = kmalloc(bytes, GFP_KERNEL);
664 if (hdr == NULL) {
665 dev_err(dev, "could not malloc firmware hdr\n");
666 return -ENOMEM;
667 }
668 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
669 status = myri10ge_validate_firmware(mgp, hdr);
670 kfree(hdr);
9dc6f0e7
BG		 671
672 /* check to see if adopted firmware has bug where adopting
673 * it will cause broadcasts to be filtered unless the NIC
674 * is kept in ALLMULTI mode */
675 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
676 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
677 mgp->adopted_rx_filter_bug = 1;
678 dev_warn(dev, "Adopting fw %d.%d.%d: "
679 "working around rx filter bug\n",
680 mgp->fw_ver_major, mgp->fw_ver_minor,
681 mgp->fw_ver_tiny);
682 }
0da34b6d
BG		 683 return status;
684}
685
0178ec3d 686static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 687{
688 struct myri10ge_cmd cmd;
689 int status;
690
691 /* probe for IPv6 TSO support */
692 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
693 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
694 &cmd, 0);
695 if (status == 0) {
696 mgp->max_tso6 = cmd.data0;
697 mgp->features |= NETIF_F_TSO6;
698 }
699
700 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
701 if (status != 0) {
702 dev_err(&mgp->pdev->dev,
703 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
704 return -ENXIO;
705 }
706
707 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
708
709 return 0;
710}
711
0dcffac1 712static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 713{
714 char __iomem *submit;
f8fd57c1 715 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 716 u32 dma_low, dma_high, size;
717 int status, i;
718
b10c0668 719 size = 0;
0da34b6d
BG		 720 status = myri10ge_load_hotplug_firmware(mgp, &size);
721 if (status) {
0dcffac1
BG		 722 if (!adopt)
723 return status;
0da34b6d
BG		 724 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
725
726 /* Do not attempt to adopt firmware if there
727 * was a bad crc */
728 if (status == -EIO)
729 return status;
730
731 status = myri10ge_adopt_running_firmware(mgp);
732 if (status != 0) {
733 dev_err(&mgp->pdev->dev,
734 "failed to adopt running firmware\n");
735 return status;
736 }
737 dev_info(&mgp->pdev->dev,
738 "Successfully adopted running firmware\n");
b53bef84 739 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 740 dev_warn(&mgp->pdev->dev,
741 "Using firmware currently running on NIC"
742 ". For optimal\n");
743 dev_warn(&mgp->pdev->dev,
744 "performance consider loading optimized "
745 "firmware\n");
746 dev_warn(&mgp->pdev->dev, "via hotplug\n");
747 }
748
749 mgp->fw_name = "adopted";
b53bef84 750 mgp->tx_boundary = 2048;
fa0a90d9
BG		 751 myri10ge_dummy_rdma(mgp, 1);
752 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 753 return status;
754 }
755
756 /* clear confirmation addr */
757 mgp->cmd->data = 0;
758 mb();
759
760 /* send a reload command to the bootstrap MCP, and wait for the
761 * response in the confirmation address. The firmware should
762 * write a -1 there to indicate it is alive and well
763 */
764 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
765 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
766
767 buf[0] = htonl(dma_high); /* confirm addr MSW */
768 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 769 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 770
771 /* FIX: All newest firmware should un-protect the bottom of
772 * the sram before handoff. However, the very first interfaces
773 * do not. Therefore the handoff copy must skip the first 8 bytes
774 */
775 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
776 buf[4] = htonl(size - 8); /* length of code */
777 buf[5] = htonl(8); /* where to copy to */
778 buf[6] = htonl(0); /* where to jump to */
779
e700f9f4 780 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 781
782 myri10ge_pio_copy(submit, &buf, sizeof(buf));
783 mb();
784 msleep(1);
785 mb();
786 i = 0;
d93ca2a4
BG		 787 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
788 msleep(1 << i);
0da34b6d
BG		 789 i++;
790 }
791 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
792 dev_err(&mgp->pdev->dev, "handoff failed\n");
793 return -ENXIO;
794 }
9a71db72 795 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 796 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 797
fa0a90d9 798 return status;
0da34b6d
BG		 799}
800
801static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
802{
803 struct myri10ge_cmd cmd;
804 int status;
805
806 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
807 | (addr[2] << 8) | addr[3]);
808
809 cmd.data1 = ((addr[4] << 8) | (addr[5]));
810
811 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
812 return status;
813}
814
815static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
816{
817 struct myri10ge_cmd cmd;
818 int status, ctl;
819
820 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
821 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
822
823 if (status) {
78ca90ea 824 netdev_err(mgp->dev, "Failed to set flow control mode\n");
0da34b6d
BG		 825 return status;
826 }
827 mgp->pause = pause;
828 return 0;
829}
830
831static void
832myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
833{
834 struct myri10ge_cmd cmd;
835 int status, ctl;
836
837 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
838 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
839 if (status)
78ca90ea 840 netdev_err(mgp->dev, "Failed to set promisc mode\n");
0da34b6d
BG		 841}
842
0d6ac257 843static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 844{
845 struct myri10ge_cmd cmd;
846 int status;
0da34b6d 847 u32 len;
34fdccea
BG		 848 struct page *dmatest_page;
849 dma_addr_t dmatest_bus;
0d6ac257
BG		 850 char *test = " ";
851
852 dmatest_page = alloc_page(GFP_KERNEL);
853 if (!dmatest_page)
854 return -ENOMEM;
855 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
856 DMA_BIDIRECTIONAL);
857
858 /* Run a small DMA test.
859 * The magic multipliers to the length tell the firmware
860 * to do DMA read, write, or read+write tests. The
861 * results are returned in cmd.data0. The upper 16
862 * bits or the return is the number of transfers completed.
863 * The lower 16 bits is the time in 0.5us ticks that the
864 * transfers took to complete.
865 */
866
b53bef84 867 len = mgp->tx_boundary;
0d6ac257
BG		 868
869 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
870 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
871 cmd.data2 = len * 0x10000;
872 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
873 if (status != 0) {
874 test = "read";
875 goto abort;
876 }
877 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
878 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
879 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
880 cmd.data2 = len * 0x1;
881 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
882 if (status != 0) {
883 test = "write";
884 goto abort;
885 }
886 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
887
888 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
889 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
890 cmd.data2 = len * 0x10001;
891 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
892 if (status != 0) {
893 test = "read/write";
894 goto abort;
895 }
896 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
897 (cmd.data0 & 0xffff);
898
899abort:
900 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
901 put_page(dmatest_page);
902
903 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
904 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
905 test, status);
906
907 return status;
908}
909
910static int myri10ge_reset(struct myri10ge_priv *mgp)
911{
912 struct myri10ge_cmd cmd;
0dcffac1
BG		 913 struct myri10ge_slice_state *ss;
914 int i, status;
0d6ac257 915 size_t bytes;
5dd2d332 916#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 917 unsigned long dca_tag_off;
918#endif
0da34b6d
BG		 919
920 /* try to send a reset command to the card to see if it
921 * is alive */
922 memset(&cmd, 0, sizeof(cmd));
923 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
924 if (status != 0) {
925 dev_err(&mgp->pdev->dev, "failed reset\n");
926 return -ENXIO;
927 }
0d6ac257
BG		 928
929 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 930 /*
931 * Use non-ndis mcp_slot (eg, 4 bytes total,
932 * no toeplitz hash value returned. Older firmware will
933 * not understand this command, but will use the correct
934 * sized mcp_slot, so we ignore error returns
935 */
936 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
937 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 938
939 /* Now exchange information about interrupts */
940
0dcffac1 941 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 942 cmd.data0 = (u32) bytes;
943 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 944
945 /*
946 * Even though we already know how many slices are supported
947 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
948 * has magic side effects, and must be called after a reset.
949 * It must be called prior to calling any RSS related cmds,
950 * including assigning an interrupt queue for anything but
951 * slice 0. It must also be called *after*
952 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
953 * the firmware to compute offsets.
954 */
955
956 if (mgp->num_slices > 1) {
957
958 /* ask the maximum number of slices it supports */
959 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
960 &cmd, 0);
961 if (status != 0) {
962 dev_err(&mgp->pdev->dev,
963 "failed to get number of slices\n");
964 }
965
966 /*
967 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
968 * to setting up the interrupt queue DMA
969 */
970
971 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 972 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
973 if (mgp->dev->real_num_tx_queues > 1)
974 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 975 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
976 &cmd, 0);
236bb5e6
BG		 977
978 /* Firmware older than 1.4.32 only supports multiple
979 * RX queues, so if we get an error, first retry using a
980 * single TX queue before giving up */
981 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
982 mgp->dev->real_num_tx_queues = 1;
983 cmd.data0 = mgp->num_slices;
984 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
985 status = myri10ge_send_cmd(mgp,
986 MXGEFW_CMD_ENABLE_RSS_QUEUES,
987 &cmd, 0);
988 }
989
0dcffac1
BG		 990 if (status != 0) {
991 dev_err(&mgp->pdev->dev,
992 "failed to set number of slices\n");
993
994 return status;
995 }
996 }
997 for (i = 0; i < mgp->num_slices; i++) {
998 ss = &mgp->ss[i];
999 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1000 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1001 cmd.data2 = i;
1002 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1003 &cmd, 0);
1004 };
0da34b6d
BG		 1005
1006 status |=
1007 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1008 for (i = 0; i < mgp->num_slices; i++) {
1009 ss = &mgp->ss[i];
1010 ss->irq_claim =
1011 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1012 }
df30a740
BG		 1013 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1014 &cmd, 0);
1015 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1016
0da34b6d
BG		 1017 status |= myri10ge_send_cmd
1018 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1019 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1020 if (status != 0) {
1021 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1022 return status;
1023 }
40f6cff5 1024 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1025
5dd2d332 1026#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1027 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1028 dca_tag_off = cmd.data0;
1029 for (i = 0; i < mgp->num_slices; i++) {
1030 ss = &mgp->ss[i];
1031 if (status == 0) {
1032 ss->dca_tag = (__iomem __be32 *)
1033 (mgp->sram + dca_tag_off + 4 * i);
1034 } else {
1035 ss->dca_tag = NULL;
1036 }
1037 }
4ee2ac51 1038#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1039
0da34b6d 1040 /* reset mcp/driver shared state back to 0 */
0dcffac1 1041
c58ac5ca 1042 mgp->link_changes = 0;
0dcffac1
BG		 1043 for (i = 0; i < mgp->num_slices; i++) {
1044 ss = &mgp->ss[i];
1045
1046 memset(ss->rx_done.entry, 0, bytes);
1047 ss->tx.req = 0;
1048 ss->tx.done = 0;
1049 ss->tx.pkt_start = 0;
1050 ss->tx.pkt_done = 0;
1051 ss->rx_big.cnt = 0;
1052 ss->rx_small.cnt = 0;
1053 ss->rx_done.idx = 0;
1054 ss->rx_done.cnt = 0;
1055 ss->tx.wake_queue = 0;
1056 ss->tx.stop_queue = 0;
1057 }
1058
0da34b6d 1059 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1060 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1061 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1062 return status;
1063}
1064
5dd2d332 1065#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1066static void
1067myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1068{
1069 ss->cpu = cpu;
1070 ss->cached_dca_tag = tag;
1071 put_be32(htonl(tag), ss->dca_tag);
1072}
1073
1074static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1075{
1076 int cpu = get_cpu();
1077 int tag;
1078
1079 if (cpu != ss->cpu) {
1080 tag = dca_get_tag(cpu);
1081 if (ss->cached_dca_tag != tag)
1082 myri10ge_write_dca(ss, cpu, tag);
1083 }
1084 put_cpu();
1085}
1086
1087static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1088{
1089 int err, i;
1090 struct pci_dev *pdev = mgp->pdev;
1091
1092 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1093 return;
1094 if (!myri10ge_dca) {
1095 dev_err(&pdev->dev, "dca disabled by administrator\n");
1096 return;
1097 }
1098 err = dca_add_requester(&pdev->dev);
1099 if (err) {
330554cb
BG		 1100 if (err != -ENODEV)
1101 dev_err(&pdev->dev,
1102 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1103 return;
1104 }
1105 mgp->dca_enabled = 1;
1106 for (i = 0; i < mgp->num_slices; i++)
1107 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1108}
1109
1110static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1111{
1112 struct pci_dev *pdev = mgp->pdev;
1113 int err;
1114
1115 if (!mgp->dca_enabled)
1116 return;
1117 mgp->dca_enabled = 0;
1118 err = dca_remove_requester(&pdev->dev);
1119}
1120
1121static int myri10ge_notify_dca_device(struct device *dev, void *data)
1122{
1123 struct myri10ge_priv *mgp;
1124 unsigned long event;
1125
1126 mgp = dev_get_drvdata(dev);
1127 event = *(unsigned long *)data;
1128
1129 if (event == DCA_PROVIDER_ADD)
1130 myri10ge_setup_dca(mgp);
1131 else if (event == DCA_PROVIDER_REMOVE)
1132 myri10ge_teardown_dca(mgp);
1133 return 0;
1134}
4ee2ac51 1135#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1136
0da34b6d
BG		 1137static inline void
1138myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1139 struct mcp_kreq_ether_recv *src)
1140{
40f6cff5 1141 __be32 low;
0da34b6d
BG		 1142
1143 low = src->addr_low;
284901a9 1144 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1145 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1146 mb();
1147 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1148 mb();
1149 src->addr_low = low;
40f6cff5 1150 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1151 mb();
1152}
1153
40f6cff5 1154static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1155{
1156 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1157
40f6cff5 1158 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1159 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1160 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1161 skb->csum = hw_csum;
84fa7933 1162 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1163 }
1164}
1165
dd50f336
BG		 1166static inline void
1167myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1168 struct skb_frag_struct *rx_frags, int len, int hlen)
1169{
1170 struct skb_frag_struct *skb_frags;
1171
1172 skb->len = skb->data_len = len;
1173 skb->truesize = len + sizeof(struct sk_buff);
1174 /* attach the page(s) */
1175
1176 skb_frags = skb_shinfo(skb)->frags;
1177 while (len > 0) {
1178 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1179 len -= rx_frags->size;
1180 skb_frags++;
1181 rx_frags++;
1182 skb_shinfo(skb)->nr_frags++;
1183 }
1184
1185 /* pskb_may_pull is not available in irq context, but
1186 * skb_pull() (for ether_pad and eth_type_trans()) requires
1187 * the beginning of the packet in skb_headlen(), move it
1188 * manually */
27d7ff46 1189 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 1190 skb_shinfo(skb)->frags[0].page_offset += hlen;
1191 skb_shinfo(skb)->frags[0].size -= hlen;
1192 skb->data_len -= hlen;
1193 skb->tail += hlen;
1194 skb_pull(skb, MXGEFW_PAD);
1195}
1196
1197static void
1198myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1199 int bytes, int watchdog)
1200{
1201 struct page *page;
1202 int idx;
2a3f2790
BG		 1203#if MYRI10GE_ALLOC_SIZE > 4096
1204 int end_offset;
1205#endif
dd50f336
BG		 1206
1207 if (unlikely(rx->watchdog_needed && !watchdog))
1208 return;
1209
1210 /* try to refill entire ring */
1211 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1212 idx = rx->fill_cnt & rx->mask;
ae8509b1 1213 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1214 /* we can use part of previous page */
1215 get_page(rx->page);
1216 } else {
1217 /* we need a new page */
1218 page =
1219 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1220 MYRI10GE_ALLOC_ORDER);
1221 if (unlikely(page == NULL)) {
1222 if (rx->fill_cnt - rx->cnt < 16)
1223 rx->watchdog_needed = 1;
1224 return;
1225 }
1226 rx->page = page;
1227 rx->page_offset = 0;
1228 rx->bus = pci_map_page(mgp->pdev, page, 0,
1229 MYRI10GE_ALLOC_SIZE,
1230 PCI_DMA_FROMDEVICE);
1231 }
1232 rx->info[idx].page = rx->page;
1233 rx->info[idx].page_offset = rx->page_offset;
1234 /* note that this is the address of the start of the
1235 * page */
1236 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1237 rx->shadow[idx].addr_low =
1238 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1239 rx->shadow[idx].addr_high =
1240 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1241
1242 /* start next packet on a cacheline boundary */
1243 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1244
1245#if MYRI10GE_ALLOC_SIZE > 4096
1246 /* don't cross a 4KB boundary */
2a3f2790
BG		 1247 end_offset = rx->page_offset + bytes - 1;
1248 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1249 rx->page_offset = end_offset & ~4095;
ae8509b1 1250#endif
dd50f336
BG		 1251 rx->fill_cnt++;
1252
1253 /* copy 8 descriptors to the firmware at a time */
1254 if ((idx & 7) == 7) {
e454e7e2
BG		 1255 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1256 &rx->shadow[idx - 7]);
dd50f336
BG		 1257 }
1258 }
1259}
1260
1261static inline void
1262myri10ge_unmap_rx_page(struct pci_dev *pdev,
1263 struct myri10ge_rx_buffer_state *info, int bytes)
1264{
1265 /* unmap the recvd page if we're the only or last user of it */
1266 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1267 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1268 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1269 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1270 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1271 }
1272}
1273
1274#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1275 * page into an skb */
1276
1277static inline int
b53bef84 1278myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
52ea6fb3 1279 int bytes, int len, __wsum csum)
dd50f336 1280{
b53bef84 1281 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1282 struct sk_buff *skb;
1283 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1284 int i, idx, hlen, remainder;
1285 struct pci_dev *pdev = mgp->pdev;
1286 struct net_device *dev = mgp->dev;
1287 u8 *va;
1288
1289 len += MXGEFW_PAD;
1290 idx = rx->cnt & rx->mask;
1291 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1292 prefetch(va);
1293 /* Fill skb_frag_struct(s) with data from our receive */
1294 for (i = 0, remainder = len; remainder > 0; i++) {
1295 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1296 rx_frags[i].page = rx->info[idx].page;
1297 rx_frags[i].page_offset = rx->info[idx].page_offset;
1298 if (remainder < MYRI10GE_ALLOC_SIZE)
1299 rx_frags[i].size = remainder;
1300 else
1301 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1302 rx->cnt++;
1303 idx = rx->cnt & rx->mask;
1304 remainder -= MYRI10GE_ALLOC_SIZE;
1305 }
1306
3a0c7d2d 1307 if (dev->features & NETIF_F_LRO) {
1e6e9342
AG		 1308 rx_frags[0].page_offset += MXGEFW_PAD;
1309 rx_frags[0].size -= MXGEFW_PAD;
1310 len -= MXGEFW_PAD;
b53bef84 1311 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
b53bef84 1312 /* opaque, will come back in get_frag_header */
0dcffac1 1313 len, len,
b53bef84 1314 (void *)(__force unsigned long)csum, csum);
0dcffac1 1315
1e6e9342
AG		 1316 return 1;
1317 }
1318
dd50f336
BG		 1319 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1320
e636b2ea
BG		 1321 /* allocate an skb to attach the page(s) to. This is done
1322 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1323
1324 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1325 if (unlikely(skb == NULL)) {
d6279c88 1326 ss->stats.rx_dropped++;
dd50f336
BG		 1327 do {
1328 i--;
1329 put_page(rx_frags[i].page);
1330 } while (i != 0);
1331 return 0;
1332 }
1333
1334 /* Attach the pages to the skb, and trim off any padding */
1335 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1336 if (skb_shinfo(skb)->frags[0].size <= 0) {
1337 put_page(skb_shinfo(skb)->frags[0].page);
1338 skb_shinfo(skb)->nr_frags = 0;
1339 }
1340 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 1341 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
dd50f336
BG		 1342
1343 if (mgp->csum_flag) {
1344 if ((skb->protocol == htons(ETH_P_IP)) ||
1345 (skb->protocol == htons(ETH_P_IPV6))) {
1346 skb->csum = csum;
1347 skb->ip_summed = CHECKSUM_COMPLETE;
1348 } else
1349 myri10ge_vlan_ip_csum(skb, csum);
1350 }
1351 netif_receive_skb(skb);
dd50f336
BG		 1352 return 1;
1353}
1354
b53bef84
BG		 1355static inline void
1356myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1357{
b53bef84
BG		 1358 struct pci_dev *pdev = ss->mgp->pdev;
1359 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1360 struct netdev_queue *dev_queue;
0da34b6d
BG		 1361 struct sk_buff *skb;
1362 int idx, len;
0da34b6d
BG		 1363
1364 while (tx->pkt_done != mcp_index) {
1365 idx = tx->done & tx->mask;
1366 skb = tx->info[idx].skb;
1367
1368 /* Mark as free */
1369 tx->info[idx].skb = NULL;
1370 if (tx->info[idx].last) {
1371 tx->pkt_done++;
1372 tx->info[idx].last = 0;
1373 }
1374 tx->done++;
1375 len = pci_unmap_len(&tx->info[idx], len);
1376 pci_unmap_len_set(&tx->info[idx], len, 0);
1377 if (skb) {
b53bef84
BG		 1378 ss->stats.tx_bytes += skb->len;
1379 ss->stats.tx_packets++;
0da34b6d
BG		 1380 dev_kfree_skb_irq(skb);
1381 if (len)
1382 pci_unmap_single(pdev,
1383 pci_unmap_addr(&tx->info[idx],
1384 bus), len,
1385 PCI_DMA_TODEVICE);
1386 } else {
1387 if (len)
1388 pci_unmap_page(pdev,
1389 pci_unmap_addr(&tx->info[idx],
1390 bus), len,
1391 PCI_DMA_TODEVICE);
1392 }
0da34b6d 1393 }
236bb5e6
BG		 1394
1395 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1396 /*
1397 * Make a minimal effort to prevent the NIC from polling an
1398 * idle tx queue. If we can't get the lock we leave the queue
1399 * active. In this case, either a thread was about to start
1400 * using the queue anyway, or we lost a race and the NIC will
1401 * waste some of its resources polling an inactive queue for a
1402 * while.
1403 */
1404
1405 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1406 __netif_tx_trylock(dev_queue)) {
1407 if (tx->req == tx->done) {
1408 tx->queue_active = 0;
1409 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1410 mb();
6824a105 1411 mmiowb();
236bb5e6
BG		 1412 }
1413 __netif_tx_unlock(dev_queue);
1414 }
1415
0da34b6d 1416 /* start the queue if we've stopped it */
8e95a202
JP		 1417 if (netif_tx_queue_stopped(dev_queue) &&
1418 tx->req - tx->done < (tx->mask >> 1)) {
b53bef84 1419 tx->wake_queue++;
236bb5e6 1420 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1421 }
1422}
1423
b53bef84
BG		 1424static inline int
1425myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1426{
b53bef84
BG		 1427 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1428 struct myri10ge_priv *mgp = ss->mgp;
18af3e7c 1429 struct net_device *netdev = mgp->dev;
0da34b6d
BG		 1430 unsigned long rx_bytes = 0;
1431 unsigned long rx_packets = 0;
1432 unsigned long rx_ok;
1433
1434 int idx = rx_done->idx;
1435 int cnt = rx_done->cnt;
bea3348e 1436 int work_done = 0;
0da34b6d 1437 u16 length;
40f6cff5 1438 __wsum checksum;
0da34b6d 1439
c956a240 1440 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1441 length = ntohs(rx_done->entry[idx].length);
1442 rx_done->entry[idx].length = 0;
40f6cff5 1443 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1444 if (length <= mgp->small_bytes)
b53bef84 1445 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
52ea6fb3
BG		 1446 mgp->small_bytes,
1447 length, checksum);
0da34b6d 1448 else
b53bef84 1449 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
52ea6fb3
BG		 1450 mgp->big_bytes,
1451 length, checksum);
0da34b6d
BG		 1452 rx_packets += rx_ok;
1453 rx_bytes += rx_ok * (unsigned long)length;
1454 cnt++;
014377a1 1455 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1456 work_done++;
0da34b6d
BG		 1457 }
1458 rx_done->idx = idx;
1459 rx_done->cnt = cnt;
b53bef84
BG		 1460 ss->stats.rx_packets += rx_packets;
1461 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1462
18af3e7c 1463 if (netdev->features & NETIF_F_LRO)
1e6e9342
AG		 1464 lro_flush_all(&rx_done->lro_mgr);
1465
c7dab99b 1466 /* restock receive rings if needed */
b53bef84
BG		 1467 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1468 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1469 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1470 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1471 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1472
bea3348e 1473 return work_done;
0da34b6d
BG		 1474}
1475
1476static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1477{
0dcffac1 1478 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1479
1480 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1481 unsigned link_up = ntohl(stats->link_up);
1482 if (mgp->link_state != link_up) {
1483 mgp->link_state = link_up;
1484
1485 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca 1486 if (netif_msg_link(mgp))
78ca90ea 1487 netdev_info(mgp->dev, "link up\n");
0da34b6d 1488 netif_carrier_on(mgp->dev);
c58ac5ca 1489 mgp->link_changes++;
0da34b6d 1490 } else {
c58ac5ca 1491 if (netif_msg_link(mgp))
78ca90ea
JP		 1492 netdev_info(mgp->dev, "link %s\n",
1493 link_up == MXGEFW_LINK_MYRINET ?
1494 "mismatch (Myrinet detected)" :
1495 "down");
0da34b6d 1496 netif_carrier_off(mgp->dev);
c58ac5ca 1497 mgp->link_changes++;
0da34b6d
BG		 1498 }
1499 }
1500 if (mgp->rdma_tags_available !=
b53bef84 1501 ntohl(stats->rdma_tags_available)) {
0da34b6d 1502 mgp->rdma_tags_available =
b53bef84 1503 ntohl(stats->rdma_tags_available);
78ca90ea
JP		 1504 netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1505 mgp->rdma_tags_available);
0da34b6d
BG		 1506 }
1507 mgp->down_cnt += stats->link_down;
1508 if (stats->link_down)
1509 wake_up(&mgp->down_wq);
1510 }
1511}
1512
bea3348e 1513static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1514{
b53bef84
BG		 1515 struct myri10ge_slice_state *ss =
1516 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1517 int work_done;
0da34b6d 1518
5dd2d332 1519#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1520 if (ss->mgp->dca_enabled)
1521 myri10ge_update_dca(ss);
1522#endif
1523
0da34b6d 1524 /* process as many rx events as NAPI will allow */
b53bef84 1525 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1526
4ec24119 1527 if (work_done < budget) {
288379f0 1528 napi_complete(napi);
b53bef84 1529 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1530 }
bea3348e 1531 return work_done;
0da34b6d
BG		 1532}
1533
7d12e780 1534static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1535{
b53bef84
BG		 1536 struct myri10ge_slice_state *ss = arg;
1537 struct myri10ge_priv *mgp = ss->mgp;
1538 struct mcp_irq_data *stats = ss->fw_stats;
1539 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1540 u32 send_done_count;
1541 int i;
1542
236bb5e6
BG		 1543 /* an interrupt on a non-zero receive-only slice is implicitly
1544 * valid since MSI-X irqs are not shared */
1545 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1546 napi_schedule(&ss->napi);
0dcffac1
BG		 1547 return (IRQ_HANDLED);
1548 }
1549
0da34b6d
BG		 1550 /* make sure it is our IRQ, and that the DMA has finished */
1551 if (unlikely(!stats->valid))
1552 return (IRQ_NONE);
1553
1554 /* low bit indicates receives are present, so schedule
1555 * napi poll handler */
1556 if (stats->valid & 1)
288379f0 1557 napi_schedule(&ss->napi);
0da34b6d 1558
0dcffac1 1559 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1560 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1561 if (!myri10ge_deassert_wait)
1562 stats->valid = 0;
1563 mb();
1564 } else
1565 stats->valid = 0;
1566
1567 /* Wait for IRQ line to go low, if using INTx */
1568 i = 0;
1569 while (1) {
1570 i++;
1571 /* check for transmit completes and receives */
1572 send_done_count = ntohl(stats->send_done_count);
1573 if (send_done_count != tx->pkt_done)
b53bef84 1574 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d 1575 if (unlikely(i > myri10ge_max_irq_loops)) {
78ca90ea 1576 netdev_err(mgp->dev, "irq stuck?\n");
0da34b6d
BG		 1577 stats->valid = 0;
1578 schedule_work(&mgp->watchdog_work);
1579 }
1580 if (likely(stats->valid == 0))
1581 break;
1582 cpu_relax();
1583 barrier();
1584 }
1585
236bb5e6
BG		 1586 /* Only slice 0 updates stats */
1587 if (ss == mgp->ss)
1588 myri10ge_check_statblock(mgp);
0da34b6d 1589
b53bef84 1590 put_be32(htonl(3), ss->irq_claim + 1);
0da34b6d
BG		 1591 return (IRQ_HANDLED);
1592}
1593
1594static int
1595myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1596{
c0bf8801
BG		 1597 struct myri10ge_priv *mgp = netdev_priv(netdev);
1598 char *ptr;
1599 int i;
1600
0da34b6d
BG		 1601 cmd->autoneg = AUTONEG_DISABLE;
1602 cmd->speed = SPEED_10000;
1603 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1604
1605 /*
1606 * parse the product code to deterimine the interface type
1607 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1608 * after the 3rd dash in the driver's cached copy of the
1609 * EEPROM's product code string.
1610 */
1611 ptr = mgp->product_code_string;
1612 if (ptr == NULL) {
78ca90ea 1613 netdev_err(netdev, "Missing product code\n");
c0bf8801
BG		 1614 return 0;
1615 }
1616 for (i = 0; i < 3; i++, ptr++) {
1617 ptr = strchr(ptr, '-');
1618 if (ptr == NULL) {
78ca90ea
JP		 1619 netdev_err(netdev, "Invalid product code %s\n",
1620 mgp->product_code_string);
c0bf8801
BG		 1621 return 0;
1622 }
1623 }
196f17eb
BG		 1624 if (*ptr == '2')
1625 ptr++;
1626 if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1627 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
c0bf8801 1628 cmd->port = PORT_FIBRE;
196f17eb
BG		 1629 cmd->supported |= SUPPORTED_FIBRE;
1630 cmd->advertising |= ADVERTISED_FIBRE;
1631 } else {
1632 cmd->port = PORT_OTHER;
c0bf8801 1633 }
196f17eb
BG		 1634 if (*ptr == 'R' || *ptr == 'S')
1635 cmd->transceiver = XCVR_EXTERNAL;
1636 else
1637 cmd->transceiver = XCVR_INTERNAL;
1638
0da34b6d
BG		 1639 return 0;
1640}
1641
1642static void
1643myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1644{
1645 struct myri10ge_priv *mgp = netdev_priv(netdev);
1646
1647 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1648 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1649 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1650 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1651}
1652
1653static int
1654myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1655{
1656 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1657
0da34b6d
BG		 1658 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1659 return 0;
1660}
1661
1662static int
1663myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1664{
1665 struct myri10ge_priv *mgp = netdev_priv(netdev);
1666
1667 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1668 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1669 return 0;
1670}
1671
1672static void
1673myri10ge_get_pauseparam(struct net_device *netdev,
1674 struct ethtool_pauseparam *pause)
1675{
1676 struct myri10ge_priv *mgp = netdev_priv(netdev);
1677
1678 pause->autoneg = 0;
1679 pause->rx_pause = mgp->pause;
1680 pause->tx_pause = mgp->pause;
1681}
1682
1683static int
1684myri10ge_set_pauseparam(struct net_device *netdev,
1685 struct ethtool_pauseparam *pause)
1686{
1687 struct myri10ge_priv *mgp = netdev_priv(netdev);
1688
1689 if (pause->tx_pause != mgp->pause)
1690 return myri10ge_change_pause(mgp, pause->tx_pause);
1691 if (pause->rx_pause != mgp->pause)
1692 return myri10ge_change_pause(mgp, pause->tx_pause);
1693 if (pause->autoneg != 0)
1694 return -EINVAL;
1695 return 0;
1696}
1697
1698static void
1699myri10ge_get_ringparam(struct net_device *netdev,
1700 struct ethtool_ringparam *ring)
1701{
1702 struct myri10ge_priv *mgp = netdev_priv(netdev);
1703
0dcffac1
BG		 1704 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1705 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1706 ring->rx_jumbo_max_pending = 0;
6498be3f 1707 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1708 ring->rx_mini_pending = ring->rx_mini_max_pending;
1709 ring->rx_pending = ring->rx_max_pending;
1710 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1711 ring->tx_pending = ring->tx_max_pending;
1712}
1713
1714static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1715{
1716 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1717
0da34b6d
BG		 1718 if (mgp->csum_flag)
1719 return 1;
1720 else
1721 return 0;
1722}
1723
1724static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1725{
1726 struct myri10ge_priv *mgp = netdev_priv(netdev);
3a0c7d2d 1727 int err = 0;
99f5f87e 1728
0da34b6d
BG		 1729 if (csum_enabled)
1730 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3a0c7d2d
BG		 1731 else {
1732 u32 flags = ethtool_op_get_flags(netdev);
1733 err = ethtool_op_set_flags(netdev, (flags & ~ETH_FLAG_LRO));
0da34b6d 1734 mgp->csum_flag = 0;
3a0c7d2d
BG		 1735
1736 }
1737 return err;
0da34b6d
BG		 1738}
1739
4f93fde0
BG		 1740static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1741{
1742 struct myri10ge_priv *mgp = netdev_priv(netdev);
1743 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1744
1745 if (tso_enabled)
1746 netdev->features |= flags;
1747 else
1748 netdev->features &= ~flags;
1749 return 0;
1750}
1751
b53bef84 1752static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1753 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1754 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1755 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1756 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1757 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1758 "tx_heartbeat_errors", "tx_window_errors",
1759 /* device-specific stats */
0dcffac1 1760 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1761 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1762 "serial_number", "watchdog_resets",
5dd2d332 1763#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1764 "dca_capable_firmware", "dca_device_present",
981813d8 1765#endif
c58ac5ca 1766 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1767 "dropped_link_error_or_filtered",
1768 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1769 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1770 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1771 "dropped_no_big_buffer"
1772};
1773
1774static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1775 "----------- slice ---------",
1776 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1777 "rx_small_cnt", "rx_big_cnt",
1778 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1779 "LRO flushed",
1e6e9342 1780 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1781};
1782
1783#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1784#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1785#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1786
1787static void
1788myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1789{
0dcffac1
BG		 1790 struct myri10ge_priv *mgp = netdev_priv(netdev);
1791 int i;
1792
0da34b6d
BG		 1793 switch (stringset) {
1794 case ETH_SS_STATS:
b53bef84
BG		 1795 memcpy(data, *myri10ge_gstrings_main_stats,
1796 sizeof(myri10ge_gstrings_main_stats));
1797 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1798 for (i = 0; i < mgp->num_slices; i++) {
1799 memcpy(data, *myri10ge_gstrings_slice_stats,
1800 sizeof(myri10ge_gstrings_slice_stats));
1801 data += sizeof(myri10ge_gstrings_slice_stats);
1802 }
0da34b6d
BG		 1803 break;
1804 }
1805}
1806
b9f2c044 1807static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1808{
0dcffac1
BG		 1809 struct myri10ge_priv *mgp = netdev_priv(netdev);
1810
b9f2c044
JG		 1811 switch (sset) {
1812 case ETH_SS_STATS:
0dcffac1
BG		 1813 return MYRI10GE_MAIN_STATS_LEN +
1814 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1815 default:
1816 return -EOPNOTSUPP;
1817 }
0da34b6d
BG		 1818}
1819
1820static void
1821myri10ge_get_ethtool_stats(struct net_device *netdev,
1822 struct ethtool_stats *stats, u64 * data)
1823{
1824 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1825 struct myri10ge_slice_state *ss;
0dcffac1 1826 int slice;
0da34b6d
BG		 1827 int i;
1828
59081825
BG		 1829 /* force stats update */
1830 (void)myri10ge_get_stats(netdev);
0da34b6d 1831 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
6dc34941 1832 data[i] = ((unsigned long *)&netdev->stats)[i];
0da34b6d 1833
b53bef84 1834 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1835 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1836 data[i++] = (unsigned int)mgp->pdev->irq;
1837 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1838 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1839 data[i++] = (unsigned int)mgp->read_dma;
1840 data[i++] = (unsigned int)mgp->write_dma;
1841 data[i++] = (unsigned int)mgp->read_write_dma;
1842 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1843 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1844#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1845 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1846 data[i++] = (unsigned int)(mgp->dca_enabled);
1847#endif
c58ac5ca 1848 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1849
1850 /* firmware stats are useful only in the first slice */
0dcffac1 1851 ss = &mgp->ss[0];
b53bef84
BG		 1852 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1853 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1854 data[i++] =
b53bef84
BG		 1855 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1856 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1857 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1858 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1859 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1860 data[i++] =
b53bef84
BG		 1861 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1862 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1863 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1864 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1865 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1866
0dcffac1
BG		 1867 for (slice = 0; slice < mgp->num_slices; slice++) {
1868 ss = &mgp->ss[slice];
1869 data[i++] = slice;
1870 data[i++] = (unsigned int)ss->tx.pkt_start;
1871 data[i++] = (unsigned int)ss->tx.pkt_done;
1872 data[i++] = (unsigned int)ss->tx.req;
1873 data[i++] = (unsigned int)ss->tx.done;
1874 data[i++] = (unsigned int)ss->rx_small.cnt;
1875 data[i++] = (unsigned int)ss->rx_big.cnt;
1876 data[i++] = (unsigned int)ss->tx.wake_queue;
1877 data[i++] = (unsigned int)ss->tx.stop_queue;
1878 data[i++] = (unsigned int)ss->tx.linearized;
1879 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1880 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1881 if (ss->rx_done.lro_mgr.stats.flushed)
1882 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1883 ss->rx_done.lro_mgr.stats.flushed;
1884 else
1885 data[i++] = 0;
1886 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1887 }
0da34b6d
BG		 1888}
1889
c58ac5ca
BG		 1890static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1891{
1892 struct myri10ge_priv *mgp = netdev_priv(netdev);
1893 mgp->msg_enable = value;
1894}
1895
1896static u32 myri10ge_get_msglevel(struct net_device *netdev)
1897{
1898 struct myri10ge_priv *mgp = netdev_priv(netdev);
1899 return mgp->msg_enable;
1900}
1901
7282d491 1902static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1903 .get_settings = myri10ge_get_settings,
1904 .get_drvinfo = myri10ge_get_drvinfo,
1905 .get_coalesce = myri10ge_get_coalesce,
1906 .set_coalesce = myri10ge_set_coalesce,
1907 .get_pauseparam = myri10ge_get_pauseparam,
1908 .set_pauseparam = myri10ge_set_pauseparam,
1909 .get_ringparam = myri10ge_get_ringparam,
1910 .get_rx_csum = myri10ge_get_rx_csum,
1911 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1912 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1913 .set_sg = ethtool_op_set_sg,
4f93fde0 1914 .set_tso = myri10ge_set_tso,
6ffdd071 1915 .get_link = ethtool_op_get_link,
0da34b6d 1916 .get_strings = myri10ge_get_strings,
b9f2c044 1917 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1918 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1919 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d
BG		 1920 .get_msglevel = myri10ge_get_msglevel,
1921 .get_flags = ethtool_op_get_flags,
1922 .set_flags = ethtool_op_set_flags
0da34b6d
BG		 1923};
1924
b53bef84 1925static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1926{
b53bef84 1927 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1928 struct myri10ge_cmd cmd;
b53bef84 1929 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1930 int tx_ring_size, rx_ring_size;
1931 int tx_ring_entries, rx_ring_entries;
0dcffac1 1932 int i, slice, status;
0da34b6d
BG		 1933 size_t bytes;
1934
0da34b6d 1935 /* get ring sizes */
0dcffac1
BG		 1936 slice = ss - mgp->ss;
1937 cmd.data0 = slice;
0da34b6d
BG		 1938 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1939 tx_ring_size = cmd.data0;
0dcffac1 1940 cmd.data0 = slice;
0da34b6d 1941 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1942 if (status != 0)
1943 return status;
0da34b6d
BG		 1944 rx_ring_size = cmd.data0;
1945
1946 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1947 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1948 ss->tx.mask = tx_ring_entries - 1;
1949 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1950
355c7265
BG		 1951 status = -ENOMEM;
1952
0da34b6d
BG		 1953 /* allocate the host shadow rings */
1954
1955 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1956 * sizeof(*ss->tx.req_list);
1957 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1958 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1959 goto abort_with_nothing;
1960
1961 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1962 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1963 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 1964 ss->tx.queue_active = 0;
0da34b6d 1965
b53bef84
BG		 1966 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1967 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1968 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1969 goto abort_with_tx_req_bytes;
1970
b53bef84
BG		 1971 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1972 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1973 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1974 goto abort_with_rx_small_shadow;
1975
1976 /* allocate the host info rings */
1977
b53bef84
BG		 1978 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1979 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1980 if (ss->tx.info == NULL)
0da34b6d
BG		 1981 goto abort_with_rx_big_shadow;
1982
b53bef84
BG		 1983 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1984 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1985 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1986 goto abort_with_tx_info;
1987
b53bef84
BG		 1988 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1989 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1990 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1991 goto abort_with_rx_small_info;
1992
1993 /* Fill the receive rings */
b53bef84
BG		 1994 ss->rx_big.cnt = 0;
1995 ss->rx_small.cnt = 0;
1996 ss->rx_big.fill_cnt = 0;
1997 ss->rx_small.fill_cnt = 0;
1998 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1999 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2000 ss->rx_small.watchdog_needed = 0;
2001 ss->rx_big.watchdog_needed = 0;
2002 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 2003 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 2004
b53bef84 2005 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
78ca90ea
JP		 2006 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2007 slice, ss->rx_small.fill_cnt);
c7dab99b 2008 goto abort_with_rx_small_ring;
0da34b6d
BG		 2009 }
2010
b53bef84
BG		 2011 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2012 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
78ca90ea
JP		 2013 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2014 slice, ss->rx_big.fill_cnt);
c7dab99b 2015 goto abort_with_rx_big_ring;
0da34b6d
BG		 2016 }
2017
2018 return 0;
2019
2020abort_with_rx_big_ring:
b53bef84
BG		 2021 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2022 int idx = i & ss->rx_big.mask;
2023 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2024 mgp->big_bytes);
b53bef84 2025 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2026 }
2027
2028abort_with_rx_small_ring:
b53bef84
BG		 2029 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2030 int idx = i & ss->rx_small.mask;
2031 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2032 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2033 put_page(ss->rx_small.info[idx].page);
0da34b6d 2034 }
c7dab99b 2035
b53bef84 2036 kfree(ss->rx_big.info);
0da34b6d
BG		 2037
2038abort_with_rx_small_info:
b53bef84 2039 kfree(ss->rx_small.info);
0da34b6d
BG		 2040
2041abort_with_tx_info:
b53bef84 2042 kfree(ss->tx.info);
0da34b6d
BG		 2043
2044abort_with_rx_big_shadow:
b53bef84 2045 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2046
2047abort_with_rx_small_shadow:
b53bef84 2048 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2049
2050abort_with_tx_req_bytes:
b53bef84
BG		 2051 kfree(ss->tx.req_bytes);
2052 ss->tx.req_bytes = NULL;
2053 ss->tx.req_list = NULL;
0da34b6d
BG		 2054
2055abort_with_nothing:
2056 return status;
2057}
2058
b53bef84 2059static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2060{
b53bef84 2061 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2062 struct sk_buff *skb;
2063 struct myri10ge_tx_buf *tx;
2064 int i, len, idx;
2065
0dcffac1
BG		 2066 /* If not allocated, skip it */
2067 if (ss->tx.req_list == NULL)
2068 return;
2069
b53bef84
BG		 2070 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2071 idx = i & ss->rx_big.mask;
2072 if (i == ss->rx_big.fill_cnt - 1)
2073 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2074 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2075 mgp->big_bytes);
b53bef84 2076 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2077 }
2078
b53bef84
BG		 2079 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2080 idx = i & ss->rx_small.mask;
2081 if (i == ss->rx_small.fill_cnt - 1)
2082 ss->rx_small.info[idx].page_offset =
c7dab99b 2083 MYRI10GE_ALLOC_SIZE;
b53bef84 2084 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2085 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2086 put_page(ss->rx_small.info[idx].page);
c7dab99b 2087 }
b53bef84 2088 tx = &ss->tx;
0da34b6d
BG		 2089 while (tx->done != tx->req) {
2090 idx = tx->done & tx->mask;
2091 skb = tx->info[idx].skb;
2092
2093 /* Mark as free */
2094 tx->info[idx].skb = NULL;
2095 tx->done++;
2096 len = pci_unmap_len(&tx->info[idx], len);
2097 pci_unmap_len_set(&tx->info[idx], len, 0);
2098 if (skb) {
b53bef84 2099 ss->stats.tx_dropped++;
0da34b6d
BG		 2100 dev_kfree_skb_any(skb);
2101 if (len)
2102 pci_unmap_single(mgp->pdev,
2103 pci_unmap_addr(&tx->info[idx],
2104 bus), len,
2105 PCI_DMA_TODEVICE);
2106 } else {
2107 if (len)
2108 pci_unmap_page(mgp->pdev,
2109 pci_unmap_addr(&tx->info[idx],
2110 bus), len,
2111 PCI_DMA_TODEVICE);
2112 }
2113 }
b53bef84 2114 kfree(ss->rx_big.info);
0da34b6d 2115
b53bef84 2116 kfree(ss->rx_small.info);
0da34b6d 2117
b53bef84 2118 kfree(ss->tx.info);
0da34b6d 2119
b53bef84 2120 kfree(ss->rx_big.shadow);
0da34b6d 2121
b53bef84 2122 kfree(ss->rx_small.shadow);
0da34b6d 2123
b53bef84
BG		 2124 kfree(ss->tx.req_bytes);
2125 ss->tx.req_bytes = NULL;
2126 ss->tx.req_list = NULL;
0da34b6d
BG		 2127}
2128
df30a740
BG		 2129static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2130{
2131 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2132 struct myri10ge_slice_state *ss;
2133 struct net_device *netdev = mgp->dev;
2134 int i;
df30a740
BG		 2135 int status;
2136
0dcffac1
BG		 2137 mgp->msi_enabled = 0;
2138 mgp->msix_enabled = 0;
2139 status = 0;
df30a740 2140 if (myri10ge_msi) {
0dcffac1
BG		 2141 if (mgp->num_slices > 1) {
2142 status =
2143 pci_enable_msix(pdev, mgp->msix_vectors,
2144 mgp->num_slices);
2145 if (status == 0) {
2146 mgp->msix_enabled = 1;
2147 } else {
2148 dev_err(&pdev->dev,
2149 "Error %d setting up MSI-X\n", status);
2150 return status;
2151 }
2152 }
2153 if (mgp->msix_enabled == 0) {
2154 status = pci_enable_msi(pdev);
2155 if (status != 0) {
2156 dev_err(&pdev->dev,
2157 "Error %d setting up MSI; falling back to xPIC\n",
2158 status);
2159 } else {
2160 mgp->msi_enabled = 1;
2161 }
2162 }
df30a740 2163 }
0dcffac1
BG		 2164 if (mgp->msix_enabled) {
2165 for (i = 0; i < mgp->num_slices; i++) {
2166 ss = &mgp->ss[i];
2167 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2168 "%s:slice-%d", netdev->name, i);
2169 status = request_irq(mgp->msix_vectors[i].vector,
2170 myri10ge_intr, 0, ss->irq_desc,
2171 ss);
2172 if (status != 0) {
2173 dev_err(&pdev->dev,
2174 "slice %d failed to allocate IRQ\n", i);
2175 i--;
2176 while (i >= 0) {
2177 free_irq(mgp->msix_vectors[i].vector,
2178 &mgp->ss[i]);
2179 i--;
2180 }
2181 pci_disable_msix(pdev);
2182 return status;
2183 }
2184 }
2185 } else {
2186 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2187 mgp->dev->name, &mgp->ss[0]);
2188 if (status != 0) {
2189 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2190 if (mgp->msi_enabled)
2191 pci_disable_msi(pdev);
2192 }
df30a740
BG		 2193 }
2194 return status;
2195}
2196
2197static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2198{
2199 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2200 int i;
df30a740 2201
0dcffac1
BG		 2202 if (mgp->msix_enabled) {
2203 for (i = 0; i < mgp->num_slices; i++)
2204 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2205 } else {
2206 free_irq(pdev->irq, &mgp->ss[0]);
2207 }
df30a740
BG		 2208 if (mgp->msi_enabled)
2209 pci_disable_msi(pdev);
0dcffac1
BG		 2210 if (mgp->msix_enabled)
2211 pci_disable_msix(pdev);
df30a740
BG		 2212}
2213
1e6e9342
AG		 2214static int
2215myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2216 void **ip_hdr, void **tcpudp_hdr,
2217 u64 * hdr_flags, void *priv)
2218{
2219 struct ethhdr *eh;
2220 struct vlan_ethhdr *veh;
2221 struct iphdr *iph;
2222 u8 *va = page_address(frag->page) + frag->page_offset;
2223 unsigned long ll_hlen;
66341fff
AV		 2224 /* passed opaque through lro_receive_frags() */
2225 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 2226
2227 /* find the mac header, aborting if not IPv4 */
2228
2229 eh = (struct ethhdr *)va;
2230 *mac_hdr = eh;
2231 ll_hlen = ETH_HLEN;
2232 if (eh->h_proto != htons(ETH_P_IP)) {
2233 if (eh->h_proto == htons(ETH_P_8021Q)) {
2234 veh = (struct vlan_ethhdr *)va;
2235 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2236 return -1;
2237
2238 ll_hlen += VLAN_HLEN;
2239
2240 /*
2241 * HW checksum starts ETH_HLEN bytes into
2242 * frame, so we must subtract off the VLAN
2243 * header's checksum before csum can be used
2244 */
2245 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2246 VLAN_HLEN, 0));
2247 } else {
2248 return -1;
2249 }
2250 }
2251 *hdr_flags = LRO_IPV4;
2252
2253 iph = (struct iphdr *)(va + ll_hlen);
2254 *ip_hdr = iph;
2255 if (iph->protocol != IPPROTO_TCP)
2256 return -1;
bcb09dc2
BG		 2257 if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2258 return -1;
1e6e9342
AG		 2259 *hdr_flags |= LRO_TCP;
2260 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2261
2262 /* verify the IP checksum */
2263 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2264 return -1;
2265
2266 /* verify the checksum */
2267 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2268 ntohs(iph->tot_len) - (iph->ihl << 2),
2269 IPPROTO_TCP, csum)))
2270 return -1;
2271
2272 return 0;
2273}
2274
77929732
BG		 2275static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2276{
2277 struct myri10ge_cmd cmd;
2278 struct myri10ge_slice_state *ss;
2279 int status;
2280
2281 ss = &mgp->ss[slice];
236bb5e6
BG		 2282 status = 0;
2283 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2284 cmd.data0 = slice;
2285 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2286 &cmd, 0);
2287 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2288 (mgp->sram + cmd.data0);
2289 }
77929732
BG		 2290 cmd.data0 = slice;
2291 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2292 &cmd, 0);
2293 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2294 (mgp->sram + cmd.data0);
2295
2296 cmd.data0 = slice;
2297 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2298 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2299 (mgp->sram + cmd.data0);
2300
236bb5e6
BG		 2301 ss->tx.send_go = (__iomem __be32 *)
2302 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2303 ss->tx.send_stop = (__iomem __be32 *)
2304 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2305 return status;
2306
2307}
2308
2309static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2310{
2311 struct myri10ge_cmd cmd;
2312 struct myri10ge_slice_state *ss;
2313 int status;
2314
2315 ss = &mgp->ss[slice];
2316 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2317 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2318 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2319 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2320 if (status == -ENOSYS) {
2321 dma_addr_t bus = ss->fw_stats_bus;
2322 if (slice != 0)
2323 return -EINVAL;
2324 bus += offsetof(struct mcp_irq_data, send_done_count);
2325 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2326 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2327 status = myri10ge_send_cmd(mgp,
2328 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2329 &cmd, 0);
2330 /* Firmware cannot support multicast without STATS_DMA_V2 */
2331 mgp->fw_multicast_support = 0;
2332 } else {
2333 mgp->fw_multicast_support = 1;
2334 }
2335 return 0;
2336}
77929732 2337
0da34b6d
BG		 2338static int myri10ge_open(struct net_device *dev)
2339{
0dcffac1 2340 struct myri10ge_slice_state *ss;
b53bef84 2341 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2342 struct myri10ge_cmd cmd;
0dcffac1
BG		 2343 int i, status, big_pow2, slice;
2344 u8 *itable;
1e6e9342 2345 struct net_lro_mgr *lro_mgr;
0da34b6d 2346
0da34b6d
BG		 2347 if (mgp->running != MYRI10GE_ETH_STOPPED)
2348 return -EBUSY;
2349
2350 mgp->running = MYRI10GE_ETH_STARTING;
2351 status = myri10ge_reset(mgp);
2352 if (status != 0) {
78ca90ea 2353 netdev_err(dev, "failed reset\n");
df30a740 2354 goto abort_with_nothing;
0da34b6d
BG		 2355 }
2356
0dcffac1
BG		 2357 if (mgp->num_slices > 1) {
2358 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2359 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2360 if (mgp->dev->real_num_tx_queues > 1)
2361 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2362 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2363 &cmd, 0);
2364 if (status != 0) {
78ca90ea 2365 netdev_err(dev, "failed to set number of slices\n");
0dcffac1
BG		 2366 goto abort_with_nothing;
2367 }
2368 /* setup the indirection table */
2369 cmd.data0 = mgp->num_slices;
2370 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2371 &cmd, 0);
2372
2373 status |= myri10ge_send_cmd(mgp,
2374 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2375 &cmd, 0);
2376 if (status != 0) {
78ca90ea 2377 netdev_err(dev, "failed to setup rss tables\n");
236bb5e6 2378 goto abort_with_nothing;
0dcffac1
BG		 2379 }
2380
2381 /* just enable an identity mapping */
2382 itable = mgp->sram + cmd.data0;
2383 for (i = 0; i < mgp->num_slices; i++)
2384 __raw_writeb(i, &itable[i]);
2385
2386 cmd.data0 = 1;
2387 cmd.data1 = myri10ge_rss_hash;
2388 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2389 &cmd, 0);
2390 if (status != 0) {
78ca90ea 2391 netdev_err(dev, "failed to enable slices\n");
0dcffac1
BG		 2392 goto abort_with_nothing;
2393 }
2394 }
2395
df30a740
BG		 2396 status = myri10ge_request_irq(mgp);
2397 if (status != 0)
2398 goto abort_with_nothing;
2399
0da34b6d
BG		 2400 /* decide what small buffer size to use. For good TCP rx
2401 * performance, it is important to not receive 1514 byte
2402 * frames into jumbo buffers, as it confuses the socket buffer
2403 * accounting code, leading to drops and erratic performance.
2404 */
2405
2406 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2407 /* enough for a TCP header */
2408 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2409 ? (128 - MXGEFW_PAD)
2410 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2411 else
de3c4507
BG		 2412 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2413 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2414
2415 /* Override the small buffer size? */
2416 if (myri10ge_small_bytes > 0)
2417 mgp->small_bytes = myri10ge_small_bytes;
2418
0da34b6d
BG		 2419 /* Firmware needs the big buff size as a power of 2. Lie and
2420 * tell him the buffer is larger, because we only use 1
2421 * buffer/pkt, and the mtu will prevent overruns.
2422 */
13348bee 2423 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2424 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2425 while (!is_power_of_2(big_pow2))
c7dab99b 2426 big_pow2++;
13348bee 2427 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2428 } else {
2429 big_pow2 = MYRI10GE_ALLOC_SIZE;
2430 mgp->big_bytes = big_pow2;
2431 }
2432
0dcffac1
BG		 2433 /* setup the per-slice data structures */
2434 for (slice = 0; slice < mgp->num_slices; slice++) {
2435 ss = &mgp->ss[slice];
2436
2437 status = myri10ge_get_txrx(mgp, slice);
2438 if (status != 0) {
78ca90ea 2439 netdev_err(dev, "failed to get ring sizes or locations\n");
0dcffac1
BG		 2440 goto abort_with_rings;
2441 }
2442 status = myri10ge_allocate_rings(ss);
2443 if (status != 0)
2444 goto abort_with_rings;
236bb5e6
BG		 2445
2446 /* only firmware which supports multiple TX queues
2447 * supports setting up the tx stats on non-zero
2448 * slices */
2449 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2450 status = myri10ge_set_stats(mgp, slice);
2451 if (status) {
78ca90ea 2452 netdev_err(dev, "Couldn't set stats DMA\n");
0dcffac1
BG		 2453 goto abort_with_rings;
2454 }
2455
2456 lro_mgr = &ss->rx_done.lro_mgr;
2457 lro_mgr->dev = dev;
2458 lro_mgr->features = LRO_F_NAPI;
2459 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2460 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2461 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2462 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2463 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2464 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
636d2f68 2465 lro_mgr->frag_align_pad = 2;
0dcffac1
BG		 2466 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2467 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2468
2469 /* must happen prior to any irq */
2470 napi_enable(&(ss)->napi);
2471 }
0da34b6d
BG		 2472
2473 /* now give firmware buffers sizes, and MTU */
2474 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2475 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2476 cmd.data0 = mgp->small_bytes;
2477 status |=
2478 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2479 cmd.data0 = big_pow2;
2480 status |=
2481 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2482 if (status) {
78ca90ea 2483 netdev_err(dev, "Couldn't set buffer sizes\n");
0da34b6d
BG		 2484 goto abort_with_rings;
2485 }
2486
0dcffac1
BG		 2487 /*
2488 * Set Linux style TSO mode; this is needed only on newer
2489 * firmware versions. Older versions default to Linux
2490 * style TSO
2491 */
2492 cmd.data0 = 0;
2493 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2494 if (status && status != -ENOSYS) {
78ca90ea 2495 netdev_err(dev, "Couldn't set TSO mode\n");
0da34b6d
BG		 2496 goto abort_with_rings;
2497 }
2498
66341fff 2499 mgp->link_state = ~0U;
0da34b6d
BG		 2500 mgp->rdma_tags_available = 15;
2501
0da34b6d
BG		 2502 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2503 if (status) {
78ca90ea 2504 netdev_err(dev, "Couldn't bring up link\n");
0da34b6d
BG		 2505 goto abort_with_rings;
2506 }
2507
0da34b6d
BG		 2508 mgp->running = MYRI10GE_ETH_RUNNING;
2509 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2510 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2511 netif_tx_wake_all_queues(dev);
2512
0da34b6d
BG		 2513 return 0;
2514
2515abort_with_rings:
051d36f3
BG		 2516 while (slice) {
2517 slice--;
2518 napi_disable(&mgp->ss[slice].napi);
2519 }
0dcffac1
BG		 2520 for (i = 0; i < mgp->num_slices; i++)
2521 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2522
df30a740
BG		 2523 myri10ge_free_irq(mgp);
2524
0da34b6d
BG		 2525abort_with_nothing:
2526 mgp->running = MYRI10GE_ETH_STOPPED;
2527 return -ENOMEM;
2528}
2529
2530static int myri10ge_close(struct net_device *dev)
2531{
b53bef84 2532 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2533 struct myri10ge_cmd cmd;
2534 int status, old_down_cnt;
0dcffac1 2535 int i;
0da34b6d 2536
0da34b6d
BG		 2537 if (mgp->running != MYRI10GE_ETH_RUNNING)
2538 return 0;
2539
0dcffac1 2540 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2541 return 0;
2542
2543 del_timer_sync(&mgp->watchdog_timer);
2544 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2545 for (i = 0; i < mgp->num_slices; i++) {
2546 napi_disable(&mgp->ss[i].napi);
2547 }
0da34b6d 2548 netif_carrier_off(dev);
236bb5e6
BG		 2549
2550 netif_tx_stop_all_queues(dev);
d0234215
BG		 2551 if (mgp->rebooted == 0) {
2552 old_down_cnt = mgp->down_cnt;
2553 mb();
2554 status =
2555 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2556 if (status)
78ca90ea 2557 netdev_err(dev, "Couldn't bring down link\n");
0da34b6d 2558
d0234215
BG		 2559 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2560 HZ);
2561 if (old_down_cnt == mgp->down_cnt)
78ca90ea 2562 netdev_err(dev, "never got down irq\n");
d0234215 2563 }
0da34b6d 2564 netif_tx_disable(dev);
df30a740 2565 myri10ge_free_irq(mgp);
0dcffac1
BG		 2566 for (i = 0; i < mgp->num_slices; i++)
2567 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2568
2569 mgp->running = MYRI10GE_ETH_STOPPED;
2570 return 0;
2571}
2572
2573/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2574 * backwards one at a time and handle ring wraps */
2575
2576static inline void
2577myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2578 struct mcp_kreq_ether_send *src, int cnt)
2579{
2580 int idx, starting_slot;
2581 starting_slot = tx->req;
2582 while (cnt > 1) {
2583 cnt--;
2584 idx = (starting_slot + cnt) & tx->mask;
2585 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2586 mb();
2587 }
2588}
2589
2590/*
2591 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2592 * at most 32 bytes at a time, so as to avoid involving the software
2593 * pio handler in the nic. We re-write the first segment's flags
2594 * to mark them valid only after writing the entire chain.
2595 */
2596
2597static inline void
2598myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2599 int cnt)
2600{
2601 int idx, i;
2602 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2603 struct mcp_kreq_ether_send *srcp;
2604 u8 last_flags;
2605
2606 idx = tx->req & tx->mask;
2607
2608 last_flags = src->flags;
2609 src->flags = 0;
2610 mb();
2611 dst = dstp = &tx->lanai[idx];
2612 srcp = src;
2613
2614 if ((idx + cnt) < tx->mask) {
2615 for (i = 0; i < (cnt - 1); i += 2) {
2616 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2617 mb(); /* force write every 32 bytes */
2618 srcp += 2;
2619 dstp += 2;
2620 }
2621 } else {
2622 /* submit all but the first request, and ensure
2623 * that it is submitted below */
2624 myri10ge_submit_req_backwards(tx, src, cnt);
2625 i = 0;
2626 }
2627 if (i < cnt) {
2628 /* submit the first request */
2629 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2630 mb(); /* barrier before setting valid flag */
2631 }
2632
2633 /* re-write the last 32-bits with the valid flags */
2634 src->flags = last_flags;
40f6cff5 2635 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2636 tx->req += cnt;
2637 mb();
2638}
2639
0da34b6d
BG		 2640/*
2641 * Transmit a packet. We need to split the packet so that a single
b53bef84 2642 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2643 * counting tricky. So rather than try to count segments up front, we
2644 * just give up if there are too few segments to hold a reasonably
2645 * fragmented packet currently available. If we run
2646 * out of segments while preparing a packet for DMA, we just linearize
2647 * it and try again.
2648 */
2649
61357325
SH		 2650static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2651 struct net_device *dev)
0da34b6d
BG		 2652{
2653 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2654 struct myri10ge_slice_state *ss;
0da34b6d 2655 struct mcp_kreq_ether_send *req;
b53bef84 2656 struct myri10ge_tx_buf *tx;
0da34b6d 2657 struct skb_frag_struct *frag;
236bb5e6 2658 struct netdev_queue *netdev_queue;
0da34b6d 2659 dma_addr_t bus;
40f6cff5
AV		 2660 u32 low;
2661 __be32 high_swapped;
0da34b6d
BG		 2662 unsigned int len;
2663 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2664 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2665 int cum_len, seglen, boundary, rdma_count;
2666 u8 flags, odd_flag;
2667
236bb5e6 2668 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2669 ss = &mgp->ss[queue];
2670 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2671 tx = &ss->tx;
236bb5e6 2672
0da34b6d
BG		 2673again:
2674 req = tx->req_list;
2675 avail = tx->mask - 1 - (tx->req - tx->done);
2676
2677 mss = 0;
2678 max_segments = MXGEFW_MAX_SEND_DESC;
2679
917690cd 2680 if (skb_is_gso(skb)) {
7967168c 2681 mss = skb_shinfo(skb)->gso_size;
917690cd 2682 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2683 }
0da34b6d
BG		 2684
2685 if ((unlikely(avail < max_segments))) {
2686 /* we are out of transmit resources */
b53bef84 2687 tx->stop_queue++;
236bb5e6 2688 netif_tx_stop_queue(netdev_queue);
5b548140 2689 return NETDEV_TX_BUSY;
0da34b6d
BG		 2690 }
2691
2692 /* Setup checksum offloading, if needed */
2693 cksum_offset = 0;
2694 pseudo_hdr_offset = 0;
2695 odd_flag = 0;
2696 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2697 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2698 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2699 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2700 /* If the headers are excessively large, then we must
2701 * fall back to a software checksum */
4f93fde0
BG		 2702 if (unlikely(!mss && (cksum_offset > 255 ||
2703 pseudo_hdr_offset > 127))) {
84fa7933 2704 if (skb_checksum_help(skb))
0da34b6d
BG		 2705 goto drop;
2706 cksum_offset = 0;
2707 pseudo_hdr_offset = 0;
2708 } else {
0da34b6d
BG		 2709 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2710 flags |= MXGEFW_FLAGS_CKSUM;
2711 }
2712 }
2713
2714 cum_len = 0;
2715
0da34b6d
BG		 2716 if (mss) { /* TSO */
2717 /* this removes any CKSUM flag from before */
2718 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2719
2720 /* negative cum_len signifies to the
2721 * send loop that we are still in the
2722 * header portion of the TSO packet.
4f93fde0 2723 * TSO header can be at most 1KB long */
ab6a5bb6 2724 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2725
4f93fde0
BG		 2726 /* for IPv6 TSO, the checksum offset stores the
2727 * TCP header length, to save the firmware from
2728 * the need to parse the headers */
2729 if (skb_is_gso_v6(skb)) {
2730 cksum_offset = tcp_hdrlen(skb);
2731 /* Can only handle headers <= max_tso6 long */
2732 if (unlikely(-cum_len > mgp->max_tso6))
2733 return myri10ge_sw_tso(skb, dev);
2734 }
0da34b6d
BG		 2735 /* for TSO, pseudo_hdr_offset holds mss.
2736 * The firmware figures out where to put
2737 * the checksum by parsing the header. */
40f6cff5 2738 pseudo_hdr_offset = mss;
0da34b6d 2739 } else
0da34b6d
BG		 2740 /* Mark small packets, and pad out tiny packets */
2741 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2742 flags |= MXGEFW_FLAGS_SMALL;
2743
2744 /* pad frames to at least ETH_ZLEN bytes */
2745 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2746 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2747 /* The packet is gone, so we must
2748 * return 0 */
b53bef84 2749 ss->stats.tx_dropped += 1;
6ed10654 2750 return NETDEV_TX_OK;
0da34b6d
BG		 2751 }
2752 /* adjust the len to account for the zero pad
2753 * so that the nic can know how long it is */
2754 skb->len = ETH_ZLEN;
2755 }
2756 }
2757
2758 /* map the skb for DMA */
2759 len = skb->len - skb->data_len;
2760 idx = tx->req & tx->mask;
2761 tx->info[idx].skb = skb;
2762 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2763 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2764 pci_unmap_len_set(&tx->info[idx], len, len);
2765
2766 frag_cnt = skb_shinfo(skb)->nr_frags;
2767 frag_idx = 0;
2768 count = 0;
2769 rdma_count = 0;
2770
2771 /* "rdma_count" is the number of RDMAs belonging to the
2772 * current packet BEFORE the current send request. For
2773 * non-TSO packets, this is equal to "count".
2774 * For TSO packets, rdma_count needs to be reset
2775 * to 0 after a segment cut.
2776 *
2777 * The rdma_count field of the send request is
2778 * the number of RDMAs of the packet starting at
2779 * that request. For TSO send requests with one ore more cuts
2780 * in the middle, this is the number of RDMAs starting
2781 * after the last cut in the request. All previous
2782 * segments before the last cut implicitly have 1 RDMA.
2783 *
2784 * Since the number of RDMAs is not known beforehand,
2785 * it must be filled-in retroactively - after each
2786 * segmentation cut or at the end of the entire packet.
2787 */
2788
2789 while (1) {
2790 /* Break the SKB or Fragment up into pieces which
b53bef84 2791 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2792 low = MYRI10GE_LOWPART_TO_U32(bus);
2793 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2794 while (len) {
2795 u8 flags_next;
2796 int cum_len_next;
2797
2798 if (unlikely(count == max_segments))
2799 goto abort_linearize;
2800
b53bef84
BG		 2801 boundary =
2802 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2803 seglen = boundary - low;
2804 if (seglen > len)
2805 seglen = len;
2806 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2807 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2808 if (mss) { /* TSO */
2809 (req - rdma_count)->rdma_count = rdma_count + 1;
2810
2811 if (likely(cum_len >= 0)) { /* payload */
2812 int next_is_first, chop;
2813
2814 chop = (cum_len_next > mss);
2815 cum_len_next = cum_len_next % mss;
2816 next_is_first = (cum_len_next == 0);
2817 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2818 flags_next |= next_is_first *
2819 MXGEFW_FLAGS_FIRST;
2820 rdma_count |= -(chop | next_is_first);
2821 rdma_count += chop & !next_is_first;
2822 } else if (likely(cum_len_next >= 0)) { /* header ends */
2823 int small;
2824
2825 rdma_count = -1;
2826 cum_len_next = 0;
2827 seglen = -cum_len;
2828 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2829 flags_next = MXGEFW_FLAGS_TSO_PLD |
2830 MXGEFW_FLAGS_FIRST |
2831 (small * MXGEFW_FLAGS_SMALL);
2832 }
2833 }
0da34b6d
BG		 2834 req->addr_high = high_swapped;
2835 req->addr_low = htonl(low);
40f6cff5 2836 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2837 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2838 req->rdma_count = 1;
2839 req->length = htons(seglen);
2840 req->cksum_offset = cksum_offset;
2841 req->flags = flags | ((cum_len & 1) * odd_flag);
2842
2843 low += seglen;
2844 len -= seglen;
2845 cum_len = cum_len_next;
2846 flags = flags_next;
2847 req++;
2848 count++;
2849 rdma_count++;
4f93fde0
BG		 2850 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2851 if (unlikely(cksum_offset > seglen))
2852 cksum_offset -= seglen;
2853 else
2854 cksum_offset = 0;
2855 }
0da34b6d
BG		 2856 }
2857 if (frag_idx == frag_cnt)
2858 break;
2859
2860 /* map next fragment for DMA */
2861 idx = (count + tx->req) & tx->mask;
2862 frag = &skb_shinfo(skb)->frags[frag_idx];
2863 frag_idx++;
2864 len = frag->size;
2865 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2866 len, PCI_DMA_TODEVICE);
2867 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2868 pci_unmap_len_set(&tx->info[idx], len, len);
2869 }
2870
2871 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2872 if (mss)
2873 do {
2874 req--;
2875 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2876 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2877 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2878 idx = ((count - 1) + tx->req) & tx->mask;
2879 tx->info[idx].last = 1;
e454e7e2 2880 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 2881 /* if using multiple tx queues, make sure NIC polls the
2882 * current slice */
2883 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2884 tx->queue_active = 1;
2885 put_be32(htonl(1), tx->send_go);
8c2f5fa5 2886 mb();
6824a105 2887 mmiowb();
236bb5e6 2888 }
0da34b6d
BG		 2889 tx->pkt_start++;
2890 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2891 tx->stop_queue++;
236bb5e6 2892 netif_tx_stop_queue(netdev_queue);
0da34b6d 2893 }
6ed10654 2894 return NETDEV_TX_OK;
0da34b6d
BG		 2895
2896abort_linearize:
2897 /* Free any DMA resources we've alloced and clear out the skb
2898 * slot so as to not trip up assertions, and to avoid a
2899 * double-free if linearizing fails */
2900
2901 last_idx = (idx + 1) & tx->mask;
2902 idx = tx->req & tx->mask;
2903 tx->info[idx].skb = NULL;
2904 do {
2905 len = pci_unmap_len(&tx->info[idx], len);
2906 if (len) {
2907 if (tx->info[idx].skb != NULL)
2908 pci_unmap_single(mgp->pdev,
2909 pci_unmap_addr(&tx->info[idx],
2910 bus), len,
2911 PCI_DMA_TODEVICE);
2912 else
2913 pci_unmap_page(mgp->pdev,
2914 pci_unmap_addr(&tx->info[idx],
2915 bus), len,
2916 PCI_DMA_TODEVICE);
2917 pci_unmap_len_set(&tx->info[idx], len, 0);
2918 tx->info[idx].skb = NULL;
2919 }
2920 idx = (idx + 1) & tx->mask;
2921 } while (idx != last_idx);
89114afd 2922 if (skb_is_gso(skb)) {
78ca90ea 2923 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
0da34b6d
BG		 2924 goto drop;
2925 }
2926
bec0e859 2927 if (skb_linearize(skb))
0da34b6d
BG		 2928 goto drop;
2929
b53bef84 2930 tx->linearized++;
0da34b6d
BG		 2931 goto again;
2932
2933drop:
2934 dev_kfree_skb_any(skb);
b53bef84 2935 ss->stats.tx_dropped += 1;
6ed10654 2936 return NETDEV_TX_OK;
0da34b6d
BG		 2937
2938}
2939
61357325
SH		 2940static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
2941 struct net_device *dev)
4f93fde0
BG		 2942{
2943 struct sk_buff *segs, *curr;
b53bef84 2944 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 2945 struct myri10ge_slice_state *ss;
61357325 2946 netdev_tx_t status;
4f93fde0
BG		 2947
2948 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2949 if (IS_ERR(segs))
4f93fde0
BG		 2950 goto drop;
2951
2952 while (segs) {
2953 curr = segs;
2954 segs = segs->next;
2955 curr->next = NULL;
2956 status = myri10ge_xmit(curr, dev);
2957 if (status != 0) {
2958 dev_kfree_skb_any(curr);
2959 if (segs != NULL) {
2960 curr = segs;
2961 segs = segs->next;
2962 curr->next = NULL;
2963 dev_kfree_skb_any(segs);
2964 }
2965 goto drop;
2966 }
2967 }
2968 dev_kfree_skb_any(skb);
ec634fe3 2969 return NETDEV_TX_OK;
4f93fde0
BG		 2970
2971drop:
d6279c88 2972 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 2973 dev_kfree_skb_any(skb);
d6279c88 2974 ss->stats.tx_dropped += 1;
ec634fe3 2975 return NETDEV_TX_OK;
4f93fde0
BG		 2976}
2977
0da34b6d
BG		 2978static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2979{
2980 struct myri10ge_priv *mgp = netdev_priv(dev);
0dcffac1 2981 struct myri10ge_slice_netstats *slice_stats;
6dc34941 2982 struct net_device_stats *stats = &dev->stats;
0dcffac1
BG		 2983 int i;
2984
59081825 2985 spin_lock(&mgp->stats_lock);
0dcffac1
BG		 2986 memset(stats, 0, sizeof(*stats));
2987 for (i = 0; i < mgp->num_slices; i++) {
2988 slice_stats = &mgp->ss[i].stats;
2989 stats->rx_packets += slice_stats->rx_packets;
2990 stats->tx_packets += slice_stats->tx_packets;
2991 stats->rx_bytes += slice_stats->rx_bytes;
2992 stats->tx_bytes += slice_stats->tx_bytes;
2993 stats->rx_dropped += slice_stats->rx_dropped;
2994 stats->tx_dropped += slice_stats->tx_dropped;
2995 }
59081825 2996 spin_unlock(&mgp->stats_lock);
0dcffac1 2997 return stats;
0da34b6d
BG		 2998}
2999
3000static void myri10ge_set_multicast_list(struct net_device *dev)
3001{
b53bef84 3002 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 3003 struct myri10ge_cmd cmd;
22bedad3 3004 struct netdev_hw_addr *ha;
6250223e 3005 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 3006 int err;
3007
0da34b6d
BG		 3008 /* can be called from atomic contexts,
3009 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 3010 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3011
3012 /* This firmware is known to not support multicast */
2f76216f 3013 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 3014 return;
3015
3016 /* Disable multicast filtering */
3017
3018 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3019 if (err != 0) {
78ca90ea
JP		 3020 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
3021 err);
85a7ea1b
BG		 3022 goto abort;
3023 }
3024
2f76216f 3025 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 3026 /* request to disable multicast filtering, so quit here */
3027 return;
3028 }
3029
3030 /* Flush the filters */
3031
3032 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3033 &cmd, 1);
3034 if (err != 0) {
78ca90ea
JP		 3035 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
3036 err);
85a7ea1b
BG		 3037 goto abort;
3038 }
3039
3040 /* Walk the multicast list, and add each address */
22bedad3
JP		 3041 netdev_for_each_mc_addr(ha, dev) {
3042 memcpy(data, &ha->addr, 6);
40f6cff5
AV		 3043 cmd.data0 = ntohl(data[0]);
3044 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 3045 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3046 &cmd, 1);
3047
3048 if (err != 0) {
78ca90ea 3049 netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
22bedad3 3050 err, ha->addr);
85a7ea1b
BG		 3051 goto abort;
3052 }
3053 }
3054 /* Enable multicast filtering */
3055 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3056 if (err != 0) {
78ca90ea
JP		 3057 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3058 err);
85a7ea1b
BG		 3059 goto abort;
3060 }
3061
3062 return;
3063
3064abort:
3065 return;
0da34b6d
BG		 3066}
3067
3068static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3069{
3070 struct sockaddr *sa = addr;
3071 struct myri10ge_priv *mgp = netdev_priv(dev);
3072 int status;
3073
3074 if (!is_valid_ether_addr(sa->sa_data))
3075 return -EADDRNOTAVAIL;
3076
3077 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3078 if (status != 0) {
78ca90ea
JP		 3079 netdev_err(dev, "changing mac address failed with %d\n",
3080 status);
0da34b6d
BG		 3081 return status;
3082 }
3083
3084 /* change the dev structure */
3085 memcpy(dev->dev_addr, sa->sa_data, 6);
3086 return 0;
3087}
3088
3089static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3090{
3091 struct myri10ge_priv *mgp = netdev_priv(dev);
3092 int error = 0;
3093
3094 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
78ca90ea 3095 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
0da34b6d
BG		 3096 return -EINVAL;
3097 }
78ca90ea 3098 netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
0da34b6d
BG		 3099 if (mgp->running) {
3100 /* if we change the mtu on an active device, we must
3101 * reset the device so the firmware sees the change */
3102 myri10ge_close(dev);
3103 dev->mtu = new_mtu;
3104 myri10ge_open(dev);
3105 } else
3106 dev->mtu = new_mtu;
3107
3108 return error;
3109}
3110
3111/*
3112 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3113 * Only do it if the bridge is a root port since we don't want to disturb
3114 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3115 */
3116
0da34b6d
BG		 3117static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3118{
3119 struct pci_dev *bridge = mgp->pdev->bus->self;
3120 struct device *dev = &mgp->pdev->dev;
3121 unsigned cap;
3122 unsigned err_cap;
3123 u16 val;
3124 u8 ext_type;
3125 int ret;
3126
3127 if (!myri10ge_ecrc_enable || !bridge)
3128 return;
3129
3130 /* check that the bridge is a root port */
3131 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3132 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3133 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3134 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3135 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3136 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3137
3138 /* Walk the hierarchy up to the root port
3139 * where ECRC has to be enabled */
3140 do {
eca3fd83 3141 prev_bridge = bridge;
0da34b6d 3142 bridge = bridge->bus->self;
eca3fd83 3143 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3144 dev_err(dev,
3145 "Failed to find root port"
3146 " to force ECRC\n");
3147 return;
3148 }
3149 cap =
3150 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3151 pci_read_config_word(bridge,
3152 cap + PCI_CAP_FLAGS, &val);
3153 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3154 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3155
3156 dev_info(dev,
3157 "Forcing ECRC on non-root port %s"
3158 " (enabling on root port %s)\n",
3159 pci_name(old_bridge), pci_name(bridge));
3160 } else {
3161 dev_err(dev,
3162 "Not enabling ECRC on non-root port %s\n",
3163 pci_name(bridge));
3164 return;
3165 }
3166 }
3167
3168 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3169 if (!cap)
3170 return;
3171
3172 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3173 if (ret) {
3174 dev_err(dev, "failed reading ext-conf-space of %s\n",
3175 pci_name(bridge));
3176 dev_err(dev, "\t pci=nommconf in use? "
3177 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3178 return;
3179 }
3180 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3181 return;
3182
3183 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3184 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3185 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3186}
3187
3188/*
3189 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3190 * when the PCI-E Completion packets are aligned on an 8-byte
3191 * boundary. Some PCI-E chip sets always align Completion packets; on
3192 * the ones that do not, the alignment can be enforced by enabling
3193 * ECRC generation (if supported).
3194 *
3195 * When PCI-E Completion packets are not aligned, it is actually more
3196 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3197 *
3198 * If the driver can neither enable ECRC nor verify that it has
3199 * already been enabled, then it must use a firmware image which works
0dcffac1 3200 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3201 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3202 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3203 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3204 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3205 */
3206
5443e9ea 3207static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3208{
5443e9ea
BG		 3209 struct pci_dev *pdev = mgp->pdev;
3210 struct device *dev = &pdev->dev;
302d242c 3211 int status;
0da34b6d 3212
b53bef84 3213 mgp->tx_boundary = 4096;
5443e9ea
BG		 3214 /*
3215 * Verify the max read request size was set to 4KB
3216 * before trying the test with 4KB.
3217 */
302d242c
BG		 3218 status = pcie_get_readrq(pdev);
3219 if (status < 0) {
5443e9ea
BG		 3220 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3221 goto abort;
3222 }
302d242c
BG		 3223 if (status != 4096) {
3224 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3225 mgp->tx_boundary = 2048;
5443e9ea
BG		 3226 }
3227 /*
3228 * load the optimized firmware (which assumes aligned PCIe
3229 * completions) in order to see if it works on this host.
3230 */
3231 mgp->fw_name = myri10ge_fw_aligned;
0dcffac1 3232 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3233 if (status != 0) {
3234 goto abort;
3235 }
3236
3237 /*
3238 * Enable ECRC if possible
3239 */
3240 myri10ge_enable_ecrc(mgp);
3241
3242 /*
3243 * Run a DMA test which watches for unaligned completions and
3244 * aborts on the first one seen.
3245 */
3246
3247 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3248 if (status == 0)
3249 return; /* keep the aligned firmware */
3250
3251 if (status != -E2BIG)
3252 dev_warn(dev, "DMA test failed: %d\n", status);
3253 if (status == -ENOSYS)
3254 dev_warn(dev, "Falling back to ethp! "
3255 "Please install up to date fw\n");
3256abort:
3257 /* fall back to using the unaligned firmware */
b53bef84 3258 mgp->tx_boundary = 2048;
0da34b6d
BG		 3259 mgp->fw_name = myri10ge_fw_unaligned;
3260
5443e9ea
BG		 3261}
3262
3263static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3264{
2d90b0aa
BG		 3265 int overridden = 0;
3266
0da34b6d 3267 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 3268 int link_width, exp_cap;
3269 u16 lnk;
3270
3271 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3272 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3273 link_width = (lnk >> 4) & 0x3f;
3274
ce7f9368
BG		 3275 /* Check to see if Link is less than 8 or if the
3276 * upstream bridge is known to provide aligned
3277 * completions */
3278 if (link_width < 8) {
3279 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3280 link_width);
b53bef84 3281 mgp->tx_boundary = 4096;
ce7f9368 3282 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 3283 } else {
3284 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3285 }
3286 } else {
3287 if (myri10ge_force_firmware == 1) {
3288 dev_info(&mgp->pdev->dev,
3289 "Assuming aligned completions (forced)\n");
b53bef84 3290 mgp->tx_boundary = 4096;
0da34b6d
BG		 3291 mgp->fw_name = myri10ge_fw_aligned;
3292 } else {
3293 dev_info(&mgp->pdev->dev,
3294 "Assuming unaligned completions (forced)\n");
b53bef84 3295 mgp->tx_boundary = 2048;
0da34b6d
BG		 3296 mgp->fw_name = myri10ge_fw_unaligned;
3297 }
3298 }
3299 if (myri10ge_fw_name != NULL) {
2d90b0aa 3300 overridden = 1;
0da34b6d
BG		 3301 mgp->fw_name = myri10ge_fw_name;
3302 }
2d90b0aa
BG		 3303 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3304 myri10ge_fw_names[mgp->board_number] != NULL &&
3305 strlen(myri10ge_fw_names[mgp->board_number])) {
3306 mgp->fw_name = myri10ge_fw_names[mgp->board_number];
3307 overridden = 1;
3308 }
3309 if (overridden)
3310 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3311 mgp->fw_name);
0da34b6d
BG		 3312}
3313
0da34b6d 3314#ifdef CONFIG_PM
0da34b6d
BG		 3315static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3316{
3317 struct myri10ge_priv *mgp;
3318 struct net_device *netdev;
3319
3320 mgp = pci_get_drvdata(pdev);
3321 if (mgp == NULL)
3322 return -EINVAL;
3323 netdev = mgp->dev;
3324
3325 netif_device_detach(netdev);
3326 if (netif_running(netdev)) {
78ca90ea 3327 netdev_info(netdev, "closing\n");
0da34b6d
BG		 3328 rtnl_lock();
3329 myri10ge_close(netdev);
3330 rtnl_unlock();
3331 }
3332 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3333 pci_save_state(pdev);
0da34b6d 3334 pci_disable_device(pdev);
1a63e846
BG		 3335
3336 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3337}
3338
3339static int myri10ge_resume(struct pci_dev *pdev)
3340{
3341 struct myri10ge_priv *mgp;
3342 struct net_device *netdev;
3343 int status;
3344 u16 vendor;
3345
3346 mgp = pci_get_drvdata(pdev);
3347 if (mgp == NULL)
3348 return -EINVAL;
3349 netdev = mgp->dev;
3350 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3351 msleep(5); /* give card time to respond */
3352 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3353 if (vendor == 0xffff) {
78ca90ea 3354 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3355 return -EIO;
3356 }
83f6e152 3357
1a63e846
BG		 3358 status = pci_restore_state(pdev);
3359 if (status)
3360 return status;
4c2248cc
BG		 3361
3362 status = pci_enable_device(pdev);
1a63e846 3363 if (status) {
4c2248cc 3364 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3365 return status;
4c2248cc
BG		 3366 }
3367
0da34b6d
BG		 3368 pci_set_master(pdev);
3369
0da34b6d 3370 myri10ge_reset(mgp);
013b68bf 3371 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3372
3373 /* Save configuration space to be restored if the
3374 * nic resets due to a parity error */
83f6e152 3375 pci_save_state(pdev);
0da34b6d
BG		 3376
3377 if (netif_running(netdev)) {
3378 rtnl_lock();
df30a740 3379 status = myri10ge_open(netdev);
0da34b6d 3380 rtnl_unlock();
df30a740
BG		 3381 if (status != 0)
3382 goto abort_with_enabled;
3383
0da34b6d
BG		 3384 }
3385 netif_device_attach(netdev);
3386
3387 return 0;
3388
4c2248cc
BG		 3389abort_with_enabled:
3390 pci_disable_device(pdev);
0da34b6d
BG		 3391 return -EIO;
3392
3393}
0da34b6d
BG		 3394#endif /* CONFIG_PM */
3395
3396static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3397{
3398 struct pci_dev *pdev = mgp->pdev;
3399 int vs = mgp->vendor_specific_offset;
3400 u32 reboot;
3401
3402 /*enter read32 mode */
3403 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3404
3405 /*read REBOOT_STATUS (0xfffffff0) */
3406 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3407 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3408 return reboot;
3409}
3410
3411/*
3412 * This watchdog is used to check whether the board has suffered
3413 * from a parity error and needs to be recovered.
3414 */
c4028958 3415static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3416{
c4028958 3417 struct myri10ge_priv *mgp =
6250223e 3418 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 3419 struct myri10ge_tx_buf *tx;
0da34b6d 3420 u32 reboot;
d0234215 3421 int status, rebooted;
0dcffac1 3422 int i;
0da34b6d
BG		 3423 u16 cmd, vendor;
3424
3425 mgp->watchdog_resets++;
3426 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
d0234215 3427 rebooted = 0;
0da34b6d
BG		 3428 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3429 /* Bus master DMA disabled? Check to see
3430 * if the card rebooted due to a parity error
3431 * For now, just report it */
3432 reboot = myri10ge_read_reboot(mgp);
78ca90ea
JP		 3433 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
3434 reboot,
3435 myri10ge_reset_recover ? "" : " not");
f181137f
BG		 3436 if (myri10ge_reset_recover == 0)
3437 return;
d0234215
BG		 3438 rtnl_lock();
3439 mgp->rebooted = 1;
3440 rebooted = 1;
3441 myri10ge_close(mgp->dev);
f181137f 3442 myri10ge_reset_recover--;
d0234215 3443 mgp->rebooted = 0;
0da34b6d
BG		 3444 /*
3445 * A rebooted nic will come back with config space as
3446 * it was after power was applied to PCIe bus.
3447 * Attempt to restore config space which was saved
3448 * when the driver was loaded, or the last time the
3449 * nic was resumed from power saving mode.
3450 */
83f6e152 3451 pci_restore_state(mgp->pdev);
7adda30c
BG		 3452
3453 /* save state again for accounting reasons */
83f6e152 3454 pci_save_state(mgp->pdev);
7adda30c 3455
0da34b6d
BG		 3456 } else {
3457 /* if we get back -1's from our slot, perhaps somebody
3458 * powered off our card. Don't try to reset it in
3459 * this case */
3460 if (cmd == 0xffff) {
3461 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3462 if (vendor == 0xffff) {
78ca90ea 3463 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3464 return;
3465 }
3466 }
3467 /* Perhaps it is a software error. Try to reset */
3468
78ca90ea 3469 netdev_err(mgp->dev, "device timeout, resetting\n");
0dcffac1
BG		 3470 for (i = 0; i < mgp->num_slices; i++) {
3471 tx = &mgp->ss[i].tx;
78ca90ea
JP		 3472 netdev_err(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3473 i, tx->queue_active, tx->req,
3474 tx->done, tx->pkt_start, tx->pkt_done,
3475 (int)ntohl(mgp->ss[i].fw_stats->
3476 send_done_count));
0dcffac1 3477 msleep(2000);
78ca90ea
JP		 3478 netdev_info(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3479 i, tx->queue_active, tx->req,
3480 tx->done, tx->pkt_start, tx->pkt_done,
3481 (int)ntohl(mgp->ss[i].fw_stats->
3482 send_done_count));
0dcffac1 3483 }
0da34b6d 3484 }
236bb5e6 3485
d0234215
BG		 3486 if (!rebooted) {
3487 rtnl_lock();
3488 myri10ge_close(mgp->dev);
3489 }
0dcffac1 3490 status = myri10ge_load_firmware(mgp, 1);
0da34b6d 3491 if (status != 0)
78ca90ea 3492 netdev_err(mgp->dev, "failed to load firmware\n");
0da34b6d
BG		 3493 else
3494 myri10ge_open(mgp->dev);
3495 rtnl_unlock();
3496}
3497
3498/*
3499 * We use our own timer routine rather than relying upon
3500 * netdev->tx_timeout because we have a very large hardware transmit
3501 * queue. Due to the large queue, the netdev->tx_timeout function
3502 * cannot detect a NIC with a parity error in a timely fashion if the
3503 * NIC is lightly loaded.
3504 */
3505static void myri10ge_watchdog_timer(unsigned long arg)
3506{
3507 struct myri10ge_priv *mgp;
b53bef84 3508 struct myri10ge_slice_state *ss;
d0234215 3509 int i, reset_needed, busy_slice_cnt;
626fda94 3510 u32 rx_pause_cnt;
d0234215 3511 u16 cmd;
0da34b6d
BG		 3512
3513 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3514
0dcffac1 3515 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
d0234215 3516 busy_slice_cnt = 0;
0dcffac1
BG		 3517 for (i = 0, reset_needed = 0;
3518 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3519
0dcffac1
BG		 3520 ss = &mgp->ss[i];
3521 if (ss->rx_small.watchdog_needed) {
3522 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3523 mgp->small_bytes + MXGEFW_PAD,
3524 1);
3525 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3526 myri10ge_fill_thresh)
3527 ss->rx_small.watchdog_needed = 0;
3528 }
3529 if (ss->rx_big.watchdog_needed) {
3530 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3531 mgp->big_bytes, 1);
3532 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3533 myri10ge_fill_thresh)
3534 ss->rx_big.watchdog_needed = 0;
3535 }
3536
3537 if (ss->tx.req != ss->tx.done &&
3538 ss->tx.done == ss->watchdog_tx_done &&
3539 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3540 /* nic seems like it might be stuck.. */
3541 if (rx_pause_cnt != mgp->watchdog_pause) {
3542 if (net_ratelimit())
78ca90ea
JP		 3543 netdev_err(mgp->dev, "slice %d: TX paused, check link partner\n",
3544 i);
0dcffac1 3545 } else {
78ca90ea 3546 netdev_warn(mgp->dev, "slice %d stuck:", i);
0dcffac1
BG		 3547 reset_needed = 1;
3548 }
626fda94 3549 }
d0234215
BG		 3550 if (ss->watchdog_tx_done != ss->tx.done ||
3551 ss->watchdog_rx_done != ss->rx_done.cnt) {
3552 busy_slice_cnt++;
3553 }
0dcffac1
BG		 3554 ss->watchdog_tx_done = ss->tx.done;
3555 ss->watchdog_tx_req = ss->tx.req;
d0234215
BG		 3556 ss->watchdog_rx_done = ss->rx_done.cnt;
3557 }
3558 /* if we've sent or received no traffic, poll the NIC to
3559 * ensure it is still there. Otherwise, we risk not noticing
3560 * an error in a timely fashion */
3561 if (busy_slice_cnt == 0) {
3562 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3563 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3564 reset_needed = 1;
3565 }
626fda94 3566 }
626fda94 3567 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3568
3569 if (reset_needed) {
3570 schedule_work(&mgp->watchdog_work);
3571 } else {
3572 /* rearm timer */
3573 mod_timer(&mgp->watchdog_timer,
3574 jiffies + myri10ge_watchdog_timeout * HZ);
3575 }
0da34b6d
BG		 3576}
3577
77929732
BG		 3578static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3579{
3580 struct myri10ge_slice_state *ss;
3581 struct pci_dev *pdev = mgp->pdev;
3582 size_t bytes;
3583 int i;
3584
3585 if (mgp->ss == NULL)
3586 return;
3587
3588 for (i = 0; i < mgp->num_slices; i++) {
3589 ss = &mgp->ss[i];
3590 if (ss->rx_done.entry != NULL) {
3591 bytes = mgp->max_intr_slots *
3592 sizeof(*ss->rx_done.entry);
3593 dma_free_coherent(&pdev->dev, bytes,
3594 ss->rx_done.entry, ss->rx_done.bus);
3595 ss->rx_done.entry = NULL;
3596 }
3597 if (ss->fw_stats != NULL) {
3598 bytes = sizeof(*ss->fw_stats);
3599 dma_free_coherent(&pdev->dev, bytes,
3600 ss->fw_stats, ss->fw_stats_bus);
3601 ss->fw_stats = NULL;
3602 }
3603 }
3604 kfree(mgp->ss);
3605 mgp->ss = NULL;
3606}
3607
3608static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3609{
3610 struct myri10ge_slice_state *ss;
3611 struct pci_dev *pdev = mgp->pdev;
3612 size_t bytes;
3613 int i;
3614
3615 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3616 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3617 if (mgp->ss == NULL) {
3618 return -ENOMEM;
3619 }
3620
3621 for (i = 0; i < mgp->num_slices; i++) {
3622 ss = &mgp->ss[i];
3623 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3624 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3625 &ss->rx_done.bus,
3626 GFP_KERNEL);
3627 if (ss->rx_done.entry == NULL)
3628 goto abort;
3629 memset(ss->rx_done.entry, 0, bytes);
3630 bytes = sizeof(*ss->fw_stats);
3631 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3632 &ss->fw_stats_bus,
3633 GFP_KERNEL);
3634 if (ss->fw_stats == NULL)
3635 goto abort;
3636 ss->mgp = mgp;
3637 ss->dev = mgp->dev;
3638 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3639 myri10ge_napi_weight);
3640 }
3641 return 0;
3642abort:
3643 myri10ge_free_slices(mgp);
3644 return -ENOMEM;
3645}
3646
3647/*
3648 * This function determines the number of slices supported.
3649 * The number slices is the minumum of the number of CPUS,
3650 * the number of MSI-X irqs supported, the number of slices
3651 * supported by the firmware
3652 */
3653static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3654{
3655 struct myri10ge_cmd cmd;
3656 struct pci_dev *pdev = mgp->pdev;
3657 char *old_fw;
3658 int i, status, ncpus, msix_cap;
3659
3660 mgp->num_slices = 1;
3661 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3662 ncpus = num_online_cpus();
3663
3664 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3665 (myri10ge_max_slices == -1 && ncpus < 2))
3666 return;
3667
3668 /* try to load the slice aware rss firmware */
3669 old_fw = mgp->fw_name;
13b2738c
BG		 3670 if (myri10ge_fw_name != NULL) {
3671 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3672 myri10ge_fw_name);
3673 mgp->fw_name = myri10ge_fw_name;
3674 } else if (old_fw == myri10ge_fw_aligned)
77929732
BG		 3675 mgp->fw_name = myri10ge_fw_rss_aligned;
3676 else
3677 mgp->fw_name = myri10ge_fw_rss_unaligned;
3678 status = myri10ge_load_firmware(mgp, 0);
3679 if (status != 0) {
3680 dev_info(&pdev->dev, "Rss firmware not found\n");
3681 return;
3682 }
3683
3684 /* hit the board with a reset to ensure it is alive */
3685 memset(&cmd, 0, sizeof(cmd));
3686 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3687 if (status != 0) {
3688 dev_err(&mgp->pdev->dev, "failed reset\n");
3689 goto abort_with_fw;
77929732
BG		 3690 }
3691
3692 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3693
3694 /* tell it the size of the interrupt queues */
3695 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3696 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3697 if (status != 0) {
3698 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3699 goto abort_with_fw;
3700 }
3701
3702 /* ask the maximum number of slices it supports */
3703 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3704 if (status != 0)
3705 goto abort_with_fw;
3706 else
3707 mgp->num_slices = cmd.data0;
3708
3709 /* Only allow multiple slices if MSI-X is usable */
3710 if (!myri10ge_msi) {
3711 goto abort_with_fw;
3712 }
3713
3714 /* if the admin did not specify a limit to how many
3715 * slices we should use, cap it automatically to the
3716 * number of CPUs currently online */
3717 if (myri10ge_max_slices == -1)
3718 myri10ge_max_slices = ncpus;
3719
3720 if (mgp->num_slices > myri10ge_max_slices)
3721 mgp->num_slices = myri10ge_max_slices;
3722
3723 /* Now try to allocate as many MSI-X vectors as we have
3724 * slices. We give up on MSI-X if we can only get a single
3725 * vector. */
3726
3727 mgp->msix_vectors = kzalloc(mgp->num_slices *
3728 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3729 if (mgp->msix_vectors == NULL)
3730 goto disable_msix;
3731 for (i = 0; i < mgp->num_slices; i++) {
3732 mgp->msix_vectors[i].entry = i;
3733 }
3734
3735 while (mgp->num_slices > 1) {
3736 /* make sure it is a power of two */
3737 while (!is_power_of_2(mgp->num_slices))
3738 mgp->num_slices--;
3739 if (mgp->num_slices == 1)
3740 goto disable_msix;
3741 status = pci_enable_msix(pdev, mgp->msix_vectors,
3742 mgp->num_slices);
3743 if (status == 0) {
3744 pci_disable_msix(pdev);
3745 return;
3746 }
3747 if (status > 0)
3748 mgp->num_slices = status;
3749 else
3750 goto disable_msix;
3751 }
3752
3753disable_msix:
3754 if (mgp->msix_vectors != NULL) {
3755 kfree(mgp->msix_vectors);
3756 mgp->msix_vectors = NULL;
3757 }
3758
3759abort_with_fw:
3760 mgp->num_slices = 1;
3761 mgp->fw_name = old_fw;
3762 myri10ge_load_firmware(mgp, 0);
3763}
77929732 3764
8126089f
SH		 3765static const struct net_device_ops myri10ge_netdev_ops = {
3766 .ndo_open = myri10ge_open,
3767 .ndo_stop = myri10ge_close,
3768 .ndo_start_xmit = myri10ge_xmit,
3769 .ndo_get_stats = myri10ge_get_stats,
3770 .ndo_validate_addr = eth_validate_addr,
3771 .ndo_change_mtu = myri10ge_change_mtu,
3772 .ndo_set_multicast_list = myri10ge_set_multicast_list,
3773 .ndo_set_mac_address = myri10ge_set_mac_address,
3774};
3775
0da34b6d
BG		 3776static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3777{
3778 struct net_device *netdev;
3779 struct myri10ge_priv *mgp;
3780 struct device *dev = &pdev->dev;
0da34b6d
BG		 3781 int i;
3782 int status = -ENXIO;
0da34b6d 3783 int dac_enabled;
00b5e505 3784 unsigned hdr_offset, ss_offset;
2d90b0aa 3785 static int board_number;
0da34b6d 3786
236bb5e6 3787 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
0da34b6d
BG		 3788 if (netdev == NULL) {
3789 dev_err(dev, "Could not allocate ethernet device\n");
3790 return -ENOMEM;
3791 }
3792
b245fb67
MH		 3793 SET_NETDEV_DEV(netdev, &pdev->dev);
3794
0da34b6d 3795 mgp = netdev_priv(netdev);
0da34b6d
BG		 3796 mgp->dev = netdev;
3797 mgp->pdev = pdev;
3798 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3799 mgp->pause = myri10ge_flow_control;
3800 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3801 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3802 mgp->board_number = board_number;
0da34b6d
BG		 3803 init_waitqueue_head(&mgp->down_wq);
3804
3805 if (pci_enable_device(pdev)) {
3806 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3807 status = -ENODEV;
3808 goto abort_with_netdev;
3809 }
0da34b6d
BG		 3810
3811 /* Find the vendor-specific cap so we can check
3812 * the reboot register later on */
3813 mgp->vendor_specific_offset
3814 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3815
3816 /* Set our max read request to 4KB */
302d242c 3817 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3818 if (status != 0) {
3819 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3820 status);
e3fd5534 3821 goto abort_with_enabled;
0da34b6d
BG		 3822 }
3823
3824 pci_set_master(pdev);
3825 dac_enabled = 1;
6a35528a 3826 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3827 if (status != 0) {
3828 dac_enabled = 0;
3829 dev_err(&pdev->dev,
898eb71c
JP		 3830 "64-bit pci address mask was refused, "
3831 "trying 32-bit\n");
284901a9 3832 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 3833 }
3834 if (status != 0) {
3835 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 3836 goto abort_with_enabled;
0da34b6d 3837 }
6a35528a 3838 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 3839 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3840 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d 3841 if (mgp->cmd == NULL)
e3fd5534 3842 goto abort_with_enabled;
0da34b6d 3843
0da34b6d
BG		 3844 mgp->board_span = pci_resource_len(pdev, 0);
3845 mgp->iomem_base = pci_resource_start(pdev, 0);
3846 mgp->mtrr = -1;
276e26c3 3847 mgp->wc_enabled = 0;
0da34b6d
BG		 3848#ifdef CONFIG_MTRR
3849 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3850 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3851 if (mgp->mtrr >= 0)
3852 mgp->wc_enabled = 1;
0da34b6d 3853#endif
c7f80993 3854 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3855 if (mgp->sram == NULL) {
3856 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3857 mgp->board_span, mgp->iomem_base);
3858 status = -ENXIO;
c7f80993 3859 goto abort_with_mtrr;
0da34b6d 3860 }
00b5e505
BG		 3861 hdr_offset =
3862 ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3863 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3864 mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3865 if (mgp->sram_size > mgp->board_span ||
3866 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3867 dev_err(&pdev->dev,
3868 "invalid sram_size %dB or board span %ldB\n",
3869 mgp->sram_size, mgp->board_span);
3870 goto abort_with_ioremap;
3871 }
0da34b6d 3872 memcpy_fromio(mgp->eeprom_strings,
00b5e505 3873 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 3874 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3875 status = myri10ge_read_mac_addr(mgp);
3876 if (status)
3877 goto abort_with_ioremap;
3878
3879 for (i = 0; i < ETH_ALEN; i++)
3880 netdev->dev_addr[i] = mgp->mac_addr[i];
3881
5443e9ea
BG		 3882 myri10ge_select_firmware(mgp);
3883
0dcffac1 3884 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3885 if (status != 0) {
3886 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3887 goto abort_with_ioremap;
3888 }
3889 myri10ge_probe_slices(mgp);
3890 status = myri10ge_alloc_slices(mgp);
3891 if (status != 0) {
3892 dev_err(&pdev->dev, "failed to alloc slice state\n");
3893 goto abort_with_firmware;
0da34b6d 3894 }
236bb5e6 3895 netdev->real_num_tx_queues = mgp->num_slices;
0da34b6d
BG		 3896 status = myri10ge_reset(mgp);
3897 if (status != 0) {
3898 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3899 goto abort_with_slices;
0da34b6d 3900 }
5dd2d332 3901#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3902 myri10ge_setup_dca(mgp);
3903#endif
0da34b6d
BG		 3904 pci_set_drvdata(pdev, mgp);
3905 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3906 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3907 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3908 myri10ge_initial_mtu = 68;
8126089f
SH		 3909
3910 netdev->netdev_ops = &myri10ge_netdev_ops;
0da34b6d 3911 netdev->mtu = myri10ge_initial_mtu;
0da34b6d 3912 netdev->base_addr = mgp->iomem_base;
4f93fde0 3913 netdev->features = mgp->features;
236bb5e6 3914
0da34b6d
BG		 3915 if (dac_enabled)
3916 netdev->features |= NETIF_F_HIGHDMA;
2552c31b 3917 netdev->features |= NETIF_F_LRO;
0da34b6d 3918
dddc045e
BG		 3919 netdev->vlan_features |= mgp->features;
3920 if (mgp->fw_ver_tiny < 37)
3921 netdev->vlan_features &= ~NETIF_F_TSO6;
3922 if (mgp->fw_ver_tiny < 32)
3923 netdev->vlan_features &= ~NETIF_F_TSO;
3924
21d05db1
BG		 3925 /* make sure we can get an irq, and that MSI can be
3926 * setup (if available). Also ensure netdev->irq
3927 * is set to correct value if MSI is enabled */
3928 status = myri10ge_request_irq(mgp);
3929 if (status != 0)
3930 goto abort_with_firmware;
3931 netdev->irq = pdev->irq;
3932 myri10ge_free_irq(mgp);
3933
0da34b6d
BG		 3934 /* Save configuration space to be restored if the
3935 * nic resets due to a parity error */
83f6e152 3936 pci_save_state(pdev);
0da34b6d
BG		 3937
3938 /* Setup the watchdog timer */
3939 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3940 (unsigned long)mgp);
3941
59081825 3942 spin_lock_init(&mgp->stats_lock);
0da34b6d 3943 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3944 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3945 status = register_netdev(netdev);
3946 if (status != 0) {
3947 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3948 goto abort_with_state;
0da34b6d 3949 }
0dcffac1
BG		 3950 if (mgp->msix_enabled)
3951 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3952 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3953 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3954 else
3955 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3956 mgp->msi_enabled ? "MSI" : "xPIC",
3957 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3958 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d 3959
2d90b0aa 3960 board_number++;
0da34b6d
BG		 3961 return 0;
3962
7adda30c 3963abort_with_state:
83f6e152 3964 pci_restore_state(pdev);
0da34b6d 3965
0dcffac1
BG		 3966abort_with_slices:
3967 myri10ge_free_slices(mgp);
3968
0da34b6d
BG		 3969abort_with_firmware:
3970 myri10ge_dummy_rdma(mgp, 0);
3971
0da34b6d 3972abort_with_ioremap:
0f840011
BG		 3973 if (mgp->mac_addr_string != NULL)
3974 dev_err(&pdev->dev,
3975 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
3976 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 3977 iounmap(mgp->sram);
3978
c7f80993 3979abort_with_mtrr:
0da34b6d
BG		 3980#ifdef CONFIG_MTRR
3981 if (mgp->mtrr >= 0)
3982 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3983#endif
b10c0668
BG		 3984 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3985 mgp->cmd, mgp->cmd_bus);
0da34b6d 3986
e3fd5534
BG		 3987abort_with_enabled:
3988 pci_disable_device(pdev);
0da34b6d 3989
e3fd5534 3990abort_with_netdev:
0da34b6d
BG		 3991 free_netdev(netdev);
3992 return status;
3993}
3994
3995/*
3996 * myri10ge_remove
3997 *
3998 * Does what is necessary to shutdown one Myrinet device. Called
3999 * once for each Myrinet card by the kernel when a module is
4000 * unloaded.
4001 */
4002static void myri10ge_remove(struct pci_dev *pdev)
4003{
4004 struct myri10ge_priv *mgp;
4005 struct net_device *netdev;
0da34b6d
BG		 4006
4007 mgp = pci_get_drvdata(pdev);
4008 if (mgp == NULL)
4009 return;
4010
4011 flush_scheduled_work();
4012 netdev = mgp->dev;
4013 unregister_netdev(netdev);
0da34b6d 4014
5dd2d332 4015#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4016 myri10ge_teardown_dca(mgp);
4017#endif
0da34b6d
BG		 4018 myri10ge_dummy_rdma(mgp, 0);
4019
7adda30c 4020 /* avoid a memory leak */
83f6e152 4021 pci_restore_state(pdev);
7adda30c 4022
0da34b6d
BG		 4023 iounmap(mgp->sram);
4024
4025#ifdef CONFIG_MTRR
4026 if (mgp->mtrr >= 0)
4027 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4028#endif
0dcffac1
BG		 4029 myri10ge_free_slices(mgp);
4030 if (mgp->msix_vectors != NULL)
4031 kfree(mgp->msix_vectors);
b10c0668
BG		 4032 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4033 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 4034
4035 free_netdev(netdev);
e3fd5534 4036 pci_disable_device(pdev);
0da34b6d
BG		 4037 pci_set_drvdata(pdev, NULL);
4038}
4039
b10c0668 4040#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 4041#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d 4042
a3aa1884 4043static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
b10c0668 4044 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 4045 {PCI_DEVICE
4046 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 4047 {0},
4048};
4049
97131079
BG		 4050MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4051
0da34b6d
BG		 4052static struct pci_driver myri10ge_driver = {
4053 .name = "myri10ge",
4054 .probe = myri10ge_probe,
4055 .remove = myri10ge_remove,
4056 .id_table = myri10ge_pci_tbl,
4057#ifdef CONFIG_PM
4058 .suspend = myri10ge_suspend,
4059 .resume = myri10ge_resume,
4060#endif
4061};
4062
5dd2d332 4063#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4064static int
4065myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4066{
4067 int err = driver_for_each_device(&myri10ge_driver.driver,
4068 NULL, &event,
4069 myri10ge_notify_dca_device);
4070
4071 if (err)
4072 return NOTIFY_BAD;
4073 return NOTIFY_DONE;
4074}
4075
4076static struct notifier_block myri10ge_dca_notifier = {
4077 .notifier_call = myri10ge_notify_dca,
4078 .next = NULL,
4079 .priority = 0,
4080};
4ee2ac51 4081#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4082
0da34b6d
BG		 4083static __init int myri10ge_init_module(void)
4084{
78ca90ea 4085 pr_info("Version %s\n", MYRI10GE_VERSION_STR);
0dcffac1 4086
236bb5e6 4087 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
78ca90ea
JP		 4088 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4089 myri10ge_rss_hash);
0dcffac1
BG		 4090 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4091 }
5dd2d332 4092#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4093 dca_register_notify(&myri10ge_dca_notifier);
4094#endif
236bb5e6
BG		 4095 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4096 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4097
0da34b6d
BG		 4098 return pci_register_driver(&myri10ge_driver);
4099}
4100
4101module_init(myri10ge_init_module);
4102
4103static __exit void myri10ge_cleanup_module(void)
4104{
5dd2d332 4105#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4106 dca_unregister_notify(&myri10ge_dca_notifier);
4107#endif
0da34b6d
BG		 4108 pci_unregister_driver(&myri10ge_driver);
4109}
4110
4111module_exit(myri10ge_cleanup_module);
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