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mlx4_en: Fix build warning in mlx4_en_create_rx_ring.
[net-next-2.6.git] / drivers / net / mlx4 / en_rx.c
CommitLineData
c27a02cd
YP
1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/mlx4/cq.h>
5a0e3ad6 35#include <linux/slab.h>
c27a02cd
YP
36#include <linux/mlx4/qp.h>
37#include <linux/skbuff.h>
38#include <linux/if_ether.h>
39#include <linux/if_vlan.h>
40#include <linux/vmalloc.h>
41
42#include "mlx4_en.h"
43
c27a02cd 44
c27a02cd
YP
45static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv,
46 struct mlx4_en_rx_desc *rx_desc,
47 struct skb_frag_struct *skb_frags,
48 struct mlx4_en_rx_alloc *ring_alloc,
49 int i)
50{
51 struct mlx4_en_dev *mdev = priv->mdev;
52 struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
53 struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i];
54 struct page *page;
55 dma_addr_t dma;
56
57 if (page_alloc->offset == frag_info->last_offset) {
58 /* Allocate new page */
59 page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER);
60 if (!page)
61 return -ENOMEM;
62
63 skb_frags[i].page = page_alloc->page;
64 skb_frags[i].page_offset = page_alloc->offset;
65 page_alloc->page = page;
66 page_alloc->offset = frag_info->frag_align;
67 } else {
68 page = page_alloc->page;
69 get_page(page);
70
71 skb_frags[i].page = page;
72 skb_frags[i].page_offset = page_alloc->offset;
73 page_alloc->offset += frag_info->frag_stride;
74 }
75 dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) +
76 skb_frags[i].page_offset, frag_info->frag_size,
77 PCI_DMA_FROMDEVICE);
78 rx_desc->data[i].addr = cpu_to_be64(dma);
79 return 0;
80}
81
82static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
83 struct mlx4_en_rx_ring *ring)
84{
85 struct mlx4_en_rx_alloc *page_alloc;
86 int i;
87
88 for (i = 0; i < priv->num_frags; i++) {
89 page_alloc = &ring->page_alloc[i];
90 page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
91 MLX4_EN_ALLOC_ORDER);
92 if (!page_alloc->page)
93 goto out;
94
95 page_alloc->offset = priv->frag_info[i].frag_align;
453a6082
YP
96 en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
97 i, page_alloc->page);
c27a02cd
YP
98 }
99 return 0;
100
101out:
102 while (i--) {
103 page_alloc = &ring->page_alloc[i];
104 put_page(page_alloc->page);
105 page_alloc->page = NULL;
106 }
107 return -ENOMEM;
108}
109
110static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
111 struct mlx4_en_rx_ring *ring)
112{
113 struct mlx4_en_rx_alloc *page_alloc;
114 int i;
115
116 for (i = 0; i < priv->num_frags; i++) {
117 page_alloc = &ring->page_alloc[i];
453a6082
YP
118 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
119 i, page_count(page_alloc->page));
c27a02cd
YP
120
121 put_page(page_alloc->page);
122 page_alloc->page = NULL;
123 }
124}
125
126
127static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
128 struct mlx4_en_rx_ring *ring, int index)
129{
130 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
131 struct skb_frag_struct *skb_frags = ring->rx_info +
132 (index << priv->log_rx_info);
133 int possible_frags;
134 int i;
135
c27a02cd
YP
136 /* Set size and memtype fields */
137 for (i = 0; i < priv->num_frags; i++) {
138 skb_frags[i].size = priv->frag_info[i].frag_size;
139 rx_desc->data[i].byte_count =
140 cpu_to_be32(priv->frag_info[i].frag_size);
141 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
142 }
143
144 /* If the number of used fragments does not fill up the ring stride,
145 * remaining (unused) fragments must be padded with null address/size
146 * and a special memory key */
147 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
148 for (i = priv->num_frags; i < possible_frags; i++) {
149 rx_desc->data[i].byte_count = 0;
150 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
151 rx_desc->data[i].addr = 0;
152 }
153}
154
155
156static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
157 struct mlx4_en_rx_ring *ring, int index)
158{
159 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
160 struct skb_frag_struct *skb_frags = ring->rx_info +
161 (index << priv->log_rx_info);
162 int i;
163
164 for (i = 0; i < priv->num_frags; i++)
165 if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i))
166 goto err;
167
168 return 0;
169
170err:
171 while (i--)
172 put_page(skb_frags[i].page);
173 return -ENOMEM;
174}
175
176static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
177{
178 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
179}
180
38aab07c
YP
181static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
182 struct mlx4_en_rx_ring *ring,
183 int index)
184{
185 struct mlx4_en_dev *mdev = priv->mdev;
186 struct skb_frag_struct *skb_frags;
187 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride);
188 dma_addr_t dma;
189 int nr;
190
191 skb_frags = ring->rx_info + (index << priv->log_rx_info);
192 for (nr = 0; nr < priv->num_frags; nr++) {
453a6082 193 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
38aab07c
YP
194 dma = be64_to_cpu(rx_desc->data[nr].addr);
195
af901ca1 196 en_dbg(DRV, priv, "Unmapping buffer at dma:0x%llx\n", (u64) dma);
38aab07c
YP
197 pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
198 PCI_DMA_FROMDEVICE);
199 put_page(skb_frags[nr].page);
200 }
201}
202
c27a02cd
YP
203static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
204{
c27a02cd
YP
205 struct mlx4_en_rx_ring *ring;
206 int ring_ind;
207 int buf_ind;
38aab07c 208 int new_size;
c27a02cd
YP
209
210 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
211 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
212 ring = &priv->rx_ring[ring_ind];
213
214 if (mlx4_en_prepare_rx_desc(priv, ring,
215 ring->actual_size)) {
216 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
453a6082
YP
217 en_err(priv, "Failed to allocate "
218 "enough rx buffers\n");
c27a02cd
YP
219 return -ENOMEM;
220 } else {
38aab07c 221 new_size = rounddown_pow_of_two(ring->actual_size);
453a6082
YP
222 en_warn(priv, "Only %d buffers allocated "
223 "reducing ring size to %d",
224 ring->actual_size, new_size);
38aab07c 225 goto reduce_rings;
c27a02cd
YP
226 }
227 }
228 ring->actual_size++;
229 ring->prod++;
230 }
231 }
38aab07c
YP
232 return 0;
233
234reduce_rings:
235 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
236 ring = &priv->rx_ring[ring_ind];
237 while (ring->actual_size > new_size) {
238 ring->actual_size--;
239 ring->prod--;
240 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
241 }
38aab07c
YP
242 }
243
c27a02cd
YP
244 return 0;
245}
246
c27a02cd
YP
247static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
248 struct mlx4_en_rx_ring *ring)
249{
c27a02cd 250 int index;
c27a02cd 251
453a6082
YP
252 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
253 ring->cons, ring->prod);
c27a02cd
YP
254
255 /* Unmap and free Rx buffers */
38aab07c 256 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
c27a02cd
YP
257 while (ring->cons != ring->prod) {
258 index = ring->cons & ring->size_mask;
453a6082 259 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
38aab07c 260 mlx4_en_free_rx_desc(priv, ring, index);
c27a02cd
YP
261 ++ring->cons;
262 }
263}
264
c27a02cd
YP
265int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
266 struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
267{
268 struct mlx4_en_dev *mdev = priv->mdev;
269 int err;
270 int tmp;
271
c27a02cd
YP
272
273 ring->prod = 0;
274 ring->cons = 0;
275 ring->size = size;
276 ring->size_mask = size - 1;
277 ring->stride = stride;
278 ring->log_stride = ffs(ring->stride) - 1;
9f519f68 279 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
c27a02cd
YP
280
281 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
282 sizeof(struct skb_frag_struct));
283 ring->rx_info = vmalloc(tmp);
284 if (!ring->rx_info) {
453a6082 285 en_err(priv, "Failed allocating rx_info ring\n");
c27a02cd
YP
286 return -ENOMEM;
287 }
453a6082 288 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
c27a02cd
YP
289 ring->rx_info, tmp);
290
291 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
292 ring->buf_size, 2 * PAGE_SIZE);
293 if (err)
294 goto err_ring;
295
296 err = mlx4_en_map_buffer(&ring->wqres.buf);
297 if (err) {
453a6082 298 en_err(priv, "Failed to map RX buffer\n");
c27a02cd
YP
299 goto err_hwq;
300 }
301 ring->buf = ring->wqres.buf.direct.buf;
302
c27a02cd
YP
303 return 0;
304
c27a02cd
YP
305err_hwq:
306 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
307err_ring:
308 vfree(ring->rx_info);
309 ring->rx_info = NULL;
310 return err;
311}
312
313int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
314{
c27a02cd
YP
315 struct mlx4_en_rx_ring *ring;
316 int i;
317 int ring_ind;
318 int err;
319 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
320 DS_SIZE * priv->num_frags);
c27a02cd
YP
321
322 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
323 ring = &priv->rx_ring[ring_ind];
324
325 ring->prod = 0;
326 ring->cons = 0;
327 ring->actual_size = 0;
328 ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
329
330 ring->stride = stride;
9f519f68
YP
331 if (ring->stride <= TXBB_SIZE)
332 ring->buf += TXBB_SIZE;
333
c27a02cd
YP
334 ring->log_stride = ffs(ring->stride) - 1;
335 ring->buf_size = ring->size * ring->stride;
336
337 memset(ring->buf, 0, ring->buf_size);
338 mlx4_en_update_rx_prod_db(ring);
339
340 /* Initailize all descriptors */
341 for (i = 0; i < ring->size; i++)
342 mlx4_en_init_rx_desc(priv, ring, i);
343
344 /* Initialize page allocators */
345 err = mlx4_en_init_allocator(priv, ring);
346 if (err) {
453a6082 347 en_err(priv, "Failed initializing ring allocator\n");
9a4f92a6
YP
348 ring_ind--;
349 goto err_allocator;
c27a02cd 350 }
c27a02cd 351 }
b58515be
IM
352 err = mlx4_en_fill_rx_buffers(priv);
353 if (err)
c27a02cd
YP
354 goto err_buffers;
355
356 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
357 ring = &priv->rx_ring[ring_ind];
358
00d7d7bc 359 ring->size_mask = ring->actual_size - 1;
c27a02cd 360 mlx4_en_update_rx_prod_db(ring);
c27a02cd
YP
361 }
362
363 return 0;
364
c27a02cd
YP
365err_buffers:
366 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
367 mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
368
369 ring_ind = priv->rx_ring_num - 1;
370err_allocator:
371 while (ring_ind >= 0) {
372 mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
373 ring_ind--;
374 }
375 return err;
376}
377
378void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
379 struct mlx4_en_rx_ring *ring)
380{
381 struct mlx4_en_dev *mdev = priv->mdev;
382
c27a02cd 383 mlx4_en_unmap_buffer(&ring->wqres.buf);
9f519f68 384 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size + TXBB_SIZE);
c27a02cd
YP
385 vfree(ring->rx_info);
386 ring->rx_info = NULL;
387}
388
389void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
390 struct mlx4_en_rx_ring *ring)
391{
c27a02cd 392 mlx4_en_free_rx_buf(priv, ring);
9f519f68
YP
393 if (ring->stride <= TXBB_SIZE)
394 ring->buf -= TXBB_SIZE;
c27a02cd
YP
395 mlx4_en_destroy_allocator(priv, ring);
396}
397
398
399/* Unmap a completed descriptor and free unused pages */
400static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
401 struct mlx4_en_rx_desc *rx_desc,
402 struct skb_frag_struct *skb_frags,
403 struct skb_frag_struct *skb_frags_rx,
404 struct mlx4_en_rx_alloc *page_alloc,
405 int length)
406{
407 struct mlx4_en_dev *mdev = priv->mdev;
408 struct mlx4_en_frag_info *frag_info;
409 int nr;
410 dma_addr_t dma;
411
412 /* Collect used fragments while replacing them in the HW descirptors */
413 for (nr = 0; nr < priv->num_frags; nr++) {
414 frag_info = &priv->frag_info[nr];
415 if (length <= frag_info->frag_prefix_size)
416 break;
417
418 /* Save page reference in skb */
419 skb_frags_rx[nr].page = skb_frags[nr].page;
420 skb_frags_rx[nr].size = skb_frags[nr].size;
421 skb_frags_rx[nr].page_offset = skb_frags[nr].page_offset;
422 dma = be64_to_cpu(rx_desc->data[nr].addr);
423
424 /* Allocate a replacement page */
425 if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr))
426 goto fail;
427
428 /* Unmap buffer */
69351a29 429 pci_unmap_single(mdev->pdev, dma, skb_frags_rx[nr].size,
c27a02cd
YP
430 PCI_DMA_FROMDEVICE);
431 }
432 /* Adjust size of last fragment to match actual length */
973507cb 433 if (nr > 0)
434 skb_frags_rx[nr - 1].size = length -
435 priv->frag_info[nr - 1].frag_prefix_size;
c27a02cd
YP
436 return nr;
437
438fail:
439 /* Drop all accumulated fragments (which have already been replaced in
440 * the descriptor) of this packet; remaining fragments are reused... */
441 while (nr > 0) {
442 nr--;
443 put_page(skb_frags_rx[nr].page);
444 }
445 return 0;
446}
447
448
449static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
450 struct mlx4_en_rx_desc *rx_desc,
451 struct skb_frag_struct *skb_frags,
452 struct mlx4_en_rx_alloc *page_alloc,
453 unsigned int length)
454{
455 struct mlx4_en_dev *mdev = priv->mdev;
456 struct sk_buff *skb;
457 void *va;
458 int used_frags;
459 dma_addr_t dma;
460
461 skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN);
462 if (!skb) {
453a6082 463 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
c27a02cd
YP
464 return NULL;
465 }
466 skb->dev = priv->dev;
467 skb_reserve(skb, NET_IP_ALIGN);
468 skb->len = length;
469 skb->truesize = length + sizeof(struct sk_buff);
470
471 /* Get pointer to first fragment so we could copy the headers into the
472 * (linear part of the) skb */
473 va = page_address(skb_frags[0].page) + skb_frags[0].page_offset;
474
475 if (length <= SMALL_PACKET_SIZE) {
476 /* We are copying all relevant data to the skb - temporarily
477 * synch buffers for the copy */
478 dma = be64_to_cpu(rx_desc->data[0].addr);
e4fc8560
FT
479 dma_sync_single_for_cpu(&mdev->pdev->dev, dma, length,
480 DMA_FROM_DEVICE);
c27a02cd 481 skb_copy_to_linear_data(skb, va, length);
e4fc8560
FT
482 dma_sync_single_for_device(&mdev->pdev->dev, dma, length,
483 DMA_FROM_DEVICE);
c27a02cd
YP
484 skb->tail += length;
485 } else {
486
487 /* Move relevant fragments to skb */
488 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags,
489 skb_shinfo(skb)->frags,
490 page_alloc, length);
785a0982
YP
491 if (unlikely(!used_frags)) {
492 kfree_skb(skb);
493 return NULL;
494 }
c27a02cd
YP
495 skb_shinfo(skb)->nr_frags = used_frags;
496
497 /* Copy headers into the skb linear buffer */
498 memcpy(skb->data, va, HEADER_COPY_SIZE);
499 skb->tail += HEADER_COPY_SIZE;
500
501 /* Skip headers in first fragment */
502 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
503
504 /* Adjust size of first fragment */
505 skb_shinfo(skb)->frags[0].size -= HEADER_COPY_SIZE;
506 skb->data_len = length - HEADER_COPY_SIZE;
507 }
508 return skb;
509}
510
e7c1c2c4
YP
511static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
512{
513 int i;
514 int offset = ETH_HLEN;
515
516 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
517 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
518 goto out_loopback;
519 }
520 /* Loopback found */
521 priv->loopback_ok = 1;
522
523out_loopback:
524 dev_kfree_skb_any(skb);
525}
c27a02cd
YP
526
527int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
528{
529 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd
YP
530 struct mlx4_cqe *cqe;
531 struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
532 struct skb_frag_struct *skb_frags;
c27a02cd
YP
533 struct mlx4_en_rx_desc *rx_desc;
534 struct sk_buff *skb;
535 int index;
536 int nr;
537 unsigned int length;
538 int polled = 0;
539 int ip_summed;
540
541 if (!priv->port_up)
542 return 0;
543
544 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
545 * descriptor offset can be deduced from the CQE index instead of
546 * reading 'cqe->index' */
547 index = cq->mcq.cons_index & ring->size_mask;
548 cqe = &cq->buf[index];
549
550 /* Process all completed CQEs */
551 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
552 cq->mcq.cons_index & cq->size)) {
553
554 skb_frags = ring->rx_info + (index << priv->log_rx_info);
555 rx_desc = ring->buf + (index << ring->log_stride);
556
557 /*
558 * make sure we read the CQE after we read the ownership bit
559 */
560 rmb();
561
562 /* Drop packet on bad receive or bad checksum */
563 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
564 MLX4_CQE_OPCODE_ERROR)) {
453a6082 565 en_err(priv, "CQE completed in error - vendor "
c27a02cd
YP
566 "syndrom:%d syndrom:%d\n",
567 ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
568 ((struct mlx4_err_cqe *) cqe)->syndrome);
569 goto next;
570 }
571 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
453a6082 572 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
c27a02cd
YP
573 goto next;
574 }
575
576 /*
577 * Packet is OK - process it.
578 */
579 length = be32_to_cpu(cqe->byte_cnt);
580 ring->bytes += length;
581 ring->packets++;
582
583 if (likely(priv->rx_csum)) {
584 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
585 (cqe->checksum == cpu_to_be16(0xffff))) {
586 priv->port_stats.rx_chksum_good++;
587 /* This packet is eligible for LRO if it is:
588 * - DIX Ethernet (type interpretation)
589 * - TCP/IP (v4)
590 * - without IP options
591 * - not an IP fragment */
fa37a958
YP
592 if (dev->features & NETIF_F_GRO) {
593 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
c27a02cd
YP
594
595 nr = mlx4_en_complete_rx_desc(
596 priv, rx_desc,
fa37a958 597 skb_frags, skb_shinfo(gro_skb)->frags,
c27a02cd
YP
598 ring->page_alloc, length);
599 if (!nr)
600 goto next;
601
fa37a958
YP
602 skb_shinfo(gro_skb)->nr_frags = nr;
603 gro_skb->len = length;
604 gro_skb->data_len = length;
605 gro_skb->truesize += length;
606 gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
607
c27a02cd 608 if (priv->vlgrp && (cqe->vlan_my_qpn &
fa37a958
YP
609 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)))
610 vlan_gro_frags(&cq->napi, priv->vlgrp, be16_to_cpu(cqe->sl_vid));
611 else
612 napi_gro_frags(&cq->napi);
c27a02cd
YP
613
614 goto next;
615 }
616
617 /* LRO not possible, complete processing here */
618 ip_summed = CHECKSUM_UNNECESSARY;
c27a02cd
YP
619 } else {
620 ip_summed = CHECKSUM_NONE;
621 priv->port_stats.rx_chksum_none++;
622 }
623 } else {
624 ip_summed = CHECKSUM_NONE;
625 priv->port_stats.rx_chksum_none++;
626 }
627
628 skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags,
629 ring->page_alloc, length);
630 if (!skb) {
631 priv->stats.rx_dropped++;
632 goto next;
633 }
634
e7c1c2c4
YP
635 if (unlikely(priv->validate_loopback)) {
636 validate_loopback(priv, skb);
637 goto next;
638 }
639
c27a02cd
YP
640 skb->ip_summed = ip_summed;
641 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 642 skb_record_rx_queue(skb, cq->ring);
c27a02cd
YP
643
644 /* Push it up the stack */
645 if (priv->vlgrp && (be32_to_cpu(cqe->vlan_my_qpn) &
646 MLX4_CQE_VLAN_PRESENT_MASK)) {
647 vlan_hwaccel_receive_skb(skb, priv->vlgrp,
648 be16_to_cpu(cqe->sl_vid));
649 } else
650 netif_receive_skb(skb);
651
c27a02cd
YP
652next:
653 ++cq->mcq.cons_index;
654 index = (cq->mcq.cons_index) & ring->size_mask;
655 cqe = &cq->buf[index];
656 if (++polled == budget) {
657 /* We are here because we reached the NAPI budget -
658 * flush only pending LRO sessions */
c27a02cd
YP
659 goto out;
660 }
661 }
662
c27a02cd
YP
663out:
664 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
665 mlx4_cq_set_ci(&cq->mcq);
666 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
667 ring->cons = cq->mcq.cons_index;
668 ring->prod += polled; /* Polled descriptors were realocated in place */
c27a02cd
YP
669 mlx4_en_update_rx_prod_db(ring);
670 return polled;
671}
672
673
674void mlx4_en_rx_irq(struct mlx4_cq *mcq)
675{
676 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
677 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
678
679 if (priv->port_up)
288379f0 680 napi_schedule(&cq->napi);
c27a02cd
YP
681 else
682 mlx4_en_arm_cq(priv, cq);
683}
684
685/* Rx CQ polling - called by NAPI */
686int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
687{
688 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
689 struct net_device *dev = cq->dev;
690 struct mlx4_en_priv *priv = netdev_priv(dev);
691 int done;
692
693 done = mlx4_en_process_rx_cq(dev, cq, budget);
694
695 /* If we used up all the quota - we're probably not done yet... */
696 if (done == budget)
697 INC_PERF_COUNTER(priv->pstats.napi_quota);
698 else {
699 /* Done for now */
288379f0 700 napi_complete(napi);
c27a02cd
YP
701 mlx4_en_arm_cq(priv, cq);
702 }
703 return done;
704}
705
706
707/* Calculate the last offset position that accomodates a full fragment
708 * (assuming fagment size = stride-align) */
709static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
710{
711 u16 res = MLX4_EN_ALLOC_SIZE % stride;
712 u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
713
453a6082 714 en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
c27a02cd
YP
715 "res:%d offset:%d\n", stride, align, res, offset);
716 return offset;
717}
718
719
720static int frag_sizes[] = {
721 FRAG_SZ0,
722 FRAG_SZ1,
723 FRAG_SZ2,
724 FRAG_SZ3
725};
726
727void mlx4_en_calc_rx_buf(struct net_device *dev)
728{
729 struct mlx4_en_priv *priv = netdev_priv(dev);
730 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
731 int buf_size = 0;
732 int i = 0;
733
734 while (buf_size < eff_mtu) {
735 priv->frag_info[i].frag_size =
736 (eff_mtu > buf_size + frag_sizes[i]) ?
737 frag_sizes[i] : eff_mtu - buf_size;
738 priv->frag_info[i].frag_prefix_size = buf_size;
739 if (!i) {
740 priv->frag_info[i].frag_align = NET_IP_ALIGN;
741 priv->frag_info[i].frag_stride =
742 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
743 } else {
744 priv->frag_info[i].frag_align = 0;
745 priv->frag_info[i].frag_stride =
746 ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
747 }
748 priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
749 priv, priv->frag_info[i].frag_stride,
750 priv->frag_info[i].frag_align);
751 buf_size += priv->frag_info[i].frag_size;
752 i++;
753 }
754
755 priv->num_frags = i;
756 priv->rx_skb_size = eff_mtu;
757 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct));
758
453a6082 759 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
c27a02cd
YP
760 "num_frags:%d):\n", eff_mtu, priv->num_frags);
761 for (i = 0; i < priv->num_frags; i++) {
453a6082 762 en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
c27a02cd
YP
763 "stride:%d last_offset:%d\n", i,
764 priv->frag_info[i].frag_size,
765 priv->frag_info[i].frag_prefix_size,
766 priv->frag_info[i].frag_align,
767 priv->frag_info[i].frag_stride,
768 priv->frag_info[i].last_offset);
769 }
770}
771
772/* RSS related functions */
773
9f519f68
YP
774static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
775 struct mlx4_en_rx_ring *ring,
c27a02cd
YP
776 enum mlx4_qp_state *state,
777 struct mlx4_qp *qp)
778{
779 struct mlx4_en_dev *mdev = priv->mdev;
780 struct mlx4_qp_context *context;
781 int err = 0;
782
783 context = kmalloc(sizeof *context , GFP_KERNEL);
784 if (!context) {
453a6082 785 en_err(priv, "Failed to allocate qp context\n");
c27a02cd
YP
786 return -ENOMEM;
787 }
788
789 err = mlx4_qp_alloc(mdev->dev, qpn, qp);
790 if (err) {
453a6082 791 en_err(priv, "Failed to allocate qp #%x\n", qpn);
c27a02cd 792 goto out;
c27a02cd
YP
793 }
794 qp->event = mlx4_en_sqp_event;
795
796 memset(context, 0, sizeof *context);
00d7d7bc 797 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
9f519f68
YP
798 qpn, ring->cqn, context);
799 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
c27a02cd 800
9f519f68 801 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
c27a02cd
YP
802 if (err) {
803 mlx4_qp_remove(mdev->dev, qp);
804 mlx4_qp_free(mdev->dev, qp);
805 }
9f519f68 806 mlx4_en_update_rx_prod_db(ring);
c27a02cd
YP
807out:
808 kfree(context);
809 return err;
810}
811
812/* Allocate rx qp's and configure them according to rss map */
813int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
814{
815 struct mlx4_en_dev *mdev = priv->mdev;
816 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
817 struct mlx4_qp_context context;
818 struct mlx4_en_rss_context *rss_context;
819 void *ptr;
0533943c 820 u8 rss_mask = 0x3f;
9f519f68 821 int i, qpn;
c27a02cd
YP
822 int err = 0;
823 int good_qps = 0;
824
453a6082 825 en_dbg(DRV, priv, "Configuring rss steering\n");
b6b912e0
YP
826 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
827 priv->rx_ring_num,
828 &rss_map->base_qpn);
c27a02cd 829 if (err) {
b6b912e0 830 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
c27a02cd
YP
831 return err;
832 }
833
b6b912e0 834 for (i = 0; i < priv->rx_ring_num; i++) {
c27a02cd 835 qpn = rss_map->base_qpn + i;
9f519f68 836 err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i],
c27a02cd
YP
837 &rss_map->state[i],
838 &rss_map->qps[i]);
839 if (err)
840 goto rss_err;
841
842 ++good_qps;
843 }
844
845 /* Configure RSS indirection qp */
846 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &priv->base_qpn);
847 if (err) {
453a6082
YP
848 en_err(priv, "Failed to reserve range for RSS "
849 "indirection qp\n");
c27a02cd
YP
850 goto rss_err;
851 }
852 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
853 if (err) {
453a6082 854 en_err(priv, "Failed to allocate RSS indirection QP\n");
c27a02cd
YP
855 goto reserve_err;
856 }
857 rss_map->indir_qp.event = mlx4_en_sqp_event;
858 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
9f519f68 859 priv->rx_ring[0].cqn, &context);
c27a02cd
YP
860
861 ptr = ((void *) &context) + 0x3c;
862 rss_context = (struct mlx4_en_rss_context *) ptr;
b6b912e0 863 rss_context->base_qpn = cpu_to_be32(ilog2(priv->rx_ring_num) << 24 |
c27a02cd
YP
864 (rss_map->base_qpn));
865 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
0533943c 866 rss_context->flags = rss_mask;
c27a02cd 867
0533943c
YP
868 if (priv->mdev->profile.udp_rss)
869 rss_context->base_qpn_udp = rss_context->default_qpn;
c27a02cd
YP
870 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
871 &rss_map->indir_qp, &rss_map->indir_state);
872 if (err)
873 goto indir_err;
874
875 return 0;
876
877indir_err:
878 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
879 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
880 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
881 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
882reserve_err:
883 mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
884rss_err:
885 for (i = 0; i < good_qps; i++) {
886 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
887 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
888 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
889 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
890 }
b6b912e0 891 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
c27a02cd
YP
892 return err;
893}
894
895void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
896{
897 struct mlx4_en_dev *mdev = priv->mdev;
898 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
899 int i;
900
901 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
902 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
903 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
904 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
905 mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
906
b6b912e0 907 for (i = 0; i < priv->rx_ring_num; i++) {
c27a02cd
YP
908 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
909 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
910 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
911 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
912 }
b6b912e0 913 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
c27a02cd
YP
914}
915
916
917
918
919