[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_dcb_82598.c

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2010 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#include "ixgbe.h"
#include "ixgbe_type.h"
#include "ixgbe_dcb.h"
#include "ixgbe_dcb_82598.h"

/**
 * ixgbe_dcb_config_packet_buffers_82598 - Configure packet buffers
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure packet buffers for DCB mode.
 */
static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw,
						 struct ixgbe_dcb_config *dcb_config)
{
	s32 ret_val = 0;
	u32 value = IXGBE_RXPBSIZE_64KB;
	u8  i = 0;

	/* Setup Rx packet buffer sizes */
	switch (dcb_config->rx_pba_cfg) {
	case pba_80_48:
		/* Setup the first four at 80KB */
		value = IXGBE_RXPBSIZE_80KB;
		for (; i < 4; i++)
			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
		/* Setup the last four at 48KB...don't re-init i */
		value = IXGBE_RXPBSIZE_48KB;
		/* Fall Through */
	case pba_equal:
	default:
		for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);

		/* Setup Tx packet buffer sizes */
		for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
			IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i),
					IXGBE_TXPBSIZE_40KB);
		}
		break;
	}

	return ret_val;
}

/**
 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure Rx Data Arbiter and credits for each traffic class.
 */
static s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
                                      struct ixgbe_dcb_config *dcb_config)
{
	struct tc_bw_alloc    *p;
	u32    reg           = 0;
	u32    credit_refill = 0;
	u32    credit_max    = 0;
	u8     i             = 0;

	reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
	IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);

	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
	/* Enable Arbiter */
	reg &= ~IXGBE_RMCS_ARBDIS;
	/* Enable Receive Recycle within the BWG */
	reg |= IXGBE_RMCS_RRM;
	/* Enable Deficit Fixed Priority arbitration*/
	reg |= IXGBE_RMCS_DFP;

	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);

	/* Configure traffic class credits and priority */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG];
		credit_refill = p->data_credits_refill;
		credit_max    = p->data_credits_max;

		reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);

		if (p->prio_type == prio_link)
			reg |= IXGBE_RT2CR_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
	}

	reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
	reg |= IXGBE_RDRXCTL_RDMTS_1_2;
	reg |= IXGBE_RDRXCTL_MPBEN;
	reg |= IXGBE_RDRXCTL_MCEN;
	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);

	reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
	/* Make sure there is enough descriptors before arbitration */
	reg &= ~IXGBE_RXCTRL_DMBYPS;
	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);

	return 0;
}

/**
 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure Tx Descriptor Arbiter and credits for each traffic class.
 */
static s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
                                           struct ixgbe_dcb_config *dcb_config)
{
	struct tc_bw_alloc *p;
	u32    reg, max_credits;
	u8     i;

	reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);

	/* Enable arbiter */
	reg &= ~IXGBE_DPMCS_ARBDIS;
	if (!(dcb_config->round_robin_enable)) {
		/* Enable DFP and Recycle mode */
		reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
	}
	reg |= IXGBE_DPMCS_TSOEF;
	/* Configure Max TSO packet size 34KB including payload and headers */
	reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);

	IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);

	/* Configure traffic class credits and priority */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
		max_credits = dcb_config->tc_config[i].desc_credits_max;
		reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
		reg |= p->data_credits_refill;
		reg |= (u32)(p->bwg_id) << IXGBE_TDTQ2TCCR_BWG_SHIFT;

		if (p->prio_type == prio_group)
			reg |= IXGBE_TDTQ2TCCR_GSP;

		if (p->prio_type == prio_link)
			reg |= IXGBE_TDTQ2TCCR_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
	}

	return 0;
}

/**
 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure Tx Data Arbiter and credits for each traffic class.
 */
static s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
                                           struct ixgbe_dcb_config *dcb_config)
{
	struct tc_bw_alloc *p;
	u32 reg;
	u8 i;

	reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
	/* Enable Data Plane Arbiter */
	reg &= ~IXGBE_PDPMCS_ARBDIS;
	/* Enable DFP and Transmit Recycle Mode */
	reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);

	IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);

	/* Configure traffic class credits and priority */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
		reg = p->data_credits_refill;
		reg |= (u32)(p->data_credits_max) << IXGBE_TDPT2TCCR_MCL_SHIFT;
		reg |= (u32)(p->bwg_id) << IXGBE_TDPT2TCCR_BWG_SHIFT;

		if (p->prio_type == prio_group)
			reg |= IXGBE_TDPT2TCCR_GSP;

		if (p->prio_type == prio_link)
			reg |= IXGBE_TDPT2TCCR_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
	}

	/* Enable Tx packet buffer division */
	reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
	reg |= IXGBE_DTXCTL_ENDBUBD;
	IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);

	return 0;
}

/**
 * ixgbe_dcb_config_pfc_82598 - Config priority flow control
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure Priority Flow Control for each traffic class.
 */
s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
                               struct ixgbe_dcb_config *dcb_config)
{
	u32 reg, rx_pba_size;
	u8  i;

	if (!dcb_config->pfc_mode_enable)
		goto out;

	/* Enable Transmit Priority Flow Control */
	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
	reg &= ~IXGBE_RMCS_TFCE_802_3X;
	/* correct the reporting of our flow control status */
	reg |= IXGBE_RMCS_TFCE_PRIORITY;
	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);

	/* Enable Receive Priority Flow Control */
	reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
	reg &= ~IXGBE_FCTRL_RFCE;
	reg |= IXGBE_FCTRL_RPFCE;
	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);

	/*
	 * Configure flow control thresholds and enable priority flow control
	 * for each traffic class.
	 */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
		rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
		reg = (rx_pba_size - hw->fc.low_water) << 10;

		if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
		    dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
			reg |= IXGBE_FCRTL_XONE;

		IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg);

		reg = (rx_pba_size - hw->fc.high_water) << 10;
		if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
		    dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
			reg |= IXGBE_FCRTH_FCEN;

		IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
	}

	/* Configure pause time */
	for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);

	/* Configure flow control refresh threshold value */
	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);

out:
	return 0;
}

/**
 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
 * @hw: pointer to hardware structure
 *
 * Configure queue statistics registers, all queues belonging to same traffic
 * class uses a single set of queue statistics counters.
 */
static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
{
	u32 reg = 0;
	u8  i   = 0;
	u8  j   = 0;

	/* Receive Queues stats setting -  8 queues per statistics reg */
	for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
		reg |= ((0x1010101) * j);
		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
		reg |= ((0x1010101) * j);
		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
	}
	/* Transmit Queues stats setting -  4 queues per statistics reg */
	for (i = 0; i < 8; i++) {
		reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
		reg |= ((0x1010101) * i);
		IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
	}

	return 0;
}

/**
 * ixgbe_dcb_hw_config_82598 - Config and enable DCB
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure dcb settings and enable dcb mode.
 */
s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
                              struct ixgbe_dcb_config *dcb_config)
{
	ixgbe_dcb_config_packet_buffers_82598(hw, dcb_config);
	ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config);
	ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config);
	ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config);
	ixgbe_dcb_config_pfc_82598(hw, dcb_config);
	ixgbe_dcb_config_tc_stats_82598(hw);

	return 0;
}
Commit	Line	Data
2f90b865 AD	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
8c47eaa7	4	Copyright(c) 1999 - 2010 Intel Corporation.
2f90b865 AD	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	Linux NICS <linux.nics@intel.com>
	24	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	26
	27	*******************************************************************************/
	28
	29	#include "ixgbe.h"
	30	#include "ixgbe_type.h"
	31	#include "ixgbe_dcb.h"
	32	#include "ixgbe_dcb_82598.h"
	33
2f90b865 AD	34	/**
	35	* ixgbe_dcb_config_packet_buffers_82598 - Configure packet buffers
	36	* @hw: pointer to hardware structure
	37	* @dcb_config: pointer to ixgbe_dcb_config structure
	38	*
	39	* Configure packet buffers for DCB mode.
	40	*/
e855aac8 HE	41	static s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw,
e855aac8 HE	42	struct ixgbe_dcb_config *dcb_config)
2f90b865 AD	43	{
	44	s32 ret_val = 0;
	45	u32 value = IXGBE_RXPBSIZE_64KB;
	46	u8 i = 0;
	47
	48	/* Setup Rx packet buffer sizes */
	49	switch (dcb_config->rx_pba_cfg) {
	50	case pba_80_48:
	51	/* Setup the first four at 80KB */
	52	value = IXGBE_RXPBSIZE_80KB;
	53	for (; i < 4; i++)
	54	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
	55	/* Setup the last four at 48KB...don't re-init i */
	56	value = IXGBE_RXPBSIZE_48KB;
	57	/* Fall Through */
	58	case pba_equal:
	59	default:
	60	for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
	61	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
	62
	63	/* Setup Tx packet buffer sizes */
	64	for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
	65	IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i),
	66	IXGBE_TXPBSIZE_40KB);
	67	}
	68	break;
	69	}
	70
	71	return ret_val;
	72	}
	73
	74	/**
	75	* ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
	76	* @hw: pointer to hardware structure
	77	* @dcb_config: pointer to ixgbe_dcb_config structure
	78	*
	79	* Configure Rx Data Arbiter and credits for each traffic class.
	80	*/
5d5b7c39	81	static s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
2f90b865 AD	82	struct ixgbe_dcb_config *dcb_config)
	83	{
	84	struct tc_bw_alloc *p;
	85	u32 reg = 0;
	86	u32 credit_refill = 0;
	87	u32 credit_max = 0;
	88	u8 i = 0;
	89
	90	reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) \| IXGBE_RUPPBMR_MQA;
	91	IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
	92
	93	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
	94	/* Enable Arbiter */
	95	reg &= ~IXGBE_RMCS_ARBDIS;
	96	/* Enable Receive Recycle within the BWG */
	97	reg \|= IXGBE_RMCS_RRM;
	98	/* Enable Deficit Fixed Priority arbitration*/
	99	reg \|= IXGBE_RMCS_DFP;
	100
	101	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
	102
	103	/* Configure traffic class credits and priority */
	104	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
	105	p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG];
	106	credit_refill = p->data_credits_refill;
	107	credit_max = p->data_credits_max;
	108
	109	reg = credit_refill \| (credit_max << IXGBE_RT2CR_MCL_SHIFT);
	110
	111	if (p->prio_type == prio_link)
	112	reg \|= IXGBE_RT2CR_LSP;
	113
	114	IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
	115	}
	116
	117	reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
	118	reg \|= IXGBE_RDRXCTL_RDMTS_1_2;
	119	reg \|= IXGBE_RDRXCTL_MPBEN;
	120	reg \|= IXGBE_RDRXCTL_MCEN;
	121	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
	122
	123	reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
	124	/* Make sure there is enough descriptors before arbitration */
	125	reg &= ~IXGBE_RXCTRL_DMBYPS;
	126	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
	127
	128	return 0;
	129	}
	130
	131	/**
	132	* ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
	133	* @hw: pointer to hardware structure
	134	* @dcb_config: pointer to ixgbe_dcb_config structure
	135	*
	136	* Configure Tx Descriptor Arbiter and credits for each traffic class.
	137	*/
5d5b7c39	138	static s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
2f90b865 AD	139	struct ixgbe_dcb_config *dcb_config)
	140	{
	141	struct tc_bw_alloc *p;
	142	u32 reg, max_credits;
	143	u8 i;
	144
	145	reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
	146
	147	/* Enable arbiter */
	148	reg &= ~IXGBE_DPMCS_ARBDIS;
	149	if (!(dcb_config->round_robin_enable)) {
	150	/* Enable DFP and Recycle mode */
	151	reg \|= (IXGBE_DPMCS_TDPAC \| IXGBE_DPMCS_TRM);
	152	}
	153	reg \|= IXGBE_DPMCS_TSOEF;
	154	/* Configure Max TSO packet size 34KB including payload and headers */
	155	reg \|= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
	156
	157	IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
	158
	159	/* Configure traffic class credits and priority */
	160	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
	161	p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
	162	max_credits = dcb_config->tc_config[i].desc_credits_max;
	163	reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
	164	reg \|= p->data_credits_refill;
	165	reg \|= (u32)(p->bwg_id) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
	166
	167	if (p->prio_type == prio_group)
	168	reg \|= IXGBE_TDTQ2TCCR_GSP;
	169
	170	if (p->prio_type == prio_link)
	171	reg \|= IXGBE_TDTQ2TCCR_LSP;
	172
	173	IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
	174	}
	175
	176	return 0;
	177	}
	178
	179	/**
	180	* ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
	181	* @hw: pointer to hardware structure
	182	* @dcb_config: pointer to ixgbe_dcb_config structure
	183	*
	184	* Configure Tx Data Arbiter and credits for each traffic class.
	185	*/
5d5b7c39	186	static s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
2f90b865 AD	187	struct ixgbe_dcb_config *dcb_config)
	188	{
	189	struct tc_bw_alloc *p;
	190	u32 reg;
	191	u8 i;
	192
	193	reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
	194	/* Enable Data Plane Arbiter */
	195	reg &= ~IXGBE_PDPMCS_ARBDIS;
	196	/* Enable DFP and Transmit Recycle Mode */
	197	reg \|= (IXGBE_PDPMCS_TPPAC \| IXGBE_PDPMCS_TRM);
	198
	199	IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
	200
	201	/* Configure traffic class credits and priority */
	202	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
	203	p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
	204	reg = p->data_credits_refill;
	205	reg \|= (u32)(p->data_credits_max) << IXGBE_TDPT2TCCR_MCL_SHIFT;
	206	reg \|= (u32)(p->bwg_id) << IXGBE_TDPT2TCCR_BWG_SHIFT;
	207
	208	if (p->prio_type == prio_group)
	209	reg \|= IXGBE_TDPT2TCCR_GSP;
	210
	211	if (p->prio_type == prio_link)
	212	reg \|= IXGBE_TDPT2TCCR_LSP;
	213
	214	IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
	215	}
	216
	217	/* Enable Tx packet buffer division */
	218	reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
	219	reg \|= IXGBE_DTXCTL_ENDBUBD;
	220	IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
	221
	222	return 0;
	223	}
	224
	225	/**
	226	* ixgbe_dcb_config_pfc_82598 - Config priority flow control
	227	* @hw: pointer to hardware structure
	228	* @dcb_config: pointer to ixgbe_dcb_config structure
	229	*
	230	* Configure Priority Flow Control for each traffic class.
	231	*/
	232	s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
	233	struct ixgbe_dcb_config *dcb_config)
	234	{
	235	u32 reg, rx_pba_size;
	236	u8 i;
	237
264857b8 PWJ	238	if (!dcb_config->pfc_mode_enable)
	239	goto out;
	240
2f90b865 AD	241	/* Enable Transmit Priority Flow Control */
	242	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
	243	reg &= ~IXGBE_RMCS_TFCE_802_3X;
	244	/* correct the reporting of our flow control status */
2f90b865 AD	245	reg \|= IXGBE_RMCS_TFCE_PRIORITY;
	246	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
	247
	248	/* Enable Receive Priority Flow Control */
	249	reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
	250	reg &= ~IXGBE_FCTRL_RFCE;
	251	reg \|= IXGBE_FCTRL_RPFCE;
	252	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
	253
	254	/*
	255	* Configure flow control thresholds and enable priority flow control
	256	* for each traffic class.
	257	*/
	258	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
16b61beb JF	259	rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
	260	rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
	261	reg = (rx_pba_size - hw->fc.low_water) << 10;
2f90b865	262
2f90b865 AD	263	if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx \|\|
	264	dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
	265	reg \|= IXGBE_FCRTL_XONE;
	266
	267	IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg);
	268
16b61beb	269	reg = (rx_pba_size - hw->fc.high_water) << 10;
2f90b865 AD	270	if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx \|\|
	271	dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
	272	reg \|= IXGBE_FCRTH_FCEN;
	273
	274	IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
	275	}
	276
	277	/* Configure pause time */
	278	for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
	279	IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
	280
	281	/* Configure flow control refresh threshold value */
	282	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
	283
264857b8	284	out:
2f90b865 AD	285	return 0;
	286	}
	287
	288	/**
	289	* ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
	290	* @hw: pointer to hardware structure
	291	*
	292	* Configure queue statistics registers, all queues belonging to same traffic
	293	* class uses a single set of queue statistics counters.
	294	*/
5d5b7c39	295	static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
2f90b865 AD	296	{
	297	u32 reg = 0;
	298	u8 i = 0;
	299	u8 j = 0;
	300
	301	/* Receive Queues stats setting - 8 queues per statistics reg */
	302	for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
	303	reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
	304	reg \|= ((0x1010101) * j);
	305	IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
	306	reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
	307	reg \|= ((0x1010101) * j);
	308	IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
	309	}
	310	/* Transmit Queues stats setting - 4 queues per statistics reg */
	311	for (i = 0; i < 8; i++) {
	312	reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
	313	reg \|= ((0x1010101) * i);
	314	IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
	315	}
	316
	317	return 0;
	318	}
	319
	320	/**
	321	* ixgbe_dcb_hw_config_82598 - Config and enable DCB
	322	* @hw: pointer to hardware structure
	323	* @dcb_config: pointer to ixgbe_dcb_config structure
	324	*
	325	* Configure dcb settings and enable dcb mode.
	326	*/
	327	s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
	328	struct ixgbe_dcb_config *dcb_config)
	329	{
	330	ixgbe_dcb_config_packet_buffers_82598(hw, dcb_config);
	331	ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config);
	332	ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config);
	333	ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config);
	334	ixgbe_dcb_config_pfc_82598(hw, dcb_config);
	335	ixgbe_dcb_config_tc_stats_82598(hw);
	336
	337	return 0;
	338	}