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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
31 | ||
9c8eb720 | 32 | #include "ixgbe.h" |
9a799d71 AK |
33 | #include "ixgbe_phy.h" |
34 | ||
35 | #define IXGBE_82598_MAX_TX_QUEUES 32 | |
36 | #define IXGBE_82598_MAX_RX_QUEUES 64 | |
37 | #define IXGBE_82598_RAR_ENTRIES 16 | |
2c5645cf CL |
38 | #define IXGBE_82598_MC_TBL_SIZE 128 |
39 | #define IXGBE_82598_VFT_TBL_SIZE 128 | |
9a799d71 | 40 | |
8620a103 | 41 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
21ce849b MC |
42 | ixgbe_link_speed speed, |
43 | bool autoneg, | |
44 | bool autoneg_wait_to_complete); | |
c4900be0 DS |
45 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
46 | u8 *eeprom_data); | |
9a799d71 | 47 | |
202ff1ec MC |
48 | /** |
49 | * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout | |
50 | * @hw: pointer to the HW structure | |
51 | * | |
52 | * The defaults for 82598 should be in the range of 50us to 50ms, | |
53 | * however the hardware default for these parts is 500us to 1ms which is less | |
54 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
55 | * increase the value to either 10ms to 250ms for capability version 1 config, | |
56 | * or 16ms to 55ms for version 2. | |
57 | **/ | |
7b25cdba | 58 | static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) |
202ff1ec MC |
59 | { |
60 | struct ixgbe_adapter *adapter = hw->back; | |
61 | u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); | |
62 | u16 pcie_devctl2; | |
63 | ||
64 | /* only take action if timeout value is defaulted to 0 */ | |
65 | if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) | |
66 | goto out; | |
67 | ||
68 | /* | |
69 | * if capababilities version is type 1 we can write the | |
70 | * timeout of 10ms to 250ms through the GCR register | |
71 | */ | |
72 | if (!(gcr & IXGBE_GCR_CAP_VER2)) { | |
73 | gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; | |
74 | goto out; | |
75 | } | |
76 | ||
77 | /* | |
78 | * for version 2 capabilities we need to write the config space | |
79 | * directly in order to set the completion timeout value for | |
80 | * 16ms to 55ms | |
81 | */ | |
82 | pci_read_config_word(adapter->pdev, | |
83 | IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2); | |
84 | pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; | |
85 | pci_write_config_word(adapter->pdev, | |
86 | IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); | |
87 | out: | |
88 | /* disable completion timeout resend */ | |
89 | gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; | |
90 | IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); | |
91 | } | |
92 | ||
eb7f139c PWJ |
93 | /** |
94 | * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count | |
95 | * @hw: pointer to hardware structure | |
96 | * | |
97 | * Read PCIe configuration space, and get the MSI-X vector count from | |
98 | * the capabilities table. | |
99 | **/ | |
1aef47c4 | 100 | static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) |
eb7f139c PWJ |
101 | { |
102 | struct ixgbe_adapter *adapter = hw->back; | |
103 | u16 msix_count; | |
104 | pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS, | |
105 | &msix_count); | |
106 | msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; | |
107 | ||
108 | /* MSI-X count is zero-based in HW, so increment to give proper value */ | |
109 | msix_count++; | |
110 | ||
111 | return msix_count; | |
112 | } | |
113 | ||
c44ade9e JB |
114 | /** |
115 | */ | |
9a799d71 | 116 | static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) |
04f165ef PW |
117 | { |
118 | struct ixgbe_mac_info *mac = &hw->mac; | |
119 | ||
120 | /* Call PHY identify routine to get the phy type */ | |
121 | ixgbe_identify_phy_generic(hw); | |
122 | ||
123 | mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; | |
124 | mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; | |
125 | mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; | |
126 | mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; | |
127 | mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; | |
128 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
133 | /** | |
134 | * ixgbe_init_phy_ops_82598 - PHY/SFP specific init | |
135 | * @hw: pointer to hardware structure | |
136 | * | |
137 | * Initialize any function pointers that were not able to be | |
138 | * set during get_invariants because the PHY/SFP type was | |
139 | * not known. Perform the SFP init if necessary. | |
140 | * | |
141 | **/ | |
7b25cdba | 142 | static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) |
9a799d71 | 143 | { |
c44ade9e JB |
144 | struct ixgbe_mac_info *mac = &hw->mac; |
145 | struct ixgbe_phy_info *phy = &hw->phy; | |
c4900be0 DS |
146 | s32 ret_val = 0; |
147 | u16 list_offset, data_offset; | |
c44ade9e | 148 | |
04f165ef PW |
149 | /* Identify the PHY */ |
150 | phy->ops.identify(hw); | |
03cfa205 | 151 | |
04f165ef PW |
152 | /* Overwrite the link function pointers if copper PHY */ |
153 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { | |
154 | mac->ops.setup_link = &ixgbe_setup_copper_link_82598; | |
04f165ef | 155 | mac->ops.get_link_capabilities = |
a391f1d5 | 156 | &ixgbe_get_copper_link_capabilities_generic; |
04f165ef | 157 | } |
c44ade9e | 158 | |
04f165ef | 159 | switch (hw->phy.type) { |
0befdb3e JB |
160 | case ixgbe_phy_tn: |
161 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; | |
162 | phy->ops.get_firmware_version = | |
163 | &ixgbe_get_phy_firmware_version_tnx; | |
164 | break; | |
c4900be0 DS |
165 | case ixgbe_phy_nl: |
166 | phy->ops.reset = &ixgbe_reset_phy_nl; | |
167 | ||
168 | /* Call SFP+ identify routine to get the SFP+ module type */ | |
169 | ret_val = phy->ops.identify_sfp(hw); | |
170 | if (ret_val != 0) | |
171 | goto out; | |
172 | else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { | |
173 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
174 | goto out; | |
175 | } | |
176 | ||
177 | /* Check to see if SFP+ module is supported */ | |
178 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, | |
04f165ef PW |
179 | &list_offset, |
180 | &data_offset); | |
c4900be0 DS |
181 | if (ret_val != 0) { |
182 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
183 | goto out; | |
184 | } | |
185 | break; | |
c44ade9e JB |
186 | default: |
187 | break; | |
188 | } | |
189 | ||
c4900be0 DS |
190 | out: |
191 | return ret_val; | |
9a799d71 AK |
192 | } |
193 | ||
202ff1ec MC |
194 | /** |
195 | * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx | |
196 | * @hw: pointer to hardware structure | |
197 | * | |
198 | * Starts the hardware using the generic start_hw function. | |
199 | * Then set pcie completion timeout | |
200 | **/ | |
7b25cdba | 201 | static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) |
202ff1ec MC |
202 | { |
203 | s32 ret_val = 0; | |
204 | ||
205 | ret_val = ixgbe_start_hw_generic(hw); | |
206 | ||
207 | /* set the completion timeout for interface */ | |
208 | if (ret_val == 0) | |
209 | ixgbe_set_pcie_completion_timeout(hw); | |
210 | ||
211 | return ret_val; | |
212 | } | |
213 | ||
9a799d71 | 214 | /** |
c44ade9e | 215 | * ixgbe_get_link_capabilities_82598 - Determines link capabilities |
9a799d71 AK |
216 | * @hw: pointer to hardware structure |
217 | * @speed: pointer to link speed | |
218 | * @autoneg: boolean auto-negotiation value | |
219 | * | |
c44ade9e | 220 | * Determines the link capabilities by reading the AUTOC register. |
9a799d71 | 221 | **/ |
c44ade9e | 222 | static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, |
b4617240 PW |
223 | ixgbe_link_speed *speed, |
224 | bool *autoneg) | |
9a799d71 AK |
225 | { |
226 | s32 status = 0; | |
1eb99d5a | 227 | u32 autoc = 0; |
9a799d71 | 228 | |
3201d313 PWJ |
229 | /* |
230 | * Determine link capabilities based on the stored value of AUTOC, | |
1eb99d5a PW |
231 | * which represents EEPROM defaults. If AUTOC value has not been |
232 | * stored, use the current register value. | |
3201d313 | 233 | */ |
1eb99d5a PW |
234 | if (hw->mac.orig_link_settings_stored) |
235 | autoc = hw->mac.orig_autoc; | |
236 | else | |
237 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
238 | ||
239 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { | |
9a799d71 AK |
240 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
241 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
242 | *autoneg = false; | |
243 | break; | |
244 | ||
245 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: | |
246 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
247 | *autoneg = false; | |
248 | break; | |
249 | ||
250 | case IXGBE_AUTOC_LMS_1G_AN: | |
251 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
252 | *autoneg = true; | |
253 | break; | |
254 | ||
255 | case IXGBE_AUTOC_LMS_KX4_AN: | |
256 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
257 | *speed = IXGBE_LINK_SPEED_UNKNOWN; | |
1eb99d5a | 258 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
9a799d71 | 259 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
1eb99d5a | 260 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
9a799d71 AK |
261 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
262 | *autoneg = true; | |
263 | break; | |
264 | ||
265 | default: | |
266 | status = IXGBE_ERR_LINK_SETUP; | |
267 | break; | |
268 | } | |
269 | ||
270 | return status; | |
271 | } | |
272 | ||
9a799d71 AK |
273 | /** |
274 | * ixgbe_get_media_type_82598 - Determines media type | |
275 | * @hw: pointer to hardware structure | |
276 | * | |
277 | * Returns the media type (fiber, copper, backplane) | |
278 | **/ | |
279 | static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) | |
280 | { | |
281 | enum ixgbe_media_type media_type; | |
282 | ||
283 | /* Media type for I82598 is based on device ID */ | |
284 | switch (hw->device_id) { | |
1e336d0f | 285 | case IXGBE_DEV_ID_82598: |
2f21bdd3 | 286 | case IXGBE_DEV_ID_82598_BX: |
1e336d0f DS |
287 | media_type = ixgbe_media_type_backplane; |
288 | break; | |
9a799d71 AK |
289 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: |
290 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
c4900be0 DS |
291 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: |
292 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
b95f5fcb | 293 | case IXGBE_DEV_ID_82598EB_XF_LR: |
c4900be0 | 294 | case IXGBE_DEV_ID_82598EB_SFP_LOM: |
9a799d71 AK |
295 | media_type = ixgbe_media_type_fiber; |
296 | break; | |
6b1be199 PWJ |
297 | case IXGBE_DEV_ID_82598EB_CX4: |
298 | case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: | |
299 | media_type = ixgbe_media_type_cx4; | |
300 | break; | |
0befdb3e | 301 | case IXGBE_DEV_ID_82598AT: |
3845bec0 | 302 | case IXGBE_DEV_ID_82598AT2: |
0befdb3e JB |
303 | media_type = ixgbe_media_type_copper; |
304 | break; | |
9a799d71 AK |
305 | default: |
306 | media_type = ixgbe_media_type_unknown; | |
307 | break; | |
308 | } | |
309 | ||
310 | return media_type; | |
311 | } | |
312 | ||
c44ade9e | 313 | /** |
0ecc061d | 314 | * ixgbe_fc_enable_82598 - Enable flow control |
c44ade9e JB |
315 | * @hw: pointer to hardware structure |
316 | * @packetbuf_num: packet buffer number (0-7) | |
317 | * | |
0ecc061d | 318 | * Enable flow control according to the current settings. |
c44ade9e | 319 | **/ |
0ecc061d | 320 | static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) |
c44ade9e | 321 | { |
0ecc061d PWJ |
322 | s32 ret_val = 0; |
323 | u32 fctrl_reg; | |
c44ade9e | 324 | u32 rmcs_reg; |
0ecc061d | 325 | u32 reg; |
16b61beb | 326 | u32 rx_pba_size; |
a626e847 DS |
327 | u32 link_speed = 0; |
328 | bool link_up; | |
c44ade9e | 329 | |
620fa036 MC |
330 | #ifdef CONFIG_DCB |
331 | if (hw->fc.requested_mode == ixgbe_fc_pfc) | |
332 | goto out; | |
333 | ||
334 | #endif /* CONFIG_DCB */ | |
a626e847 DS |
335 | /* |
336 | * On 82598 having Rx FC on causes resets while doing 1G | |
337 | * so if it's on turn it off once we know link_speed. For | |
338 | * more details see 82598 Specification update. | |
339 | */ | |
340 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
341 | if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { | |
342 | switch (hw->fc.requested_mode) { | |
343 | case ixgbe_fc_full: | |
344 | hw->fc.requested_mode = ixgbe_fc_tx_pause; | |
345 | break; | |
346 | case ixgbe_fc_rx_pause: | |
347 | hw->fc.requested_mode = ixgbe_fc_none; | |
348 | break; | |
349 | default: | |
350 | /* no change */ | |
351 | break; | |
352 | } | |
353 | } | |
354 | ||
620fa036 MC |
355 | /* Negotiate the fc mode to use */ |
356 | ret_val = ixgbe_fc_autoneg(hw); | |
357 | if (ret_val) | |
358 | goto out; | |
359 | ||
360 | /* Disable any previous flow control settings */ | |
0ecc061d PWJ |
361 | fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
362 | fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); | |
c44ade9e JB |
363 | |
364 | rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
365 | rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); | |
366 | ||
367 | /* | |
0ecc061d | 368 | * The possible values of fc.current_mode are: |
c44ade9e | 369 | * 0: Flow control is completely disabled |
0ecc061d PWJ |
370 | * 1: Rx flow control is enabled (we can receive pause frames, |
371 | * but not send pause frames). | |
620fa036 | 372 | * 2: Tx flow control is enabled (we can send pause frames but |
0ecc061d | 373 | * we do not support receiving pause frames). |
c44ade9e JB |
374 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
375 | * other: Invalid. | |
620fa036 MC |
376 | #ifdef CONFIG_DCB |
377 | * 4: Priority Flow Control is enabled. | |
378 | #endif | |
c44ade9e | 379 | */ |
0ecc061d | 380 | switch (hw->fc.current_mode) { |
c44ade9e | 381 | case ixgbe_fc_none: |
620fa036 MC |
382 | /* |
383 | * Flow control is disabled by software override or autoneg. | |
384 | * The code below will actually disable it in the HW. | |
385 | */ | |
c44ade9e JB |
386 | break; |
387 | case ixgbe_fc_rx_pause: | |
388 | /* | |
0ecc061d PWJ |
389 | * Rx Flow control is enabled and Tx Flow control is |
390 | * disabled by software override. Since there really | |
391 | * isn't a way to advertise that we are capable of RX | |
392 | * Pause ONLY, we will advertise that we support both | |
393 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
394 | * disable the adapter's ability to send PAUSE frames. | |
c44ade9e | 395 | */ |
0ecc061d | 396 | fctrl_reg |= IXGBE_FCTRL_RFCE; |
c44ade9e JB |
397 | break; |
398 | case ixgbe_fc_tx_pause: | |
399 | /* | |
0ecc061d PWJ |
400 | * Tx Flow control is enabled, and Rx Flow control is |
401 | * disabled by software override. | |
c44ade9e JB |
402 | */ |
403 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; | |
404 | break; | |
405 | case ixgbe_fc_full: | |
0ecc061d PWJ |
406 | /* Flow control (both Rx and Tx) is enabled by SW override. */ |
407 | fctrl_reg |= IXGBE_FCTRL_RFCE; | |
c44ade9e JB |
408 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; |
409 | break; | |
620fa036 MC |
410 | #ifdef CONFIG_DCB |
411 | case ixgbe_fc_pfc: | |
412 | goto out; | |
413 | break; | |
414 | #endif /* CONFIG_DCB */ | |
c44ade9e | 415 | default: |
c44ade9e | 416 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
539e5f02 | 417 | ret_val = IXGBE_ERR_CONFIG; |
0ecc061d | 418 | goto out; |
c44ade9e JB |
419 | break; |
420 | } | |
421 | ||
620fa036 | 422 | /* Set 802.3x based flow control settings. */ |
2132d381 | 423 | fctrl_reg |= IXGBE_FCTRL_DPF; |
0ecc061d | 424 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); |
c44ade9e JB |
425 | IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); |
426 | ||
0ecc061d PWJ |
427 | /* Set up and enable Rx high/low water mark thresholds, enable XON. */ |
428 | if (hw->fc.current_mode & ixgbe_fc_tx_pause) { | |
16b61beb JF |
429 | rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); |
430 | rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT; | |
431 | ||
432 | reg = (rx_pba_size - hw->fc.low_water) << 6; | |
433 | if (hw->fc.send_xon) | |
434 | reg |= IXGBE_FCRTL_XONE; | |
435 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg); | |
436 | ||
437 | reg = (rx_pba_size - hw->fc.high_water) << 10; | |
438 | reg |= IXGBE_FCRTH_FCEN; | |
0ecc061d | 439 | |
16b61beb | 440 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg); |
c44ade9e JB |
441 | } |
442 | ||
0ecc061d | 443 | /* Configure pause time (2 TCs per register) */ |
264857b8 | 444 | reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); |
0ecc061d PWJ |
445 | if ((packetbuf_num & 1) == 0) |
446 | reg = (reg & 0xFFFF0000) | hw->fc.pause_time; | |
447 | else | |
448 | reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); | |
449 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); | |
450 | ||
c44ade9e JB |
451 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); |
452 | ||
0ecc061d PWJ |
453 | out: |
454 | return ret_val; | |
455 | } | |
456 | ||
9a799d71 | 457 | /** |
8620a103 | 458 | * ixgbe_start_mac_link_82598 - Configures MAC link settings |
9a799d71 AK |
459 | * @hw: pointer to hardware structure |
460 | * | |
461 | * Configures link settings based on values in the ixgbe_hw struct. | |
462 | * Restarts the link. Performs autonegotiation if needed. | |
463 | **/ | |
8620a103 MC |
464 | static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, |
465 | bool autoneg_wait_to_complete) | |
9a799d71 AK |
466 | { |
467 | u32 autoc_reg; | |
468 | u32 links_reg; | |
469 | u32 i; | |
470 | s32 status = 0; | |
471 | ||
9a799d71 | 472 | /* Restart link */ |
3201d313 | 473 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
9a799d71 AK |
474 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
475 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); | |
476 | ||
477 | /* Only poll for autoneg to complete if specified to do so */ | |
8620a103 | 478 | if (autoneg_wait_to_complete) { |
3201d313 PWJ |
479 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
480 | IXGBE_AUTOC_LMS_KX4_AN || | |
481 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == | |
482 | IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
9a799d71 AK |
483 | links_reg = 0; /* Just in case Autoneg time = 0 */ |
484 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { | |
485 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
486 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) | |
487 | break; | |
488 | msleep(100); | |
489 | } | |
490 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { | |
491 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; | |
c44ade9e | 492 | hw_dbg(hw, "Autonegotiation did not complete.\n"); |
9a799d71 AK |
493 | } |
494 | } | |
495 | } | |
496 | ||
9a799d71 AK |
497 | /* Add delay to filter out noises during initial link setup */ |
498 | msleep(50); | |
499 | ||
500 | return status; | |
501 | } | |
502 | ||
734e979f MC |
503 | /** |
504 | * ixgbe_validate_link_ready - Function looks for phy link | |
505 | * @hw: pointer to hardware structure | |
506 | * | |
507 | * Function indicates success when phy link is available. If phy is not ready | |
508 | * within 5 seconds of MAC indicating link, the function returns error. | |
509 | **/ | |
510 | static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) | |
511 | { | |
512 | u32 timeout; | |
513 | u16 an_reg; | |
514 | ||
515 | if (hw->device_id != IXGBE_DEV_ID_82598AT2) | |
516 | return 0; | |
517 | ||
518 | for (timeout = 0; | |
519 | timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { | |
520 | hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); | |
521 | ||
522 | if ((an_reg & MDIO_AN_STAT1_COMPLETE) && | |
523 | (an_reg & MDIO_STAT1_LSTATUS)) | |
524 | break; | |
525 | ||
526 | msleep(100); | |
527 | } | |
528 | ||
529 | if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { | |
530 | hw_dbg(hw, "Link was indicated but link is down\n"); | |
531 | return IXGBE_ERR_LINK_SETUP; | |
532 | } | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
9a799d71 AK |
537 | /** |
538 | * ixgbe_check_mac_link_82598 - Get link/speed status | |
539 | * @hw: pointer to hardware structure | |
540 | * @speed: pointer to link speed | |
541 | * @link_up: true is link is up, false otherwise | |
cf8280ee | 542 | * @link_up_wait_to_complete: bool used to wait for link up or not |
9a799d71 AK |
543 | * |
544 | * Reads the links register to determine if link is up and the current speed | |
545 | **/ | |
b4617240 PW |
546 | static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, |
547 | ixgbe_link_speed *speed, bool *link_up, | |
548 | bool link_up_wait_to_complete) | |
9a799d71 AK |
549 | { |
550 | u32 links_reg; | |
cf8280ee | 551 | u32 i; |
c4900be0 DS |
552 | u16 link_reg, adapt_comp_reg; |
553 | ||
554 | /* | |
555 | * SERDES PHY requires us to read link status from register 0xC79F. | |
556 | * Bit 0 set indicates link is up/ready; clear indicates link down. | |
557 | * 0xC00C is read to check that the XAUI lanes are active. Bit 0 | |
558 | * clear indicates active; set indicates inactive. | |
559 | */ | |
560 | if (hw->phy.type == ixgbe_phy_nl) { | |
6b73e10d BH |
561 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); |
562 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); | |
563 | hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, | |
c4900be0 DS |
564 | &adapt_comp_reg); |
565 | if (link_up_wait_to_complete) { | |
566 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
567 | if ((link_reg & 1) && | |
568 | ((adapt_comp_reg & 1) == 0)) { | |
569 | *link_up = true; | |
570 | break; | |
571 | } else { | |
572 | *link_up = false; | |
573 | } | |
574 | msleep(100); | |
575 | hw->phy.ops.read_reg(hw, 0xC79F, | |
6b73e10d | 576 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
577 | &link_reg); |
578 | hw->phy.ops.read_reg(hw, 0xC00C, | |
6b73e10d | 579 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
580 | &adapt_comp_reg); |
581 | } | |
582 | } else { | |
583 | if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) | |
584 | *link_up = true; | |
585 | else | |
586 | *link_up = false; | |
587 | } | |
588 | ||
589 | if (*link_up == false) | |
590 | goto out; | |
591 | } | |
9a799d71 AK |
592 | |
593 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
cf8280ee JB |
594 | if (link_up_wait_to_complete) { |
595 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
596 | if (links_reg & IXGBE_LINKS_UP) { | |
597 | *link_up = true; | |
598 | break; | |
599 | } else { | |
600 | *link_up = false; | |
601 | } | |
602 | msleep(100); | |
603 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
604 | } | |
605 | } else { | |
606 | if (links_reg & IXGBE_LINKS_UP) | |
607 | *link_up = true; | |
608 | else | |
609 | *link_up = false; | |
610 | } | |
9a799d71 AK |
611 | |
612 | if (links_reg & IXGBE_LINKS_SPEED) | |
613 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
614 | else | |
615 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
616 | ||
734e979f MC |
617 | if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) && |
618 | (ixgbe_validate_link_ready(hw) != 0)) | |
619 | *link_up = false; | |
620 | ||
620fa036 MC |
621 | /* if link is down, zero out the current_mode */ |
622 | if (*link_up == false) { | |
623 | hw->fc.current_mode = ixgbe_fc_none; | |
624 | hw->fc.fc_was_autonegged = false; | |
625 | } | |
c4900be0 | 626 | out: |
9a799d71 AK |
627 | return 0; |
628 | } | |
629 | ||
c44ade9e | 630 | |
9a799d71 | 631 | /** |
8620a103 | 632 | * ixgbe_setup_mac_link_82598 - Set MAC link speed |
9a799d71 AK |
633 | * @hw: pointer to hardware structure |
634 | * @speed: new link speed | |
635 | * @autoneg: true if auto-negotiation enabled | |
636 | * @autoneg_wait_to_complete: true if waiting is needed to complete | |
637 | * | |
638 | * Set the link speed in the AUTOC register and restarts link. | |
639 | **/ | |
8620a103 | 640 | static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, |
3201d313 PWJ |
641 | ixgbe_link_speed speed, bool autoneg, |
642 | bool autoneg_wait_to_complete) | |
9a799d71 | 643 | { |
3201d313 PWJ |
644 | s32 status = 0; |
645 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; | |
646 | u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
647 | u32 autoc = curr_autoc; | |
648 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; | |
9a799d71 | 649 | |
3201d313 PWJ |
650 | /* Check to see if speed passed in is supported. */ |
651 | ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); | |
652 | speed &= link_capabilities; | |
653 | ||
654 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) | |
9a799d71 | 655 | status = IXGBE_ERR_LINK_SETUP; |
3201d313 PWJ |
656 | |
657 | /* Set KX4/KX support according to speed requested */ | |
658 | else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || | |
659 | link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
660 | autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; | |
661 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
662 | autoc |= IXGBE_AUTOC_KX4_SUPP; | |
663 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | |
664 | autoc |= IXGBE_AUTOC_KX_SUPP; | |
665 | if (autoc != curr_autoc) | |
666 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); | |
9a799d71 AK |
667 | } |
668 | ||
669 | if (status == 0) { | |
9a799d71 AK |
670 | /* |
671 | * Setup and restart the link based on the new values in | |
672 | * ixgbe_hw This will write the AUTOC register based on the new | |
673 | * stored values | |
674 | */ | |
8620a103 | 675 | status = ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); |
9a799d71 AK |
676 | } |
677 | ||
678 | return status; | |
679 | } | |
680 | ||
681 | ||
682 | /** | |
8620a103 | 683 | * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field |
9a799d71 AK |
684 | * @hw: pointer to hardware structure |
685 | * @speed: new link speed | |
686 | * @autoneg: true if autonegotiation enabled | |
687 | * @autoneg_wait_to_complete: true if waiting is needed to complete | |
688 | * | |
689 | * Sets the link speed in the AUTOC register in the MAC and restarts link. | |
690 | **/ | |
8620a103 | 691 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
b4617240 PW |
692 | ixgbe_link_speed speed, |
693 | bool autoneg, | |
694 | bool autoneg_wait_to_complete) | |
9a799d71 | 695 | { |
c44ade9e | 696 | s32 status; |
9a799d71 AK |
697 | |
698 | /* Setup the PHY according to input speed */ | |
b4617240 PW |
699 | status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, |
700 | autoneg_wait_to_complete); | |
3957d63d | 701 | |
3957d63d | 702 | /* Set up MAC */ |
8620a103 | 703 | ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); |
9a799d71 AK |
704 | |
705 | return status; | |
706 | } | |
707 | ||
708 | /** | |
709 | * ixgbe_reset_hw_82598 - Performs hardware reset | |
710 | * @hw: pointer to hardware structure | |
711 | * | |
c44ade9e | 712 | * Resets the hardware by resetting the transmit and receive units, masks and |
9a799d71 AK |
713 | * clears all interrupts, performing a PHY reset, and performing a link (MAC) |
714 | * reset. | |
715 | **/ | |
716 | static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) | |
717 | { | |
718 | s32 status = 0; | |
8ca783ab | 719 | s32 phy_status = 0; |
9a799d71 AK |
720 | u32 ctrl; |
721 | u32 gheccr; | |
722 | u32 i; | |
723 | u32 autoc; | |
724 | u8 analog_val; | |
725 | ||
726 | /* Call adapter stop to disable tx/rx and clear interrupts */ | |
c44ade9e | 727 | hw->mac.ops.stop_adapter(hw); |
9a799d71 AK |
728 | |
729 | /* | |
c44ade9e JB |
730 | * Power up the Atlas Tx lanes if they are currently powered down. |
731 | * Atlas Tx lanes are powered down for MAC loopback tests, but | |
9a799d71 AK |
732 | * they are not automatically restored on reset. |
733 | */ | |
c44ade9e | 734 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); |
9a799d71 | 735 | if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { |
c44ade9e JB |
736 | /* Enable Tx Atlas so packets can be transmitted again */ |
737 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, | |
738 | &analog_val); | |
9a799d71 | 739 | analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; |
c44ade9e JB |
740 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, |
741 | analog_val); | |
9a799d71 | 742 | |
c44ade9e JB |
743 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
744 | &analog_val); | |
9a799d71 | 745 | analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; |
c44ade9e JB |
746 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
747 | analog_val); | |
9a799d71 | 748 | |
c44ade9e JB |
749 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
750 | &analog_val); | |
9a799d71 | 751 | analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; |
c44ade9e JB |
752 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
753 | analog_val); | |
9a799d71 | 754 | |
c44ade9e JB |
755 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
756 | &analog_val); | |
9a799d71 | 757 | analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; |
c44ade9e JB |
758 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
759 | analog_val); | |
9a799d71 AK |
760 | } |
761 | ||
762 | /* Reset PHY */ | |
04f165ef PW |
763 | if (hw->phy.reset_disable == false) { |
764 | /* PHY ops must be identified and initialized prior to reset */ | |
765 | ||
766 | /* Init PHY and function pointers, perform SFP setup */ | |
8ca783ab DS |
767 | phy_status = hw->phy.ops.init(hw); |
768 | if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
04f165ef | 769 | goto reset_hw_out; |
8ca783ab DS |
770 | else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) |
771 | goto no_phy_reset; | |
772 | ||
04f165ef | 773 | |
c44ade9e | 774 | hw->phy.ops.reset(hw); |
04f165ef | 775 | } |
9a799d71 | 776 | |
8ca783ab | 777 | no_phy_reset: |
9a799d71 AK |
778 | /* |
779 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | |
780 | * access and verify no pending requests before reset | |
781 | */ | |
04f165ef PW |
782 | status = ixgbe_disable_pcie_master(hw); |
783 | if (status != 0) { | |
9a799d71 AK |
784 | status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
785 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
786 | } | |
787 | ||
788 | /* | |
789 | * Issue global reset to the MAC. This needs to be a SW reset. | |
790 | * If link reset is used, it might reset the MAC when mng is using it | |
791 | */ | |
792 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
793 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); | |
794 | IXGBE_WRITE_FLUSH(hw); | |
795 | ||
796 | /* Poll for reset bit to self-clear indicating reset is complete */ | |
797 | for (i = 0; i < 10; i++) { | |
798 | udelay(1); | |
799 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
800 | if (!(ctrl & IXGBE_CTRL_RST)) | |
801 | break; | |
802 | } | |
803 | if (ctrl & IXGBE_CTRL_RST) { | |
804 | status = IXGBE_ERR_RESET_FAILED; | |
805 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
806 | } | |
807 | ||
808 | msleep(50); | |
809 | ||
810 | gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); | |
811 | gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); | |
812 | IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); | |
813 | ||
814 | /* | |
3201d313 PWJ |
815 | * Store the original AUTOC value if it has not been |
816 | * stored off yet. Otherwise restore the stored original | |
817 | * AUTOC value since the reset operation sets back to deaults. | |
9a799d71 AK |
818 | */ |
819 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
3201d313 PWJ |
820 | if (hw->mac.orig_link_settings_stored == false) { |
821 | hw->mac.orig_autoc = autoc; | |
822 | hw->mac.orig_link_settings_stored = true; | |
823 | } else if (autoc != hw->mac.orig_autoc) { | |
824 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); | |
9a799d71 AK |
825 | } |
826 | ||
aca6bee7 WJP |
827 | /* |
828 | * Store MAC address from RAR0, clear receive address registers, and | |
829 | * clear the multicast table | |
830 | */ | |
831 | hw->mac.ops.init_rx_addrs(hw); | |
832 | ||
9a799d71 | 833 | /* Store the permanent mac address */ |
c44ade9e | 834 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); |
9a799d71 | 835 | |
04f165ef | 836 | reset_hw_out: |
8ca783ab DS |
837 | if (phy_status) |
838 | status = phy_status; | |
839 | ||
9a799d71 AK |
840 | return status; |
841 | } | |
842 | ||
c44ade9e JB |
843 | /** |
844 | * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address | |
845 | * @hw: pointer to hardware struct | |
846 | * @rar: receive address register index to associate with a VMDq index | |
847 | * @vmdq: VMDq set index | |
848 | **/ | |
e855aac8 | 849 | static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) |
c44ade9e JB |
850 | { |
851 | u32 rar_high; | |
852 | ||
853 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
854 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
855 | rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); | |
856 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
857 | return 0; | |
858 | } | |
859 | ||
860 | /** | |
861 | * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address | |
862 | * @hw: pointer to hardware struct | |
863 | * @rar: receive address register index to associate with a VMDq index | |
864 | * @vmdq: VMDq clear index (not used in 82598, but elsewhere) | |
865 | **/ | |
866 | static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) | |
867 | { | |
868 | u32 rar_high; | |
869 | u32 rar_entries = hw->mac.num_rar_entries; | |
870 | ||
871 | if (rar < rar_entries) { | |
872 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
873 | if (rar_high & IXGBE_RAH_VIND_MASK) { | |
874 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
875 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
876 | } | |
877 | } else { | |
878 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); | |
879 | } | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
884 | /** | |
885 | * ixgbe_set_vfta_82598 - Set VLAN filter table | |
886 | * @hw: pointer to hardware structure | |
887 | * @vlan: VLAN id to write to VLAN filter | |
888 | * @vind: VMDq output index that maps queue to VLAN id in VFTA | |
889 | * @vlan_on: boolean flag to turn on/off VLAN in VFTA | |
890 | * | |
891 | * Turn on/off specified VLAN in the VLAN filter table. | |
892 | **/ | |
e855aac8 HE |
893 | static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
894 | bool vlan_on) | |
c44ade9e JB |
895 | { |
896 | u32 regindex; | |
897 | u32 bitindex; | |
898 | u32 bits; | |
899 | u32 vftabyte; | |
900 | ||
901 | if (vlan > 4095) | |
902 | return IXGBE_ERR_PARAM; | |
903 | ||
904 | /* Determine 32-bit word position in array */ | |
905 | regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ | |
906 | ||
907 | /* Determine the location of the (VMD) queue index */ | |
908 | vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ | |
909 | bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ | |
910 | ||
911 | /* Set the nibble for VMD queue index */ | |
912 | bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); | |
913 | bits &= (~(0x0F << bitindex)); | |
914 | bits |= (vind << bitindex); | |
915 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); | |
916 | ||
917 | /* Determine the location of the bit for this VLAN id */ | |
918 | bitindex = vlan & 0x1F; /* lower five bits */ | |
919 | ||
920 | bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); | |
921 | if (vlan_on) | |
922 | /* Turn on this VLAN id */ | |
923 | bits |= (1 << bitindex); | |
924 | else | |
925 | /* Turn off this VLAN id */ | |
926 | bits &= ~(1 << bitindex); | |
927 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); | |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
932 | /** | |
933 | * ixgbe_clear_vfta_82598 - Clear VLAN filter table | |
934 | * @hw: pointer to hardware structure | |
935 | * | |
936 | * Clears the VLAN filer table, and the VMDq index associated with the filter | |
937 | **/ | |
938 | static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) | |
939 | { | |
940 | u32 offset; | |
941 | u32 vlanbyte; | |
942 | ||
943 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
944 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); | |
945 | ||
946 | for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) | |
947 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
948 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), | |
b4617240 | 949 | 0); |
c44ade9e JB |
950 | |
951 | return 0; | |
952 | } | |
953 | ||
c44ade9e JB |
954 | /** |
955 | * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register | |
956 | * @hw: pointer to hardware structure | |
957 | * @reg: analog register to read | |
958 | * @val: read value | |
959 | * | |
960 | * Performs read operation to Atlas analog register specified. | |
961 | **/ | |
e855aac8 | 962 | static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) |
c44ade9e JB |
963 | { |
964 | u32 atlas_ctl; | |
965 | ||
966 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, | |
967 | IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); | |
968 | IXGBE_WRITE_FLUSH(hw); | |
969 | udelay(10); | |
970 | atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); | |
971 | *val = (u8)atlas_ctl; | |
972 | ||
973 | return 0; | |
974 | } | |
975 | ||
976 | /** | |
977 | * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register | |
978 | * @hw: pointer to hardware structure | |
979 | * @reg: atlas register to write | |
980 | * @val: value to write | |
981 | * | |
982 | * Performs write operation to Atlas analog register specified. | |
983 | **/ | |
e855aac8 | 984 | static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) |
c44ade9e JB |
985 | { |
986 | u32 atlas_ctl; | |
987 | ||
988 | atlas_ctl = (reg << 8) | val; | |
989 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); | |
990 | IXGBE_WRITE_FLUSH(hw); | |
991 | udelay(10); | |
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
c4900be0 DS |
996 | /** |
997 | * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module | |
998 | * over I2C interface through an intermediate phy. | |
999 | * @hw: pointer to hardware structure | |
1000 | * @byte_offset: EEPROM byte offset to read | |
1001 | * @eeprom_data: value read | |
1002 | * | |
1003 | * Performs byte read operation to SFP module's EEPROM over I2C interface. | |
1004 | **/ | |
e855aac8 HE |
1005 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
1006 | u8 *eeprom_data) | |
c4900be0 DS |
1007 | { |
1008 | s32 status = 0; | |
1009 | u16 sfp_addr = 0; | |
1010 | u16 sfp_data = 0; | |
1011 | u16 sfp_stat = 0; | |
1012 | u32 i; | |
1013 | ||
1014 | if (hw->phy.type == ixgbe_phy_nl) { | |
1015 | /* | |
1016 | * phy SDA/SCL registers are at addresses 0xC30A to | |
1017 | * 0xC30D. These registers are used to talk to the SFP+ | |
1018 | * module's EEPROM through the SDA/SCL (I2C) interface. | |
1019 | */ | |
1020 | sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; | |
1021 | sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); | |
1022 | hw->phy.ops.write_reg(hw, | |
1023 | IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, | |
6b73e10d | 1024 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
1025 | sfp_addr); |
1026 | ||
1027 | /* Poll status */ | |
1028 | for (i = 0; i < 100; i++) { | |
1029 | hw->phy.ops.read_reg(hw, | |
1030 | IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, | |
6b73e10d | 1031 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
1032 | &sfp_stat); |
1033 | sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; | |
1034 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) | |
1035 | break; | |
1036 | msleep(10); | |
1037 | } | |
1038 | ||
1039 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { | |
1040 | hw_dbg(hw, "EEPROM read did not pass.\n"); | |
1041 | status = IXGBE_ERR_SFP_NOT_PRESENT; | |
1042 | goto out; | |
1043 | } | |
1044 | ||
1045 | /* Read data */ | |
1046 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, | |
6b73e10d | 1047 | MDIO_MMD_PMAPMD, &sfp_data); |
c4900be0 DS |
1048 | |
1049 | *eeprom_data = (u8)(sfp_data >> 8); | |
1050 | } else { | |
1051 | status = IXGBE_ERR_PHY; | |
1052 | goto out; | |
1053 | } | |
1054 | ||
1055 | out: | |
1056 | return status; | |
1057 | } | |
1058 | ||
c44ade9e JB |
1059 | /** |
1060 | * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type | |
1061 | * @hw: pointer to hardware structure | |
1062 | * | |
1063 | * Determines physical layer capabilities of the current configuration. | |
1064 | **/ | |
11afc1b1 | 1065 | static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) |
c44ade9e | 1066 | { |
11afc1b1 | 1067 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; |
04193058 PWJ |
1068 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
1069 | u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; | |
1070 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; | |
1071 | u16 ext_ability = 0; | |
1072 | ||
1073 | hw->phy.ops.identify(hw); | |
1074 | ||
1075 | /* Copper PHY must be checked before AUTOC LMS to determine correct | |
1076 | * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ | |
1077 | if (hw->phy.type == ixgbe_phy_tn || | |
1078 | hw->phy.type == ixgbe_phy_cu_unknown) { | |
6b73e10d BH |
1079 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, |
1080 | &ext_ability); | |
1081 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) | |
04193058 | 1082 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
6b73e10d | 1083 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) |
04193058 | 1084 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
6b73e10d | 1085 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) |
04193058 PWJ |
1086 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
1087 | goto out; | |
1088 | } | |
c44ade9e | 1089 | |
04193058 PWJ |
1090 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
1091 | case IXGBE_AUTOC_LMS_1G_AN: | |
1092 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: | |
1093 | if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) | |
1094 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1095 | else | |
1096 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; | |
c4900be0 | 1097 | break; |
04193058 PWJ |
1098 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
1099 | if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) | |
1100 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; | |
1101 | else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) | |
1102 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
1103 | else /* XAUI */ | |
1104 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
c44ade9e | 1105 | break; |
04193058 PWJ |
1106 | case IXGBE_AUTOC_LMS_KX4_AN: |
1107 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
1108 | if (autoc & IXGBE_AUTOC_KX_SUPP) | |
1109 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1110 | if (autoc & IXGBE_AUTOC_KX4_SUPP) | |
1111 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
c44ade9e | 1112 | break; |
04193058 | 1113 | default: |
0befdb3e | 1114 | break; |
04193058 PWJ |
1115 | } |
1116 | ||
1117 | if (hw->phy.type == ixgbe_phy_nl) { | |
c4900be0 DS |
1118 | hw->phy.ops.identify_sfp(hw); |
1119 | ||
1120 | switch (hw->phy.sfp_type) { | |
1121 | case ixgbe_sfp_type_da_cu: | |
1122 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1123 | break; | |
1124 | case ixgbe_sfp_type_sr: | |
1125 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1126 | break; | |
1127 | case ixgbe_sfp_type_lr: | |
1128 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1129 | break; | |
1130 | default: | |
1131 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
1132 | break; | |
1133 | } | |
04193058 | 1134 | } |
c44ade9e | 1135 | |
04193058 PWJ |
1136 | switch (hw->device_id) { |
1137 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: | |
1138 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1139 | break; | |
1140 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: | |
1141 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
1142 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
1143 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1144 | break; | |
1145 | case IXGBE_DEV_ID_82598EB_XF_LR: | |
1146 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1147 | break; | |
c44ade9e | 1148 | default: |
c44ade9e JB |
1149 | break; |
1150 | } | |
1151 | ||
04193058 | 1152 | out: |
c44ade9e JB |
1153 | return physical_layer; |
1154 | } | |
1155 | ||
9a799d71 | 1156 | static struct ixgbe_mac_operations mac_ops_82598 = { |
c44ade9e JB |
1157 | .init_hw = &ixgbe_init_hw_generic, |
1158 | .reset_hw = &ixgbe_reset_hw_82598, | |
202ff1ec | 1159 | .start_hw = &ixgbe_start_hw_82598, |
c44ade9e | 1160 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
9a799d71 | 1161 | .get_media_type = &ixgbe_get_media_type_82598, |
c44ade9e | 1162 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, |
11afc1b1 | 1163 | .enable_rx_dma = &ixgbe_enable_rx_dma_generic, |
c44ade9e JB |
1164 | .get_mac_addr = &ixgbe_get_mac_addr_generic, |
1165 | .stop_adapter = &ixgbe_stop_adapter_generic, | |
11afc1b1 PW |
1166 | .get_bus_info = &ixgbe_get_bus_info_generic, |
1167 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, | |
c44ade9e JB |
1168 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, |
1169 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, | |
3957d63d | 1170 | .setup_link = &ixgbe_setup_mac_link_82598, |
c44ade9e JB |
1171 | .check_link = &ixgbe_check_mac_link_82598, |
1172 | .get_link_capabilities = &ixgbe_get_link_capabilities_82598, | |
1173 | .led_on = &ixgbe_led_on_generic, | |
1174 | .led_off = &ixgbe_led_off_generic, | |
87c12017 PW |
1175 | .blink_led_start = &ixgbe_blink_led_start_generic, |
1176 | .blink_led_stop = &ixgbe_blink_led_stop_generic, | |
c44ade9e JB |
1177 | .set_rar = &ixgbe_set_rar_generic, |
1178 | .clear_rar = &ixgbe_clear_rar_generic, | |
1179 | .set_vmdq = &ixgbe_set_vmdq_82598, | |
1180 | .clear_vmdq = &ixgbe_clear_vmdq_82598, | |
1181 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, | |
1182 | .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, | |
1183 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, | |
1184 | .enable_mc = &ixgbe_enable_mc_generic, | |
1185 | .disable_mc = &ixgbe_disable_mc_generic, | |
1186 | .clear_vfta = &ixgbe_clear_vfta_82598, | |
1187 | .set_vfta = &ixgbe_set_vfta_82598, | |
620fa036 | 1188 | .fc_enable = &ixgbe_fc_enable_82598, |
c44ade9e JB |
1189 | }; |
1190 | ||
1191 | static struct ixgbe_eeprom_operations eeprom_ops_82598 = { | |
1192 | .init_params = &ixgbe_init_eeprom_params_generic, | |
21ce849b | 1193 | .read = &ixgbe_read_eerd_generic, |
a391f1d5 | 1194 | .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, |
c44ade9e JB |
1195 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, |
1196 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, | |
1197 | }; | |
1198 | ||
1199 | static struct ixgbe_phy_operations phy_ops_82598 = { | |
1200 | .identify = &ixgbe_identify_phy_generic, | |
c4900be0 | 1201 | .identify_sfp = &ixgbe_identify_sfp_module_generic, |
04f165ef | 1202 | .init = &ixgbe_init_phy_ops_82598, |
c44ade9e JB |
1203 | .reset = &ixgbe_reset_phy_generic, |
1204 | .read_reg = &ixgbe_read_phy_reg_generic, | |
1205 | .write_reg = &ixgbe_write_phy_reg_generic, | |
1206 | .setup_link = &ixgbe_setup_phy_link_generic, | |
1207 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, | |
c4900be0 | 1208 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, |
119fc60a | 1209 | .check_overtemp = &ixgbe_tn_check_overtemp, |
9a799d71 AK |
1210 | }; |
1211 | ||
3957d63d | 1212 | struct ixgbe_info ixgbe_82598_info = { |
9a799d71 AK |
1213 | .mac = ixgbe_mac_82598EB, |
1214 | .get_invariants = &ixgbe_get_invariants_82598, | |
1215 | .mac_ops = &mac_ops_82598, | |
c44ade9e JB |
1216 | .eeprom_ops = &eeprom_ops_82598, |
1217 | .phy_ops = &phy_ops_82598, | |
9a799d71 AK |
1218 | }; |
1219 |