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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
31 | ||
9c8eb720 | 32 | #include "ixgbe.h" |
9a799d71 AK |
33 | #include "ixgbe_phy.h" |
34 | ||
35 | #define IXGBE_82598_MAX_TX_QUEUES 32 | |
36 | #define IXGBE_82598_MAX_RX_QUEUES 64 | |
37 | #define IXGBE_82598_RAR_ENTRIES 16 | |
2c5645cf CL |
38 | #define IXGBE_82598_MC_TBL_SIZE 128 |
39 | #define IXGBE_82598_VFT_TBL_SIZE 128 | |
9a799d71 | 40 | |
c44ade9e JB |
41 | static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, |
42 | ixgbe_link_speed *speed, | |
43 | bool *autoneg); | |
8620a103 | 44 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
21ce849b MC |
45 | ixgbe_link_speed speed, |
46 | bool autoneg, | |
47 | bool autoneg_wait_to_complete); | |
c4900be0 DS |
48 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
49 | u8 *eeprom_data); | |
9a799d71 | 50 | |
202ff1ec MC |
51 | /** |
52 | * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout | |
53 | * @hw: pointer to the HW structure | |
54 | * | |
55 | * The defaults for 82598 should be in the range of 50us to 50ms, | |
56 | * however the hardware default for these parts is 500us to 1ms which is less | |
57 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
58 | * increase the value to either 10ms to 250ms for capability version 1 config, | |
59 | * or 16ms to 55ms for version 2. | |
60 | **/ | |
7b25cdba | 61 | static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) |
202ff1ec MC |
62 | { |
63 | struct ixgbe_adapter *adapter = hw->back; | |
64 | u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); | |
65 | u16 pcie_devctl2; | |
66 | ||
67 | /* only take action if timeout value is defaulted to 0 */ | |
68 | if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) | |
69 | goto out; | |
70 | ||
71 | /* | |
72 | * if capababilities version is type 1 we can write the | |
73 | * timeout of 10ms to 250ms through the GCR register | |
74 | */ | |
75 | if (!(gcr & IXGBE_GCR_CAP_VER2)) { | |
76 | gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; | |
77 | goto out; | |
78 | } | |
79 | ||
80 | /* | |
81 | * for version 2 capabilities we need to write the config space | |
82 | * directly in order to set the completion timeout value for | |
83 | * 16ms to 55ms | |
84 | */ | |
85 | pci_read_config_word(adapter->pdev, | |
86 | IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2); | |
87 | pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; | |
88 | pci_write_config_word(adapter->pdev, | |
89 | IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); | |
90 | out: | |
91 | /* disable completion timeout resend */ | |
92 | gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; | |
93 | IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); | |
94 | } | |
95 | ||
eb7f139c PWJ |
96 | /** |
97 | * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count | |
98 | * @hw: pointer to hardware structure | |
99 | * | |
100 | * Read PCIe configuration space, and get the MSI-X vector count from | |
101 | * the capabilities table. | |
102 | **/ | |
1aef47c4 | 103 | static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) |
eb7f139c PWJ |
104 | { |
105 | struct ixgbe_adapter *adapter = hw->back; | |
106 | u16 msix_count; | |
107 | pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS, | |
108 | &msix_count); | |
109 | msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; | |
110 | ||
111 | /* MSI-X count is zero-based in HW, so increment to give proper value */ | |
112 | msix_count++; | |
113 | ||
114 | return msix_count; | |
115 | } | |
116 | ||
c44ade9e JB |
117 | /** |
118 | */ | |
9a799d71 | 119 | static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) |
04f165ef PW |
120 | { |
121 | struct ixgbe_mac_info *mac = &hw->mac; | |
122 | ||
123 | /* Call PHY identify routine to get the phy type */ | |
124 | ixgbe_identify_phy_generic(hw); | |
125 | ||
126 | mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; | |
127 | mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; | |
128 | mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; | |
129 | mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; | |
130 | mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; | |
131 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | /** | |
137 | * ixgbe_init_phy_ops_82598 - PHY/SFP specific init | |
138 | * @hw: pointer to hardware structure | |
139 | * | |
140 | * Initialize any function pointers that were not able to be | |
141 | * set during get_invariants because the PHY/SFP type was | |
142 | * not known. Perform the SFP init if necessary. | |
143 | * | |
144 | **/ | |
7b25cdba | 145 | static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) |
9a799d71 | 146 | { |
c44ade9e JB |
147 | struct ixgbe_mac_info *mac = &hw->mac; |
148 | struct ixgbe_phy_info *phy = &hw->phy; | |
c4900be0 DS |
149 | s32 ret_val = 0; |
150 | u16 list_offset, data_offset; | |
c44ade9e | 151 | |
04f165ef PW |
152 | /* Identify the PHY */ |
153 | phy->ops.identify(hw); | |
03cfa205 | 154 | |
04f165ef PW |
155 | /* Overwrite the link function pointers if copper PHY */ |
156 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { | |
157 | mac->ops.setup_link = &ixgbe_setup_copper_link_82598; | |
04f165ef PW |
158 | mac->ops.get_link_capabilities = |
159 | &ixgbe_get_copper_link_capabilities_82598; | |
160 | } | |
c44ade9e | 161 | |
04f165ef | 162 | switch (hw->phy.type) { |
0befdb3e JB |
163 | case ixgbe_phy_tn: |
164 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; | |
165 | phy->ops.get_firmware_version = | |
166 | &ixgbe_get_phy_firmware_version_tnx; | |
167 | break; | |
c4900be0 DS |
168 | case ixgbe_phy_nl: |
169 | phy->ops.reset = &ixgbe_reset_phy_nl; | |
170 | ||
171 | /* Call SFP+ identify routine to get the SFP+ module type */ | |
172 | ret_val = phy->ops.identify_sfp(hw); | |
173 | if (ret_val != 0) | |
174 | goto out; | |
175 | else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { | |
176 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
177 | goto out; | |
178 | } | |
179 | ||
180 | /* Check to see if SFP+ module is supported */ | |
181 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, | |
04f165ef PW |
182 | &list_offset, |
183 | &data_offset); | |
c4900be0 DS |
184 | if (ret_val != 0) { |
185 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
186 | goto out; | |
187 | } | |
188 | break; | |
c44ade9e JB |
189 | default: |
190 | break; | |
191 | } | |
192 | ||
c4900be0 DS |
193 | out: |
194 | return ret_val; | |
9a799d71 AK |
195 | } |
196 | ||
202ff1ec MC |
197 | /** |
198 | * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx | |
199 | * @hw: pointer to hardware structure | |
200 | * | |
201 | * Starts the hardware using the generic start_hw function. | |
202 | * Then set pcie completion timeout | |
203 | **/ | |
7b25cdba | 204 | static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) |
202ff1ec MC |
205 | { |
206 | s32 ret_val = 0; | |
207 | ||
208 | ret_val = ixgbe_start_hw_generic(hw); | |
209 | ||
210 | /* set the completion timeout for interface */ | |
211 | if (ret_val == 0) | |
212 | ixgbe_set_pcie_completion_timeout(hw); | |
213 | ||
214 | return ret_val; | |
215 | } | |
216 | ||
9a799d71 | 217 | /** |
c44ade9e | 218 | * ixgbe_get_link_capabilities_82598 - Determines link capabilities |
9a799d71 AK |
219 | * @hw: pointer to hardware structure |
220 | * @speed: pointer to link speed | |
221 | * @autoneg: boolean auto-negotiation value | |
222 | * | |
c44ade9e | 223 | * Determines the link capabilities by reading the AUTOC register. |
9a799d71 | 224 | **/ |
c44ade9e | 225 | static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, |
b4617240 PW |
226 | ixgbe_link_speed *speed, |
227 | bool *autoneg) | |
9a799d71 AK |
228 | { |
229 | s32 status = 0; | |
1eb99d5a | 230 | u32 autoc = 0; |
9a799d71 | 231 | |
3201d313 PWJ |
232 | /* |
233 | * Determine link capabilities based on the stored value of AUTOC, | |
1eb99d5a PW |
234 | * which represents EEPROM defaults. If AUTOC value has not been |
235 | * stored, use the current register value. | |
3201d313 | 236 | */ |
1eb99d5a PW |
237 | if (hw->mac.orig_link_settings_stored) |
238 | autoc = hw->mac.orig_autoc; | |
239 | else | |
240 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
241 | ||
242 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { | |
9a799d71 AK |
243 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
244 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
245 | *autoneg = false; | |
246 | break; | |
247 | ||
248 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: | |
249 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
250 | *autoneg = false; | |
251 | break; | |
252 | ||
253 | case IXGBE_AUTOC_LMS_1G_AN: | |
254 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
255 | *autoneg = true; | |
256 | break; | |
257 | ||
258 | case IXGBE_AUTOC_LMS_KX4_AN: | |
259 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
260 | *speed = IXGBE_LINK_SPEED_UNKNOWN; | |
1eb99d5a | 261 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
9a799d71 | 262 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
1eb99d5a | 263 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
9a799d71 AK |
264 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
265 | *autoneg = true; | |
266 | break; | |
267 | ||
268 | default: | |
269 | status = IXGBE_ERR_LINK_SETUP; | |
270 | break; | |
271 | } | |
272 | ||
273 | return status; | |
274 | } | |
275 | ||
276 | /** | |
c44ade9e | 277 | * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities |
9a799d71 AK |
278 | * @hw: pointer to hardware structure |
279 | * @speed: pointer to link speed | |
280 | * @autoneg: boolean auto-negotiation value | |
281 | * | |
c44ade9e | 282 | * Determines the link capabilities by reading the AUTOC register. |
9a799d71 | 283 | **/ |
e855aac8 HE |
284 | static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, |
285 | ixgbe_link_speed *speed, | |
286 | bool *autoneg) | |
9a799d71 AK |
287 | { |
288 | s32 status = IXGBE_ERR_LINK_SETUP; | |
289 | u16 speed_ability; | |
290 | ||
291 | *speed = 0; | |
292 | *autoneg = true; | |
293 | ||
6b73e10d | 294 | status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, |
b4617240 | 295 | &speed_ability); |
9a799d71 AK |
296 | |
297 | if (status == 0) { | |
6b73e10d | 298 | if (speed_ability & MDIO_SPEED_10G) |
9a799d71 | 299 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
6b73e10d | 300 | if (speed_ability & MDIO_PMA_SPEED_1000) |
9a799d71 AK |
301 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
302 | } | |
303 | ||
304 | return status; | |
305 | } | |
306 | ||
307 | /** | |
308 | * ixgbe_get_media_type_82598 - Determines media type | |
309 | * @hw: pointer to hardware structure | |
310 | * | |
311 | * Returns the media type (fiber, copper, backplane) | |
312 | **/ | |
313 | static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) | |
314 | { | |
315 | enum ixgbe_media_type media_type; | |
316 | ||
317 | /* Media type for I82598 is based on device ID */ | |
318 | switch (hw->device_id) { | |
1e336d0f | 319 | case IXGBE_DEV_ID_82598: |
2f21bdd3 | 320 | case IXGBE_DEV_ID_82598_BX: |
1e336d0f DS |
321 | media_type = ixgbe_media_type_backplane; |
322 | break; | |
9a799d71 AK |
323 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: |
324 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
c4900be0 DS |
325 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: |
326 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
b95f5fcb | 327 | case IXGBE_DEV_ID_82598EB_XF_LR: |
c4900be0 | 328 | case IXGBE_DEV_ID_82598EB_SFP_LOM: |
9a799d71 AK |
329 | media_type = ixgbe_media_type_fiber; |
330 | break; | |
6b1be199 PWJ |
331 | case IXGBE_DEV_ID_82598EB_CX4: |
332 | case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: | |
333 | media_type = ixgbe_media_type_cx4; | |
334 | break; | |
0befdb3e | 335 | case IXGBE_DEV_ID_82598AT: |
3845bec0 | 336 | case IXGBE_DEV_ID_82598AT2: |
0befdb3e JB |
337 | media_type = ixgbe_media_type_copper; |
338 | break; | |
9a799d71 AK |
339 | default: |
340 | media_type = ixgbe_media_type_unknown; | |
341 | break; | |
342 | } | |
343 | ||
344 | return media_type; | |
345 | } | |
346 | ||
c44ade9e | 347 | /** |
0ecc061d | 348 | * ixgbe_fc_enable_82598 - Enable flow control |
c44ade9e JB |
349 | * @hw: pointer to hardware structure |
350 | * @packetbuf_num: packet buffer number (0-7) | |
351 | * | |
0ecc061d | 352 | * Enable flow control according to the current settings. |
c44ade9e | 353 | **/ |
0ecc061d | 354 | static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) |
c44ade9e | 355 | { |
0ecc061d PWJ |
356 | s32 ret_val = 0; |
357 | u32 fctrl_reg; | |
c44ade9e | 358 | u32 rmcs_reg; |
0ecc061d | 359 | u32 reg; |
16b61beb | 360 | u32 rx_pba_size; |
a626e847 DS |
361 | u32 link_speed = 0; |
362 | bool link_up; | |
c44ade9e | 363 | |
620fa036 MC |
364 | #ifdef CONFIG_DCB |
365 | if (hw->fc.requested_mode == ixgbe_fc_pfc) | |
366 | goto out; | |
367 | ||
368 | #endif /* CONFIG_DCB */ | |
a626e847 DS |
369 | /* |
370 | * On 82598 having Rx FC on causes resets while doing 1G | |
371 | * so if it's on turn it off once we know link_speed. For | |
372 | * more details see 82598 Specification update. | |
373 | */ | |
374 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
375 | if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { | |
376 | switch (hw->fc.requested_mode) { | |
377 | case ixgbe_fc_full: | |
378 | hw->fc.requested_mode = ixgbe_fc_tx_pause; | |
379 | break; | |
380 | case ixgbe_fc_rx_pause: | |
381 | hw->fc.requested_mode = ixgbe_fc_none; | |
382 | break; | |
383 | default: | |
384 | /* no change */ | |
385 | break; | |
386 | } | |
387 | } | |
388 | ||
620fa036 MC |
389 | /* Negotiate the fc mode to use */ |
390 | ret_val = ixgbe_fc_autoneg(hw); | |
391 | if (ret_val) | |
392 | goto out; | |
393 | ||
394 | /* Disable any previous flow control settings */ | |
0ecc061d PWJ |
395 | fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
396 | fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); | |
c44ade9e JB |
397 | |
398 | rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
399 | rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); | |
400 | ||
401 | /* | |
0ecc061d | 402 | * The possible values of fc.current_mode are: |
c44ade9e | 403 | * 0: Flow control is completely disabled |
0ecc061d PWJ |
404 | * 1: Rx flow control is enabled (we can receive pause frames, |
405 | * but not send pause frames). | |
620fa036 | 406 | * 2: Tx flow control is enabled (we can send pause frames but |
0ecc061d | 407 | * we do not support receiving pause frames). |
c44ade9e JB |
408 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
409 | * other: Invalid. | |
620fa036 MC |
410 | #ifdef CONFIG_DCB |
411 | * 4: Priority Flow Control is enabled. | |
412 | #endif | |
c44ade9e | 413 | */ |
0ecc061d | 414 | switch (hw->fc.current_mode) { |
c44ade9e | 415 | case ixgbe_fc_none: |
620fa036 MC |
416 | /* |
417 | * Flow control is disabled by software override or autoneg. | |
418 | * The code below will actually disable it in the HW. | |
419 | */ | |
c44ade9e JB |
420 | break; |
421 | case ixgbe_fc_rx_pause: | |
422 | /* | |
0ecc061d PWJ |
423 | * Rx Flow control is enabled and Tx Flow control is |
424 | * disabled by software override. Since there really | |
425 | * isn't a way to advertise that we are capable of RX | |
426 | * Pause ONLY, we will advertise that we support both | |
427 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
428 | * disable the adapter's ability to send PAUSE frames. | |
c44ade9e | 429 | */ |
0ecc061d | 430 | fctrl_reg |= IXGBE_FCTRL_RFCE; |
c44ade9e JB |
431 | break; |
432 | case ixgbe_fc_tx_pause: | |
433 | /* | |
0ecc061d PWJ |
434 | * Tx Flow control is enabled, and Rx Flow control is |
435 | * disabled by software override. | |
c44ade9e JB |
436 | */ |
437 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; | |
438 | break; | |
439 | case ixgbe_fc_full: | |
0ecc061d PWJ |
440 | /* Flow control (both Rx and Tx) is enabled by SW override. */ |
441 | fctrl_reg |= IXGBE_FCTRL_RFCE; | |
c44ade9e JB |
442 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; |
443 | break; | |
620fa036 MC |
444 | #ifdef CONFIG_DCB |
445 | case ixgbe_fc_pfc: | |
446 | goto out; | |
447 | break; | |
448 | #endif /* CONFIG_DCB */ | |
c44ade9e | 449 | default: |
c44ade9e | 450 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
539e5f02 | 451 | ret_val = IXGBE_ERR_CONFIG; |
0ecc061d | 452 | goto out; |
c44ade9e JB |
453 | break; |
454 | } | |
455 | ||
620fa036 | 456 | /* Set 802.3x based flow control settings. */ |
2132d381 | 457 | fctrl_reg |= IXGBE_FCTRL_DPF; |
0ecc061d | 458 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); |
c44ade9e JB |
459 | IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); |
460 | ||
0ecc061d PWJ |
461 | /* Set up and enable Rx high/low water mark thresholds, enable XON. */ |
462 | if (hw->fc.current_mode & ixgbe_fc_tx_pause) { | |
16b61beb JF |
463 | rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); |
464 | rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT; | |
465 | ||
466 | reg = (rx_pba_size - hw->fc.low_water) << 6; | |
467 | if (hw->fc.send_xon) | |
468 | reg |= IXGBE_FCRTL_XONE; | |
469 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg); | |
470 | ||
471 | reg = (rx_pba_size - hw->fc.high_water) << 10; | |
472 | reg |= IXGBE_FCRTH_FCEN; | |
0ecc061d | 473 | |
16b61beb | 474 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg); |
c44ade9e JB |
475 | } |
476 | ||
0ecc061d | 477 | /* Configure pause time (2 TCs per register) */ |
264857b8 | 478 | reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); |
0ecc061d PWJ |
479 | if ((packetbuf_num & 1) == 0) |
480 | reg = (reg & 0xFFFF0000) | hw->fc.pause_time; | |
481 | else | |
482 | reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); | |
483 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); | |
484 | ||
c44ade9e JB |
485 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); |
486 | ||
0ecc061d PWJ |
487 | out: |
488 | return ret_val; | |
489 | } | |
490 | ||
9a799d71 | 491 | /** |
8620a103 | 492 | * ixgbe_start_mac_link_82598 - Configures MAC link settings |
9a799d71 AK |
493 | * @hw: pointer to hardware structure |
494 | * | |
495 | * Configures link settings based on values in the ixgbe_hw struct. | |
496 | * Restarts the link. Performs autonegotiation if needed. | |
497 | **/ | |
8620a103 MC |
498 | static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, |
499 | bool autoneg_wait_to_complete) | |
9a799d71 AK |
500 | { |
501 | u32 autoc_reg; | |
502 | u32 links_reg; | |
503 | u32 i; | |
504 | s32 status = 0; | |
505 | ||
9a799d71 | 506 | /* Restart link */ |
3201d313 | 507 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
9a799d71 AK |
508 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
509 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); | |
510 | ||
511 | /* Only poll for autoneg to complete if specified to do so */ | |
8620a103 | 512 | if (autoneg_wait_to_complete) { |
3201d313 PWJ |
513 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
514 | IXGBE_AUTOC_LMS_KX4_AN || | |
515 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == | |
516 | IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
9a799d71 AK |
517 | links_reg = 0; /* Just in case Autoneg time = 0 */ |
518 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { | |
519 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
520 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) | |
521 | break; | |
522 | msleep(100); | |
523 | } | |
524 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { | |
525 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; | |
c44ade9e | 526 | hw_dbg(hw, "Autonegotiation did not complete.\n"); |
9a799d71 AK |
527 | } |
528 | } | |
529 | } | |
530 | ||
9a799d71 AK |
531 | /* Add delay to filter out noises during initial link setup */ |
532 | msleep(50); | |
533 | ||
534 | return status; | |
535 | } | |
536 | ||
734e979f MC |
537 | /** |
538 | * ixgbe_validate_link_ready - Function looks for phy link | |
539 | * @hw: pointer to hardware structure | |
540 | * | |
541 | * Function indicates success when phy link is available. If phy is not ready | |
542 | * within 5 seconds of MAC indicating link, the function returns error. | |
543 | **/ | |
544 | static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) | |
545 | { | |
546 | u32 timeout; | |
547 | u16 an_reg; | |
548 | ||
549 | if (hw->device_id != IXGBE_DEV_ID_82598AT2) | |
550 | return 0; | |
551 | ||
552 | for (timeout = 0; | |
553 | timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { | |
554 | hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg); | |
555 | ||
556 | if ((an_reg & MDIO_AN_STAT1_COMPLETE) && | |
557 | (an_reg & MDIO_STAT1_LSTATUS)) | |
558 | break; | |
559 | ||
560 | msleep(100); | |
561 | } | |
562 | ||
563 | if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { | |
564 | hw_dbg(hw, "Link was indicated but link is down\n"); | |
565 | return IXGBE_ERR_LINK_SETUP; | |
566 | } | |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
9a799d71 AK |
571 | /** |
572 | * ixgbe_check_mac_link_82598 - Get link/speed status | |
573 | * @hw: pointer to hardware structure | |
574 | * @speed: pointer to link speed | |
575 | * @link_up: true is link is up, false otherwise | |
cf8280ee | 576 | * @link_up_wait_to_complete: bool used to wait for link up or not |
9a799d71 AK |
577 | * |
578 | * Reads the links register to determine if link is up and the current speed | |
579 | **/ | |
b4617240 PW |
580 | static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, |
581 | ixgbe_link_speed *speed, bool *link_up, | |
582 | bool link_up_wait_to_complete) | |
9a799d71 AK |
583 | { |
584 | u32 links_reg; | |
cf8280ee | 585 | u32 i; |
c4900be0 DS |
586 | u16 link_reg, adapt_comp_reg; |
587 | ||
588 | /* | |
589 | * SERDES PHY requires us to read link status from register 0xC79F. | |
590 | * Bit 0 set indicates link is up/ready; clear indicates link down. | |
591 | * 0xC00C is read to check that the XAUI lanes are active. Bit 0 | |
592 | * clear indicates active; set indicates inactive. | |
593 | */ | |
594 | if (hw->phy.type == ixgbe_phy_nl) { | |
6b73e10d BH |
595 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); |
596 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); | |
597 | hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, | |
c4900be0 DS |
598 | &adapt_comp_reg); |
599 | if (link_up_wait_to_complete) { | |
600 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
601 | if ((link_reg & 1) && | |
602 | ((adapt_comp_reg & 1) == 0)) { | |
603 | *link_up = true; | |
604 | break; | |
605 | } else { | |
606 | *link_up = false; | |
607 | } | |
608 | msleep(100); | |
609 | hw->phy.ops.read_reg(hw, 0xC79F, | |
6b73e10d | 610 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
611 | &link_reg); |
612 | hw->phy.ops.read_reg(hw, 0xC00C, | |
6b73e10d | 613 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
614 | &adapt_comp_reg); |
615 | } | |
616 | } else { | |
617 | if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) | |
618 | *link_up = true; | |
619 | else | |
620 | *link_up = false; | |
621 | } | |
622 | ||
623 | if (*link_up == false) | |
624 | goto out; | |
625 | } | |
9a799d71 AK |
626 | |
627 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
cf8280ee JB |
628 | if (link_up_wait_to_complete) { |
629 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
630 | if (links_reg & IXGBE_LINKS_UP) { | |
631 | *link_up = true; | |
632 | break; | |
633 | } else { | |
634 | *link_up = false; | |
635 | } | |
636 | msleep(100); | |
637 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
638 | } | |
639 | } else { | |
640 | if (links_reg & IXGBE_LINKS_UP) | |
641 | *link_up = true; | |
642 | else | |
643 | *link_up = false; | |
644 | } | |
9a799d71 AK |
645 | |
646 | if (links_reg & IXGBE_LINKS_SPEED) | |
647 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
648 | else | |
649 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
650 | ||
734e979f MC |
651 | if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) && |
652 | (ixgbe_validate_link_ready(hw) != 0)) | |
653 | *link_up = false; | |
654 | ||
620fa036 MC |
655 | /* if link is down, zero out the current_mode */ |
656 | if (*link_up == false) { | |
657 | hw->fc.current_mode = ixgbe_fc_none; | |
658 | hw->fc.fc_was_autonegged = false; | |
659 | } | |
c4900be0 | 660 | out: |
9a799d71 AK |
661 | return 0; |
662 | } | |
663 | ||
c44ade9e | 664 | |
9a799d71 | 665 | /** |
8620a103 | 666 | * ixgbe_setup_mac_link_82598 - Set MAC link speed |
9a799d71 AK |
667 | * @hw: pointer to hardware structure |
668 | * @speed: new link speed | |
669 | * @autoneg: true if auto-negotiation enabled | |
670 | * @autoneg_wait_to_complete: true if waiting is needed to complete | |
671 | * | |
672 | * Set the link speed in the AUTOC register and restarts link. | |
673 | **/ | |
8620a103 | 674 | static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, |
3201d313 PWJ |
675 | ixgbe_link_speed speed, bool autoneg, |
676 | bool autoneg_wait_to_complete) | |
9a799d71 | 677 | { |
3201d313 PWJ |
678 | s32 status = 0; |
679 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; | |
680 | u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
681 | u32 autoc = curr_autoc; | |
682 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; | |
9a799d71 | 683 | |
3201d313 PWJ |
684 | /* Check to see if speed passed in is supported. */ |
685 | ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); | |
686 | speed &= link_capabilities; | |
687 | ||
688 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) | |
9a799d71 | 689 | status = IXGBE_ERR_LINK_SETUP; |
3201d313 PWJ |
690 | |
691 | /* Set KX4/KX support according to speed requested */ | |
692 | else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || | |
693 | link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
694 | autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; | |
695 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
696 | autoc |= IXGBE_AUTOC_KX4_SUPP; | |
697 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | |
698 | autoc |= IXGBE_AUTOC_KX_SUPP; | |
699 | if (autoc != curr_autoc) | |
700 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); | |
9a799d71 AK |
701 | } |
702 | ||
703 | if (status == 0) { | |
9a799d71 AK |
704 | /* |
705 | * Setup and restart the link based on the new values in | |
706 | * ixgbe_hw This will write the AUTOC register based on the new | |
707 | * stored values | |
708 | */ | |
8620a103 | 709 | status = ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); |
9a799d71 AK |
710 | } |
711 | ||
712 | return status; | |
713 | } | |
714 | ||
715 | ||
716 | /** | |
8620a103 | 717 | * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field |
9a799d71 AK |
718 | * @hw: pointer to hardware structure |
719 | * @speed: new link speed | |
720 | * @autoneg: true if autonegotiation enabled | |
721 | * @autoneg_wait_to_complete: true if waiting is needed to complete | |
722 | * | |
723 | * Sets the link speed in the AUTOC register in the MAC and restarts link. | |
724 | **/ | |
8620a103 | 725 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, |
b4617240 PW |
726 | ixgbe_link_speed speed, |
727 | bool autoneg, | |
728 | bool autoneg_wait_to_complete) | |
9a799d71 | 729 | { |
c44ade9e | 730 | s32 status; |
9a799d71 AK |
731 | |
732 | /* Setup the PHY according to input speed */ | |
b4617240 PW |
733 | status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, |
734 | autoneg_wait_to_complete); | |
3957d63d | 735 | |
3957d63d | 736 | /* Set up MAC */ |
8620a103 | 737 | ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); |
9a799d71 AK |
738 | |
739 | return status; | |
740 | } | |
741 | ||
742 | /** | |
743 | * ixgbe_reset_hw_82598 - Performs hardware reset | |
744 | * @hw: pointer to hardware structure | |
745 | * | |
c44ade9e | 746 | * Resets the hardware by resetting the transmit and receive units, masks and |
9a799d71 AK |
747 | * clears all interrupts, performing a PHY reset, and performing a link (MAC) |
748 | * reset. | |
749 | **/ | |
750 | static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) | |
751 | { | |
752 | s32 status = 0; | |
8ca783ab | 753 | s32 phy_status = 0; |
9a799d71 AK |
754 | u32 ctrl; |
755 | u32 gheccr; | |
756 | u32 i; | |
757 | u32 autoc; | |
758 | u8 analog_val; | |
759 | ||
760 | /* Call adapter stop to disable tx/rx and clear interrupts */ | |
c44ade9e | 761 | hw->mac.ops.stop_adapter(hw); |
9a799d71 AK |
762 | |
763 | /* | |
c44ade9e JB |
764 | * Power up the Atlas Tx lanes if they are currently powered down. |
765 | * Atlas Tx lanes are powered down for MAC loopback tests, but | |
9a799d71 AK |
766 | * they are not automatically restored on reset. |
767 | */ | |
c44ade9e | 768 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); |
9a799d71 | 769 | if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { |
c44ade9e JB |
770 | /* Enable Tx Atlas so packets can be transmitted again */ |
771 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, | |
772 | &analog_val); | |
9a799d71 | 773 | analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; |
c44ade9e JB |
774 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, |
775 | analog_val); | |
9a799d71 | 776 | |
c44ade9e JB |
777 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
778 | &analog_val); | |
9a799d71 | 779 | analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; |
c44ade9e JB |
780 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
781 | analog_val); | |
9a799d71 | 782 | |
c44ade9e JB |
783 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
784 | &analog_val); | |
9a799d71 | 785 | analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; |
c44ade9e JB |
786 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
787 | analog_val); | |
9a799d71 | 788 | |
c44ade9e JB |
789 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
790 | &analog_val); | |
9a799d71 | 791 | analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; |
c44ade9e JB |
792 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
793 | analog_val); | |
9a799d71 AK |
794 | } |
795 | ||
796 | /* Reset PHY */ | |
04f165ef PW |
797 | if (hw->phy.reset_disable == false) { |
798 | /* PHY ops must be identified and initialized prior to reset */ | |
799 | ||
800 | /* Init PHY and function pointers, perform SFP setup */ | |
8ca783ab DS |
801 | phy_status = hw->phy.ops.init(hw); |
802 | if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
04f165ef | 803 | goto reset_hw_out; |
8ca783ab DS |
804 | else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) |
805 | goto no_phy_reset; | |
806 | ||
04f165ef | 807 | |
c44ade9e | 808 | hw->phy.ops.reset(hw); |
04f165ef | 809 | } |
9a799d71 | 810 | |
8ca783ab | 811 | no_phy_reset: |
9a799d71 AK |
812 | /* |
813 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | |
814 | * access and verify no pending requests before reset | |
815 | */ | |
04f165ef PW |
816 | status = ixgbe_disable_pcie_master(hw); |
817 | if (status != 0) { | |
9a799d71 AK |
818 | status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
819 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
820 | } | |
821 | ||
822 | /* | |
823 | * Issue global reset to the MAC. This needs to be a SW reset. | |
824 | * If link reset is used, it might reset the MAC when mng is using it | |
825 | */ | |
826 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
827 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); | |
828 | IXGBE_WRITE_FLUSH(hw); | |
829 | ||
830 | /* Poll for reset bit to self-clear indicating reset is complete */ | |
831 | for (i = 0; i < 10; i++) { | |
832 | udelay(1); | |
833 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
834 | if (!(ctrl & IXGBE_CTRL_RST)) | |
835 | break; | |
836 | } | |
837 | if (ctrl & IXGBE_CTRL_RST) { | |
838 | status = IXGBE_ERR_RESET_FAILED; | |
839 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
840 | } | |
841 | ||
842 | msleep(50); | |
843 | ||
844 | gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); | |
845 | gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); | |
846 | IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); | |
847 | ||
848 | /* | |
3201d313 PWJ |
849 | * Store the original AUTOC value if it has not been |
850 | * stored off yet. Otherwise restore the stored original | |
851 | * AUTOC value since the reset operation sets back to deaults. | |
9a799d71 AK |
852 | */ |
853 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
3201d313 PWJ |
854 | if (hw->mac.orig_link_settings_stored == false) { |
855 | hw->mac.orig_autoc = autoc; | |
856 | hw->mac.orig_link_settings_stored = true; | |
857 | } else if (autoc != hw->mac.orig_autoc) { | |
858 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); | |
9a799d71 AK |
859 | } |
860 | ||
aca6bee7 WJP |
861 | /* |
862 | * Store MAC address from RAR0, clear receive address registers, and | |
863 | * clear the multicast table | |
864 | */ | |
865 | hw->mac.ops.init_rx_addrs(hw); | |
866 | ||
9a799d71 | 867 | /* Store the permanent mac address */ |
c44ade9e | 868 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); |
9a799d71 | 869 | |
04f165ef | 870 | reset_hw_out: |
8ca783ab DS |
871 | if (phy_status) |
872 | status = phy_status; | |
873 | ||
9a799d71 AK |
874 | return status; |
875 | } | |
876 | ||
c44ade9e JB |
877 | /** |
878 | * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address | |
879 | * @hw: pointer to hardware struct | |
880 | * @rar: receive address register index to associate with a VMDq index | |
881 | * @vmdq: VMDq set index | |
882 | **/ | |
e855aac8 | 883 | static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) |
c44ade9e JB |
884 | { |
885 | u32 rar_high; | |
886 | ||
887 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
888 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
889 | rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); | |
890 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
891 | return 0; | |
892 | } | |
893 | ||
894 | /** | |
895 | * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address | |
896 | * @hw: pointer to hardware struct | |
897 | * @rar: receive address register index to associate with a VMDq index | |
898 | * @vmdq: VMDq clear index (not used in 82598, but elsewhere) | |
899 | **/ | |
900 | static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) | |
901 | { | |
902 | u32 rar_high; | |
903 | u32 rar_entries = hw->mac.num_rar_entries; | |
904 | ||
905 | if (rar < rar_entries) { | |
906 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
907 | if (rar_high & IXGBE_RAH_VIND_MASK) { | |
908 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
909 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
910 | } | |
911 | } else { | |
912 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); | |
913 | } | |
914 | ||
915 | return 0; | |
916 | } | |
917 | ||
918 | /** | |
919 | * ixgbe_set_vfta_82598 - Set VLAN filter table | |
920 | * @hw: pointer to hardware structure | |
921 | * @vlan: VLAN id to write to VLAN filter | |
922 | * @vind: VMDq output index that maps queue to VLAN id in VFTA | |
923 | * @vlan_on: boolean flag to turn on/off VLAN in VFTA | |
924 | * | |
925 | * Turn on/off specified VLAN in the VLAN filter table. | |
926 | **/ | |
e855aac8 HE |
927 | static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
928 | bool vlan_on) | |
c44ade9e JB |
929 | { |
930 | u32 regindex; | |
931 | u32 bitindex; | |
932 | u32 bits; | |
933 | u32 vftabyte; | |
934 | ||
935 | if (vlan > 4095) | |
936 | return IXGBE_ERR_PARAM; | |
937 | ||
938 | /* Determine 32-bit word position in array */ | |
939 | regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ | |
940 | ||
941 | /* Determine the location of the (VMD) queue index */ | |
942 | vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ | |
943 | bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ | |
944 | ||
945 | /* Set the nibble for VMD queue index */ | |
946 | bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); | |
947 | bits &= (~(0x0F << bitindex)); | |
948 | bits |= (vind << bitindex); | |
949 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); | |
950 | ||
951 | /* Determine the location of the bit for this VLAN id */ | |
952 | bitindex = vlan & 0x1F; /* lower five bits */ | |
953 | ||
954 | bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); | |
955 | if (vlan_on) | |
956 | /* Turn on this VLAN id */ | |
957 | bits |= (1 << bitindex); | |
958 | else | |
959 | /* Turn off this VLAN id */ | |
960 | bits &= ~(1 << bitindex); | |
961 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
966 | /** | |
967 | * ixgbe_clear_vfta_82598 - Clear VLAN filter table | |
968 | * @hw: pointer to hardware structure | |
969 | * | |
970 | * Clears the VLAN filer table, and the VMDq index associated with the filter | |
971 | **/ | |
972 | static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) | |
973 | { | |
974 | u32 offset; | |
975 | u32 vlanbyte; | |
976 | ||
977 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
978 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); | |
979 | ||
980 | for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) | |
981 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
982 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), | |
b4617240 | 983 | 0); |
c44ade9e JB |
984 | |
985 | return 0; | |
986 | } | |
987 | ||
c44ade9e JB |
988 | /** |
989 | * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register | |
990 | * @hw: pointer to hardware structure | |
991 | * @reg: analog register to read | |
992 | * @val: read value | |
993 | * | |
994 | * Performs read operation to Atlas analog register specified. | |
995 | **/ | |
e855aac8 | 996 | static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) |
c44ade9e JB |
997 | { |
998 | u32 atlas_ctl; | |
999 | ||
1000 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, | |
1001 | IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); | |
1002 | IXGBE_WRITE_FLUSH(hw); | |
1003 | udelay(10); | |
1004 | atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); | |
1005 | *val = (u8)atlas_ctl; | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | /** | |
1011 | * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register | |
1012 | * @hw: pointer to hardware structure | |
1013 | * @reg: atlas register to write | |
1014 | * @val: value to write | |
1015 | * | |
1016 | * Performs write operation to Atlas analog register specified. | |
1017 | **/ | |
e855aac8 | 1018 | static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) |
c44ade9e JB |
1019 | { |
1020 | u32 atlas_ctl; | |
1021 | ||
1022 | atlas_ctl = (reg << 8) | val; | |
1023 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); | |
1024 | IXGBE_WRITE_FLUSH(hw); | |
1025 | udelay(10); | |
1026 | ||
1027 | return 0; | |
1028 | } | |
1029 | ||
c4900be0 DS |
1030 | /** |
1031 | * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module | |
1032 | * over I2C interface through an intermediate phy. | |
1033 | * @hw: pointer to hardware structure | |
1034 | * @byte_offset: EEPROM byte offset to read | |
1035 | * @eeprom_data: value read | |
1036 | * | |
1037 | * Performs byte read operation to SFP module's EEPROM over I2C interface. | |
1038 | **/ | |
e855aac8 HE |
1039 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
1040 | u8 *eeprom_data) | |
c4900be0 DS |
1041 | { |
1042 | s32 status = 0; | |
1043 | u16 sfp_addr = 0; | |
1044 | u16 sfp_data = 0; | |
1045 | u16 sfp_stat = 0; | |
1046 | u32 i; | |
1047 | ||
1048 | if (hw->phy.type == ixgbe_phy_nl) { | |
1049 | /* | |
1050 | * phy SDA/SCL registers are at addresses 0xC30A to | |
1051 | * 0xC30D. These registers are used to talk to the SFP+ | |
1052 | * module's EEPROM through the SDA/SCL (I2C) interface. | |
1053 | */ | |
1054 | sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; | |
1055 | sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); | |
1056 | hw->phy.ops.write_reg(hw, | |
1057 | IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, | |
6b73e10d | 1058 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
1059 | sfp_addr); |
1060 | ||
1061 | /* Poll status */ | |
1062 | for (i = 0; i < 100; i++) { | |
1063 | hw->phy.ops.read_reg(hw, | |
1064 | IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, | |
6b73e10d | 1065 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
1066 | &sfp_stat); |
1067 | sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; | |
1068 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) | |
1069 | break; | |
1070 | msleep(10); | |
1071 | } | |
1072 | ||
1073 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { | |
1074 | hw_dbg(hw, "EEPROM read did not pass.\n"); | |
1075 | status = IXGBE_ERR_SFP_NOT_PRESENT; | |
1076 | goto out; | |
1077 | } | |
1078 | ||
1079 | /* Read data */ | |
1080 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, | |
6b73e10d | 1081 | MDIO_MMD_PMAPMD, &sfp_data); |
c4900be0 DS |
1082 | |
1083 | *eeprom_data = (u8)(sfp_data >> 8); | |
1084 | } else { | |
1085 | status = IXGBE_ERR_PHY; | |
1086 | goto out; | |
1087 | } | |
1088 | ||
1089 | out: | |
1090 | return status; | |
1091 | } | |
1092 | ||
c44ade9e JB |
1093 | /** |
1094 | * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type | |
1095 | * @hw: pointer to hardware structure | |
1096 | * | |
1097 | * Determines physical layer capabilities of the current configuration. | |
1098 | **/ | |
11afc1b1 | 1099 | static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) |
c44ade9e | 1100 | { |
11afc1b1 | 1101 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; |
04193058 PWJ |
1102 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
1103 | u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; | |
1104 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; | |
1105 | u16 ext_ability = 0; | |
1106 | ||
1107 | hw->phy.ops.identify(hw); | |
1108 | ||
1109 | /* Copper PHY must be checked before AUTOC LMS to determine correct | |
1110 | * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ | |
1111 | if (hw->phy.type == ixgbe_phy_tn || | |
1112 | hw->phy.type == ixgbe_phy_cu_unknown) { | |
6b73e10d BH |
1113 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, |
1114 | &ext_ability); | |
1115 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) | |
04193058 | 1116 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
6b73e10d | 1117 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) |
04193058 | 1118 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
6b73e10d | 1119 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) |
04193058 PWJ |
1120 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
1121 | goto out; | |
1122 | } | |
c44ade9e | 1123 | |
04193058 PWJ |
1124 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
1125 | case IXGBE_AUTOC_LMS_1G_AN: | |
1126 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: | |
1127 | if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) | |
1128 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1129 | else | |
1130 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; | |
c4900be0 | 1131 | break; |
04193058 PWJ |
1132 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
1133 | if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) | |
1134 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; | |
1135 | else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) | |
1136 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
1137 | else /* XAUI */ | |
1138 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
c44ade9e | 1139 | break; |
04193058 PWJ |
1140 | case IXGBE_AUTOC_LMS_KX4_AN: |
1141 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
1142 | if (autoc & IXGBE_AUTOC_KX_SUPP) | |
1143 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1144 | if (autoc & IXGBE_AUTOC_KX4_SUPP) | |
1145 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
c44ade9e | 1146 | break; |
04193058 | 1147 | default: |
0befdb3e | 1148 | break; |
04193058 PWJ |
1149 | } |
1150 | ||
1151 | if (hw->phy.type == ixgbe_phy_nl) { | |
c4900be0 DS |
1152 | hw->phy.ops.identify_sfp(hw); |
1153 | ||
1154 | switch (hw->phy.sfp_type) { | |
1155 | case ixgbe_sfp_type_da_cu: | |
1156 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1157 | break; | |
1158 | case ixgbe_sfp_type_sr: | |
1159 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1160 | break; | |
1161 | case ixgbe_sfp_type_lr: | |
1162 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1163 | break; | |
1164 | default: | |
1165 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
1166 | break; | |
1167 | } | |
04193058 | 1168 | } |
c44ade9e | 1169 | |
04193058 PWJ |
1170 | switch (hw->device_id) { |
1171 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: | |
1172 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1173 | break; | |
1174 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: | |
1175 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
1176 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
1177 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1178 | break; | |
1179 | case IXGBE_DEV_ID_82598EB_XF_LR: | |
1180 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1181 | break; | |
c44ade9e | 1182 | default: |
c44ade9e JB |
1183 | break; |
1184 | } | |
1185 | ||
04193058 | 1186 | out: |
c44ade9e JB |
1187 | return physical_layer; |
1188 | } | |
1189 | ||
9a799d71 | 1190 | static struct ixgbe_mac_operations mac_ops_82598 = { |
c44ade9e JB |
1191 | .init_hw = &ixgbe_init_hw_generic, |
1192 | .reset_hw = &ixgbe_reset_hw_82598, | |
202ff1ec | 1193 | .start_hw = &ixgbe_start_hw_82598, |
c44ade9e | 1194 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
9a799d71 | 1195 | .get_media_type = &ixgbe_get_media_type_82598, |
c44ade9e | 1196 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, |
11afc1b1 | 1197 | .enable_rx_dma = &ixgbe_enable_rx_dma_generic, |
c44ade9e JB |
1198 | .get_mac_addr = &ixgbe_get_mac_addr_generic, |
1199 | .stop_adapter = &ixgbe_stop_adapter_generic, | |
11afc1b1 PW |
1200 | .get_bus_info = &ixgbe_get_bus_info_generic, |
1201 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, | |
c44ade9e JB |
1202 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, |
1203 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, | |
3957d63d | 1204 | .setup_link = &ixgbe_setup_mac_link_82598, |
c44ade9e JB |
1205 | .check_link = &ixgbe_check_mac_link_82598, |
1206 | .get_link_capabilities = &ixgbe_get_link_capabilities_82598, | |
1207 | .led_on = &ixgbe_led_on_generic, | |
1208 | .led_off = &ixgbe_led_off_generic, | |
87c12017 PW |
1209 | .blink_led_start = &ixgbe_blink_led_start_generic, |
1210 | .blink_led_stop = &ixgbe_blink_led_stop_generic, | |
c44ade9e JB |
1211 | .set_rar = &ixgbe_set_rar_generic, |
1212 | .clear_rar = &ixgbe_clear_rar_generic, | |
1213 | .set_vmdq = &ixgbe_set_vmdq_82598, | |
1214 | .clear_vmdq = &ixgbe_clear_vmdq_82598, | |
1215 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, | |
1216 | .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, | |
1217 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, | |
1218 | .enable_mc = &ixgbe_enable_mc_generic, | |
1219 | .disable_mc = &ixgbe_disable_mc_generic, | |
1220 | .clear_vfta = &ixgbe_clear_vfta_82598, | |
1221 | .set_vfta = &ixgbe_set_vfta_82598, | |
620fa036 | 1222 | .fc_enable = &ixgbe_fc_enable_82598, |
c44ade9e JB |
1223 | }; |
1224 | ||
1225 | static struct ixgbe_eeprom_operations eeprom_ops_82598 = { | |
1226 | .init_params = &ixgbe_init_eeprom_params_generic, | |
21ce849b | 1227 | .read = &ixgbe_read_eerd_generic, |
c44ade9e JB |
1228 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, |
1229 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, | |
1230 | }; | |
1231 | ||
1232 | static struct ixgbe_phy_operations phy_ops_82598 = { | |
1233 | .identify = &ixgbe_identify_phy_generic, | |
c4900be0 | 1234 | .identify_sfp = &ixgbe_identify_sfp_module_generic, |
04f165ef | 1235 | .init = &ixgbe_init_phy_ops_82598, |
c44ade9e JB |
1236 | .reset = &ixgbe_reset_phy_generic, |
1237 | .read_reg = &ixgbe_read_phy_reg_generic, | |
1238 | .write_reg = &ixgbe_write_phy_reg_generic, | |
1239 | .setup_link = &ixgbe_setup_phy_link_generic, | |
1240 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, | |
c4900be0 | 1241 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, |
119fc60a | 1242 | .check_overtemp = &ixgbe_tn_check_overtemp, |
9a799d71 AK |
1243 | }; |
1244 | ||
3957d63d | 1245 | struct ixgbe_info ixgbe_82598_info = { |
9a799d71 AK |
1246 | .mac = ixgbe_mac_82598EB, |
1247 | .get_invariants = &ixgbe_get_invariants_82598, | |
1248 | .mac_ops = &mac_ops_82598, | |
c44ade9e JB |
1249 | .eeprom_ops = &eeprom_ops_82598, |
1250 | .phy_ops = &phy_ops_82598, | |
9a799d71 AK |
1251 | }; |
1252 |