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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
451152d9 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
1605927f | 31 | * 82571EB Gigabit Ethernet Controller (Copper) |
bc7f75fa | 32 | * 82571EB Gigabit Ethernet Controller (Fiber) |
ad68076e BA |
33 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
34 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
35 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
36 | * 82572EI Gigabit Ethernet Controller (Copper) |
37 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
38 | * 82572EI Gigabit Ethernet Controller | |
39 | * 82573V Gigabit Ethernet Controller (Copper) | |
40 | * 82573E Gigabit Ethernet Controller (Copper) | |
41 | * 82573L Gigabit Ethernet Controller | |
4662e82b | 42 | * 82574L Gigabit Network Connection |
8c81c9c3 | 43 | * 82583V Gigabit Network Connection |
bc7f75fa AK |
44 | */ |
45 | ||
bc7f75fa AK |
46 | #include "e1000.h" |
47 | ||
48 | #define ID_LED_RESERVED_F746 0xF746 | |
49 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
50 | (ID_LED_OFF1_ON2 << 8) | \ | |
51 | (ID_LED_DEF1_DEF2 << 4) | \ | |
52 | (ID_LED_DEF1_DEF2)) | |
53 | ||
54 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
ff10e13c CW |
55 | #define E1000_BASE1000T_STATUS 10 |
56 | #define E1000_IDLE_ERROR_COUNT_MASK 0xFF | |
57 | #define E1000_RECEIVE_ERROR_COUNTER 21 | |
58 | #define E1000_RECEIVE_ERROR_MAX 0xFFFF | |
bc7f75fa | 59 | |
4662e82b BA |
60 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
61 | ||
bc7f75fa AK |
62 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
63 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
64 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
c9523379 | 65 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
bc7f75fa AK |
66 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
67 | u16 words, u16 *data); | |
68 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
69 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
70 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
71 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
caaddaf8 | 72 | static void e1000_clear_vfta_82571(struct e1000_hw *hw); |
4662e82b BA |
73 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
74 | static s32 e1000_led_on_82574(struct e1000_hw *hw); | |
23a2d1b2 | 75 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); |
17f208de | 76 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); |
1b98c2bb BA |
77 | static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); |
78 | static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); | |
79 | static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); | |
bc7f75fa AK |
80 | |
81 | /** | |
82 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
83 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
84 | **/ |
85 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
86 | { | |
87 | struct e1000_phy_info *phy = &hw->phy; | |
88 | s32 ret_val; | |
89 | ||
318a94d6 | 90 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
91 | phy->type = e1000_phy_none; |
92 | return 0; | |
93 | } | |
94 | ||
95 | phy->addr = 1; | |
96 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
97 | phy->reset_delay_us = 100; | |
98 | ||
17f208de BA |
99 | phy->ops.power_up = e1000_power_up_phy_copper; |
100 | phy->ops.power_down = e1000_power_down_phy_copper_82571; | |
101 | ||
bc7f75fa AK |
102 | switch (hw->mac.type) { |
103 | case e1000_82571: | |
104 | case e1000_82572: | |
105 | phy->type = e1000_phy_igp_2; | |
106 | break; | |
107 | case e1000_82573: | |
108 | phy->type = e1000_phy_m88; | |
109 | break; | |
4662e82b | 110 | case e1000_82574: |
8c81c9c3 | 111 | case e1000_82583: |
4662e82b | 112 | phy->type = e1000_phy_bm; |
1b98c2bb BA |
113 | phy->ops.acquire = e1000_get_hw_semaphore_82574; |
114 | phy->ops.release = e1000_put_hw_semaphore_82574; | |
4662e82b | 115 | break; |
bc7f75fa AK |
116 | default: |
117 | return -E1000_ERR_PHY; | |
118 | break; | |
119 | } | |
120 | ||
121 | /* This can only be done after all function pointers are setup. */ | |
122 | ret_val = e1000_get_phy_id_82571(hw); | |
123 | ||
124 | /* Verify phy id */ | |
125 | switch (hw->mac.type) { | |
126 | case e1000_82571: | |
127 | case e1000_82572: | |
128 | if (phy->id != IGP01E1000_I_PHY_ID) | |
129 | return -E1000_ERR_PHY; | |
130 | break; | |
131 | case e1000_82573: | |
132 | if (phy->id != M88E1111_I_PHY_ID) | |
133 | return -E1000_ERR_PHY; | |
134 | break; | |
4662e82b | 135 | case e1000_82574: |
8c81c9c3 | 136 | case e1000_82583: |
4662e82b BA |
137 | if (phy->id != BME1000_E_PHY_ID_R2) |
138 | return -E1000_ERR_PHY; | |
139 | break; | |
bc7f75fa AK |
140 | default: |
141 | return -E1000_ERR_PHY; | |
142 | break; | |
143 | } | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | /** | |
149 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
150 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
151 | **/ |
152 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
153 | { | |
154 | struct e1000_nvm_info *nvm = &hw->nvm; | |
155 | u32 eecd = er32(EECD); | |
156 | u16 size; | |
157 | ||
158 | nvm->opcode_bits = 8; | |
159 | nvm->delay_usec = 1; | |
160 | switch (nvm->override) { | |
161 | case e1000_nvm_override_spi_large: | |
162 | nvm->page_size = 32; | |
163 | nvm->address_bits = 16; | |
164 | break; | |
165 | case e1000_nvm_override_spi_small: | |
166 | nvm->page_size = 8; | |
167 | nvm->address_bits = 8; | |
168 | break; | |
169 | default: | |
170 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
171 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
172 | break; | |
173 | } | |
174 | ||
175 | switch (hw->mac.type) { | |
176 | case e1000_82573: | |
4662e82b | 177 | case e1000_82574: |
8c81c9c3 | 178 | case e1000_82583: |
bc7f75fa AK |
179 | if (((eecd >> 15) & 0x3) == 0x3) { |
180 | nvm->type = e1000_nvm_flash_hw; | |
181 | nvm->word_size = 2048; | |
ad68076e BA |
182 | /* |
183 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
184 | * to Flash update issue. |
185 | */ | |
186 | eecd &= ~E1000_EECD_AUPDEN; | |
187 | ew32(EECD, eecd); | |
188 | break; | |
189 | } | |
190 | /* Fall Through */ | |
191 | default: | |
ad68076e | 192 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
193 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
194 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
195 | /* |
196 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
197 | * for setting word_size. |
198 | */ | |
199 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
200 | |
201 | /* EEPROM access above 16k is unsupported */ | |
202 | if (size > 14) | |
203 | size = 14; | |
bc7f75fa AK |
204 | nvm->word_size = 1 << size; |
205 | break; | |
206 | } | |
207 | ||
1b98c2bb BA |
208 | /* Function Pointers */ |
209 | switch (hw->mac.type) { | |
210 | case e1000_82574: | |
211 | case e1000_82583: | |
212 | nvm->ops.acquire = e1000_get_hw_semaphore_82574; | |
213 | nvm->ops.release = e1000_put_hw_semaphore_82574; | |
214 | break; | |
215 | default: | |
216 | break; | |
217 | } | |
218 | ||
bc7f75fa AK |
219 | return 0; |
220 | } | |
221 | ||
222 | /** | |
223 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
224 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
225 | **/ |
226 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
227 | { | |
228 | struct e1000_hw *hw = &adapter->hw; | |
229 | struct e1000_mac_info *mac = &hw->mac; | |
230 | struct e1000_mac_operations *func = &mac->ops; | |
23a2d1b2 DG |
231 | u32 swsm = 0; |
232 | u32 swsm2 = 0; | |
233 | bool force_clear_smbi = false; | |
bc7f75fa AK |
234 | |
235 | /* Set media type */ | |
236 | switch (adapter->pdev->device) { | |
237 | case E1000_DEV_ID_82571EB_FIBER: | |
238 | case E1000_DEV_ID_82572EI_FIBER: | |
239 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 240 | hw->phy.media_type = e1000_media_type_fiber; |
bc7f75fa AK |
241 | break; |
242 | case E1000_DEV_ID_82571EB_SERDES: | |
243 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
244 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
245 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
318a94d6 | 246 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
247 | break; |
248 | default: | |
318a94d6 | 249 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
250 | break; |
251 | } | |
252 | ||
253 | /* Set mta register count */ | |
254 | mac->mta_reg_count = 128; | |
255 | /* Set rar entry count */ | |
256 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
f464ba87 BA |
257 | /* Adaptive IFS supported */ |
258 | mac->adaptive_ifs = true; | |
bc7f75fa AK |
259 | |
260 | /* check for link */ | |
318a94d6 | 261 | switch (hw->phy.media_type) { |
bc7f75fa AK |
262 | case e1000_media_type_copper: |
263 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
264 | func->check_for_link = e1000e_check_for_copper_link; | |
265 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
266 | break; | |
267 | case e1000_media_type_fiber: | |
ad68076e BA |
268 | func->setup_physical_interface = |
269 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 270 | func->check_for_link = e1000e_check_for_fiber_link; |
ad68076e BA |
271 | func->get_link_up_info = |
272 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
273 | break; |
274 | case e1000_media_type_internal_serdes: | |
ad68076e BA |
275 | func->setup_physical_interface = |
276 | e1000_setup_fiber_serdes_link_82571; | |
c9523379 | 277 | func->check_for_link = e1000_check_for_serdes_link_82571; |
ad68076e BA |
278 | func->get_link_up_info = |
279 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
280 | break; |
281 | default: | |
282 | return -E1000_ERR_CONFIG; | |
283 | break; | |
284 | } | |
285 | ||
4662e82b | 286 | switch (hw->mac.type) { |
f4d2dd4c BA |
287 | case e1000_82573: |
288 | func->set_lan_id = e1000_set_lan_id_single_port; | |
289 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
290 | func->led_on = e1000e_led_on_generic; | |
a65a4a0d BA |
291 | |
292 | /* FWSM register */ | |
293 | mac->has_fwsm = true; | |
294 | /* | |
295 | * ARC supported; valid only if manageability features are | |
296 | * enabled. | |
297 | */ | |
298 | mac->arc_subsystem_valid = | |
299 | (er32(FWSM) & E1000_FWSM_MODE_MASK) | |
300 | ? true : false; | |
f4d2dd4c | 301 | break; |
4662e82b | 302 | case e1000_82574: |
8c81c9c3 | 303 | case e1000_82583: |
f4d2dd4c | 304 | func->set_lan_id = e1000_set_lan_id_single_port; |
4662e82b BA |
305 | func->check_mng_mode = e1000_check_mng_mode_82574; |
306 | func->led_on = e1000_led_on_82574; | |
307 | break; | |
308 | default: | |
309 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
310 | func->led_on = e1000e_led_on_generic; | |
a65a4a0d BA |
311 | |
312 | /* FWSM register */ | |
313 | mac->has_fwsm = true; | |
4662e82b BA |
314 | break; |
315 | } | |
316 | ||
23a2d1b2 DG |
317 | /* |
318 | * Ensure that the inter-port SWSM.SMBI lock bit is clear before | |
319 | * first NVM or PHY acess. This should be done for single-port | |
320 | * devices, and for one port only on dual-port devices so that | |
321 | * for those devices we can still use the SMBI lock to synchronize | |
322 | * inter-port accesses to the PHY & NVM. | |
323 | */ | |
324 | switch (hw->mac.type) { | |
325 | case e1000_82571: | |
326 | case e1000_82572: | |
327 | swsm2 = er32(SWSM2); | |
328 | ||
329 | if (!(swsm2 & E1000_SWSM2_LOCK)) { | |
330 | /* Only do this for the first interface on this card */ | |
331 | ew32(SWSM2, | |
332 | swsm2 | E1000_SWSM2_LOCK); | |
333 | force_clear_smbi = true; | |
334 | } else | |
335 | force_clear_smbi = false; | |
336 | break; | |
337 | default: | |
338 | force_clear_smbi = true; | |
339 | break; | |
340 | } | |
341 | ||
342 | if (force_clear_smbi) { | |
343 | /* Make sure SWSM.SMBI is clear */ | |
344 | swsm = er32(SWSM); | |
345 | if (swsm & E1000_SWSM_SMBI) { | |
346 | /* This bit should not be set on a first interface, and | |
347 | * indicates that the bootagent or EFI code has | |
348 | * improperly left this bit enabled | |
349 | */ | |
3bb99fe2 | 350 | e_dbg("Please update your 82571 Bootagent\n"); |
23a2d1b2 DG |
351 | } |
352 | ew32(SWSM, swsm & ~E1000_SWSM_SMBI); | |
353 | } | |
354 | ||
355 | /* | |
2c73e1fe | 356 | * Initialize device specific counter of SMBI acquisition |
23a2d1b2 DG |
357 | * timeouts. |
358 | */ | |
359 | hw->dev_spec.e82571.smb_counter = 0; | |
360 | ||
bc7f75fa AK |
361 | return 0; |
362 | } | |
363 | ||
69e3fd8c | 364 | static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
bc7f75fa AK |
365 | { |
366 | struct e1000_hw *hw = &adapter->hw; | |
367 | static int global_quad_port_a; /* global port a indication */ | |
368 | struct pci_dev *pdev = adapter->pdev; | |
bc7f75fa AK |
369 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; |
370 | s32 rc; | |
371 | ||
372 | rc = e1000_init_mac_params_82571(adapter); | |
373 | if (rc) | |
374 | return rc; | |
375 | ||
376 | rc = e1000_init_nvm_params_82571(hw); | |
377 | if (rc) | |
378 | return rc; | |
379 | ||
380 | rc = e1000_init_phy_params_82571(hw); | |
381 | if (rc) | |
382 | return rc; | |
383 | ||
384 | /* tag quad port adapters first, it's used below */ | |
385 | switch (pdev->device) { | |
386 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
387 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
388 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 389 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
390 | adapter->flags |= FLAG_IS_QUAD_PORT; |
391 | /* mark the first port */ | |
392 | if (global_quad_port_a == 0) | |
393 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
394 | /* Reset for multiple quad port adapters */ | |
395 | global_quad_port_a++; | |
396 | if (global_quad_port_a == 4) | |
397 | global_quad_port_a = 0; | |
398 | break; | |
399 | default: | |
400 | break; | |
401 | } | |
402 | ||
403 | switch (adapter->hw.mac.type) { | |
404 | case e1000_82571: | |
405 | /* these dual ports don't have WoL on port B at all */ | |
406 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
407 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
408 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
409 | (is_port_b)) | |
410 | adapter->flags &= ~FLAG_HAS_WOL; | |
411 | /* quad ports only support WoL on port A */ | |
412 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 413 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 414 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
415 | /* Does not support WoL on any port */ |
416 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
417 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa | 418 | break; |
bc7f75fa | 419 | case e1000_82573: |
6f461f6c BA |
420 | case e1000_82574: |
421 | case e1000_82583: | |
422 | /* Disable ASPM L0s due to hardware errata */ | |
423 | e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L0S); | |
424 | ||
bc7f75fa | 425 | if (pdev->device == E1000_DEV_ID_82573L) { |
6f461f6c BA |
426 | adapter->flags |= FLAG_HAS_JUMBO_FRAMES; |
427 | adapter->max_hw_frame_size = DEFAULT_JUMBO; | |
bc7f75fa AK |
428 | } |
429 | break; | |
430 | default: | |
431 | break; | |
432 | } | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | /** | |
438 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
439 | * @hw: pointer to the HW structure | |
440 | * | |
441 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
442 | * revision in the hardware structure. | |
443 | **/ | |
444 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
445 | { | |
446 | struct e1000_phy_info *phy = &hw->phy; | |
4662e82b BA |
447 | s32 ret_val; |
448 | u16 phy_id = 0; | |
bc7f75fa AK |
449 | |
450 | switch (hw->mac.type) { | |
451 | case e1000_82571: | |
452 | case e1000_82572: | |
ad68076e BA |
453 | /* |
454 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
455 | * In this case, we cannot access the PHY until the |
456 | * configuration is done. So we explicitly set the | |
ad68076e BA |
457 | * PHY ID. |
458 | */ | |
bc7f75fa AK |
459 | phy->id = IGP01E1000_I_PHY_ID; |
460 | break; | |
461 | case e1000_82573: | |
462 | return e1000e_get_phy_id(hw); | |
463 | break; | |
4662e82b | 464 | case e1000_82574: |
8c81c9c3 | 465 | case e1000_82583: |
4662e82b BA |
466 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
467 | if (ret_val) | |
468 | return ret_val; | |
469 | ||
470 | phy->id = (u32)(phy_id << 16); | |
471 | udelay(20); | |
472 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
473 | if (ret_val) | |
474 | return ret_val; | |
475 | ||
476 | phy->id |= (u32)(phy_id); | |
477 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
478 | break; | |
bc7f75fa AK |
479 | default: |
480 | return -E1000_ERR_PHY; | |
481 | break; | |
482 | } | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | /** | |
488 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
489 | * @hw: pointer to the HW structure | |
490 | * | |
491 | * Acquire the HW semaphore to access the PHY or NVM | |
492 | **/ | |
493 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
494 | { | |
495 | u32 swsm; | |
23a2d1b2 DG |
496 | s32 sw_timeout = hw->nvm.word_size + 1; |
497 | s32 fw_timeout = hw->nvm.word_size + 1; | |
bc7f75fa AK |
498 | s32 i = 0; |
499 | ||
23a2d1b2 DG |
500 | /* |
501 | * If we have timedout 3 times on trying to acquire | |
502 | * the inter-port SMBI semaphore, there is old code | |
503 | * operating on the other port, and it is not | |
504 | * releasing SMBI. Modify the number of times that | |
505 | * we try for the semaphore to interwork with this | |
506 | * older code. | |
507 | */ | |
508 | if (hw->dev_spec.e82571.smb_counter > 2) | |
509 | sw_timeout = 1; | |
510 | ||
511 | /* Get the SW semaphore */ | |
512 | while (i < sw_timeout) { | |
513 | swsm = er32(SWSM); | |
514 | if (!(swsm & E1000_SWSM_SMBI)) | |
515 | break; | |
516 | ||
517 | udelay(50); | |
518 | i++; | |
519 | } | |
520 | ||
521 | if (i == sw_timeout) { | |
3bb99fe2 | 522 | e_dbg("Driver can't access device - SMBI bit is set.\n"); |
23a2d1b2 DG |
523 | hw->dev_spec.e82571.smb_counter++; |
524 | } | |
bc7f75fa | 525 | /* Get the FW semaphore. */ |
23a2d1b2 | 526 | for (i = 0; i < fw_timeout; i++) { |
bc7f75fa AK |
527 | swsm = er32(SWSM); |
528 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
529 | ||
530 | /* Semaphore acquired if bit latched */ | |
531 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
532 | break; | |
533 | ||
534 | udelay(50); | |
535 | } | |
536 | ||
23a2d1b2 | 537 | if (i == fw_timeout) { |
bc7f75fa | 538 | /* Release semaphores */ |
23a2d1b2 | 539 | e1000_put_hw_semaphore_82571(hw); |
3bb99fe2 | 540 | e_dbg("Driver can't access the NVM\n"); |
bc7f75fa AK |
541 | return -E1000_ERR_NVM; |
542 | } | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
547 | /** | |
548 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
549 | * @hw: pointer to the HW structure | |
550 | * | |
551 | * Release hardware semaphore used to access the PHY or NVM | |
552 | **/ | |
553 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
554 | { | |
555 | u32 swsm; | |
556 | ||
557 | swsm = er32(SWSM); | |
23a2d1b2 | 558 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
bc7f75fa AK |
559 | ew32(SWSM, swsm); |
560 | } | |
1b98c2bb BA |
561 | /** |
562 | * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore | |
563 | * @hw: pointer to the HW structure | |
564 | * | |
565 | * Acquire the HW semaphore during reset. | |
566 | * | |
567 | **/ | |
568 | static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) | |
569 | { | |
570 | u32 extcnf_ctrl; | |
571 | s32 ret_val = 0; | |
572 | s32 i = 0; | |
573 | ||
574 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
575 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
576 | do { | |
577 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
578 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
579 | ||
580 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
581 | break; | |
582 | ||
583 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
584 | ||
585 | msleep(2); | |
586 | i++; | |
587 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
588 | ||
589 | if (i == MDIO_OWNERSHIP_TIMEOUT) { | |
590 | /* Release semaphores */ | |
591 | e1000_put_hw_semaphore_82573(hw); | |
592 | e_dbg("Driver can't access the PHY\n"); | |
593 | ret_val = -E1000_ERR_PHY; | |
594 | goto out; | |
595 | } | |
596 | ||
597 | out: | |
598 | return ret_val; | |
599 | } | |
600 | ||
601 | /** | |
602 | * e1000_put_hw_semaphore_82573 - Release hardware semaphore | |
603 | * @hw: pointer to the HW structure | |
604 | * | |
605 | * Release hardware semaphore used during reset. | |
606 | * | |
607 | **/ | |
608 | static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) | |
609 | { | |
610 | u32 extcnf_ctrl; | |
611 | ||
612 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
613 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
614 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
615 | } | |
616 | ||
617 | static DEFINE_MUTEX(swflag_mutex); | |
618 | ||
619 | /** | |
620 | * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore | |
621 | * @hw: pointer to the HW structure | |
622 | * | |
623 | * Acquire the HW semaphore to access the PHY or NVM. | |
624 | * | |
625 | **/ | |
626 | static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) | |
627 | { | |
628 | s32 ret_val; | |
629 | ||
630 | mutex_lock(&swflag_mutex); | |
631 | ret_val = e1000_get_hw_semaphore_82573(hw); | |
632 | if (ret_val) | |
633 | mutex_unlock(&swflag_mutex); | |
634 | return ret_val; | |
635 | } | |
636 | ||
637 | /** | |
638 | * e1000_put_hw_semaphore_82574 - Release hardware semaphore | |
639 | * @hw: pointer to the HW structure | |
640 | * | |
641 | * Release hardware semaphore used to access the PHY or NVM | |
642 | * | |
643 | **/ | |
644 | static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) | |
645 | { | |
646 | e1000_put_hw_semaphore_82573(hw); | |
647 | mutex_unlock(&swflag_mutex); | |
648 | } | |
bc7f75fa AK |
649 | |
650 | /** | |
651 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
652 | * @hw: pointer to the HW structure | |
653 | * | |
654 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
655 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
656 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
657 | * hardware semaphore. | |
658 | **/ | |
659 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
660 | { | |
661 | s32 ret_val; | |
662 | ||
663 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
664 | if (ret_val) | |
665 | return ret_val; | |
666 | ||
8c81c9c3 AD |
667 | switch (hw->mac.type) { |
668 | case e1000_82573: | |
8c81c9c3 AD |
669 | break; |
670 | default: | |
bc7f75fa | 671 | ret_val = e1000e_acquire_nvm(hw); |
8c81c9c3 AD |
672 | break; |
673 | } | |
bc7f75fa AK |
674 | |
675 | if (ret_val) | |
676 | e1000_put_hw_semaphore_82571(hw); | |
677 | ||
678 | return ret_val; | |
679 | } | |
680 | ||
681 | /** | |
682 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
683 | * @hw: pointer to the HW structure | |
684 | * | |
685 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
686 | **/ | |
687 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
688 | { | |
689 | e1000e_release_nvm(hw); | |
690 | e1000_put_hw_semaphore_82571(hw); | |
691 | } | |
692 | ||
693 | /** | |
694 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
695 | * @hw: pointer to the HW structure | |
696 | * @offset: offset within the EEPROM to be written to | |
697 | * @words: number of words to write | |
698 | * @data: 16 bit word(s) to be written to the EEPROM | |
699 | * | |
700 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
701 | * | |
702 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 703 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
704 | **/ |
705 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
706 | u16 *data) | |
707 | { | |
708 | s32 ret_val; | |
709 | ||
710 | switch (hw->mac.type) { | |
711 | case e1000_82573: | |
4662e82b | 712 | case e1000_82574: |
8c81c9c3 | 713 | case e1000_82583: |
bc7f75fa AK |
714 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
715 | break; | |
716 | case e1000_82571: | |
717 | case e1000_82572: | |
718 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
719 | break; | |
720 | default: | |
721 | ret_val = -E1000_ERR_NVM; | |
722 | break; | |
723 | } | |
724 | ||
725 | return ret_val; | |
726 | } | |
727 | ||
728 | /** | |
729 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
730 | * @hw: pointer to the HW structure | |
731 | * | |
732 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
733 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
734 | * value to the EEPROM. | |
735 | **/ | |
736 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
737 | { | |
738 | u32 eecd; | |
739 | s32 ret_val; | |
740 | u16 i; | |
741 | ||
742 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
743 | if (ret_val) | |
744 | return ret_val; | |
745 | ||
ad68076e BA |
746 | /* |
747 | * If our nvm is an EEPROM, then we're done | |
748 | * otherwise, commit the checksum to the flash NVM. | |
749 | */ | |
bc7f75fa AK |
750 | if (hw->nvm.type != e1000_nvm_flash_hw) |
751 | return ret_val; | |
752 | ||
753 | /* Check for pending operations. */ | |
754 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
755 | msleep(1); | |
756 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
757 | break; | |
758 | } | |
759 | ||
760 | if (i == E1000_FLASH_UPDATES) | |
761 | return -E1000_ERR_NVM; | |
762 | ||
763 | /* Reset the firmware if using STM opcode. */ | |
764 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
765 | /* |
766 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
767 | * in two write cycles. |
768 | */ | |
769 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
770 | e1e_flush(); | |
771 | ew32(HICR, E1000_HICR_FW_RESET); | |
772 | } | |
773 | ||
774 | /* Commit the write to flash */ | |
775 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
776 | ew32(EECD, eecd); | |
777 | ||
778 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
779 | msleep(1); | |
780 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
781 | break; | |
782 | } | |
783 | ||
784 | if (i == E1000_FLASH_UPDATES) | |
785 | return -E1000_ERR_NVM; | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
790 | /** | |
791 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
792 | * @hw: pointer to the HW structure | |
793 | * | |
794 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
795 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
796 | **/ | |
797 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
798 | { | |
799 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
800 | e1000_fix_nvm_checksum_82571(hw); | |
801 | ||
802 | return e1000e_validate_nvm_checksum_generic(hw); | |
803 | } | |
804 | ||
805 | /** | |
806 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
807 | * @hw: pointer to the HW structure | |
808 | * @offset: offset within the EEPROM to be written to | |
809 | * @words: number of words to write | |
810 | * @data: 16 bit word(s) to be written to the EEPROM | |
811 | * | |
812 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
813 | * command has completed before trying to write the next word. After write | |
814 | * poll for completion. | |
815 | * | |
816 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 817 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
818 | **/ |
819 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
820 | u16 words, u16 *data) | |
821 | { | |
822 | struct e1000_nvm_info *nvm = &hw->nvm; | |
a708dd88 | 823 | u32 i, eewr = 0; |
bc7f75fa AK |
824 | s32 ret_val = 0; |
825 | ||
ad68076e BA |
826 | /* |
827 | * A check for invalid values: offset too large, too many words, | |
828 | * and not enough words. | |
829 | */ | |
bc7f75fa AK |
830 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
831 | (words == 0)) { | |
3bb99fe2 | 832 | e_dbg("nvm parameter(s) out of bounds\n"); |
bc7f75fa AK |
833 | return -E1000_ERR_NVM; |
834 | } | |
835 | ||
836 | for (i = 0; i < words; i++) { | |
837 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
838 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
839 | E1000_NVM_RW_REG_START; | |
840 | ||
841 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
842 | if (ret_val) | |
843 | break; | |
844 | ||
845 | ew32(EEWR, eewr); | |
846 | ||
847 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
848 | if (ret_val) | |
849 | break; | |
850 | } | |
851 | ||
852 | return ret_val; | |
853 | } | |
854 | ||
855 | /** | |
856 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
857 | * @hw: pointer to the HW structure | |
858 | * | |
859 | * Reads the management control register for the config done bit to be set. | |
860 | **/ | |
861 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
862 | { | |
863 | s32 timeout = PHY_CFG_TIMEOUT; | |
864 | ||
865 | while (timeout) { | |
866 | if (er32(EEMNGCTL) & | |
867 | E1000_NVM_CFG_DONE_PORT_0) | |
868 | break; | |
869 | msleep(1); | |
870 | timeout--; | |
871 | } | |
872 | if (!timeout) { | |
3bb99fe2 | 873 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
874 | return -E1000_ERR_RESET; |
875 | } | |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
880 | /** | |
881 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
882 | * @hw: pointer to the HW structure | |
564ea9bb | 883 | * @active: true to enable LPLU, false to disable |
bc7f75fa AK |
884 | * |
885 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
886 | * this function also disables smart speed and vice versa. LPLU will not be | |
887 | * activated unless the device autonegotiation advertisement meets standards | |
888 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
889 | * pointer entry point only called by PHY setup routines. | |
890 | **/ | |
891 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
892 | { | |
893 | struct e1000_phy_info *phy = &hw->phy; | |
894 | s32 ret_val; | |
895 | u16 data; | |
896 | ||
897 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
898 | if (ret_val) | |
899 | return ret_val; | |
900 | ||
901 | if (active) { | |
902 | data |= IGP02E1000_PM_D0_LPLU; | |
903 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
904 | if (ret_val) | |
905 | return ret_val; | |
906 | ||
907 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
908 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
909 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
910 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
911 | if (ret_val) | |
912 | return ret_val; | |
913 | } else { | |
914 | data &= ~IGP02E1000_PM_D0_LPLU; | |
915 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
916 | /* |
917 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
918 | * during Dx states where the power conservation is most |
919 | * important. During driver activity we should enable | |
ad68076e BA |
920 | * SmartSpeed, so performance is maintained. |
921 | */ | |
bc7f75fa AK |
922 | if (phy->smart_speed == e1000_smart_speed_on) { |
923 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 924 | &data); |
bc7f75fa AK |
925 | if (ret_val) |
926 | return ret_val; | |
927 | ||
928 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
929 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 930 | data); |
bc7f75fa AK |
931 | if (ret_val) |
932 | return ret_val; | |
933 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
934 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 935 | &data); |
bc7f75fa AK |
936 | if (ret_val) |
937 | return ret_val; | |
938 | ||
939 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
940 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 941 | data); |
bc7f75fa AK |
942 | if (ret_val) |
943 | return ret_val; | |
944 | } | |
945 | } | |
946 | ||
947 | return 0; | |
948 | } | |
949 | ||
950 | /** | |
951 | * e1000_reset_hw_82571 - Reset hardware | |
952 | * @hw: pointer to the HW structure | |
953 | * | |
fe401674 | 954 | * This resets the hardware into a known state. |
bc7f75fa AK |
955 | **/ |
956 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
957 | { | |
1b98c2bb | 958 | u32 ctrl, ctrl_ext, icr; |
bc7f75fa | 959 | s32 ret_val; |
bc7f75fa | 960 | |
ad68076e BA |
961 | /* |
962 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
963 | * on the last TLP read/write transaction when MAC is reset. |
964 | */ | |
965 | ret_val = e1000e_disable_pcie_master(hw); | |
966 | if (ret_val) | |
3bb99fe2 | 967 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 968 | |
3bb99fe2 | 969 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
970 | ew32(IMC, 0xffffffff); |
971 | ||
972 | ew32(RCTL, 0); | |
973 | ew32(TCTL, E1000_TCTL_PSP); | |
974 | e1e_flush(); | |
975 | ||
976 | msleep(10); | |
977 | ||
ad68076e BA |
978 | /* |
979 | * Must acquire the MDIO ownership before MAC reset. | |
980 | * Ownership defaults to firmware after a reset. | |
981 | */ | |
8c81c9c3 AD |
982 | switch (hw->mac.type) { |
983 | case e1000_82573: | |
1b98c2bb BA |
984 | ret_val = e1000_get_hw_semaphore_82573(hw); |
985 | break; | |
8c81c9c3 AD |
986 | case e1000_82574: |
987 | case e1000_82583: | |
1b98c2bb | 988 | ret_val = e1000_get_hw_semaphore_82574(hw); |
8c81c9c3 AD |
989 | break; |
990 | default: | |
991 | break; | |
bc7f75fa | 992 | } |
1b98c2bb BA |
993 | if (ret_val) |
994 | e_dbg("Cannot acquire MDIO ownership\n"); | |
bc7f75fa AK |
995 | |
996 | ctrl = er32(CTRL); | |
997 | ||
3bb99fe2 | 998 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa AK |
999 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
1000 | ||
1b98c2bb BA |
1001 | /* Must release MDIO ownership and mutex after MAC reset. */ |
1002 | switch (hw->mac.type) { | |
1003 | case e1000_82574: | |
1004 | case e1000_82583: | |
1005 | e1000_put_hw_semaphore_82574(hw); | |
1006 | break; | |
1007 | default: | |
1008 | break; | |
1009 | } | |
1010 | ||
bc7f75fa AK |
1011 | if (hw->nvm.type == e1000_nvm_flash_hw) { |
1012 | udelay(10); | |
1013 | ctrl_ext = er32(CTRL_EXT); | |
1014 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
1015 | ew32(CTRL_EXT, ctrl_ext); | |
1016 | e1e_flush(); | |
1017 | } | |
1018 | ||
1019 | ret_val = e1000e_get_auto_rd_done(hw); | |
1020 | if (ret_val) | |
1021 | /* We don't want to continue accessing MAC registers. */ | |
1022 | return ret_val; | |
1023 | ||
ad68076e BA |
1024 | /* |
1025 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
1026 | * Need to wait for Phy configuration completion before accessing |
1027 | * NVM and Phy. | |
1028 | */ | |
8c81c9c3 AD |
1029 | |
1030 | switch (hw->mac.type) { | |
1031 | case e1000_82573: | |
1032 | case e1000_82574: | |
1033 | case e1000_82583: | |
bc7f75fa | 1034 | msleep(25); |
8c81c9c3 AD |
1035 | break; |
1036 | default: | |
1037 | break; | |
1038 | } | |
bc7f75fa AK |
1039 | |
1040 | /* Clear any pending interrupt events. */ | |
1041 | ew32(IMC, 0xffffffff); | |
1042 | icr = er32(ICR); | |
1043 | ||
1aef70ef BA |
1044 | if (hw->mac.type == e1000_82571) { |
1045 | /* Install any alternate MAC address into RAR0 */ | |
1046 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
1047 | if (ret_val) | |
1048 | return ret_val; | |
608f8a0d | 1049 | |
1aef70ef BA |
1050 | e1000e_set_laa_state_82571(hw, true); |
1051 | } | |
93ca1610 | 1052 | |
c9523379 | 1053 | /* Reinitialize the 82571 serdes link state machine */ |
1054 | if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
1055 | hw->mac.serdes_link_state = e1000_serdes_link_down; | |
1056 | ||
bc7f75fa AK |
1057 | return 0; |
1058 | } | |
1059 | ||
1060 | /** | |
1061 | * e1000_init_hw_82571 - Initialize hardware | |
1062 | * @hw: pointer to the HW structure | |
1063 | * | |
1064 | * This inits the hardware readying it for operation. | |
1065 | **/ | |
1066 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
1067 | { | |
1068 | struct e1000_mac_info *mac = &hw->mac; | |
1069 | u32 reg_data; | |
1070 | s32 ret_val; | |
a708dd88 | 1071 | u16 i, rar_count = mac->rar_entry_count; |
bc7f75fa AK |
1072 | |
1073 | e1000_initialize_hw_bits_82571(hw); | |
1074 | ||
1075 | /* Initialize identification LED */ | |
1076 | ret_val = e1000e_id_led_init(hw); | |
de39b752 | 1077 | if (ret_val) |
3bb99fe2 | 1078 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 1079 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
1080 | |
1081 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 1082 | e_dbg("Initializing the IEEE VLAN\n"); |
caaddaf8 | 1083 | mac->ops.clear_vfta(hw); |
bc7f75fa AK |
1084 | |
1085 | /* Setup the receive address. */ | |
ad68076e BA |
1086 | /* |
1087 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
1088 | * 82571, we must reserve a RAR for it to work around an issue where |
1089 | * resetting one port will reload the MAC on the other port. | |
1090 | */ | |
1091 | if (e1000e_get_laa_state_82571(hw)) | |
1092 | rar_count--; | |
1093 | e1000e_init_rx_addrs(hw, rar_count); | |
1094 | ||
1095 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 1096 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
1097 | for (i = 0; i < mac->mta_reg_count; i++) |
1098 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
1099 | ||
1100 | /* Setup link and flow control */ | |
1101 | ret_val = e1000_setup_link_82571(hw); | |
1102 | ||
1103 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 1104 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
1105 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
1106 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
1107 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1108 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
1109 | |
1110 | /* ...for both queues. */ | |
8c81c9c3 AD |
1111 | switch (mac->type) { |
1112 | case e1000_82573: | |
a65a4a0d BA |
1113 | e1000e_enable_tx_pkt_filtering(hw); |
1114 | /* fall through */ | |
8c81c9c3 AD |
1115 | case e1000_82574: |
1116 | case e1000_82583: | |
8c81c9c3 AD |
1117 | reg_data = er32(GCR); |
1118 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
1119 | ew32(GCR, reg_data); | |
1120 | break; | |
1121 | default: | |
e9ec2c0f | 1122 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
1123 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
1124 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
1125 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1126 | ew32(TXDCTL(1), reg_data); |
8c81c9c3 | 1127 | break; |
bc7f75fa AK |
1128 | } |
1129 | ||
ad68076e BA |
1130 | /* |
1131 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
1132 | * important that we do this after we have tried to establish link |
1133 | * because the symbol error count will increment wildly if there | |
1134 | * is no link. | |
1135 | */ | |
1136 | e1000_clear_hw_cntrs_82571(hw); | |
1137 | ||
1138 | return ret_val; | |
1139 | } | |
1140 | ||
1141 | /** | |
1142 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
1143 | * @hw: pointer to the HW structure | |
1144 | * | |
1145 | * Initializes required hardware-dependent bits needed for normal operation. | |
1146 | **/ | |
1147 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
1148 | { | |
1149 | u32 reg; | |
1150 | ||
1151 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 1152 | reg = er32(TXDCTL(0)); |
bc7f75fa | 1153 | reg |= (1 << 22); |
e9ec2c0f | 1154 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
1155 | |
1156 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 1157 | reg = er32(TXDCTL(1)); |
bc7f75fa | 1158 | reg |= (1 << 22); |
e9ec2c0f | 1159 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
1160 | |
1161 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 1162 | reg = er32(TARC(0)); |
bc7f75fa AK |
1163 | reg &= ~(0xF << 27); /* 30:27 */ |
1164 | switch (hw->mac.type) { | |
1165 | case e1000_82571: | |
1166 | case e1000_82572: | |
1167 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
1168 | break; | |
1169 | default: | |
1170 | break; | |
1171 | } | |
e9ec2c0f | 1172 | ew32(TARC(0), reg); |
bc7f75fa AK |
1173 | |
1174 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 1175 | reg = er32(TARC(1)); |
bc7f75fa AK |
1176 | switch (hw->mac.type) { |
1177 | case e1000_82571: | |
1178 | case e1000_82572: | |
1179 | reg &= ~((1 << 29) | (1 << 30)); | |
1180 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
1181 | if (er32(TCTL) & E1000_TCTL_MULR) | |
1182 | reg &= ~(1 << 28); | |
1183 | else | |
1184 | reg |= (1 << 28); | |
e9ec2c0f | 1185 | ew32(TARC(1), reg); |
bc7f75fa AK |
1186 | break; |
1187 | default: | |
1188 | break; | |
1189 | } | |
1190 | ||
1191 | /* Device Control */ | |
8c81c9c3 AD |
1192 | switch (hw->mac.type) { |
1193 | case e1000_82573: | |
1194 | case e1000_82574: | |
1195 | case e1000_82583: | |
bc7f75fa AK |
1196 | reg = er32(CTRL); |
1197 | reg &= ~(1 << 29); | |
1198 | ew32(CTRL, reg); | |
8c81c9c3 AD |
1199 | break; |
1200 | default: | |
1201 | break; | |
bc7f75fa AK |
1202 | } |
1203 | ||
1204 | /* Extended Device Control */ | |
8c81c9c3 AD |
1205 | switch (hw->mac.type) { |
1206 | case e1000_82573: | |
1207 | case e1000_82574: | |
1208 | case e1000_82583: | |
bc7f75fa AK |
1209 | reg = er32(CTRL_EXT); |
1210 | reg &= ~(1 << 23); | |
1211 | reg |= (1 << 22); | |
1212 | ew32(CTRL_EXT, reg); | |
8c81c9c3 AD |
1213 | break; |
1214 | default: | |
1215 | break; | |
bc7f75fa | 1216 | } |
4662e82b | 1217 | |
6ea7ae1d AD |
1218 | if (hw->mac.type == e1000_82571) { |
1219 | reg = er32(PBA_ECC); | |
1220 | reg |= E1000_PBA_ECC_CORR_EN; | |
1221 | ew32(PBA_ECC, reg); | |
1222 | } | |
5df3f0ea | 1223 | /* |
1224 | * Workaround for hardware errata. | |
1225 | * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 | |
1226 | */ | |
1227 | ||
1228 | if ((hw->mac.type == e1000_82571) || | |
1229 | (hw->mac.type == e1000_82572)) { | |
1230 | reg = er32(CTRL_EXT); | |
1231 | reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; | |
1232 | ew32(CTRL_EXT, reg); | |
1233 | } | |
1234 | ||
6ea7ae1d | 1235 | |
78272bba | 1236 | /* PCI-Ex Control Registers */ |
8c81c9c3 AD |
1237 | switch (hw->mac.type) { |
1238 | case e1000_82574: | |
1239 | case e1000_82583: | |
4662e82b BA |
1240 | reg = er32(GCR); |
1241 | reg |= (1 << 22); | |
1242 | ew32(GCR, reg); | |
78272bba | 1243 | |
84efb7b9 BA |
1244 | /* |
1245 | * Workaround for hardware errata. | |
1246 | * apply workaround for hardware errata documented in errata | |
1247 | * docs Fixes issue where some error prone or unreliable PCIe | |
1248 | * completions are occurring, particularly with ASPM enabled. | |
1249 | * Without fix, issue can cause tx timeouts. | |
1250 | */ | |
78272bba JB |
1251 | reg = er32(GCR2); |
1252 | reg |= 1; | |
1253 | ew32(GCR2, reg); | |
8c81c9c3 AD |
1254 | break; |
1255 | default: | |
1256 | break; | |
4662e82b | 1257 | } |
bc7f75fa AK |
1258 | } |
1259 | ||
1260 | /** | |
caaddaf8 | 1261 | * e1000_clear_vfta_82571 - Clear VLAN filter table |
bc7f75fa AK |
1262 | * @hw: pointer to the HW structure |
1263 | * | |
1264 | * Clears the register array which contains the VLAN filter table by | |
1265 | * setting all the values to 0. | |
1266 | **/ | |
caaddaf8 | 1267 | static void e1000_clear_vfta_82571(struct e1000_hw *hw) |
bc7f75fa AK |
1268 | { |
1269 | u32 offset; | |
1270 | u32 vfta_value = 0; | |
1271 | u32 vfta_offset = 0; | |
1272 | u32 vfta_bit_in_reg = 0; | |
1273 | ||
8c81c9c3 AD |
1274 | switch (hw->mac.type) { |
1275 | case e1000_82573: | |
1276 | case e1000_82574: | |
1277 | case e1000_82583: | |
bc7f75fa | 1278 | if (hw->mng_cookie.vlan_id != 0) { |
ad68076e BA |
1279 | /* |
1280 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
1281 | * a single VLAN ID. The following operations |
1282 | * determine which 32b entry (i.e. offset) into the | |
1283 | * array we want to set the VLAN ID (i.e. bit) of | |
1284 | * the manageability unit. | |
1285 | */ | |
1286 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
1287 | E1000_VFTA_ENTRY_SHIFT) & | |
1288 | E1000_VFTA_ENTRY_MASK; | |
1289 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
1290 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
1291 | } | |
8c81c9c3 AD |
1292 | break; |
1293 | default: | |
1294 | break; | |
bc7f75fa AK |
1295 | } |
1296 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
1297 | /* |
1298 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
1299 | * manageability VLAN ID, then clear all bits except that of |
1300 | * the manageability unit. | |
1301 | */ | |
1302 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
1303 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
1304 | e1e_flush(); | |
1305 | } | |
1306 | } | |
1307 | ||
4662e82b BA |
1308 | /** |
1309 | * e1000_check_mng_mode_82574 - Check manageability is enabled | |
1310 | * @hw: pointer to the HW structure | |
1311 | * | |
1312 | * Reads the NVM Initialization Control Word 2 and returns true | |
1313 | * (>0) if any manageability is enabled, else false (0). | |
1314 | **/ | |
1315 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) | |
1316 | { | |
1317 | u16 data; | |
1318 | ||
1319 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
1320 | return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; | |
1321 | } | |
1322 | ||
1323 | /** | |
1324 | * e1000_led_on_82574 - Turn LED on | |
1325 | * @hw: pointer to the HW structure | |
1326 | * | |
1327 | * Turn LED on. | |
1328 | **/ | |
1329 | static s32 e1000_led_on_82574(struct e1000_hw *hw) | |
1330 | { | |
1331 | u32 ctrl; | |
1332 | u32 i; | |
1333 | ||
1334 | ctrl = hw->mac.ledctl_mode2; | |
1335 | if (!(E1000_STATUS_LU & er32(STATUS))) { | |
1336 | /* | |
1337 | * If no link, then turn LED on by setting the invert bit | |
1338 | * for each LED that's "on" (0x0E) in ledctl_mode2. | |
1339 | */ | |
1340 | for (i = 0; i < 4; i++) | |
1341 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1342 | E1000_LEDCTL_MODE_LED_ON) | |
1343 | ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); | |
1344 | } | |
1345 | ew32(LEDCTL, ctrl); | |
1346 | ||
1347 | return 0; | |
1348 | } | |
1349 | ||
ff10e13c CW |
1350 | /** |
1351 | * e1000_check_phy_82574 - check 82574 phy hung state | |
1352 | * @hw: pointer to the HW structure | |
1353 | * | |
1354 | * Returns whether phy is hung or not | |
1355 | **/ | |
1356 | bool e1000_check_phy_82574(struct e1000_hw *hw) | |
1357 | { | |
1358 | u16 status_1kbt = 0; | |
1359 | u16 receive_errors = 0; | |
1360 | bool phy_hung = false; | |
1361 | s32 ret_val = 0; | |
1362 | ||
1363 | /* | |
1364 | * Read PHY Receive Error counter first, if its is max - all F's then | |
1365 | * read the Base1000T status register If both are max then PHY is hung. | |
1366 | */ | |
1367 | ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); | |
1368 | ||
1369 | if (ret_val) | |
1370 | goto out; | |
1371 | if (receive_errors == E1000_RECEIVE_ERROR_MAX) { | |
1372 | ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt); | |
1373 | if (ret_val) | |
1374 | goto out; | |
1375 | if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == | |
1376 | E1000_IDLE_ERROR_COUNT_MASK) | |
1377 | phy_hung = true; | |
1378 | } | |
1379 | out: | |
1380 | return phy_hung; | |
1381 | } | |
1382 | ||
bc7f75fa AK |
1383 | /** |
1384 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1385 | * @hw: pointer to the HW structure | |
1386 | * | |
1387 | * Determines which flow control settings to use, then configures flow | |
1388 | * control. Calls the appropriate media-specific link configuration | |
1389 | * function. Assuming the adapter has a valid link partner, a valid link | |
1390 | * should be established. Assumes the hardware has previously been reset | |
1391 | * and the transmitter and receiver are not enabled. | |
1392 | **/ | |
1393 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1394 | { | |
ad68076e BA |
1395 | /* |
1396 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1397 | * the default flow control setting, so we explicitly |
1398 | * set it to full. | |
1399 | */ | |
8c81c9c3 AD |
1400 | switch (hw->mac.type) { |
1401 | case e1000_82573: | |
1402 | case e1000_82574: | |
1403 | case e1000_82583: | |
1404 | if (hw->fc.requested_mode == e1000_fc_default) | |
1405 | hw->fc.requested_mode = e1000_fc_full; | |
1406 | break; | |
1407 | default: | |
1408 | break; | |
1409 | } | |
bc7f75fa AK |
1410 | |
1411 | return e1000e_setup_link(hw); | |
1412 | } | |
1413 | ||
1414 | /** | |
1415 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1416 | * @hw: pointer to the HW structure | |
1417 | * | |
1418 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1419 | * for link, once link is established calls to configure collision distance | |
1420 | * and flow control are called. | |
1421 | **/ | |
1422 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1423 | { | |
1424 | u32 ctrl; | |
bc7f75fa AK |
1425 | s32 ret_val; |
1426 | ||
1427 | ctrl = er32(CTRL); | |
1428 | ctrl |= E1000_CTRL_SLU; | |
1429 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1430 | ew32(CTRL, ctrl); | |
1431 | ||
1432 | switch (hw->phy.type) { | |
1433 | case e1000_phy_m88: | |
4662e82b | 1434 | case e1000_phy_bm: |
bc7f75fa AK |
1435 | ret_val = e1000e_copper_link_setup_m88(hw); |
1436 | break; | |
1437 | case e1000_phy_igp_2: | |
1438 | ret_val = e1000e_copper_link_setup_igp(hw); | |
bc7f75fa AK |
1439 | break; |
1440 | default: | |
1441 | return -E1000_ERR_PHY; | |
1442 | break; | |
1443 | } | |
1444 | ||
1445 | if (ret_val) | |
1446 | return ret_val; | |
1447 | ||
1448 | ret_val = e1000e_setup_copper_link(hw); | |
1449 | ||
1450 | return ret_val; | |
1451 | } | |
1452 | ||
1453 | /** | |
1454 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1455 | * @hw: pointer to the HW structure | |
1456 | * | |
1457 | * Configures collision distance and flow control for fiber and serdes links. | |
1458 | * Upon successful setup, poll for link. | |
1459 | **/ | |
1460 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1461 | { | |
1462 | switch (hw->mac.type) { | |
1463 | case e1000_82571: | |
1464 | case e1000_82572: | |
ad68076e BA |
1465 | /* |
1466 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1467 | * of reset to take the adapter out of that mode. So we |
1468 | * have to explicitly take the adapter out of loopback | |
489815ce | 1469 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1470 | * if another tool failed to take it out of loopback mode. |
1471 | */ | |
ad68076e | 1472 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1473 | break; |
1474 | default: | |
1475 | break; | |
1476 | } | |
1477 | ||
1478 | return e1000e_setup_fiber_serdes_link(hw); | |
1479 | } | |
1480 | ||
c9523379 | 1481 | /** |
1482 | * e1000_check_for_serdes_link_82571 - Check for link (Serdes) | |
1483 | * @hw: pointer to the HW structure | |
1484 | * | |
1a40d5c1 BA |
1485 | * Reports the link state as up or down. |
1486 | * | |
1487 | * If autonegotiation is supported by the link partner, the link state is | |
1488 | * determined by the result of autonegotiation. This is the most likely case. | |
1489 | * If autonegotiation is not supported by the link partner, and the link | |
1490 | * has a valid signal, force the link up. | |
1491 | * | |
1492 | * The link state is represented internally here by 4 states: | |
1493 | * | |
1494 | * 1) down | |
1495 | * 2) autoneg_progress | |
3ad2f3fb | 1496 | * 3) autoneg_complete (the link successfully autonegotiated) |
1a40d5c1 BA |
1497 | * 4) forced_up (the link has been forced up, it did not autonegotiate) |
1498 | * | |
c9523379 | 1499 | **/ |
f6370117 | 1500 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
c9523379 | 1501 | { |
1502 | struct e1000_mac_info *mac = &hw->mac; | |
1503 | u32 rxcw; | |
1504 | u32 ctrl; | |
1505 | u32 status; | |
1506 | s32 ret_val = 0; | |
1507 | ||
1508 | ctrl = er32(CTRL); | |
1509 | status = er32(STATUS); | |
1510 | rxcw = er32(RXCW); | |
1511 | ||
1512 | if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { | |
1513 | ||
1514 | /* Receiver is synchronized with no invalid bits. */ | |
1515 | switch (mac->serdes_link_state) { | |
1516 | case e1000_serdes_link_autoneg_complete: | |
1517 | if (!(status & E1000_STATUS_LU)) { | |
1518 | /* | |
1519 | * We have lost link, retry autoneg before | |
1520 | * reporting link failure | |
1521 | */ | |
1522 | mac->serdes_link_state = | |
1523 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1524 | mac->serdes_has_link = false; |
3bb99fe2 | 1525 | e_dbg("AN_UP -> AN_PROG\n"); |
c9523379 | 1526 | } |
1527 | break; | |
1528 | ||
1529 | case e1000_serdes_link_forced_up: | |
1530 | /* | |
1531 | * If we are receiving /C/ ordered sets, re-enable | |
1532 | * auto-negotiation in the TXCW register and disable | |
1533 | * forced link in the Device Control register in an | |
1534 | * attempt to auto-negotiate with our link partner. | |
d478eb44 BA |
1535 | * If the partner code word is null, stop forcing |
1536 | * and restart auto negotiation. | |
c9523379 | 1537 | */ |
d478eb44 | 1538 | if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { |
c9523379 | 1539 | /* Enable autoneg, and unforce link up */ |
1540 | ew32(TXCW, mac->txcw); | |
1a40d5c1 | 1541 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1542 | mac->serdes_link_state = |
1543 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1544 | mac->serdes_has_link = false; |
3bb99fe2 | 1545 | e_dbg("FORCED_UP -> AN_PROG\n"); |
c9523379 | 1546 | } |
1547 | break; | |
1548 | ||
1549 | case e1000_serdes_link_autoneg_progress: | |
1a40d5c1 BA |
1550 | if (rxcw & E1000_RXCW_C) { |
1551 | /* | |
1552 | * We received /C/ ordered sets, meaning the | |
1553 | * link partner has autonegotiated, and we can | |
1554 | * trust the Link Up (LU) status bit. | |
1555 | */ | |
1556 | if (status & E1000_STATUS_LU) { | |
1557 | mac->serdes_link_state = | |
1558 | e1000_serdes_link_autoneg_complete; | |
1559 | e_dbg("AN_PROG -> AN_UP\n"); | |
1560 | mac->serdes_has_link = true; | |
1561 | } else { | |
1562 | /* Autoneg completed, but failed. */ | |
1563 | mac->serdes_link_state = | |
1564 | e1000_serdes_link_down; | |
1565 | e_dbg("AN_PROG -> DOWN\n"); | |
1566 | } | |
c9523379 | 1567 | } else { |
1568 | /* | |
1a40d5c1 BA |
1569 | * The link partner did not autoneg. |
1570 | * Force link up and full duplex, and change | |
1571 | * state to forced. | |
c9523379 | 1572 | */ |
1a40d5c1 | 1573 | ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
c9523379 | 1574 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
1575 | ew32(CTRL, ctrl); | |
1576 | ||
1577 | /* Configure Flow Control after link up. */ | |
1a40d5c1 | 1578 | ret_val = e1000e_config_fc_after_link_up(hw); |
c9523379 | 1579 | if (ret_val) { |
3bb99fe2 | 1580 | e_dbg("Error config flow control\n"); |
c9523379 | 1581 | break; |
1582 | } | |
1583 | mac->serdes_link_state = | |
1584 | e1000_serdes_link_forced_up; | |
1a40d5c1 | 1585 | mac->serdes_has_link = true; |
3bb99fe2 | 1586 | e_dbg("AN_PROG -> FORCED_UP\n"); |
c9523379 | 1587 | } |
c9523379 | 1588 | break; |
1589 | ||
1590 | case e1000_serdes_link_down: | |
1591 | default: | |
1a40d5c1 BA |
1592 | /* |
1593 | * The link was down but the receiver has now gained | |
c9523379 | 1594 | * valid sync, so lets see if we can bring the link |
1a40d5c1 BA |
1595 | * up. |
1596 | */ | |
c9523379 | 1597 | ew32(TXCW, mac->txcw); |
1a40d5c1 | 1598 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1599 | mac->serdes_link_state = |
1600 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1601 | e_dbg("DOWN -> AN_PROG\n"); |
c9523379 | 1602 | break; |
1603 | } | |
1604 | } else { | |
1605 | if (!(rxcw & E1000_RXCW_SYNCH)) { | |
1606 | mac->serdes_has_link = false; | |
1607 | mac->serdes_link_state = e1000_serdes_link_down; | |
3bb99fe2 | 1608 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1609 | } else { |
1610 | /* | |
1a40d5c1 BA |
1611 | * We have sync, and can tolerate one invalid (IV) |
1612 | * codeword before declaring link down, so reread | |
1613 | * to look again. | |
c9523379 | 1614 | */ |
1615 | udelay(10); | |
1616 | rxcw = er32(RXCW); | |
1617 | if (rxcw & E1000_RXCW_IV) { | |
1618 | mac->serdes_link_state = e1000_serdes_link_down; | |
1619 | mac->serdes_has_link = false; | |
3bb99fe2 | 1620 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1621 | } |
1622 | } | |
1623 | } | |
1624 | ||
1625 | return ret_val; | |
1626 | } | |
1627 | ||
bc7f75fa AK |
1628 | /** |
1629 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1630 | * @hw: pointer to the HW structure | |
1631 | * @data: pointer to the NVM (EEPROM) | |
1632 | * | |
1633 | * Read the EEPROM for the current default LED configuration. If the | |
1634 | * LED configuration is not valid, set to a valid LED configuration. | |
1635 | **/ | |
1636 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1637 | { | |
1638 | s32 ret_val; | |
1639 | ||
1640 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1641 | if (ret_val) { | |
3bb99fe2 | 1642 | e_dbg("NVM Read Error\n"); |
bc7f75fa AK |
1643 | return ret_val; |
1644 | } | |
1645 | ||
8c81c9c3 AD |
1646 | switch (hw->mac.type) { |
1647 | case e1000_82573: | |
1648 | case e1000_82574: | |
1649 | case e1000_82583: | |
1650 | if (*data == ID_LED_RESERVED_F746) | |
1651 | *data = ID_LED_DEFAULT_82573; | |
1652 | break; | |
1653 | default: | |
1654 | if (*data == ID_LED_RESERVED_0000 || | |
1655 | *data == ID_LED_RESERVED_FFFF) | |
1656 | *data = ID_LED_DEFAULT; | |
1657 | break; | |
1658 | } | |
bc7f75fa AK |
1659 | |
1660 | return 0; | |
1661 | } | |
1662 | ||
1663 | /** | |
1664 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1665 | * @hw: pointer to the HW structure | |
1666 | * | |
489815ce | 1667 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1668 | **/ |
1669 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1670 | { | |
1671 | if (hw->mac.type != e1000_82571) | |
564ea9bb | 1672 | return false; |
bc7f75fa AK |
1673 | |
1674 | return hw->dev_spec.e82571.laa_is_present; | |
1675 | } | |
1676 | ||
1677 | /** | |
1678 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1679 | * @hw: pointer to the HW structure | |
1680 | * @state: enable/disable locally administered address | |
1681 | * | |
5ff5b664 | 1682 | * Enable/Disable the current locally administered address state. |
bc7f75fa AK |
1683 | **/ |
1684 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1685 | { | |
1686 | if (hw->mac.type != e1000_82571) | |
1687 | return; | |
1688 | ||
1689 | hw->dev_spec.e82571.laa_is_present = state; | |
1690 | ||
1691 | /* If workaround is activated... */ | |
1692 | if (state) | |
ad68076e BA |
1693 | /* |
1694 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1695 | * between the time RAR[0] gets clobbered and the time it |
1696 | * gets fixed, the actual LAA is in one of the RARs and no | |
1697 | * incoming packets directed to this port are dropped. | |
1698 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1699 | */ | |
1700 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1701 | } | |
1702 | ||
1703 | /** | |
1704 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1705 | * @hw: pointer to the HW structure | |
1706 | * | |
1707 | * Verifies that the EEPROM has completed the update. After updating the | |
1708 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1709 | * the checksum fix is not implemented, we need to set the bit and update | |
1710 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1711 | * we need to return bad checksum. | |
1712 | **/ | |
1713 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1714 | { | |
1715 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1716 | s32 ret_val; | |
1717 | u16 data; | |
1718 | ||
1719 | if (nvm->type != e1000_nvm_flash_hw) | |
1720 | return 0; | |
1721 | ||
ad68076e BA |
1722 | /* |
1723 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1724 | * 10h-12h. Checksum may need to be fixed. |
1725 | */ | |
1726 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1727 | if (ret_val) | |
1728 | return ret_val; | |
1729 | ||
1730 | if (!(data & 0x10)) { | |
ad68076e BA |
1731 | /* |
1732 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1733 | * when the checksum has already been fixed. If |
1734 | * the checksum is still wrong and this bit is a | |
1735 | * 1, we need to return bad checksum. Otherwise, | |
1736 | * we need to set this bit to a 1 and update the | |
1737 | * checksum. | |
1738 | */ | |
1739 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1740 | if (ret_val) | |
1741 | return ret_val; | |
1742 | ||
1743 | if (!(data & 0x8000)) { | |
1744 | data |= 0x8000; | |
1745 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1746 | if (ret_val) | |
1747 | return ret_val; | |
1748 | ret_val = e1000e_update_nvm_checksum(hw); | |
1749 | } | |
1750 | } | |
1751 | ||
1752 | return 0; | |
1753 | } | |
1754 | ||
608f8a0d BA |
1755 | /** |
1756 | * e1000_read_mac_addr_82571 - Read device MAC address | |
1757 | * @hw: pointer to the HW structure | |
1758 | **/ | |
1759 | static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) | |
1760 | { | |
1761 | s32 ret_val = 0; | |
1762 | ||
1aef70ef BA |
1763 | if (hw->mac.type == e1000_82571) { |
1764 | /* | |
1765 | * If there's an alternate MAC address place it in RAR0 | |
1766 | * so that it will override the Si installed default perm | |
1767 | * address. | |
1768 | */ | |
1769 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
1770 | if (ret_val) | |
1771 | goto out; | |
1772 | } | |
608f8a0d BA |
1773 | |
1774 | ret_val = e1000_read_mac_addr_generic(hw); | |
1775 | ||
1776 | out: | |
1777 | return ret_val; | |
1778 | } | |
1779 | ||
17f208de BA |
1780 | /** |
1781 | * e1000_power_down_phy_copper_82571 - Remove link during PHY power down | |
1782 | * @hw: pointer to the HW structure | |
1783 | * | |
1784 | * In the case of a PHY power down to save power, or to turn off link during a | |
1785 | * driver unload, or wake on lan is not enabled, remove the link. | |
1786 | **/ | |
1787 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) | |
1788 | { | |
1789 | struct e1000_phy_info *phy = &hw->phy; | |
1790 | struct e1000_mac_info *mac = &hw->mac; | |
1791 | ||
1792 | if (!(phy->ops.check_reset_block)) | |
1793 | return; | |
1794 | ||
1795 | /* If the management interface is not enabled, then power down */ | |
1796 | if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) | |
1797 | e1000_power_down_phy_copper(hw); | |
17f208de BA |
1798 | } |
1799 | ||
bc7f75fa AK |
1800 | /** |
1801 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1802 | * @hw: pointer to the HW structure | |
1803 | * | |
1804 | * Clears the hardware counters by reading the counter registers. | |
1805 | **/ | |
1806 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1807 | { | |
bc7f75fa AK |
1808 | e1000e_clear_hw_cntrs_base(hw); |
1809 | ||
99673d9b BA |
1810 | er32(PRC64); |
1811 | er32(PRC127); | |
1812 | er32(PRC255); | |
1813 | er32(PRC511); | |
1814 | er32(PRC1023); | |
1815 | er32(PRC1522); | |
1816 | er32(PTC64); | |
1817 | er32(PTC127); | |
1818 | er32(PTC255); | |
1819 | er32(PTC511); | |
1820 | er32(PTC1023); | |
1821 | er32(PTC1522); | |
1822 | ||
1823 | er32(ALGNERRC); | |
1824 | er32(RXERRC); | |
1825 | er32(TNCRS); | |
1826 | er32(CEXTERR); | |
1827 | er32(TSCTC); | |
1828 | er32(TSCTFC); | |
1829 | ||
1830 | er32(MGTPRC); | |
1831 | er32(MGTPDC); | |
1832 | er32(MGTPTC); | |
1833 | ||
1834 | er32(IAC); | |
1835 | er32(ICRXOC); | |
1836 | ||
1837 | er32(ICRXPTC); | |
1838 | er32(ICRXATC); | |
1839 | er32(ICTXPTC); | |
1840 | er32(ICTXATC); | |
1841 | er32(ICTXQEC); | |
1842 | er32(ICTXQMTC); | |
1843 | er32(ICRXDMTC); | |
bc7f75fa AK |
1844 | } |
1845 | ||
1846 | static struct e1000_mac_operations e82571_mac_ops = { | |
4662e82b | 1847 | /* .check_mng_mode: mac type dependent */ |
bc7f75fa | 1848 | /* .check_for_link: media type dependent */ |
a4f58f54 | 1849 | .id_led_init = e1000e_id_led_init, |
bc7f75fa AK |
1850 | .cleanup_led = e1000e_cleanup_led_generic, |
1851 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1852 | .get_bus_info = e1000e_get_bus_info_pcie, | |
f4d2dd4c | 1853 | .set_lan_id = e1000_set_lan_id_multi_port_pcie, |
bc7f75fa | 1854 | /* .get_link_up_info: media type dependent */ |
4662e82b | 1855 | /* .led_on: mac type dependent */ |
bc7f75fa | 1856 | .led_off = e1000e_led_off_generic, |
ab8932f3 | 1857 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
caaddaf8 BA |
1858 | .write_vfta = e1000_write_vfta_generic, |
1859 | .clear_vfta = e1000_clear_vfta_82571, | |
bc7f75fa AK |
1860 | .reset_hw = e1000_reset_hw_82571, |
1861 | .init_hw = e1000_init_hw_82571, | |
1862 | .setup_link = e1000_setup_link_82571, | |
1863 | /* .setup_physical_interface: media type dependent */ | |
a4f58f54 | 1864 | .setup_led = e1000e_setup_led_generic, |
608f8a0d | 1865 | .read_mac_addr = e1000_read_mac_addr_82571, |
bc7f75fa AK |
1866 | }; |
1867 | ||
1868 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
94d8186a | 1869 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1870 | .check_polarity = e1000_check_polarity_igp, |
bc7f75fa | 1871 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1872 | .commit = NULL, |
bc7f75fa AK |
1873 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, |
1874 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1875 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
94d8186a BA |
1876 | .get_info = e1000e_get_phy_info_igp, |
1877 | .read_reg = e1000e_read_phy_reg_igp, | |
1878 | .release = e1000_put_hw_semaphore_82571, | |
1879 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1880 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1881 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1882 | .write_reg = e1000e_write_phy_reg_igp, |
75eb0fad | 1883 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1884 | }; |
1885 | ||
1886 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
94d8186a | 1887 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1888 | .check_polarity = e1000_check_polarity_m88, |
bc7f75fa | 1889 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1890 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1891 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1892 | .get_cfg_done = e1000e_get_cfg_done, | |
1893 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1894 | .get_info = e1000e_get_phy_info_m88, |
1895 | .read_reg = e1000e_read_phy_reg_m88, | |
1896 | .release = e1000_put_hw_semaphore_82571, | |
1897 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1898 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1899 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1900 | .write_reg = e1000e_write_phy_reg_m88, |
75eb0fad | 1901 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1902 | }; |
1903 | ||
4662e82b | 1904 | static struct e1000_phy_operations e82_phy_ops_bm = { |
94d8186a | 1905 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1906 | .check_polarity = e1000_check_polarity_m88, |
4662e82b | 1907 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1908 | .commit = e1000e_phy_sw_reset, |
4662e82b BA |
1909 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1910 | .get_cfg_done = e1000e_get_cfg_done, | |
1911 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1912 | .get_info = e1000e_get_phy_info_m88, |
1913 | .read_reg = e1000e_read_phy_reg_bm2, | |
1914 | .release = e1000_put_hw_semaphore_82571, | |
1915 | .reset = e1000e_phy_hw_reset_generic, | |
4662e82b BA |
1916 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1917 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1918 | .write_reg = e1000e_write_phy_reg_bm2, |
75eb0fad | 1919 | .cfg_on_link_up = NULL, |
4662e82b BA |
1920 | }; |
1921 | ||
bc7f75fa | 1922 | static struct e1000_nvm_operations e82571_nvm_ops = { |
94d8186a BA |
1923 | .acquire = e1000_acquire_nvm_82571, |
1924 | .read = e1000e_read_nvm_eerd, | |
1925 | .release = e1000_release_nvm_82571, | |
1926 | .update = e1000_update_nvm_checksum_82571, | |
bc7f75fa | 1927 | .valid_led_default = e1000_valid_led_default_82571, |
94d8186a BA |
1928 | .validate = e1000_validate_nvm_checksum_82571, |
1929 | .write = e1000_write_nvm_82571, | |
bc7f75fa AK |
1930 | }; |
1931 | ||
1932 | struct e1000_info e1000_82571_info = { | |
1933 | .mac = e1000_82571, | |
1934 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1935 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1936 | | FLAG_HAS_WOL |
1937 | | FLAG_APME_IN_CTRL3 | |
1938 | | FLAG_RX_CSUM_ENABLED | |
1939 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1940 | | FLAG_HAS_SMART_POWER_DOWN |
1941 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1942 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1943 | | FLAG_APME_CHECK_PORT_B, | |
3a3b7586 JB |
1944 | .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
1945 | | FLAG2_DMA_BURST, | |
bc7f75fa | 1946 | .pba = 38, |
2adc55c9 | 1947 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1948 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1949 | .mac_ops = &e82571_mac_ops, |
1950 | .phy_ops = &e82_phy_ops_igp, | |
1951 | .nvm_ops = &e82571_nvm_ops, | |
1952 | }; | |
1953 | ||
1954 | struct e1000_info e1000_82572_info = { | |
1955 | .mac = e1000_82572, | |
1956 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1957 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1958 | | FLAG_HAS_WOL |
1959 | | FLAG_APME_IN_CTRL3 | |
1960 | | FLAG_RX_CSUM_ENABLED | |
1961 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa | 1962 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
3a3b7586 JB |
1963 | .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
1964 | | FLAG2_DMA_BURST, | |
bc7f75fa | 1965 | .pba = 38, |
2adc55c9 | 1966 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1967 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1968 | .mac_ops = &e82571_mac_ops, |
1969 | .phy_ops = &e82_phy_ops_igp, | |
1970 | .nvm_ops = &e82571_nvm_ops, | |
1971 | }; | |
1972 | ||
1973 | struct e1000_info e1000_82573_info = { | |
1974 | .mac = e1000_82573, | |
1975 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
bc7f75fa AK |
1976 | | FLAG_HAS_WOL |
1977 | | FLAG_APME_IN_CTRL3 | |
1978 | | FLAG_RX_CSUM_ENABLED | |
bc7f75fa AK |
1979 | | FLAG_HAS_SMART_POWER_DOWN |
1980 | | FLAG_HAS_AMT | |
bc7f75fa | 1981 | | FLAG_HAS_SWSM_ON_LOAD, |
19833b5d | 1982 | .flags2 = FLAG2_DISABLE_ASPM_L1, |
bc7f75fa | 1983 | .pba = 20, |
2adc55c9 | 1984 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 1985 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1986 | .mac_ops = &e82571_mac_ops, |
1987 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 1988 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
1989 | }; |
1990 | ||
4662e82b BA |
1991 | struct e1000_info e1000_82574_info = { |
1992 | .mac = e1000_82574, | |
1993 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1994 | | FLAG_HAS_MSIX | |
1995 | | FLAG_HAS_JUMBO_FRAMES | |
1996 | | FLAG_HAS_WOL | |
1997 | | FLAG_APME_IN_CTRL3 | |
1998 | | FLAG_RX_CSUM_ENABLED | |
1999 | | FLAG_HAS_SMART_POWER_DOWN | |
2000 | | FLAG_HAS_AMT | |
2001 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
ff10e13c | 2002 | .flags2 = FLAG2_CHECK_PHY_HANG, |
edf15c17 | 2003 | .pba = 36, |
a825e00c | 2004 | .max_hw_frame_size = DEFAULT_JUMBO, |
4662e82b BA |
2005 | .get_variants = e1000_get_variants_82571, |
2006 | .mac_ops = &e82571_mac_ops, | |
2007 | .phy_ops = &e82_phy_ops_bm, | |
2008 | .nvm_ops = &e82571_nvm_ops, | |
2009 | }; | |
2010 | ||
8c81c9c3 AD |
2011 | struct e1000_info e1000_82583_info = { |
2012 | .mac = e1000_82583, | |
2013 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
2014 | | FLAG_HAS_WOL | |
2015 | | FLAG_APME_IN_CTRL3 | |
2016 | | FLAG_RX_CSUM_ENABLED | |
2017 | | FLAG_HAS_SMART_POWER_DOWN | |
2018 | | FLAG_HAS_AMT | |
2019 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
edf15c17 | 2020 | .pba = 36, |
a825e00c | 2021 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
8c81c9c3 AD |
2022 | .get_variants = e1000_get_variants_82571, |
2023 | .mac_ops = &e82571_mac_ops, | |
2024 | .phy_ops = &e82_phy_ops_bm, | |
2025 | .nvm_ops = &e82571_nvm_ops, | |
2026 | }; | |
2027 |