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can: EG20T PCH: add prefix to macro
[net-next-2.6.git] / drivers / net / can / pch_can.c
CommitLineData
b21d18b5
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/errno.h>
29#include <linux/netdevice.h>
30#include <linux/skbuff.h>
31#include <linux/can.h>
32#include <linux/can/dev.h>
33#include <linux/can/error.h>
34
086b5650
T		 35#define PCH_MAX_MSG_OBJ 32
36#define PCH_MSG_OBJ_RX 0 /* The receive message object flag. */
37#define PCH_MSG_OBJ_TX 1 /* The transmit message object flag. */
38
39#define PCH_ENABLE 1 /* The enable flag */
40#define PCH_DISABLE 0 /* The disable flag */
41#define PCH_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */
42#define PCH_CTRL_IE 0x0002 /* The IE bit of CAN control register */
43#define PCH_CTRL_IE_SIE_EIE 0x000e
44#define PCH_CTRL_CCE 0x0040
45#define PCH_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */
46#define PCH_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */
47#define PCH_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */
48#define PCH_CMASK_RX_TX_SET 0x00f3
49#define PCH_CMASK_RX_TX_GET 0x0073
50#define PCH_CMASK_ALL 0xff
51#define PCH_CMASK_RDWR 0x80
52#define PCH_CMASK_ARB 0x20
53#define PCH_CMASK_CTRL 0x10
54#define PCH_CMASK_MASK 0x40
55#define PCH_CMASK_NEWDAT 0x04
56#define PCH_CMASK_CLRINTPND 0x08
57#define PCH_IF_MCONT_NEWDAT 0x8000
58#define PCH_IF_MCONT_INTPND 0x2000
59#define PCH_IF_MCONT_UMASK 0x1000
60#define PCH_IF_MCONT_TXIE 0x0800
61#define PCH_IF_MCONT_RXIE 0x0400
62#define PCH_IF_MCONT_RMTEN 0x0200
63#define PCH_IF_MCONT_TXRQXT 0x0100
64#define PCH_IF_MCONT_EOB 0x0080
65#define PCH_IF_MCONT_DLC 0x000f
66#define PCH_IF_MCONT_MSGLOST 0x4000
67#define PCH_MASK2_MDIR_MXTD 0xc000
68#define PCH_ID2_DIR 0x2000
69#define PCH_ID2_XTD 0x4000
70#define PCH_ID_MSGVAL 0x8000
71#define PCH_IF_CREQ_BUSY 0x8000
72
73#define PCH_STATUS_INT 0x8000
74#define PCH_REC 0x00007f00
75#define PCH_TEC 0x000000ff
b21d18b5
MO		 76
77#define PCH_RX_OK 0x00000010
78#define PCH_TX_OK 0x00000008
79#define PCH_BUS_OFF 0x00000080
80#define PCH_EWARN 0x00000040
81#define PCH_EPASSIV 0x00000020
82#define PCH_LEC0 0x00000001
83#define PCH_LEC1 0x00000002
84#define PCH_LEC2 0x00000004
85#define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
86#define PCH_STUF_ERR PCH_LEC0
87#define PCH_FORM_ERR PCH_LEC1
88#define PCH_ACK_ERR (PCH_LEC0 | PCH_LEC1)
89#define PCH_BIT1_ERR PCH_LEC2
90#define PCH_BIT0_ERR (PCH_LEC0 | PCH_LEC2)
91#define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2)
92
93/* bit position of certain controller bits. */
086b5650
T		 94#define PCH_BIT_BRP 0
95#define PCH_BIT_SJW 6
96#define PCH_BIT_TSEG1 8
97#define PCH_BIT_TSEG2 12
98#define PCH_BIT_BRPE_BRPE 6
99#define PCH_MSK_BITT_BRP 0x3f
100#define PCH_MSK_BRPE_BRPE 0x3c0
101#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
102#define PCH_COUNTER_LIMIT 10
b21d18b5
MO		 103
104#define PCH_CAN_CLK 50000000 /* 50MHz */
105
106/* Define the number of message object.
107 * PCH CAN communications are done via Message RAM.
108 * The Message RAM consists of 32 message objects. */
109#define PCH_RX_OBJ_NUM 26 /* 1~ PCH_RX_OBJ_NUM is Rx*/
110#define PCH_TX_OBJ_NUM 6 /* PCH_RX_OBJ_NUM is RX ~ Tx*/
111#define PCH_OBJ_NUM (PCH_TX_OBJ_NUM + PCH_RX_OBJ_NUM)
112
113#define PCH_FIFO_THRESH 16
114
115enum pch_can_mode {
116 PCH_CAN_ENABLE,
117 PCH_CAN_DISABLE,
118 PCH_CAN_ALL,
119 PCH_CAN_NONE,
120 PCH_CAN_STOP,
121 PCH_CAN_RUN
122};
123
124struct pch_can_regs {
125 u32 cont;
126 u32 stat;
127 u32 errc;
128 u32 bitt;
129 u32 intr;
130 u32 opt;
131 u32 brpe;
132 u32 reserve1;
133 u32 if1_creq;
134 u32 if1_cmask;
135 u32 if1_mask1;
136 u32 if1_mask2;
137 u32 if1_id1;
138 u32 if1_id2;
139 u32 if1_mcont;
140 u32 if1_dataa1;
141 u32 if1_dataa2;
142 u32 if1_datab1;
143 u32 if1_datab2;
144 u32 reserve2;
145 u32 reserve3[12];
146 u32 if2_creq;
147 u32 if2_cmask;
148 u32 if2_mask1;
149 u32 if2_mask2;
150 u32 if2_id1;
151 u32 if2_id2;
152 u32 if2_mcont;
153 u32 if2_dataa1;
154 u32 if2_dataa2;
155 u32 if2_datab1;
156 u32 if2_datab2;
157 u32 reserve4;
158 u32 reserve5[20];
159 u32 treq1;
160 u32 treq2;
161 u32 reserve6[2];
162 u32 reserve7[56];
163 u32 reserve8[3];
164 u32 srst;
165};
166
167struct pch_can_priv {
168 struct can_priv can;
169 unsigned int can_num;
170 struct pci_dev *dev;
086b5650
T		 171 unsigned int tx_enable[PCH_MAX_MSG_OBJ];
172 unsigned int rx_enable[PCH_MAX_MSG_OBJ];
173 unsigned int rx_link[PCH_MAX_MSG_OBJ];
b21d18b5
MO		 174 unsigned int int_enables;
175 unsigned int int_stat;
176 struct net_device *ndev;
177 spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/
086b5650 178 unsigned int msg_obj[PCH_MAX_MSG_OBJ];
b21d18b5
MO		 179 struct pch_can_regs __iomem *regs;
180 struct napi_struct napi;
181 unsigned int tx_obj; /* Point next Tx Obj index */
182 unsigned int use_msi;
183};
184
185static struct can_bittiming_const pch_can_bittiming_const = {
186 .name = KBUILD_MODNAME,
187 .tseg1_min = 1,
188 .tseg1_max = 16,
189 .tseg2_min = 1,
190 .tseg2_max = 8,
191 .sjw_max = 4,
192 .brp_min = 1,
193 .brp_max = 1024, /* 6bit + extended 4bit */
194 .brp_inc = 1,
195};
196
197static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
198 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
199 {0,}
200};
201MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
202
526de53c 203static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
b21d18b5
MO		 204{
205 iowrite32(ioread32(addr) | mask, addr);
206}
207
526de53c 208static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
b21d18b5
MO		 209{
210 iowrite32(ioread32(addr) & ~mask, addr);
211}
212
213static void pch_can_set_run_mode(struct pch_can_priv *priv,
214 enum pch_can_mode mode)
215{
216 switch (mode) {
217 case PCH_CAN_RUN:
086b5650 218 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 219 break;
220
221 case PCH_CAN_STOP:
086b5650 222 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 223 break;
224
225 default:
226 dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__);
227 break;
228 }
229}
230
231static void pch_can_set_optmode(struct pch_can_priv *priv)
232{
233 u32 reg_val = ioread32(&priv->regs->opt);
234
235 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
086b5650 236 reg_val |= PCH_OPT_SILENT;
b21d18b5
MO		 237
238 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
086b5650 239 reg_val |= PCH_OPT_LBACK;
b21d18b5 240
086b5650 241 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
b21d18b5
MO		 242 iowrite32(reg_val, &priv->regs->opt);
243}
244
245static void pch_can_set_int_custom(struct pch_can_priv *priv)
246{
247 /* Clearing the IE, SIE and EIE bits of Can control register. */
086b5650 248 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 249
250 /* Appropriately setting them. */
251 pch_can_bit_set(&priv->regs->cont,
086b5650 252 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
b21d18b5
MO		 253}
254
255/* This function retrieves interrupt enabled for the CAN device. */
256static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
257{
258 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
086b5650 259 *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1);
b21d18b5
MO		 260}
261
262static void pch_can_set_int_enables(struct pch_can_priv *priv,
263 enum pch_can_mode interrupt_no)
264{
265 switch (interrupt_no) {
266 case PCH_CAN_ENABLE:
086b5650 267 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE);
b21d18b5
MO		 268 break;
269
270 case PCH_CAN_DISABLE:
086b5650 271 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
b21d18b5
MO		 272 break;
273
274 case PCH_CAN_ALL:
086b5650 275 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 276 break;
277
278 case PCH_CAN_NONE:
086b5650 279 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 280 break;
281
282 default:
283 dev_err(&priv->ndev->dev, "Invalid interrupt number.\n");
284 break;
285 }
286}
287
288static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
289{
086b5650 290 u32 counter = PCH_COUNTER_LIMIT;
b21d18b5
MO		 291 u32 ifx_creq;
292
293 iowrite32(num, creq_addr);
294 while (counter) {
086b5650 295 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
b21d18b5
MO		 296 if (!ifx_creq)
297 break;
298 counter--;
299 udelay(1);
300 }
301 if (!counter)
302 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
303}
304
305static void pch_can_set_rx_enable(struct pch_can_priv *priv, u32 buff_num,
306 u32 set)
307{
308 unsigned long flags;
309
310 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
311 /* Reading the receive buffer data from RAM to Interface1 registers */
086b5650 312 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
b21d18b5
MO		 313 pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
314
315 /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
086b5650 316 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
b21d18b5
MO		 317 &priv->regs->if1_cmask);
318
086b5650 319 if (set == PCH_ENABLE) {
b21d18b5 320 /* Setting the MsgVal and RxIE bits */
086b5650
T		 321 pch_can_bit_set(&priv->regs->if1_mcont, PCH_IF_MCONT_RXIE);
322 pch_can_bit_set(&priv->regs->if1_id2, PCH_ID_MSGVAL);
b21d18b5 323
086b5650 324 } else if (set == PCH_DISABLE) {
b21d18b5 325 /* Resetting the MsgVal and RxIE bits */
086b5650
T		 326 pch_can_bit_clear(&priv->regs->if1_mcont, PCH_IF_MCONT_RXIE);
327 pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID_MSGVAL);
b21d18b5
MO		 328 }
329
330 pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
331 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
332}
333
334static void pch_can_rx_enable_all(struct pch_can_priv *priv)
335{
336 int i;
337
338 /* Traversing to obtain the object configured as receivers. */
339 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650
T		 340 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX)
341 pch_can_set_rx_enable(priv, i + 1, PCH_ENABLE);
b21d18b5
MO		 342 }
343}
344
345static void pch_can_rx_disable_all(struct pch_can_priv *priv)
346{
347 int i;
348
349 /* Traversing to obtain the object configured as receivers. */
350 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650
T		 351 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX)
352 pch_can_set_rx_enable(priv, i + 1, PCH_DISABLE);
b21d18b5
MO		 353 }
354}
355
356static void pch_can_set_tx_enable(struct pch_can_priv *priv, u32 buff_num,
357 u32 set)
358{
359 unsigned long flags;
360
361 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
362 /* Reading the Msg buffer from Message RAM to Interface2 registers. */
086b5650 363 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
b21d18b5
MO		 364 pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
365
366 /* Setting the IF2CMASK register for accessing the
367 MsgVal and TxIE bits */
086b5650 368 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
b21d18b5
MO		 369 &priv->regs->if2_cmask);
370
086b5650 371 if (set == PCH_ENABLE) {
b21d18b5 372 /* Setting the MsgVal and TxIE bits */
086b5650
T		 373 pch_can_bit_set(&priv->regs->if2_mcont, PCH_IF_MCONT_TXIE);
374 pch_can_bit_set(&priv->regs->if2_id2, PCH_ID_MSGVAL);
375 } else if (set == PCH_DISABLE) {
b21d18b5 376 /* Resetting the MsgVal and TxIE bits. */
086b5650
T		 377 pch_can_bit_clear(&priv->regs->if2_mcont, PCH_IF_MCONT_TXIE);
378 pch_can_bit_clear(&priv->regs->if2_id2, PCH_ID_MSGVAL);
b21d18b5
MO		 379 }
380
381 pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
382 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
383}
384
385static void pch_can_tx_enable_all(struct pch_can_priv *priv)
386{
387 int i;
388
389 /* Traversing to obtain the object configured as transmit object. */
390 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650
T		 391 if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
392 pch_can_set_tx_enable(priv, i + 1, PCH_ENABLE);
b21d18b5
MO		 393 }
394}
395
396static void pch_can_tx_disable_all(struct pch_can_priv *priv)
397{
398 int i;
399
400 /* Traversing to obtain the object configured as transmit object. */
401 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650
T		 402 if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
403 pch_can_set_tx_enable(priv, i + 1, PCH_DISABLE);
b21d18b5
MO		 404 }
405}
406
407static void pch_can_get_rx_enable(struct pch_can_priv *priv, u32 buff_num,
408 u32 *enable)
409{
410 unsigned long flags;
411
412 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
086b5650 413 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
b21d18b5
MO		 414 pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
415
086b5650 416 if (((ioread32(&priv->regs->if1_id2)) & PCH_ID_MSGVAL) &&
b21d18b5 417 ((ioread32(&priv->regs->if1_mcont)) &
086b5650
T		 418 PCH_IF_MCONT_RXIE))
419 *enable = PCH_ENABLE;
b21d18b5 420 else
086b5650 421 *enable = PCH_DISABLE;
b21d18b5
MO		 422 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
423}
424
425static void pch_can_get_tx_enable(struct pch_can_priv *priv, u32 buff_num,
426 u32 *enable)
427{
428 unsigned long flags;
429
430 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
086b5650 431 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
b21d18b5
MO		 432 pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
433
086b5650 434 if (((ioread32(&priv->regs->if2_id2)) & PCH_ID_MSGVAL) &&
b21d18b5 435 ((ioread32(&priv->regs->if2_mcont)) &
086b5650
T		 436 PCH_IF_MCONT_TXIE)) {
437 *enable = PCH_ENABLE;
b21d18b5 438 } else {
086b5650 439 *enable = PCH_DISABLE;
b21d18b5
MO		 440 }
441 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
442}
443
444static int pch_can_int_pending(struct pch_can_priv *priv)
445{
446 return ioread32(&priv->regs->intr) & 0xffff;
447}
448
449static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
450 u32 buffer_num, u32 set)
451{
452 unsigned long flags;
453
454 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
086b5650 455 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
b21d18b5 456 pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
086b5650
T		 457 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, &priv->regs->if1_cmask);
458 if (set == PCH_ENABLE)
459 pch_can_bit_clear(&priv->regs->if1_mcont, PCH_IF_MCONT_EOB);
b21d18b5 460 else
086b5650 461 pch_can_bit_set(&priv->regs->if1_mcont, PCH_IF_MCONT_EOB);
b21d18b5
MO		 462
463 pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
464 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
465}
466
467static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
468 u32 buffer_num, u32 *link)
469{
470 unsigned long flags;
471
472 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
086b5650 473 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
b21d18b5
MO		 474 pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
475
086b5650
T		 476 if (ioread32(&priv->regs->if1_mcont) & PCH_IF_MCONT_EOB)
477 *link = PCH_DISABLE;
b21d18b5 478 else
086b5650 479 *link = PCH_ENABLE;
b21d18b5
MO		 480 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
481}
482
483static void pch_can_clear_buffers(struct pch_can_priv *priv)
484{
485 int i;
486
487 for (i = 0; i < PCH_RX_OBJ_NUM; i++) {
086b5650 488 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->if1_cmask);
b21d18b5
MO		 489 iowrite32(0xffff, &priv->regs->if1_mask1);
490 iowrite32(0xffff, &priv->regs->if1_mask2);
491 iowrite32(0x0, &priv->regs->if1_id1);
492 iowrite32(0x0, &priv->regs->if1_id2);
493 iowrite32(0x0, &priv->regs->if1_mcont);
494 iowrite32(0x0, &priv->regs->if1_dataa1);
495 iowrite32(0x0, &priv->regs->if1_dataa2);
496 iowrite32(0x0, &priv->regs->if1_datab1);
497 iowrite32(0x0, &priv->regs->if1_datab2);
086b5650
T		 498 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
499 PCH_CMASK_ARB | PCH_CMASK_CTRL,
b21d18b5
MO		 500 &priv->regs->if1_cmask);
501 pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
502 }
503
504 for (i = i; i < PCH_OBJ_NUM; i++) {
086b5650 505 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
b21d18b5
MO		 506 iowrite32(0xffff, &priv->regs->if2_mask1);
507 iowrite32(0xffff, &priv->regs->if2_mask2);
508 iowrite32(0x0, &priv->regs->if2_id1);
509 iowrite32(0x0, &priv->regs->if2_id2);
510 iowrite32(0x0, &priv->regs->if2_mcont);
511 iowrite32(0x0, &priv->regs->if2_dataa1);
512 iowrite32(0x0, &priv->regs->if2_dataa2);
513 iowrite32(0x0, &priv->regs->if2_datab1);
514 iowrite32(0x0, &priv->regs->if2_datab2);
086b5650
T		 515 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
516 PCH_CMASK_ARB | PCH_CMASK_CTRL,
b21d18b5
MO		 517 &priv->regs->if2_cmask);
518 pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
519 }
520}
521
522static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
523{
524 int i;
525 unsigned long flags;
526
527 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
528
529 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650
T		 530 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
531 iowrite32(PCH_CMASK_RX_TX_GET,
b21d18b5
MO		 532 &priv->regs->if1_cmask);
533 pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
534
535 iowrite32(0x0, &priv->regs->if1_id1);
536 iowrite32(0x0, &priv->regs->if1_id2);
537
538 pch_can_bit_set(&priv->regs->if1_mcont,
086b5650 539 PCH_IF_MCONT_UMASK);
b21d18b5
MO		 540
541 /* Set FIFO mode set to 0 except last Rx Obj*/
542 pch_can_bit_clear(&priv->regs->if1_mcont,
086b5650 543 PCH_IF_MCONT_EOB);
b21d18b5
MO		 544 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
545 if (i == (PCH_RX_OBJ_NUM - 1))
546 pch_can_bit_set(&priv->regs->if1_mcont,
086b5650 547 PCH_IF_MCONT_EOB);
b21d18b5
MO		 548
549 iowrite32(0, &priv->regs->if1_mask1);
550 pch_can_bit_clear(&priv->regs->if1_mask2,
086b5650 551 0x1fff | PCH_MASK2_MDIR_MXTD);
b21d18b5
MO		 552
553 /* Setting CMASK for writing */
086b5650
T		 554 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
555 PCH_CMASK_ARB | PCH_CMASK_CTRL,
b21d18b5
MO		 556 &priv->regs->if1_cmask);
557
558 pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
086b5650
T		 559 } else if (priv->msg_obj[i] == PCH_MSG_OBJ_TX) {
560 iowrite32(PCH_CMASK_RX_TX_GET,
b21d18b5
MO		 561 &priv->regs->if2_cmask);
562 pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
563
564 /* Resetting DIR bit for reception */
565 iowrite32(0x0, &priv->regs->if2_id1);
566 iowrite32(0x0, &priv->regs->if2_id2);
086b5650 567 pch_can_bit_set(&priv->regs->if2_id2, PCH_ID2_DIR);
b21d18b5
MO		 568
569 /* Setting EOB bit for transmitter */
086b5650 570 iowrite32(PCH_IF_MCONT_EOB, &priv->regs->if2_mcont);
b21d18b5
MO		 571
572 pch_can_bit_set(&priv->regs->if2_mcont,
086b5650 573 PCH_IF_MCONT_UMASK);
b21d18b5
MO		 574
575 iowrite32(0, &priv->regs->if2_mask1);
576 pch_can_bit_clear(&priv->regs->if2_mask2, 0x1fff);
577
578 /* Setting CMASK for writing */
086b5650
T		 579 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
580 PCH_CMASK_ARB | PCH_CMASK_CTRL,
b21d18b5
MO		 581 &priv->regs->if2_cmask);
582
583 pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
584 }
585 }
586 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
587}
588
589static void pch_can_init(struct pch_can_priv *priv)
590{
591 /* Stopping the Can device. */
592 pch_can_set_run_mode(priv, PCH_CAN_STOP);
593
594 /* Clearing all the message object buffers. */
595 pch_can_clear_buffers(priv);
596
597 /* Configuring the respective message object as either rx/tx object. */
598 pch_can_config_rx_tx_buffers(priv);
599
600 /* Enabling the interrupts. */
601 pch_can_set_int_enables(priv, PCH_CAN_ALL);
602}
603
604static void pch_can_release(struct pch_can_priv *priv)
605{
606 /* Stooping the CAN device. */
607 pch_can_set_run_mode(priv, PCH_CAN_STOP);
608
609 /* Disabling the interrupts. */
610 pch_can_set_int_enables(priv, PCH_CAN_NONE);
611
612 /* Disabling all the receive object. */
613 pch_can_rx_disable_all(priv);
614
615 /* Disabling all the transmit object. */
616 pch_can_tx_disable_all(priv);
617}
618
619/* This function clears interrupt(s) from the CAN device. */
620static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
621{
086b5650 622 if (mask == PCH_STATUS_INT) {
b21d18b5
MO		 623 ioread32(&priv->regs->stat);
624 return;
625 }
626
627 /* Clear interrupt for transmit object */
086b5650 628 if (priv->msg_obj[mask - 1] == PCH_MSG_OBJ_TX) {
b21d18b5
MO		 629 /* Setting CMASK for clearing interrupts for
630 frame transmission. */
086b5650 631 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
b21d18b5
MO		 632 &priv->regs->if2_cmask);
633
634 /* Resetting the ID registers. */
635 pch_can_bit_set(&priv->regs->if2_id2,
086b5650 636 PCH_ID2_DIR | (0x7ff << 2));
b21d18b5
MO		 637 iowrite32(0x0, &priv->regs->if2_id1);
638
639 /* Claring NewDat, TxRqst & IntPnd */
640 pch_can_bit_clear(&priv->regs->if2_mcont,
086b5650
T		 641 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
642 PCH_IF_MCONT_TXRQXT);
b21d18b5 643 pch_can_check_if_busy(&priv->regs->if2_creq, mask);
086b5650 644 } else if (priv->msg_obj[mask - 1] == PCH_MSG_OBJ_RX) {
b21d18b5 645 /* Setting CMASK for clearing the reception interrupts. */
086b5650 646 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
b21d18b5
MO		 647 &priv->regs->if1_cmask);
648
649 /* Clearing the Dir bit. */
086b5650 650 pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID2_DIR);
b21d18b5
MO		 651
652 /* Clearing NewDat & IntPnd */
653 pch_can_bit_clear(&priv->regs->if1_mcont,
086b5650 654 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
b21d18b5
MO		 655
656 pch_can_check_if_busy(&priv->regs->if1_creq, mask);
657 }
658}
659
660static int pch_can_get_buffer_status(struct pch_can_priv *priv)
661{
662 return (ioread32(&priv->regs->treq1) & 0xffff) |
663 ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
664}
665
666static void pch_can_reset(struct pch_can_priv *priv)
667{
668 /* write to sw reset register */
669 iowrite32(1, &priv->regs->srst);
670 iowrite32(0, &priv->regs->srst);
671}
672
673static void pch_can_error(struct net_device *ndev, u32 status)
674{
675 struct sk_buff *skb;
676 struct pch_can_priv *priv = netdev_priv(ndev);
677 struct can_frame *cf;
678 u32 errc;
679 struct net_device_stats *stats = &(priv->ndev->stats);
680 enum can_state state = priv->can.state;
681
682 skb = alloc_can_err_skb(ndev, &cf);
683 if (!skb)
684 return;
685
686 if (status & PCH_BUS_OFF) {
687 pch_can_tx_disable_all(priv);
688 pch_can_rx_disable_all(priv);
689 state = CAN_STATE_BUS_OFF;
690 cf->can_id |= CAN_ERR_BUSOFF;
691 can_bus_off(ndev);
692 pch_can_set_run_mode(priv, PCH_CAN_RUN);
693 dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__);
694 }
695
696 /* Warning interrupt. */
697 if (status & PCH_EWARN) {
698 state = CAN_STATE_ERROR_WARNING;
699 priv->can.can_stats.error_warning++;
700 cf->can_id |= CAN_ERR_CRTL;
701 errc = ioread32(&priv->regs->errc);
086b5650 702 if (((errc & PCH_REC) >> 8) > 96)
b21d18b5 703 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
086b5650 704 if ((errc & PCH_TEC) > 96)
b21d18b5
MO		 705 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
706 dev_warn(&ndev->dev,
707 "%s -> Error Counter is more than 96.\n", __func__);
708 }
709 /* Error passive interrupt. */
710 if (status & PCH_EPASSIV) {
711 priv->can.can_stats.error_passive++;
712 state = CAN_STATE_ERROR_PASSIVE;
713 cf->can_id |= CAN_ERR_CRTL;
714 errc = ioread32(&priv->regs->errc);
086b5650 715 if (((errc & PCH_REC) >> 8) > 127)
b21d18b5 716 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
086b5650 717 if ((errc & PCH_TEC) > 127)
b21d18b5
MO		 718 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
719 dev_err(&ndev->dev,
720 "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
721 }
722
723 if (status & PCH_LEC_ALL) {
724 priv->can.can_stats.bus_error++;
725 stats->rx_errors++;
726 switch (status & PCH_LEC_ALL) {
727 case PCH_STUF_ERR:
728 cf->data[2] |= CAN_ERR_PROT_STUFF;
729 break;
730 case PCH_FORM_ERR:
731 cf->data[2] |= CAN_ERR_PROT_FORM;
732 break;
733 case PCH_ACK_ERR:
734 cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
735 CAN_ERR_PROT_LOC_ACK_DEL;
736 break;
737 case PCH_BIT1_ERR:
738 case PCH_BIT0_ERR:
739 cf->data[2] |= CAN_ERR_PROT_BIT;
740 break;
741 case PCH_CRC_ERR:
742 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
743 CAN_ERR_PROT_LOC_CRC_DEL;
744 break;
745 default:
746 iowrite32(status | PCH_LEC_ALL, &priv->regs->stat);
747 break;
748 }
749
750 }
751
752 priv->can.state = state;
753 netif_rx(skb);
754
755 stats->rx_packets++;
756 stats->rx_bytes += cf->can_dlc;
757}
758
759static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
760{
761 struct net_device *ndev = (struct net_device *)dev_id;
762 struct pch_can_priv *priv = netdev_priv(ndev);
763
764 pch_can_set_int_enables(priv, PCH_CAN_NONE);
765
766 napi_schedule(&priv->napi);
767
768 return IRQ_HANDLED;
769}
770
771static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
772{
773 u32 reg;
774 canid_t id;
775 u32 ide;
776 u32 rtr;
777 int i, j, k;
778 int rcv_pkts = 0;
779 struct sk_buff *skb;
780 struct can_frame *cf;
781 struct pch_can_priv *priv = netdev_priv(ndev);
782 struct net_device_stats *stats = &(priv->ndev->stats);
783
784 /* Reading the messsage object from the Message RAM */
086b5650 785 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
b21d18b5
MO		 786 pch_can_check_if_busy(&priv->regs->if1_creq, int_stat);
787
788 /* Reading the MCONT register. */
789 reg = ioread32(&priv->regs->if1_mcont);
790 reg &= 0xffff;
791
086b5650 792 for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) {
b21d18b5 793 /* If MsgLost bit set. */
086b5650 794 if (reg & PCH_IF_MCONT_MSGLOST) {
b21d18b5
MO		 795 dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
796 pch_can_bit_clear(&priv->regs->if1_mcont,
086b5650
T		 797 PCH_IF_MCONT_MSGLOST);
798 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
b21d18b5
MO		 799 &priv->regs->if1_cmask);
800 pch_can_check_if_busy(&priv->regs->if1_creq, k);
801
802 skb = alloc_can_err_skb(ndev, &cf);
803 if (!skb)
804 return -ENOMEM;
805
806 priv->can.can_stats.error_passive++;
807 priv->can.state = CAN_STATE_ERROR_PASSIVE;
808 cf->can_id |= CAN_ERR_CRTL;
809 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
810 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
811 stats->rx_packets++;
812 stats->rx_bytes += cf->can_dlc;
813
814 netif_receive_skb(skb);
815 rcv_pkts++;
816 goto RX_NEXT;
817 }
086b5650 818 if (!(reg & PCH_IF_MCONT_NEWDAT))
b21d18b5
MO		 819 goto RX_NEXT;
820
821 skb = alloc_can_skb(priv->ndev, &cf);
822 if (!skb)
823 return -ENOMEM;
824
825 /* Get Received data */
086b5650 826 ide = ((ioread32(&priv->regs->if1_id2)) & PCH_ID2_XTD) >> 14;
b21d18b5
MO		 827 if (ide) {
828 id = (ioread32(&priv->regs->if1_id1) & 0xffff);
829 id |= (((ioread32(&priv->regs->if1_id2)) &
830 0x1fff) << 16);
831 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
832 } else {
833 id = (((ioread32(&priv->regs->if1_id2)) &
834 (CAN_SFF_MASK << 2)) >> 2);
835 cf->can_id = (id & CAN_SFF_MASK);
836 }
837
086b5650 838 rtr = (ioread32(&priv->regs->if1_id2) & PCH_ID2_DIR);
b21d18b5
MO		 839 if (rtr) {
840 cf->can_dlc = 0;
841 cf->can_id |= CAN_RTR_FLAG;
842 } else {
843 cf->can_dlc = ((ioread32(&priv->regs->if1_mcont)) &
844 0x0f);
845 }
846
847 for (i = 0, j = 0; i < cf->can_dlc; j++) {
848 reg = ioread32(&priv->regs->if1_dataa1 + j*4);
849 cf->data[i++] = cpu_to_le32(reg & 0xff);
850 if (i == cf->can_dlc)
851 break;
852 cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff);
853 }
854
855 netif_receive_skb(skb);
856 rcv_pkts++;
857 stats->rx_packets++;
858 stats->rx_bytes += cf->can_dlc;
859
860 if (k < PCH_FIFO_THRESH) {
086b5650
T		 861 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
862 PCH_CMASK_ARB, &priv->regs->if1_cmask);
b21d18b5
MO		 863
864 /* Clearing the Dir bit. */
086b5650 865 pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID2_DIR);
b21d18b5
MO		 866
867 /* Clearing NewDat & IntPnd */
868 pch_can_bit_clear(&priv->regs->if1_mcont,
086b5650 869 PCH_IF_MCONT_INTPND);
b21d18b5
MO		 870 pch_can_check_if_busy(&priv->regs->if1_creq, k);
871 } else if (k > PCH_FIFO_THRESH) {
872 pch_can_int_clr(priv, k);
873 } else if (k == PCH_FIFO_THRESH) {
874 int cnt;
875 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
876 pch_can_int_clr(priv, cnt+1);
877 }
878RX_NEXT:
879 /* Reading the messsage object from the Message RAM */
086b5650 880 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
b21d18b5
MO		 881 pch_can_check_if_busy(&priv->regs->if1_creq, k + 1);
882 reg = ioread32(&priv->regs->if1_mcont);
883 }
884
885 return rcv_pkts;
886}
887static int pch_can_rx_poll(struct napi_struct *napi, int quota)
888{
889 struct net_device *ndev = napi->dev;
890 struct pch_can_priv *priv = netdev_priv(ndev);
891 struct net_device_stats *stats = &(priv->ndev->stats);
892 u32 dlc;
893 u32 int_stat;
894 int rcv_pkts = 0;
895 u32 reg_stat;
896 unsigned long flags;
897
898 int_stat = pch_can_int_pending(priv);
899 if (!int_stat)
900 return 0;
901
902INT_STAT:
086b5650 903 if (int_stat == PCH_STATUS_INT) {
b21d18b5
MO		 904 reg_stat = ioread32(&priv->regs->stat);
905 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
906 if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)
907 pch_can_error(ndev, reg_stat);
908 }
909
910 if (reg_stat & PCH_TX_OK) {
911 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
086b5650 912 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
b21d18b5
MO		 913 pch_can_check_if_busy(&priv->regs->if2_creq,
914 ioread32(&priv->regs->intr));
915 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
916 pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
917 }
918
919 if (reg_stat & PCH_RX_OK)
920 pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
921
922 int_stat = pch_can_int_pending(priv);
086b5650 923 if (int_stat == PCH_STATUS_INT)
b21d18b5
MO		 924 goto INT_STAT;
925 }
926
927MSG_OBJ:
928 if ((int_stat >= 1) && (int_stat <= PCH_RX_OBJ_NUM)) {
929 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
930 rcv_pkts = pch_can_rx_normal(ndev, int_stat);
931 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
932 if (rcv_pkts < 0)
933 return 0;
934 } else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) {
086b5650 935 if (priv->msg_obj[int_stat - 1] == PCH_MSG_OBJ_TX) {
b21d18b5
MO		 936 /* Handle transmission interrupt */
937 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1);
938 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
086b5650 939 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
b21d18b5
MO		 940 &priv->regs->if2_cmask);
941 dlc = ioread32(&priv->regs->if2_mcont) &
086b5650 942 PCH_IF_MCONT_DLC;
b21d18b5
MO		 943 pch_can_check_if_busy(&priv->regs->if2_creq, int_stat);
944 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
945 if (dlc > 8)
946 dlc = 8;
947 stats->tx_bytes += dlc;
948 stats->tx_packets++;
949 }
950 }
951
952 int_stat = pch_can_int_pending(priv);
086b5650 953 if (int_stat == PCH_STATUS_INT)
b21d18b5
MO		 954 goto INT_STAT;
955 else if (int_stat >= 1 && int_stat <= 32)
956 goto MSG_OBJ;
957
958 napi_complete(napi);
959 pch_can_set_int_enables(priv, PCH_CAN_ALL);
960
961 return rcv_pkts;
962}
963
964static int pch_set_bittiming(struct net_device *ndev)
965{
966 struct pch_can_priv *priv = netdev_priv(ndev);
967 const struct can_bittiming *bt = &priv->can.bittiming;
968 u32 canbit;
969 u32 bepe;
970 u32 brp;
971
972 /* Setting the CCE bit for accessing the Can Timing register. */
086b5650 973 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5
MO		 974
975 brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
086b5650
T		 976 canbit = brp & PCH_MSK_BITT_BRP;
977 canbit |= (bt->sjw - 1) << PCH_BIT_SJW;
978 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1;
979 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2;
980 bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE;
b21d18b5
MO		 981 iowrite32(canbit, &priv->regs->bitt);
982 iowrite32(bepe, &priv->regs->brpe);
086b5650 983 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5
MO		 984
985 return 0;
986}
987
988static void pch_can_start(struct net_device *ndev)
989{
990 struct pch_can_priv *priv = netdev_priv(ndev);
991
992 if (priv->can.state != CAN_STATE_STOPPED)
993 pch_can_reset(priv);
994
995 pch_set_bittiming(ndev);
996 pch_can_set_optmode(priv);
997
998 pch_can_tx_enable_all(priv);
999 pch_can_rx_enable_all(priv);
1000
1001 /* Setting the CAN to run mode. */
1002 pch_can_set_run_mode(priv, PCH_CAN_RUN);
1003
1004 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1005
1006 return;
1007}
1008
1009static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
1010{
1011 int ret = 0;
1012
1013 switch (mode) {
1014 case CAN_MODE_START:
1015 pch_can_start(ndev);
1016 netif_wake_queue(ndev);
1017 break;
1018 default:
1019 ret = -EOPNOTSUPP;
1020 break;
1021 }
1022
1023 return ret;
1024}
1025
1026static int pch_can_open(struct net_device *ndev)
1027{
1028 struct pch_can_priv *priv = netdev_priv(ndev);
1029 int retval;
1030
1031 retval = pci_enable_msi(priv->dev);
1032 if (retval) {
1033 dev_info(&ndev->dev, "PCH CAN opened without MSI\n");
1034 priv->use_msi = 0;
1035 } else {
1036 dev_info(&ndev->dev, "PCH CAN opened with MSI\n");
1037 priv->use_msi = 1;
1038 }
1039
1040 /* Regsitering the interrupt. */
1041 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
1042 ndev->name, ndev);
1043 if (retval) {
1044 dev_err(&ndev->dev, "request_irq failed.\n");
1045 goto req_irq_err;
1046 }
1047
1048 /* Open common can device */
1049 retval = open_candev(ndev);
1050 if (retval) {
1051 dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval);
1052 goto err_open_candev;
1053 }
1054
1055 pch_can_init(priv);
1056 pch_can_start(ndev);
1057 napi_enable(&priv->napi);
1058 netif_start_queue(ndev);
1059
1060 return 0;
1061
1062err_open_candev:
1063 free_irq(priv->dev->irq, ndev);
1064req_irq_err:
1065 if (priv->use_msi)
1066 pci_disable_msi(priv->dev);
1067
1068 pch_can_release(priv);
1069
1070 return retval;
1071}
1072
1073static int pch_close(struct net_device *ndev)
1074{
1075 struct pch_can_priv *priv = netdev_priv(ndev);
1076
1077 netif_stop_queue(ndev);
1078 napi_disable(&priv->napi);
1079 pch_can_release(priv);
1080 free_irq(priv->dev->irq, ndev);
1081 if (priv->use_msi)
1082 pci_disable_msi(priv->dev);
1083 close_candev(ndev);
1084 priv->can.state = CAN_STATE_STOPPED;
1085 return 0;
1086}
1087
1088static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id)
1089{
1090 u32 buffer_status = 0;
1091 struct pch_can_priv *priv = netdev_priv(ndev);
1092
1093 /* Getting the message object status. */
1094 buffer_status = (u32) pch_can_get_buffer_status(priv);
1095
1096 return buffer_status & obj_id;
1097}
1098
1099
1100static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
1101{
1102 int i, j;
1103 unsigned long flags;
1104 struct pch_can_priv *priv = netdev_priv(ndev);
1105 struct can_frame *cf = (struct can_frame *)skb->data;
1106 int tx_buffer_avail = 0;
1107
1108 if (can_dropped_invalid_skb(ndev, skb))
1109 return NETDEV_TX_OK;
1110
1111 if (priv->tx_obj == (PCH_OBJ_NUM + 1)) { /* Point tail Obj */
1112 while (pch_get_msg_obj_sts(ndev, (((1 << PCH_TX_OBJ_NUM)-1) <<
1113 PCH_RX_OBJ_NUM)))
1114 udelay(500);
1115
1116 priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj ID */
1117 tx_buffer_avail = priv->tx_obj; /* Point Tail of Tx Obj */
1118 } else {
1119 tx_buffer_avail = priv->tx_obj;
1120 }
1121 priv->tx_obj++;
1122
1123 /* Attaining the lock. */
1124 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
1125
1126 /* Reading the Msg Obj from the Msg RAM to the Interface register. */
086b5650 1127 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
b21d18b5
MO		 1128 pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
1129
1130 /* Setting the CMASK register. */
086b5650 1131 pch_can_bit_set(&priv->regs->if2_cmask, PCH_CMASK_ALL);
b21d18b5
MO		 1132
1133 /* If ID extended is set. */
1134 pch_can_bit_clear(&priv->regs->if2_id1, 0xffff);
086b5650 1135 pch_can_bit_clear(&priv->regs->if2_id2, 0x1fff | PCH_ID2_XTD);
b21d18b5
MO		 1136 if (cf->can_id & CAN_EFF_FLAG) {
1137 pch_can_bit_set(&priv->regs->if2_id1, cf->can_id & 0xffff);
1138 pch_can_bit_set(&priv->regs->if2_id2,
086b5650 1139 ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD);
b21d18b5
MO		 1140 } else {
1141 pch_can_bit_set(&priv->regs->if2_id1, 0);
1142 pch_can_bit_set(&priv->regs->if2_id2,
1143 (cf->can_id & CAN_SFF_MASK) << 2);
1144 }
1145
1146 /* If remote frame has to be transmitted.. */
1147 if (cf->can_id & CAN_RTR_FLAG)
086b5650 1148 pch_can_bit_clear(&priv->regs->if2_id2, PCH_ID2_DIR);
b21d18b5
MO		 1149
1150 for (i = 0, j = 0; i < cf->can_dlc; j++) {
1151 iowrite32(le32_to_cpu(cf->data[i++]),
1152 (&priv->regs->if2_dataa1) + j*4);
1153 if (i == cf->can_dlc)
1154 break;
1155 iowrite32(le32_to_cpu(cf->data[i++] << 8),
1156 (&priv->regs->if2_dataa1) + j*4);
1157 }
1158
1159 can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_NUM - 1);
1160
1161 /* Updating the size of the data. */
1162 pch_can_bit_clear(&priv->regs->if2_mcont, 0x0f);
1163 pch_can_bit_set(&priv->regs->if2_mcont, cf->can_dlc);
1164
1165 /* Clearing IntPend, NewDat & TxRqst */
1166 pch_can_bit_clear(&priv->regs->if2_mcont,
086b5650
T		 1167 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
1168 PCH_IF_MCONT_TXRQXT);
b21d18b5
MO		 1169
1170 /* Setting NewDat, TxRqst bits */
1171 pch_can_bit_set(&priv->regs->if2_mcont,
086b5650 1172 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT);
b21d18b5
MO		 1173
1174 pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
1175
1176 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
1177
1178 return NETDEV_TX_OK;
1179}
1180
1181static const struct net_device_ops pch_can_netdev_ops = {
1182 .ndo_open = pch_can_open,
1183 .ndo_stop = pch_close,
1184 .ndo_start_xmit = pch_xmit,
1185};
1186
1187static void __devexit pch_can_remove(struct pci_dev *pdev)
1188{
1189 struct net_device *ndev = pci_get_drvdata(pdev);
1190 struct pch_can_priv *priv = netdev_priv(ndev);
1191
1192 unregister_candev(priv->ndev);
1193 free_candev(priv->ndev);
1194 pci_iounmap(pdev, priv->regs);
1195 pci_release_regions(pdev);
1196 pci_disable_device(pdev);
1197 pci_set_drvdata(pdev, NULL);
1198 pch_can_reset(priv);
1199}
1200
1201#ifdef CONFIG_PM
1202static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
1203{
1204 int i; /* Counter variable. */
1205 int retval; /* Return value. */
1206 u32 buf_stat; /* Variable for reading the transmit buffer status. */
1207 u32 counter = 0xFFFFFF;
1208
1209 struct net_device *dev = pci_get_drvdata(pdev);
1210 struct pch_can_priv *priv = netdev_priv(dev);
1211
1212 /* Stop the CAN controller */
1213 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1214
1215 /* Indicate that we are aboutto/in suspend */
1216 priv->can.state = CAN_STATE_SLEEPING;
1217
1218 /* Waiting for all transmission to complete. */
1219 while (counter) {
1220 buf_stat = pch_can_get_buffer_status(priv);
1221 if (!buf_stat)
1222 break;
1223 counter--;
1224 udelay(1);
1225 }
1226 if (!counter)
1227 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
1228
1229 /* Save interrupt configuration and then disable them */
1230 pch_can_get_int_enables(priv, &(priv->int_enables));
1231 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1232
1233 /* Save Tx buffer enable state */
1234 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650 1235 if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
b21d18b5
MO		 1236 pch_can_get_tx_enable(priv, i + 1,
1237 &(priv->tx_enable[i]));
1238 }
1239
1240 /* Disable all Transmit buffers */
1241 pch_can_tx_disable_all(priv);
1242
1243 /* Save Rx buffer enable state */
1244 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650 1245 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
b21d18b5
MO		 1246 pch_can_get_rx_enable(priv, i + 1,
1247 &(priv->rx_enable[i]));
1248 pch_can_get_rx_buffer_link(priv, i + 1,
1249 &(priv->rx_link[i]));
1250 }
1251 }
1252
1253 /* Disable all Receive buffers */
1254 pch_can_rx_disable_all(priv);
1255 retval = pci_save_state(pdev);
1256 if (retval) {
1257 dev_err(&pdev->dev, "pci_save_state failed.\n");
1258 } else {
1259 pci_enable_wake(pdev, PCI_D3hot, 0);
1260 pci_disable_device(pdev);
1261 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1262 }
1263
1264 return retval;
1265}
1266
1267static int pch_can_resume(struct pci_dev *pdev)
1268{
1269 int i; /* Counter variable. */
1270 int retval; /* Return variable. */
1271 struct net_device *dev = pci_get_drvdata(pdev);
1272 struct pch_can_priv *priv = netdev_priv(dev);
1273
1274 pci_set_power_state(pdev, PCI_D0);
1275 pci_restore_state(pdev);
1276 retval = pci_enable_device(pdev);
1277 if (retval) {
1278 dev_err(&pdev->dev, "pci_enable_device failed.\n");
1279 return retval;
1280 }
1281
1282 pci_enable_wake(pdev, PCI_D3hot, 0);
1283
1284 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1285
1286 /* Disabling all interrupts. */
1287 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1288
1289 /* Setting the CAN device in Stop Mode. */
1290 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1291
1292 /* Configuring the transmit and receive buffers. */
1293 pch_can_config_rx_tx_buffers(priv);
1294
1295 /* Restore the CAN state */
1296 pch_set_bittiming(dev);
1297
1298 /* Listen/Active */
1299 pch_can_set_optmode(priv);
1300
1301 /* Enabling the transmit buffer. */
1302 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650 1303 if (priv->msg_obj[i] == PCH_MSG_OBJ_TX) {
b21d18b5
MO		 1304 pch_can_set_tx_enable(priv, i + 1,
1305 priv->tx_enable[i]);
1306 }
1307 }
1308
1309 /* Configuring the receive buffer and enabling them. */
1310 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650 1311 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
b21d18b5
MO		 1312 /* Restore buffer link */
1313 pch_can_set_rx_buffer_link(priv, i + 1,
1314 priv->rx_link[i]);
1315
1316 /* Restore buffer enables */
1317 pch_can_set_rx_enable(priv, i + 1, priv->rx_enable[i]);
1318 }
1319 }
1320
1321 /* Enable CAN Interrupts */
1322 pch_can_set_int_custom(priv);
1323
1324 /* Restore Run Mode */
1325 pch_can_set_run_mode(priv, PCH_CAN_RUN);
1326
1327 return retval;
1328}
1329#else
1330#define pch_can_suspend NULL
1331#define pch_can_resume NULL
1332#endif
1333
1334static int pch_can_get_berr_counter(const struct net_device *dev,
1335 struct can_berr_counter *bec)
1336{
1337 struct pch_can_priv *priv = netdev_priv(dev);
1338
086b5650
T		 1339 bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC;
1340 bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8;
b21d18b5
MO		 1341
1342 return 0;
1343}
1344
1345static int __devinit pch_can_probe(struct pci_dev *pdev,
1346 const struct pci_device_id *id)
1347{
1348 struct net_device *ndev;
1349 struct pch_can_priv *priv;
1350 int rc;
1351 int index;
1352 void __iomem *addr;
1353
1354 rc = pci_enable_device(pdev);
1355 if (rc) {
1356 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1357 goto probe_exit_endev;
1358 }
1359
1360 rc = pci_request_regions(pdev, KBUILD_MODNAME);
1361 if (rc) {
1362 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1363 goto probe_exit_pcireq;
1364 }
1365
1366 addr = pci_iomap(pdev, 1, 0);
1367 if (!addr) {
1368 rc = -EIO;
1369 dev_err(&pdev->dev, "Failed pci_iomap\n");
1370 goto probe_exit_ipmap;
1371 }
1372
1373 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_NUM);
1374 if (!ndev) {
1375 rc = -ENOMEM;
1376 dev_err(&pdev->dev, "Failed alloc_candev\n");
1377 goto probe_exit_alloc_candev;
1378 }
1379
1380 priv = netdev_priv(ndev);
1381 priv->ndev = ndev;
1382 priv->regs = addr;
1383 priv->dev = pdev;
1384 priv->can.bittiming_const = &pch_can_bittiming_const;
1385 priv->can.do_set_mode = pch_can_do_set_mode;
1386 priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1387 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1388 CAN_CTRLMODE_LOOPBACK;
1389 priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj */
1390
1391 ndev->irq = pdev->irq;
1392 ndev->flags |= IFF_ECHO;
1393
1394 pci_set_drvdata(pdev, ndev);
1395 SET_NETDEV_DEV(ndev, &pdev->dev);
1396 ndev->netdev_ops = &pch_can_netdev_ops;
1397
1398 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
1399 for (index = 0; index < PCH_RX_OBJ_NUM;)
086b5650 1400 priv->msg_obj[index++] = PCH_MSG_OBJ_RX;
b21d18b5
MO		 1401
1402 for (index = index; index < PCH_OBJ_NUM;)
086b5650 1403 priv->msg_obj[index++] = PCH_MSG_OBJ_TX;
b21d18b5
MO		 1404
1405 netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM);
1406
1407 rc = register_candev(ndev);
1408 if (rc) {
1409 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1410 goto probe_exit_reg_candev;
1411 }
1412
1413 return 0;
1414
1415probe_exit_reg_candev:
1416 free_candev(ndev);
1417probe_exit_alloc_candev:
1418 pci_iounmap(pdev, addr);
1419probe_exit_ipmap:
1420 pci_release_regions(pdev);
1421probe_exit_pcireq:
1422 pci_disable_device(pdev);
1423probe_exit_endev:
1424 return rc;
1425}
1426
bdfa3d8f 1427static struct pci_driver pch_can_pci_driver = {
b21d18b5
MO		 1428 .name = "pch_can",
1429 .id_table = pch_pci_tbl,
1430 .probe = pch_can_probe,
1431 .remove = __devexit_p(pch_can_remove),
1432 .suspend = pch_can_suspend,
1433 .resume = pch_can_resume,
1434};
1435
1436static int __init pch_can_pci_init(void)
1437{
bdfa3d8f 1438 return pci_register_driver(&pch_can_pci_driver);
b21d18b5
MO		 1439}
1440module_init(pch_can_pci_init);
1441
1442static void __exit pch_can_pci_exit(void)
1443{
bdfa3d8f 1444 pci_unregister_driver(&pch_can_pci_driver);
b21d18b5
MO		 1445}
1446module_exit(pch_can_pci_exit);
1447
1448MODULE_DESCRIPTION("Controller Area Network Driver");
1449MODULE_LICENSE("GPL v2");
1450MODULE_VERSION("0.94");
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