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Commit | Line | Data |
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8b230ed8 RM |
1 | /* |
2 | * Linux network driver for Brocade Converged Network Adapter. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License (GPL) Version 2 as | |
6 | * published by the Free Software Foundation | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | */ | |
13 | /* | |
14 | * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. | |
15 | * All rights reserved | |
16 | * www.brocade.com | |
17 | */ | |
18 | #include <linux/netdevice.h> | |
19 | #include <linux/skbuff.h> | |
20 | #include <linux/etherdevice.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ethtool.h> | |
23 | #include <linux/if_vlan.h> | |
24 | #include <linux/if_ether.h> | |
25 | #include <linux/ip.h> | |
26 | ||
27 | #include "bnad.h" | |
28 | #include "bna.h" | |
29 | #include "cna.h" | |
30 | ||
31 | DEFINE_MUTEX(bnad_fwimg_mutex); | |
32 | ||
33 | /* | |
34 | * Module params | |
35 | */ | |
36 | static uint bnad_msix_disable; | |
37 | module_param(bnad_msix_disable, uint, 0444); | |
38 | MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode"); | |
39 | ||
40 | static uint bnad_ioc_auto_recover = 1; | |
41 | module_param(bnad_ioc_auto_recover, uint, 0444); | |
42 | MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery"); | |
43 | ||
44 | /* | |
45 | * Global variables | |
46 | */ | |
47 | u32 bnad_rxqs_per_cq = 2; | |
48 | ||
49 | const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; | |
50 | ||
51 | /* | |
52 | * Local MACROS | |
53 | */ | |
54 | #define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2) | |
55 | ||
56 | #define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth) | |
57 | ||
58 | #define BNAD_GET_MBOX_IRQ(_bnad) \ | |
59 | (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \ | |
60 | ((_bnad)->msix_table[(_bnad)->msix_num - 1].vector) : \ | |
61 | ((_bnad)->pcidev->irq)) | |
62 | ||
63 | #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \ | |
64 | do { \ | |
65 | (_res_info)->res_type = BNA_RES_T_MEM; \ | |
66 | (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \ | |
67 | (_res_info)->res_u.mem_info.num = (_num); \ | |
68 | (_res_info)->res_u.mem_info.len = \ | |
69 | sizeof(struct bnad_unmap_q) + \ | |
70 | (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \ | |
71 | } while (0) | |
72 | ||
73 | /* | |
74 | * Reinitialize completions in CQ, once Rx is taken down | |
75 | */ | |
76 | static void | |
77 | bnad_cq_cmpl_init(struct bnad *bnad, struct bna_ccb *ccb) | |
78 | { | |
79 | struct bna_cq_entry *cmpl, *next_cmpl; | |
80 | unsigned int wi_range, wis = 0, ccb_prod = 0; | |
81 | int i; | |
82 | ||
83 | BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt, cmpl, | |
84 | wi_range); | |
85 | ||
86 | for (i = 0; i < ccb->q_depth; i++) { | |
87 | wis++; | |
88 | if (likely(--wi_range)) | |
89 | next_cmpl = cmpl + 1; | |
90 | else { | |
91 | BNA_QE_INDX_ADD(ccb_prod, wis, ccb->q_depth); | |
92 | wis = 0; | |
93 | BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt, | |
94 | next_cmpl, wi_range); | |
95 | } | |
96 | cmpl->valid = 0; | |
97 | cmpl = next_cmpl; | |
98 | } | |
99 | } | |
100 | ||
101 | /* | |
102 | * Frees all pending Tx Bufs | |
103 | * At this point no activity is expected on the Q, | |
104 | * so DMA unmap & freeing is fine. | |
105 | */ | |
106 | static void | |
107 | bnad_free_all_txbufs(struct bnad *bnad, | |
108 | struct bna_tcb *tcb) | |
109 | { | |
110 | u16 unmap_cons; | |
111 | struct bnad_unmap_q *unmap_q = tcb->unmap_q; | |
112 | struct bnad_skb_unmap *unmap_array; | |
113 | struct sk_buff *skb = NULL; | |
114 | int i; | |
115 | ||
116 | unmap_array = unmap_q->unmap_array; | |
117 | ||
118 | unmap_cons = 0; | |
119 | while (unmap_cons < unmap_q->q_depth) { | |
120 | skb = unmap_array[unmap_cons].skb; | |
121 | if (!skb) { | |
122 | unmap_cons++; | |
123 | continue; | |
124 | } | |
125 | unmap_array[unmap_cons].skb = NULL; | |
126 | ||
127 | pci_unmap_single(bnad->pcidev, | |
128 | pci_unmap_addr(&unmap_array[unmap_cons], | |
129 | dma_addr), skb_headlen(skb), | |
130 | PCI_DMA_TODEVICE); | |
131 | ||
132 | pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0); | |
133 | unmap_cons++; | |
134 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
135 | pci_unmap_page(bnad->pcidev, | |
136 | pci_unmap_addr(&unmap_array[unmap_cons], | |
137 | dma_addr), | |
138 | skb_shinfo(skb)->frags[i].size, | |
139 | PCI_DMA_TODEVICE); | |
140 | pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, | |
141 | 0); | |
142 | unmap_cons++; | |
143 | } | |
144 | dev_kfree_skb_any(skb); | |
145 | } | |
146 | } | |
147 | ||
148 | /* Data Path Handlers */ | |
149 | ||
150 | /* | |
151 | * bnad_free_txbufs : Frees the Tx bufs on Tx completion | |
152 | * Can be called in a) Interrupt context | |
153 | * b) Sending context | |
154 | * c) Tasklet context | |
155 | */ | |
156 | static u32 | |
157 | bnad_free_txbufs(struct bnad *bnad, | |
158 | struct bna_tcb *tcb) | |
159 | { | |
160 | u32 sent_packets = 0, sent_bytes = 0; | |
161 | u16 wis, unmap_cons, updated_hw_cons; | |
162 | struct bnad_unmap_q *unmap_q = tcb->unmap_q; | |
163 | struct bnad_skb_unmap *unmap_array; | |
164 | struct sk_buff *skb; | |
165 | int i; | |
166 | ||
167 | /* | |
168 | * Just return if TX is stopped. This check is useful | |
169 | * when bnad_free_txbufs() runs out of a tasklet scheduled | |
170 | * before bnad_cb_tx_cleanup() cleared BNAD_RF_TX_STARTED bit | |
171 | * but this routine runs actually after the cleanup has been | |
172 | * executed. | |
173 | */ | |
174 | if (!test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags)) | |
175 | return 0; | |
176 | ||
177 | updated_hw_cons = *(tcb->hw_consumer_index); | |
178 | ||
179 | wis = BNA_Q_INDEX_CHANGE(tcb->consumer_index, | |
180 | updated_hw_cons, tcb->q_depth); | |
181 | ||
182 | BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth))); | |
183 | ||
184 | unmap_array = unmap_q->unmap_array; | |
185 | unmap_cons = unmap_q->consumer_index; | |
186 | ||
187 | prefetch(&unmap_array[unmap_cons + 1]); | |
188 | while (wis) { | |
189 | skb = unmap_array[unmap_cons].skb; | |
190 | ||
191 | unmap_array[unmap_cons].skb = NULL; | |
192 | ||
193 | sent_packets++; | |
194 | sent_bytes += skb->len; | |
195 | wis -= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags); | |
196 | ||
197 | pci_unmap_single(bnad->pcidev, | |
198 | pci_unmap_addr(&unmap_array[unmap_cons], | |
199 | dma_addr), skb_headlen(skb), | |
200 | PCI_DMA_TODEVICE); | |
201 | pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0); | |
202 | BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth); | |
203 | ||
204 | prefetch(&unmap_array[unmap_cons + 1]); | |
205 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
206 | prefetch(&unmap_array[unmap_cons + 1]); | |
207 | ||
208 | pci_unmap_page(bnad->pcidev, | |
209 | pci_unmap_addr(&unmap_array[unmap_cons], | |
210 | dma_addr), | |
211 | skb_shinfo(skb)->frags[i].size, | |
212 | PCI_DMA_TODEVICE); | |
213 | pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, | |
214 | 0); | |
215 | BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth); | |
216 | } | |
217 | dev_kfree_skb_any(skb); | |
218 | } | |
219 | ||
220 | /* Update consumer pointers. */ | |
221 | tcb->consumer_index = updated_hw_cons; | |
222 | unmap_q->consumer_index = unmap_cons; | |
223 | ||
224 | tcb->txq->tx_packets += sent_packets; | |
225 | tcb->txq->tx_bytes += sent_bytes; | |
226 | ||
227 | return sent_packets; | |
228 | } | |
229 | ||
230 | /* Tx Free Tasklet function */ | |
231 | /* Frees for all the tcb's in all the Tx's */ | |
232 | /* | |
233 | * Scheduled from sending context, so that | |
234 | * the fat Tx lock is not held for too long | |
235 | * in the sending context. | |
236 | */ | |
237 | static void | |
238 | bnad_tx_free_tasklet(unsigned long bnad_ptr) | |
239 | { | |
240 | struct bnad *bnad = (struct bnad *)bnad_ptr; | |
241 | struct bna_tcb *tcb; | |
242 | u32 acked; | |
243 | int i, j; | |
244 | ||
245 | for (i = 0; i < bnad->num_tx; i++) { | |
246 | for (j = 0; j < bnad->num_txq_per_tx; j++) { | |
247 | tcb = bnad->tx_info[i].tcb[j]; | |
248 | if (!tcb) | |
249 | continue; | |
250 | if (((u16) (*tcb->hw_consumer_index) != | |
251 | tcb->consumer_index) && | |
252 | (!test_and_set_bit(BNAD_TXQ_FREE_SENT, | |
253 | &tcb->flags))) { | |
254 | acked = bnad_free_txbufs(bnad, tcb); | |
255 | bna_ib_ack(tcb->i_dbell, acked); | |
256 | smp_mb__before_clear_bit(); | |
257 | clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); | |
258 | } | |
259 | } | |
260 | } | |
261 | } | |
262 | ||
263 | static u32 | |
264 | bnad_tx(struct bnad *bnad, struct bna_tcb *tcb) | |
265 | { | |
266 | struct net_device *netdev = bnad->netdev; | |
267 | u32 sent; | |
268 | ||
269 | if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) | |
270 | return 0; | |
271 | ||
272 | sent = bnad_free_txbufs(bnad, tcb); | |
273 | if (sent) { | |
274 | if (netif_queue_stopped(netdev) && | |
275 | netif_carrier_ok(netdev) && | |
276 | BNA_QE_FREE_CNT(tcb, tcb->q_depth) >= | |
277 | BNAD_NETIF_WAKE_THRESHOLD) { | |
278 | netif_wake_queue(netdev); | |
279 | BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); | |
280 | } | |
281 | bna_ib_ack(tcb->i_dbell, sent); | |
282 | } else | |
283 | bna_ib_ack(tcb->i_dbell, 0); | |
284 | ||
285 | smp_mb__before_clear_bit(); | |
286 | clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); | |
287 | ||
288 | return sent; | |
289 | } | |
290 | ||
291 | /* MSIX Tx Completion Handler */ | |
292 | static irqreturn_t | |
293 | bnad_msix_tx(int irq, void *data) | |
294 | { | |
295 | struct bna_tcb *tcb = (struct bna_tcb *)data; | |
296 | struct bnad *bnad = tcb->bnad; | |
297 | ||
298 | bnad_tx(bnad, tcb); | |
299 | ||
300 | return IRQ_HANDLED; | |
301 | } | |
302 | ||
303 | static void | |
304 | bnad_reset_rcb(struct bnad *bnad, struct bna_rcb *rcb) | |
305 | { | |
306 | struct bnad_unmap_q *unmap_q = rcb->unmap_q; | |
307 | ||
308 | rcb->producer_index = 0; | |
309 | rcb->consumer_index = 0; | |
310 | ||
311 | unmap_q->producer_index = 0; | |
312 | unmap_q->consumer_index = 0; | |
313 | } | |
314 | ||
315 | static void | |
316 | bnad_free_rxbufs(struct bnad *bnad, struct bna_rcb *rcb) | |
317 | { | |
318 | struct bnad_unmap_q *unmap_q; | |
319 | struct sk_buff *skb; | |
320 | ||
321 | unmap_q = rcb->unmap_q; | |
322 | while (BNA_QE_IN_USE_CNT(unmap_q, unmap_q->q_depth)) { | |
323 | skb = unmap_q->unmap_array[unmap_q->consumer_index].skb; | |
324 | BUG_ON(!(skb)); | |
325 | unmap_q->unmap_array[unmap_q->consumer_index].skb = NULL; | |
326 | pci_unmap_single(bnad->pcidev, pci_unmap_addr(&unmap_q-> | |
327 | unmap_array[unmap_q->consumer_index], | |
328 | dma_addr), rcb->rxq->buffer_size + | |
329 | NET_IP_ALIGN, PCI_DMA_FROMDEVICE); | |
330 | dev_kfree_skb(skb); | |
331 | BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth); | |
332 | BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth); | |
333 | } | |
334 | ||
335 | bnad_reset_rcb(bnad, rcb); | |
336 | } | |
337 | ||
338 | static void | |
339 | bnad_alloc_n_post_rxbufs(struct bnad *bnad, struct bna_rcb *rcb) | |
340 | { | |
341 | u16 to_alloc, alloced, unmap_prod, wi_range; | |
342 | struct bnad_unmap_q *unmap_q = rcb->unmap_q; | |
343 | struct bnad_skb_unmap *unmap_array; | |
344 | struct bna_rxq_entry *rxent; | |
345 | struct sk_buff *skb; | |
346 | dma_addr_t dma_addr; | |
347 | ||
348 | alloced = 0; | |
349 | to_alloc = | |
350 | BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth); | |
351 | ||
352 | unmap_array = unmap_q->unmap_array; | |
353 | unmap_prod = unmap_q->producer_index; | |
354 | ||
355 | BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent, wi_range); | |
356 | ||
357 | while (to_alloc--) { | |
358 | if (!wi_range) { | |
359 | BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent, | |
360 | wi_range); | |
361 | } | |
362 | skb = alloc_skb(rcb->rxq->buffer_size + NET_IP_ALIGN, | |
363 | GFP_ATOMIC); | |
364 | if (unlikely(!skb)) { | |
365 | BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed); | |
366 | goto finishing; | |
367 | } | |
368 | skb->dev = bnad->netdev; | |
369 | skb_reserve(skb, NET_IP_ALIGN); | |
370 | unmap_array[unmap_prod].skb = skb; | |
371 | dma_addr = pci_map_single(bnad->pcidev, skb->data, | |
372 | rcb->rxq->buffer_size, PCI_DMA_FROMDEVICE); | |
373 | pci_unmap_addr_set(&unmap_array[unmap_prod], dma_addr, | |
374 | dma_addr); | |
375 | BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr); | |
376 | BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth); | |
377 | ||
378 | rxent++; | |
379 | wi_range--; | |
380 | alloced++; | |
381 | } | |
382 | ||
383 | finishing: | |
384 | if (likely(alloced)) { | |
385 | unmap_q->producer_index = unmap_prod; | |
386 | rcb->producer_index = unmap_prod; | |
387 | smp_mb(); | |
388 | bna_rxq_prod_indx_doorbell(rcb); | |
389 | } | |
390 | } | |
391 | ||
392 | /* | |
393 | * Locking is required in the enable path | |
394 | * because it is called from a napi poll | |
395 | * context, where the bna_lock is not held | |
396 | * unlike the IRQ context. | |
397 | */ | |
398 | static void | |
399 | bnad_enable_txrx_irqs(struct bnad *bnad) | |
400 | { | |
401 | struct bna_tcb *tcb; | |
402 | struct bna_ccb *ccb; | |
403 | int i, j; | |
404 | unsigned long flags; | |
405 | ||
406 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
407 | for (i = 0; i < bnad->num_tx; i++) { | |
408 | for (j = 0; j < bnad->num_txq_per_tx; j++) { | |
409 | tcb = bnad->tx_info[i].tcb[j]; | |
410 | bna_ib_coalescing_timer_set(tcb->i_dbell, | |
411 | tcb->txq->ib->ib_config.coalescing_timeo); | |
412 | bna_ib_ack(tcb->i_dbell, 0); | |
413 | } | |
414 | } | |
415 | ||
416 | for (i = 0; i < bnad->num_rx; i++) { | |
417 | for (j = 0; j < bnad->num_rxp_per_rx; j++) { | |
418 | ccb = bnad->rx_info[i].rx_ctrl[j].ccb; | |
419 | bnad_enable_rx_irq_unsafe(ccb); | |
420 | } | |
421 | } | |
422 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
423 | } | |
424 | ||
425 | static inline void | |
426 | bnad_refill_rxq(struct bnad *bnad, struct bna_rcb *rcb) | |
427 | { | |
428 | struct bnad_unmap_q *unmap_q = rcb->unmap_q; | |
429 | ||
430 | if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) { | |
431 | if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth) | |
432 | >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT) | |
433 | bnad_alloc_n_post_rxbufs(bnad, rcb); | |
434 | smp_mb__before_clear_bit(); | |
435 | clear_bit(BNAD_RXQ_REFILL, &rcb->flags); | |
436 | } | |
437 | } | |
438 | ||
439 | static u32 | |
440 | bnad_poll_cq(struct bnad *bnad, struct bna_ccb *ccb, int budget) | |
441 | { | |
442 | struct bna_cq_entry *cmpl, *next_cmpl; | |
443 | struct bna_rcb *rcb = NULL; | |
444 | unsigned int wi_range, packets = 0, wis = 0; | |
445 | struct bnad_unmap_q *unmap_q; | |
446 | struct sk_buff *skb; | |
447 | u32 flags; | |
448 | u32 qid0 = ccb->rcb[0]->rxq->rxq_id; | |
449 | struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate; | |
450 | ||
451 | prefetch(bnad->netdev); | |
452 | BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl, | |
453 | wi_range); | |
454 | BUG_ON(!(wi_range <= ccb->q_depth)); | |
455 | while (cmpl->valid && packets < budget) { | |
456 | packets++; | |
457 | BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length)); | |
458 | ||
459 | if (qid0 == cmpl->rxq_id) | |
460 | rcb = ccb->rcb[0]; | |
461 | else | |
462 | rcb = ccb->rcb[1]; | |
463 | ||
464 | unmap_q = rcb->unmap_q; | |
465 | ||
466 | skb = unmap_q->unmap_array[unmap_q->consumer_index].skb; | |
467 | BUG_ON(!(skb)); | |
468 | unmap_q->unmap_array[unmap_q->consumer_index].skb = NULL; | |
469 | pci_unmap_single(bnad->pcidev, | |
470 | pci_unmap_addr(&unmap_q-> | |
471 | unmap_array[unmap_q-> | |
472 | consumer_index], | |
473 | dma_addr), | |
474 | rcb->rxq->buffer_size, | |
475 | PCI_DMA_FROMDEVICE); | |
476 | BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth); | |
477 | ||
478 | /* Should be more efficient ? Performance ? */ | |
479 | BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth); | |
480 | ||
481 | wis++; | |
482 | if (likely(--wi_range)) | |
483 | next_cmpl = cmpl + 1; | |
484 | else { | |
485 | BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth); | |
486 | wis = 0; | |
487 | BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, | |
488 | next_cmpl, wi_range); | |
489 | BUG_ON(!(wi_range <= ccb->q_depth)); | |
490 | } | |
491 | prefetch(next_cmpl); | |
492 | ||
493 | flags = ntohl(cmpl->flags); | |
494 | if (unlikely | |
495 | (flags & | |
496 | (BNA_CQ_EF_MAC_ERROR | BNA_CQ_EF_FCS_ERROR | | |
497 | BNA_CQ_EF_TOO_LONG))) { | |
498 | dev_kfree_skb_any(skb); | |
499 | rcb->rxq->rx_packets_with_error++; | |
500 | goto next; | |
501 | } | |
502 | ||
503 | skb_put(skb, ntohs(cmpl->length)); | |
504 | if (likely | |
505 | (bnad->rx_csum && | |
506 | (((flags & BNA_CQ_EF_IPV4) && | |
507 | (flags & BNA_CQ_EF_L3_CKSUM_OK)) || | |
508 | (flags & BNA_CQ_EF_IPV6)) && | |
509 | (flags & (BNA_CQ_EF_TCP | BNA_CQ_EF_UDP)) && | |
510 | (flags & BNA_CQ_EF_L4_CKSUM_OK))) | |
511 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
512 | else | |
bc8acf2c | 513 | skb_checksum_none_assert(skb); |
8b230ed8 RM |
514 | |
515 | rcb->rxq->rx_packets++; | |
516 | rcb->rxq->rx_bytes += skb->len; | |
517 | skb->protocol = eth_type_trans(skb, bnad->netdev); | |
518 | ||
519 | if (bnad->vlan_grp && (flags & BNA_CQ_EF_VLAN)) { | |
520 | struct bnad_rx_ctrl *rx_ctrl = | |
521 | (struct bnad_rx_ctrl *)ccb->ctrl; | |
522 | if (skb->ip_summed == CHECKSUM_UNNECESSARY) | |
523 | vlan_gro_receive(&rx_ctrl->napi, bnad->vlan_grp, | |
524 | ntohs(cmpl->vlan_tag), skb); | |
525 | else | |
526 | vlan_hwaccel_receive_skb(skb, | |
527 | bnad->vlan_grp, | |
528 | ntohs(cmpl->vlan_tag)); | |
529 | ||
530 | } else { /* Not VLAN tagged/stripped */ | |
531 | struct bnad_rx_ctrl *rx_ctrl = | |
532 | (struct bnad_rx_ctrl *)ccb->ctrl; | |
533 | if (skb->ip_summed == CHECKSUM_UNNECESSARY) | |
534 | napi_gro_receive(&rx_ctrl->napi, skb); | |
535 | else | |
536 | netif_receive_skb(skb); | |
537 | } | |
538 | ||
539 | next: | |
540 | cmpl->valid = 0; | |
541 | cmpl = next_cmpl; | |
542 | } | |
543 | ||
544 | BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth); | |
545 | ||
546 | if (likely(ccb)) { | |
547 | bna_ib_ack(ccb->i_dbell, packets); | |
548 | bnad_refill_rxq(bnad, ccb->rcb[0]); | |
549 | if (ccb->rcb[1]) | |
550 | bnad_refill_rxq(bnad, ccb->rcb[1]); | |
551 | } else | |
552 | bna_ib_ack(ccb->i_dbell, 0); | |
553 | ||
554 | return packets; | |
555 | } | |
556 | ||
557 | static void | |
558 | bnad_disable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb) | |
559 | { | |
560 | bna_ib_coalescing_timer_set(ccb->i_dbell, 0); | |
561 | bna_ib_ack(ccb->i_dbell, 0); | |
562 | } | |
563 | ||
564 | static void | |
565 | bnad_enable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb) | |
566 | { | |
567 | spin_lock_irq(&bnad->bna_lock); /* Because of polling context */ | |
568 | bnad_enable_rx_irq_unsafe(ccb); | |
569 | spin_unlock_irq(&bnad->bna_lock); | |
570 | } | |
571 | ||
572 | static void | |
573 | bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb) | |
574 | { | |
575 | struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl); | |
576 | if (likely(napi_schedule_prep((&rx_ctrl->napi)))) { | |
577 | bnad_disable_rx_irq(bnad, ccb); | |
578 | __napi_schedule((&rx_ctrl->napi)); | |
579 | } | |
580 | BNAD_UPDATE_CTR(bnad, netif_rx_schedule); | |
581 | } | |
582 | ||
583 | /* MSIX Rx Path Handler */ | |
584 | static irqreturn_t | |
585 | bnad_msix_rx(int irq, void *data) | |
586 | { | |
587 | struct bna_ccb *ccb = (struct bna_ccb *)data; | |
588 | struct bnad *bnad = ccb->bnad; | |
589 | ||
590 | bnad_netif_rx_schedule_poll(bnad, ccb); | |
591 | ||
592 | return IRQ_HANDLED; | |
593 | } | |
594 | ||
595 | /* Interrupt handlers */ | |
596 | ||
597 | /* Mbox Interrupt Handlers */ | |
598 | static irqreturn_t | |
599 | bnad_msix_mbox_handler(int irq, void *data) | |
600 | { | |
601 | u32 intr_status; | |
602 | unsigned long flags; | |
603 | struct net_device *netdev = data; | |
604 | struct bnad *bnad; | |
605 | ||
606 | bnad = netdev_priv(netdev); | |
607 | ||
608 | /* BNA_ISR_GET(bnad); Inc Ref count */ | |
609 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
610 | ||
611 | bna_intr_status_get(&bnad->bna, intr_status); | |
612 | ||
613 | if (BNA_IS_MBOX_ERR_INTR(intr_status)) | |
614 | bna_mbox_handler(&bnad->bna, intr_status); | |
615 | ||
616 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
617 | ||
618 | /* BNAD_ISR_PUT(bnad); Dec Ref count */ | |
619 | return IRQ_HANDLED; | |
620 | } | |
621 | ||
622 | static irqreturn_t | |
623 | bnad_isr(int irq, void *data) | |
624 | { | |
625 | int i, j; | |
626 | u32 intr_status; | |
627 | unsigned long flags; | |
628 | struct net_device *netdev = data; | |
629 | struct bnad *bnad = netdev_priv(netdev); | |
630 | struct bnad_rx_info *rx_info; | |
631 | struct bnad_rx_ctrl *rx_ctrl; | |
632 | ||
633 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
634 | ||
635 | bna_intr_status_get(&bnad->bna, intr_status); | |
636 | if (!intr_status) { | |
637 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
638 | return IRQ_NONE; | |
639 | } | |
640 | ||
641 | if (BNA_IS_MBOX_ERR_INTR(intr_status)) { | |
642 | bna_mbox_handler(&bnad->bna, intr_status); | |
643 | if (!BNA_IS_INTX_DATA_INTR(intr_status)) { | |
644 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
645 | goto done; | |
646 | } | |
647 | } | |
648 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
649 | ||
650 | /* Process data interrupts */ | |
651 | for (i = 0; i < bnad->num_rx; i++) { | |
652 | rx_info = &bnad->rx_info[i]; | |
653 | if (!rx_info->rx) | |
654 | continue; | |
655 | for (j = 0; j < bnad->num_rxp_per_rx; j++) { | |
656 | rx_ctrl = &rx_info->rx_ctrl[j]; | |
657 | if (rx_ctrl->ccb) | |
658 | bnad_netif_rx_schedule_poll(bnad, | |
659 | rx_ctrl->ccb); | |
660 | } | |
661 | } | |
662 | done: | |
663 | return IRQ_HANDLED; | |
664 | } | |
665 | ||
666 | /* | |
667 | * Called in interrupt / callback context | |
668 | * with bna_lock held, so cfg_flags access is OK | |
669 | */ | |
670 | static void | |
671 | bnad_enable_mbox_irq(struct bnad *bnad) | |
672 | { | |
673 | int irq = BNAD_GET_MBOX_IRQ(bnad); | |
674 | ||
675 | if (!(bnad->cfg_flags & BNAD_CF_MSIX)) | |
676 | return; | |
677 | ||
678 | if (test_and_clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)) | |
679 | enable_irq(irq); | |
680 | BNAD_UPDATE_CTR(bnad, mbox_intr_enabled); | |
681 | } | |
682 | ||
683 | /* | |
684 | * Called with bnad->bna_lock held b'cos of | |
685 | * bnad->cfg_flags access. | |
686 | */ | |
687 | void | |
688 | bnad_disable_mbox_irq(struct bnad *bnad) | |
689 | { | |
690 | int irq = BNAD_GET_MBOX_IRQ(bnad); | |
691 | ||
692 | if (!(bnad->cfg_flags & BNAD_CF_MSIX)) | |
693 | return; | |
694 | ||
695 | if (!test_and_set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)) | |
696 | disable_irq_nosync(irq); | |
697 | BNAD_UPDATE_CTR(bnad, mbox_intr_disabled); | |
698 | } | |
699 | ||
700 | /* Control Path Handlers */ | |
701 | ||
702 | /* Callbacks */ | |
703 | void | |
704 | bnad_cb_device_enable_mbox_intr(struct bnad *bnad) | |
705 | { | |
706 | bnad_enable_mbox_irq(bnad); | |
707 | } | |
708 | ||
709 | void | |
710 | bnad_cb_device_disable_mbox_intr(struct bnad *bnad) | |
711 | { | |
712 | bnad_disable_mbox_irq(bnad); | |
713 | } | |
714 | ||
715 | void | |
716 | bnad_cb_device_enabled(struct bnad *bnad, enum bna_cb_status status) | |
717 | { | |
718 | complete(&bnad->bnad_completions.ioc_comp); | |
719 | bnad->bnad_completions.ioc_comp_status = status; | |
720 | } | |
721 | ||
722 | void | |
723 | bnad_cb_device_disabled(struct bnad *bnad, enum bna_cb_status status) | |
724 | { | |
725 | complete(&bnad->bnad_completions.ioc_comp); | |
726 | bnad->bnad_completions.ioc_comp_status = status; | |
727 | } | |
728 | ||
729 | static void | |
730 | bnad_cb_port_disabled(void *arg, enum bna_cb_status status) | |
731 | { | |
732 | struct bnad *bnad = (struct bnad *)arg; | |
733 | ||
734 | complete(&bnad->bnad_completions.port_comp); | |
735 | ||
736 | netif_carrier_off(bnad->netdev); | |
737 | } | |
738 | ||
739 | void | |
740 | bnad_cb_port_link_status(struct bnad *bnad, | |
741 | enum bna_link_status link_status) | |
742 | { | |
743 | bool link_up = 0; | |
744 | ||
745 | link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP); | |
746 | ||
747 | if (link_status == BNA_CEE_UP) { | |
748 | set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags); | |
749 | BNAD_UPDATE_CTR(bnad, cee_up); | |
750 | } else | |
751 | clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags); | |
752 | ||
753 | if (link_up) { | |
754 | if (!netif_carrier_ok(bnad->netdev)) { | |
755 | pr_warn("bna: %s link up\n", | |
756 | bnad->netdev->name); | |
757 | netif_carrier_on(bnad->netdev); | |
758 | BNAD_UPDATE_CTR(bnad, link_toggle); | |
759 | if (test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags)) { | |
760 | /* Force an immediate Transmit Schedule */ | |
761 | pr_info("bna: %s TX_STARTED\n", | |
762 | bnad->netdev->name); | |
763 | netif_wake_queue(bnad->netdev); | |
764 | BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); | |
765 | } else { | |
766 | netif_stop_queue(bnad->netdev); | |
767 | BNAD_UPDATE_CTR(bnad, netif_queue_stop); | |
768 | } | |
769 | } | |
770 | } else { | |
771 | if (netif_carrier_ok(bnad->netdev)) { | |
772 | pr_warn("bna: %s link down\n", | |
773 | bnad->netdev->name); | |
774 | netif_carrier_off(bnad->netdev); | |
775 | BNAD_UPDATE_CTR(bnad, link_toggle); | |
776 | } | |
777 | } | |
778 | } | |
779 | ||
780 | static void | |
781 | bnad_cb_tx_disabled(void *arg, struct bna_tx *tx, | |
782 | enum bna_cb_status status) | |
783 | { | |
784 | struct bnad *bnad = (struct bnad *)arg; | |
785 | ||
786 | complete(&bnad->bnad_completions.tx_comp); | |
787 | } | |
788 | ||
789 | static void | |
790 | bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb) | |
791 | { | |
792 | struct bnad_tx_info *tx_info = | |
793 | (struct bnad_tx_info *)tcb->txq->tx->priv; | |
794 | struct bnad_unmap_q *unmap_q = tcb->unmap_q; | |
795 | ||
796 | tx_info->tcb[tcb->id] = tcb; | |
797 | unmap_q->producer_index = 0; | |
798 | unmap_q->consumer_index = 0; | |
799 | unmap_q->q_depth = BNAD_TX_UNMAPQ_DEPTH; | |
800 | } | |
801 | ||
802 | static void | |
803 | bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb) | |
804 | { | |
805 | struct bnad_tx_info *tx_info = | |
806 | (struct bnad_tx_info *)tcb->txq->tx->priv; | |
807 | ||
808 | tx_info->tcb[tcb->id] = NULL; | |
809 | } | |
810 | ||
811 | static void | |
812 | bnad_cb_rcb_setup(struct bnad *bnad, struct bna_rcb *rcb) | |
813 | { | |
814 | struct bnad_unmap_q *unmap_q = rcb->unmap_q; | |
815 | ||
816 | unmap_q->producer_index = 0; | |
817 | unmap_q->consumer_index = 0; | |
818 | unmap_q->q_depth = BNAD_RX_UNMAPQ_DEPTH; | |
819 | } | |
820 | ||
821 | static void | |
822 | bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb) | |
823 | { | |
824 | struct bnad_rx_info *rx_info = | |
825 | (struct bnad_rx_info *)ccb->cq->rx->priv; | |
826 | ||
827 | rx_info->rx_ctrl[ccb->id].ccb = ccb; | |
828 | ccb->ctrl = &rx_info->rx_ctrl[ccb->id]; | |
829 | } | |
830 | ||
831 | static void | |
832 | bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb) | |
833 | { | |
834 | struct bnad_rx_info *rx_info = | |
835 | (struct bnad_rx_info *)ccb->cq->rx->priv; | |
836 | ||
837 | rx_info->rx_ctrl[ccb->id].ccb = NULL; | |
838 | } | |
839 | ||
840 | static void | |
841 | bnad_cb_tx_stall(struct bnad *bnad, struct bna_tcb *tcb) | |
842 | { | |
843 | struct bnad_tx_info *tx_info = | |
844 | (struct bnad_tx_info *)tcb->txq->tx->priv; | |
845 | ||
846 | if (tx_info != &bnad->tx_info[0]) | |
847 | return; | |
848 | ||
849 | clear_bit(BNAD_RF_TX_STARTED, &bnad->run_flags); | |
850 | netif_stop_queue(bnad->netdev); | |
851 | pr_info("bna: %s TX_STOPPED\n", bnad->netdev->name); | |
852 | } | |
853 | ||
854 | static void | |
855 | bnad_cb_tx_resume(struct bnad *bnad, struct bna_tcb *tcb) | |
856 | { | |
857 | if (test_and_set_bit(BNAD_RF_TX_STARTED, &bnad->run_flags)) | |
858 | return; | |
859 | ||
860 | if (netif_carrier_ok(bnad->netdev)) { | |
861 | pr_info("bna: %s TX_STARTED\n", bnad->netdev->name); | |
862 | netif_wake_queue(bnad->netdev); | |
863 | BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); | |
864 | } | |
865 | } | |
866 | ||
867 | static void | |
868 | bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tcb *tcb) | |
869 | { | |
0ea05ce7 | 870 | struct bnad_unmap_q *unmap_q; |
8b230ed8 RM |
871 | |
872 | if (!tcb || (!tcb->unmap_q)) | |
873 | return; | |
874 | ||
0ea05ce7 | 875 | unmap_q = tcb->unmap_q; |
8b230ed8 RM |
876 | if (!unmap_q->unmap_array) |
877 | return; | |
878 | ||
879 | if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) | |
880 | return; | |
881 | ||
882 | bnad_free_all_txbufs(bnad, tcb); | |
883 | ||
884 | unmap_q->producer_index = 0; | |
885 | unmap_q->consumer_index = 0; | |
886 | ||
887 | smp_mb__before_clear_bit(); | |
888 | clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); | |
889 | } | |
890 | ||
891 | static void | |
892 | bnad_cb_rx_cleanup(struct bnad *bnad, | |
893 | struct bna_ccb *ccb) | |
894 | { | |
895 | bnad_cq_cmpl_init(bnad, ccb); | |
896 | ||
897 | bnad_free_rxbufs(bnad, ccb->rcb[0]); | |
898 | clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags); | |
899 | ||
900 | if (ccb->rcb[1]) { | |
901 | bnad_free_rxbufs(bnad, ccb->rcb[1]); | |
902 | clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags); | |
903 | } | |
904 | } | |
905 | ||
906 | static void | |
907 | bnad_cb_rx_post(struct bnad *bnad, struct bna_rcb *rcb) | |
908 | { | |
909 | struct bnad_unmap_q *unmap_q = rcb->unmap_q; | |
910 | ||
911 | set_bit(BNAD_RXQ_STARTED, &rcb->flags); | |
912 | ||
913 | /* Now allocate & post buffers for this RCB */ | |
914 | /* !!Allocation in callback context */ | |
915 | if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) { | |
916 | if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth) | |
917 | >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT) | |
918 | bnad_alloc_n_post_rxbufs(bnad, rcb); | |
919 | smp_mb__before_clear_bit(); | |
920 | clear_bit(BNAD_RXQ_REFILL, &rcb->flags); | |
921 | } | |
922 | } | |
923 | ||
924 | static void | |
925 | bnad_cb_rx_disabled(void *arg, struct bna_rx *rx, | |
926 | enum bna_cb_status status) | |
927 | { | |
928 | struct bnad *bnad = (struct bnad *)arg; | |
929 | ||
930 | complete(&bnad->bnad_completions.rx_comp); | |
931 | } | |
932 | ||
933 | static void | |
934 | bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx, | |
935 | enum bna_cb_status status) | |
936 | { | |
937 | bnad->bnad_completions.mcast_comp_status = status; | |
938 | complete(&bnad->bnad_completions.mcast_comp); | |
939 | } | |
940 | ||
941 | void | |
942 | bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status, | |
943 | struct bna_stats *stats) | |
944 | { | |
945 | if (status == BNA_CB_SUCCESS) | |
946 | BNAD_UPDATE_CTR(bnad, hw_stats_updates); | |
947 | ||
948 | if (!netif_running(bnad->netdev) || | |
949 | !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) | |
950 | return; | |
951 | ||
952 | mod_timer(&bnad->stats_timer, | |
953 | jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ)); | |
954 | } | |
955 | ||
956 | void | |
957 | bnad_cb_stats_clr(struct bnad *bnad) | |
958 | { | |
959 | } | |
960 | ||
961 | /* Resource allocation, free functions */ | |
962 | ||
963 | static void | |
964 | bnad_mem_free(struct bnad *bnad, | |
965 | struct bna_mem_info *mem_info) | |
966 | { | |
967 | int i; | |
968 | dma_addr_t dma_pa; | |
969 | ||
970 | if (mem_info->mdl == NULL) | |
971 | return; | |
972 | ||
973 | for (i = 0; i < mem_info->num; i++) { | |
974 | if (mem_info->mdl[i].kva != NULL) { | |
975 | if (mem_info->mem_type == BNA_MEM_T_DMA) { | |
976 | BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma), | |
977 | dma_pa); | |
978 | pci_free_consistent(bnad->pcidev, | |
979 | mem_info->mdl[i].len, | |
980 | mem_info->mdl[i].kva, dma_pa); | |
981 | } else | |
982 | kfree(mem_info->mdl[i].kva); | |
983 | } | |
984 | } | |
985 | kfree(mem_info->mdl); | |
986 | mem_info->mdl = NULL; | |
987 | } | |
988 | ||
989 | static int | |
990 | bnad_mem_alloc(struct bnad *bnad, | |
991 | struct bna_mem_info *mem_info) | |
992 | { | |
993 | int i; | |
994 | dma_addr_t dma_pa; | |
995 | ||
996 | if ((mem_info->num == 0) || (mem_info->len == 0)) { | |
997 | mem_info->mdl = NULL; | |
998 | return 0; | |
999 | } | |
1000 | ||
1001 | mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr), | |
1002 | GFP_KERNEL); | |
1003 | if (mem_info->mdl == NULL) | |
1004 | return -ENOMEM; | |
1005 | ||
1006 | if (mem_info->mem_type == BNA_MEM_T_DMA) { | |
1007 | for (i = 0; i < mem_info->num; i++) { | |
1008 | mem_info->mdl[i].len = mem_info->len; | |
1009 | mem_info->mdl[i].kva = | |
1010 | pci_alloc_consistent(bnad->pcidev, | |
1011 | mem_info->len, &dma_pa); | |
1012 | ||
1013 | if (mem_info->mdl[i].kva == NULL) | |
1014 | goto err_return; | |
1015 | ||
1016 | BNA_SET_DMA_ADDR(dma_pa, | |
1017 | &(mem_info->mdl[i].dma)); | |
1018 | } | |
1019 | } else { | |
1020 | for (i = 0; i < mem_info->num; i++) { | |
1021 | mem_info->mdl[i].len = mem_info->len; | |
1022 | mem_info->mdl[i].kva = kzalloc(mem_info->len, | |
1023 | GFP_KERNEL); | |
1024 | if (mem_info->mdl[i].kva == NULL) | |
1025 | goto err_return; | |
1026 | } | |
1027 | } | |
1028 | ||
1029 | return 0; | |
1030 | ||
1031 | err_return: | |
1032 | bnad_mem_free(bnad, mem_info); | |
1033 | return -ENOMEM; | |
1034 | } | |
1035 | ||
1036 | /* Free IRQ for Mailbox */ | |
1037 | static void | |
1038 | bnad_mbox_irq_free(struct bnad *bnad, | |
1039 | struct bna_intr_info *intr_info) | |
1040 | { | |
1041 | int irq; | |
1042 | unsigned long flags; | |
1043 | ||
1044 | if (intr_info->idl == NULL) | |
1045 | return; | |
1046 | ||
1047 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1048 | ||
1049 | bnad_disable_mbox_irq(bnad); | |
1050 | ||
1051 | irq = BNAD_GET_MBOX_IRQ(bnad); | |
1052 | free_irq(irq, bnad->netdev); | |
1053 | ||
1054 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1055 | ||
1056 | kfree(intr_info->idl); | |
1057 | } | |
1058 | ||
1059 | /* | |
1060 | * Allocates IRQ for Mailbox, but keep it disabled | |
1061 | * This will be enabled once we get the mbox enable callback | |
1062 | * from bna | |
1063 | */ | |
1064 | static int | |
1065 | bnad_mbox_irq_alloc(struct bnad *bnad, | |
1066 | struct bna_intr_info *intr_info) | |
1067 | { | |
1068 | int err; | |
1069 | unsigned long flags; | |
1070 | u32 irq; | |
1071 | irq_handler_t irq_handler; | |
1072 | ||
1073 | /* Mbox should use only 1 vector */ | |
1074 | ||
1075 | intr_info->idl = kzalloc(sizeof(*(intr_info->idl)), GFP_KERNEL); | |
1076 | if (!intr_info->idl) | |
1077 | return -ENOMEM; | |
1078 | ||
1079 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1080 | if (bnad->cfg_flags & BNAD_CF_MSIX) { | |
1081 | irq_handler = (irq_handler_t)bnad_msix_mbox_handler; | |
1082 | irq = bnad->msix_table[bnad->msix_num - 1].vector; | |
1083 | flags = 0; | |
1084 | intr_info->intr_type = BNA_INTR_T_MSIX; | |
1085 | intr_info->idl[0].vector = bnad->msix_num - 1; | |
1086 | } else { | |
1087 | irq_handler = (irq_handler_t)bnad_isr; | |
1088 | irq = bnad->pcidev->irq; | |
1089 | flags = IRQF_SHARED; | |
1090 | intr_info->intr_type = BNA_INTR_T_INTX; | |
1091 | /* intr_info->idl.vector = 0 ? */ | |
1092 | } | |
1093 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1094 | ||
1095 | sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME); | |
1096 | ||
1097 | err = request_irq(irq, irq_handler, flags, | |
1098 | bnad->mbox_irq_name, bnad->netdev); | |
1099 | if (err) { | |
1100 | kfree(intr_info->idl); | |
1101 | intr_info->idl = NULL; | |
1102 | return err; | |
1103 | } | |
1104 | ||
1105 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1106 | bnad_disable_mbox_irq(bnad); | |
1107 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | static void | |
1112 | bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info) | |
1113 | { | |
1114 | kfree(intr_info->idl); | |
1115 | intr_info->idl = NULL; | |
1116 | } | |
1117 | ||
1118 | /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */ | |
1119 | static int | |
1120 | bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src, | |
1121 | uint txrx_id, struct bna_intr_info *intr_info) | |
1122 | { | |
1123 | int i, vector_start = 0; | |
1124 | u32 cfg_flags; | |
1125 | unsigned long flags; | |
1126 | ||
1127 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1128 | cfg_flags = bnad->cfg_flags; | |
1129 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1130 | ||
1131 | if (cfg_flags & BNAD_CF_MSIX) { | |
1132 | intr_info->intr_type = BNA_INTR_T_MSIX; | |
1133 | intr_info->idl = kcalloc(intr_info->num, | |
1134 | sizeof(struct bna_intr_descr), | |
1135 | GFP_KERNEL); | |
1136 | if (!intr_info->idl) | |
1137 | return -ENOMEM; | |
1138 | ||
1139 | switch (src) { | |
1140 | case BNAD_INTR_TX: | |
1141 | vector_start = txrx_id; | |
1142 | break; | |
1143 | ||
1144 | case BNAD_INTR_RX: | |
1145 | vector_start = bnad->num_tx * bnad->num_txq_per_tx + | |
1146 | txrx_id; | |
1147 | break; | |
1148 | ||
1149 | default: | |
1150 | BUG(); | |
1151 | } | |
1152 | ||
1153 | for (i = 0; i < intr_info->num; i++) | |
1154 | intr_info->idl[i].vector = vector_start + i; | |
1155 | } else { | |
1156 | intr_info->intr_type = BNA_INTR_T_INTX; | |
1157 | intr_info->num = 1; | |
1158 | intr_info->idl = kcalloc(intr_info->num, | |
1159 | sizeof(struct bna_intr_descr), | |
1160 | GFP_KERNEL); | |
1161 | if (!intr_info->idl) | |
1162 | return -ENOMEM; | |
1163 | ||
1164 | switch (src) { | |
1165 | case BNAD_INTR_TX: | |
1166 | intr_info->idl[0].vector = 0x1; /* Bit mask : Tx IB */ | |
1167 | break; | |
1168 | ||
1169 | case BNAD_INTR_RX: | |
1170 | intr_info->idl[0].vector = 0x2; /* Bit mask : Rx IB */ | |
1171 | break; | |
1172 | } | |
1173 | } | |
1174 | return 0; | |
1175 | } | |
1176 | ||
1177 | /** | |
1178 | * NOTE: Should be called for MSIX only | |
1179 | * Unregisters Tx MSIX vector(s) from the kernel | |
1180 | */ | |
1181 | static void | |
1182 | bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info, | |
1183 | int num_txqs) | |
1184 | { | |
1185 | int i; | |
1186 | int vector_num; | |
1187 | ||
1188 | for (i = 0; i < num_txqs; i++) { | |
1189 | if (tx_info->tcb[i] == NULL) | |
1190 | continue; | |
1191 | ||
1192 | vector_num = tx_info->tcb[i]->intr_vector; | |
1193 | free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]); | |
1194 | } | |
1195 | } | |
1196 | ||
1197 | /** | |
1198 | * NOTE: Should be called for MSIX only | |
1199 | * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel | |
1200 | */ | |
1201 | static int | |
1202 | bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info, | |
1203 | uint tx_id, int num_txqs) | |
1204 | { | |
1205 | int i; | |
1206 | int err; | |
1207 | int vector_num; | |
1208 | ||
1209 | for (i = 0; i < num_txqs; i++) { | |
1210 | vector_num = tx_info->tcb[i]->intr_vector; | |
1211 | sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name, | |
1212 | tx_id + tx_info->tcb[i]->id); | |
1213 | err = request_irq(bnad->msix_table[vector_num].vector, | |
1214 | (irq_handler_t)bnad_msix_tx, 0, | |
1215 | tx_info->tcb[i]->name, | |
1216 | tx_info->tcb[i]); | |
1217 | if (err) | |
1218 | goto err_return; | |
1219 | } | |
1220 | ||
1221 | return 0; | |
1222 | ||
1223 | err_return: | |
1224 | if (i > 0) | |
1225 | bnad_tx_msix_unregister(bnad, tx_info, (i - 1)); | |
1226 | return -1; | |
1227 | } | |
1228 | ||
1229 | /** | |
1230 | * NOTE: Should be called for MSIX only | |
1231 | * Unregisters Rx MSIX vector(s) from the kernel | |
1232 | */ | |
1233 | static void | |
1234 | bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info, | |
1235 | int num_rxps) | |
1236 | { | |
1237 | int i; | |
1238 | int vector_num; | |
1239 | ||
1240 | for (i = 0; i < num_rxps; i++) { | |
1241 | if (rx_info->rx_ctrl[i].ccb == NULL) | |
1242 | continue; | |
1243 | ||
1244 | vector_num = rx_info->rx_ctrl[i].ccb->intr_vector; | |
1245 | free_irq(bnad->msix_table[vector_num].vector, | |
1246 | rx_info->rx_ctrl[i].ccb); | |
1247 | } | |
1248 | } | |
1249 | ||
1250 | /** | |
1251 | * NOTE: Should be called for MSIX only | |
1252 | * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel | |
1253 | */ | |
1254 | static int | |
1255 | bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info, | |
1256 | uint rx_id, int num_rxps) | |
1257 | { | |
1258 | int i; | |
1259 | int err; | |
1260 | int vector_num; | |
1261 | ||
1262 | for (i = 0; i < num_rxps; i++) { | |
1263 | vector_num = rx_info->rx_ctrl[i].ccb->intr_vector; | |
1264 | sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d", | |
1265 | bnad->netdev->name, | |
1266 | rx_id + rx_info->rx_ctrl[i].ccb->id); | |
1267 | err = request_irq(bnad->msix_table[vector_num].vector, | |
1268 | (irq_handler_t)bnad_msix_rx, 0, | |
1269 | rx_info->rx_ctrl[i].ccb->name, | |
1270 | rx_info->rx_ctrl[i].ccb); | |
1271 | if (err) | |
1272 | goto err_return; | |
1273 | } | |
1274 | ||
1275 | return 0; | |
1276 | ||
1277 | err_return: | |
1278 | if (i > 0) | |
1279 | bnad_rx_msix_unregister(bnad, rx_info, (i - 1)); | |
1280 | return -1; | |
1281 | } | |
1282 | ||
1283 | /* Free Tx object Resources */ | |
1284 | static void | |
1285 | bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info) | |
1286 | { | |
1287 | int i; | |
1288 | ||
1289 | for (i = 0; i < BNA_TX_RES_T_MAX; i++) { | |
1290 | if (res_info[i].res_type == BNA_RES_T_MEM) | |
1291 | bnad_mem_free(bnad, &res_info[i].res_u.mem_info); | |
1292 | else if (res_info[i].res_type == BNA_RES_T_INTR) | |
1293 | bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info); | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | /* Allocates memory and interrupt resources for Tx object */ | |
1298 | static int | |
1299 | bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, | |
1300 | uint tx_id) | |
1301 | { | |
1302 | int i, err = 0; | |
1303 | ||
1304 | for (i = 0; i < BNA_TX_RES_T_MAX; i++) { | |
1305 | if (res_info[i].res_type == BNA_RES_T_MEM) | |
1306 | err = bnad_mem_alloc(bnad, | |
1307 | &res_info[i].res_u.mem_info); | |
1308 | else if (res_info[i].res_type == BNA_RES_T_INTR) | |
1309 | err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id, | |
1310 | &res_info[i].res_u.intr_info); | |
1311 | if (err) | |
1312 | goto err_return; | |
1313 | } | |
1314 | return 0; | |
1315 | ||
1316 | err_return: | |
1317 | bnad_tx_res_free(bnad, res_info); | |
1318 | return err; | |
1319 | } | |
1320 | ||
1321 | /* Free Rx object Resources */ | |
1322 | static void | |
1323 | bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info) | |
1324 | { | |
1325 | int i; | |
1326 | ||
1327 | for (i = 0; i < BNA_RX_RES_T_MAX; i++) { | |
1328 | if (res_info[i].res_type == BNA_RES_T_MEM) | |
1329 | bnad_mem_free(bnad, &res_info[i].res_u.mem_info); | |
1330 | else if (res_info[i].res_type == BNA_RES_T_INTR) | |
1331 | bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info); | |
1332 | } | |
1333 | } | |
1334 | ||
1335 | /* Allocates memory and interrupt resources for Rx object */ | |
1336 | static int | |
1337 | bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info, | |
1338 | uint rx_id) | |
1339 | { | |
1340 | int i, err = 0; | |
1341 | ||
1342 | /* All memory needs to be allocated before setup_ccbs */ | |
1343 | for (i = 0; i < BNA_RX_RES_T_MAX; i++) { | |
1344 | if (res_info[i].res_type == BNA_RES_T_MEM) | |
1345 | err = bnad_mem_alloc(bnad, | |
1346 | &res_info[i].res_u.mem_info); | |
1347 | else if (res_info[i].res_type == BNA_RES_T_INTR) | |
1348 | err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id, | |
1349 | &res_info[i].res_u.intr_info); | |
1350 | if (err) | |
1351 | goto err_return; | |
1352 | } | |
1353 | return 0; | |
1354 | ||
1355 | err_return: | |
1356 | bnad_rx_res_free(bnad, res_info); | |
1357 | return err; | |
1358 | } | |
1359 | ||
1360 | /* Timer callbacks */ | |
1361 | /* a) IOC timer */ | |
1362 | static void | |
1363 | bnad_ioc_timeout(unsigned long data) | |
1364 | { | |
1365 | struct bnad *bnad = (struct bnad *)data; | |
1366 | unsigned long flags; | |
1367 | ||
1368 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
8a891429 | 1369 | bfa_nw_ioc_timeout((void *) &bnad->bna.device.ioc); |
8b230ed8 RM |
1370 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
1371 | } | |
1372 | ||
1373 | static void | |
1374 | bnad_ioc_hb_check(unsigned long data) | |
1375 | { | |
1376 | struct bnad *bnad = (struct bnad *)data; | |
1377 | unsigned long flags; | |
1378 | ||
1379 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
8a891429 | 1380 | bfa_nw_ioc_hb_check((void *) &bnad->bna.device.ioc); |
8b230ed8 RM |
1381 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
1382 | } | |
1383 | ||
1384 | static void | |
1385 | bnad_ioc_sem_timeout(unsigned long data) | |
1386 | { | |
1387 | struct bnad *bnad = (struct bnad *)data; | |
1388 | unsigned long flags; | |
1389 | ||
1390 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
8a891429 | 1391 | bfa_nw_ioc_sem_timeout((void *) &bnad->bna.device.ioc); |
8b230ed8 RM |
1392 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
1393 | } | |
1394 | ||
1395 | /* | |
1396 | * All timer routines use bnad->bna_lock to protect against | |
1397 | * the following race, which may occur in case of no locking: | |
1398 | * Time CPU m CPU n | |
1399 | * 0 1 = test_bit | |
1400 | * 1 clear_bit | |
1401 | * 2 del_timer_sync | |
1402 | * 3 mod_timer | |
1403 | */ | |
1404 | ||
1405 | /* b) Dynamic Interrupt Moderation Timer */ | |
1406 | static void | |
1407 | bnad_dim_timeout(unsigned long data) | |
1408 | { | |
1409 | struct bnad *bnad = (struct bnad *)data; | |
1410 | struct bnad_rx_info *rx_info; | |
1411 | struct bnad_rx_ctrl *rx_ctrl; | |
1412 | int i, j; | |
1413 | unsigned long flags; | |
1414 | ||
1415 | if (!netif_carrier_ok(bnad->netdev)) | |
1416 | return; | |
1417 | ||
1418 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1419 | for (i = 0; i < bnad->num_rx; i++) { | |
1420 | rx_info = &bnad->rx_info[i]; | |
1421 | if (!rx_info->rx) | |
1422 | continue; | |
1423 | for (j = 0; j < bnad->num_rxp_per_rx; j++) { | |
1424 | rx_ctrl = &rx_info->rx_ctrl[j]; | |
1425 | if (!rx_ctrl->ccb) | |
1426 | continue; | |
1427 | bna_rx_dim_update(rx_ctrl->ccb); | |
1428 | } | |
1429 | } | |
1430 | ||
1431 | /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */ | |
1432 | if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) | |
1433 | mod_timer(&bnad->dim_timer, | |
1434 | jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ)); | |
1435 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1436 | } | |
1437 | ||
1438 | /* c) Statistics Timer */ | |
1439 | static void | |
1440 | bnad_stats_timeout(unsigned long data) | |
1441 | { | |
1442 | struct bnad *bnad = (struct bnad *)data; | |
1443 | unsigned long flags; | |
1444 | ||
1445 | if (!netif_running(bnad->netdev) || | |
1446 | !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) | |
1447 | return; | |
1448 | ||
1449 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1450 | bna_stats_get(&bnad->bna); | |
1451 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1452 | } | |
1453 | ||
1454 | /* | |
1455 | * Set up timer for DIM | |
1456 | * Called with bnad->bna_lock held | |
1457 | */ | |
1458 | void | |
1459 | bnad_dim_timer_start(struct bnad *bnad) | |
1460 | { | |
1461 | if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED && | |
1462 | !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) { | |
1463 | setup_timer(&bnad->dim_timer, bnad_dim_timeout, | |
1464 | (unsigned long)bnad); | |
1465 | set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags); | |
1466 | mod_timer(&bnad->dim_timer, | |
1467 | jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ)); | |
1468 | } | |
1469 | } | |
1470 | ||
1471 | /* | |
1472 | * Set up timer for statistics | |
1473 | * Called with mutex_lock(&bnad->conf_mutex) held | |
1474 | */ | |
1475 | static void | |
1476 | bnad_stats_timer_start(struct bnad *bnad) | |
1477 | { | |
1478 | unsigned long flags; | |
1479 | ||
1480 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1481 | if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) { | |
1482 | setup_timer(&bnad->stats_timer, bnad_stats_timeout, | |
1483 | (unsigned long)bnad); | |
1484 | mod_timer(&bnad->stats_timer, | |
1485 | jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ)); | |
1486 | } | |
1487 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1488 | ||
1489 | } | |
1490 | ||
1491 | /* | |
1492 | * Stops the stats timer | |
1493 | * Called with mutex_lock(&bnad->conf_mutex) held | |
1494 | */ | |
1495 | static void | |
1496 | bnad_stats_timer_stop(struct bnad *bnad) | |
1497 | { | |
1498 | int to_del = 0; | |
1499 | unsigned long flags; | |
1500 | ||
1501 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1502 | if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) | |
1503 | to_del = 1; | |
1504 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1505 | if (to_del) | |
1506 | del_timer_sync(&bnad->stats_timer); | |
1507 | } | |
1508 | ||
1509 | /* Utilities */ | |
1510 | ||
1511 | static void | |
1512 | bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list) | |
1513 | { | |
1514 | int i = 1; /* Index 0 has broadcast address */ | |
1515 | struct netdev_hw_addr *mc_addr; | |
1516 | ||
1517 | netdev_for_each_mc_addr(mc_addr, netdev) { | |
1518 | memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0], | |
1519 | ETH_ALEN); | |
1520 | i++; | |
1521 | } | |
1522 | } | |
1523 | ||
1524 | static int | |
1525 | bnad_napi_poll_rx(struct napi_struct *napi, int budget) | |
1526 | { | |
1527 | struct bnad_rx_ctrl *rx_ctrl = | |
1528 | container_of(napi, struct bnad_rx_ctrl, napi); | |
1529 | struct bna_ccb *ccb; | |
1530 | struct bnad *bnad; | |
1531 | int rcvd = 0; | |
1532 | ||
1533 | ccb = rx_ctrl->ccb; | |
1534 | ||
1535 | bnad = ccb->bnad; | |
1536 | ||
1537 | if (!netif_carrier_ok(bnad->netdev)) | |
1538 | goto poll_exit; | |
1539 | ||
1540 | rcvd = bnad_poll_cq(bnad, ccb, budget); | |
1541 | if (rcvd == budget) | |
1542 | return rcvd; | |
1543 | ||
1544 | poll_exit: | |
1545 | napi_complete((napi)); | |
1546 | ||
1547 | BNAD_UPDATE_CTR(bnad, netif_rx_complete); | |
1548 | ||
1549 | bnad_enable_rx_irq(bnad, ccb); | |
1550 | return rcvd; | |
1551 | } | |
1552 | ||
1553 | static int | |
1554 | bnad_napi_poll_txrx(struct napi_struct *napi, int budget) | |
1555 | { | |
1556 | struct bnad_rx_ctrl *rx_ctrl = | |
1557 | container_of(napi, struct bnad_rx_ctrl, napi); | |
1558 | struct bna_ccb *ccb; | |
1559 | struct bnad *bnad; | |
1560 | int rcvd = 0; | |
1561 | int i, j; | |
1562 | ||
1563 | ccb = rx_ctrl->ccb; | |
1564 | ||
1565 | bnad = ccb->bnad; | |
1566 | ||
1567 | if (!netif_carrier_ok(bnad->netdev)) | |
1568 | goto poll_exit; | |
1569 | ||
1570 | /* Handle Tx Completions, if any */ | |
1571 | for (i = 0; i < bnad->num_tx; i++) { | |
1572 | for (j = 0; j < bnad->num_txq_per_tx; j++) | |
1573 | bnad_tx(bnad, bnad->tx_info[i].tcb[j]); | |
1574 | } | |
1575 | ||
1576 | /* Handle Rx Completions */ | |
1577 | rcvd = bnad_poll_cq(bnad, ccb, budget); | |
1578 | if (rcvd == budget) | |
1579 | return rcvd; | |
1580 | poll_exit: | |
1581 | napi_complete((napi)); | |
1582 | ||
1583 | BNAD_UPDATE_CTR(bnad, netif_rx_complete); | |
1584 | ||
1585 | bnad_enable_txrx_irqs(bnad); | |
1586 | return rcvd; | |
1587 | } | |
1588 | ||
1589 | static void | |
1590 | bnad_napi_enable(struct bnad *bnad, u32 rx_id) | |
1591 | { | |
1592 | int (*napi_poll) (struct napi_struct *, int); | |
1593 | struct bnad_rx_ctrl *rx_ctrl; | |
1594 | int i; | |
1595 | unsigned long flags; | |
1596 | ||
1597 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1598 | if (bnad->cfg_flags & BNAD_CF_MSIX) | |
1599 | napi_poll = bnad_napi_poll_rx; | |
1600 | else | |
1601 | napi_poll = bnad_napi_poll_txrx; | |
1602 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1603 | ||
1604 | /* Initialize & enable NAPI */ | |
1605 | for (i = 0; i < bnad->num_rxp_per_rx; i++) { | |
1606 | rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i]; | |
1607 | netif_napi_add(bnad->netdev, &rx_ctrl->napi, | |
1608 | napi_poll, 64); | |
1609 | napi_enable(&rx_ctrl->napi); | |
1610 | } | |
1611 | } | |
1612 | ||
1613 | static void | |
1614 | bnad_napi_disable(struct bnad *bnad, u32 rx_id) | |
1615 | { | |
1616 | int i; | |
1617 | ||
1618 | /* First disable and then clean up */ | |
1619 | for (i = 0; i < bnad->num_rxp_per_rx; i++) { | |
1620 | napi_disable(&bnad->rx_info[rx_id].rx_ctrl[i].napi); | |
1621 | netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi); | |
1622 | } | |
1623 | } | |
1624 | ||
1625 | /* Should be held with conf_lock held */ | |
1626 | void | |
1627 | bnad_cleanup_tx(struct bnad *bnad, uint tx_id) | |
1628 | { | |
1629 | struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id]; | |
1630 | struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0]; | |
1631 | unsigned long flags; | |
1632 | ||
1633 | if (!tx_info->tx) | |
1634 | return; | |
1635 | ||
1636 | init_completion(&bnad->bnad_completions.tx_comp); | |
1637 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1638 | bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled); | |
1639 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1640 | wait_for_completion(&bnad->bnad_completions.tx_comp); | |
1641 | ||
1642 | if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX) | |
1643 | bnad_tx_msix_unregister(bnad, tx_info, | |
1644 | bnad->num_txq_per_tx); | |
1645 | ||
1646 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1647 | bna_tx_destroy(tx_info->tx); | |
1648 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1649 | ||
1650 | tx_info->tx = NULL; | |
1651 | ||
1652 | if (0 == tx_id) | |
1653 | tasklet_kill(&bnad->tx_free_tasklet); | |
1654 | ||
1655 | bnad_tx_res_free(bnad, res_info); | |
1656 | } | |
1657 | ||
1658 | /* Should be held with conf_lock held */ | |
1659 | int | |
1660 | bnad_setup_tx(struct bnad *bnad, uint tx_id) | |
1661 | { | |
1662 | int err; | |
1663 | struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id]; | |
1664 | struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0]; | |
1665 | struct bna_intr_info *intr_info = | |
1666 | &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info; | |
1667 | struct bna_tx_config *tx_config = &bnad->tx_config[tx_id]; | |
1668 | struct bna_tx_event_cbfn tx_cbfn; | |
1669 | struct bna_tx *tx; | |
1670 | unsigned long flags; | |
1671 | ||
1672 | /* Initialize the Tx object configuration */ | |
1673 | tx_config->num_txq = bnad->num_txq_per_tx; | |
1674 | tx_config->txq_depth = bnad->txq_depth; | |
1675 | tx_config->tx_type = BNA_TX_T_REGULAR; | |
1676 | ||
1677 | /* Initialize the tx event handlers */ | |
1678 | tx_cbfn.tcb_setup_cbfn = bnad_cb_tcb_setup; | |
1679 | tx_cbfn.tcb_destroy_cbfn = bnad_cb_tcb_destroy; | |
1680 | tx_cbfn.tx_stall_cbfn = bnad_cb_tx_stall; | |
1681 | tx_cbfn.tx_resume_cbfn = bnad_cb_tx_resume; | |
1682 | tx_cbfn.tx_cleanup_cbfn = bnad_cb_tx_cleanup; | |
1683 | ||
1684 | /* Get BNA's resource requirement for one tx object */ | |
1685 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1686 | bna_tx_res_req(bnad->num_txq_per_tx, | |
1687 | bnad->txq_depth, res_info); | |
1688 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1689 | ||
1690 | /* Fill Unmap Q memory requirements */ | |
1691 | BNAD_FILL_UNMAPQ_MEM_REQ( | |
1692 | &res_info[BNA_TX_RES_MEM_T_UNMAPQ], | |
1693 | bnad->num_txq_per_tx, | |
1694 | BNAD_TX_UNMAPQ_DEPTH); | |
1695 | ||
1696 | /* Allocate resources */ | |
1697 | err = bnad_tx_res_alloc(bnad, res_info, tx_id); | |
1698 | if (err) | |
1699 | return err; | |
1700 | ||
1701 | /* Ask BNA to create one Tx object, supplying required resources */ | |
1702 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1703 | tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info, | |
1704 | tx_info); | |
1705 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1706 | if (!tx) | |
1707 | goto err_return; | |
1708 | tx_info->tx = tx; | |
1709 | ||
1710 | /* Register ISR for the Tx object */ | |
1711 | if (intr_info->intr_type == BNA_INTR_T_MSIX) { | |
1712 | err = bnad_tx_msix_register(bnad, tx_info, | |
1713 | tx_id, bnad->num_txq_per_tx); | |
1714 | if (err) | |
1715 | goto err_return; | |
1716 | } | |
1717 | ||
1718 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1719 | bna_tx_enable(tx); | |
1720 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1721 | ||
1722 | return 0; | |
1723 | ||
1724 | err_return: | |
1725 | bnad_tx_res_free(bnad, res_info); | |
1726 | return err; | |
1727 | } | |
1728 | ||
1729 | /* Setup the rx config for bna_rx_create */ | |
1730 | /* bnad decides the configuration */ | |
1731 | static void | |
1732 | bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config) | |
1733 | { | |
1734 | rx_config->rx_type = BNA_RX_T_REGULAR; | |
1735 | rx_config->num_paths = bnad->num_rxp_per_rx; | |
1736 | ||
1737 | if (bnad->num_rxp_per_rx > 1) { | |
1738 | rx_config->rss_status = BNA_STATUS_T_ENABLED; | |
1739 | rx_config->rss_config.hash_type = | |
1740 | (BFI_RSS_T_V4_TCP | | |
1741 | BFI_RSS_T_V6_TCP | | |
1742 | BFI_RSS_T_V4_IP | | |
1743 | BFI_RSS_T_V6_IP); | |
1744 | rx_config->rss_config.hash_mask = | |
1745 | bnad->num_rxp_per_rx - 1; | |
1746 | get_random_bytes(rx_config->rss_config.toeplitz_hash_key, | |
1747 | sizeof(rx_config->rss_config.toeplitz_hash_key)); | |
1748 | } else { | |
1749 | rx_config->rss_status = BNA_STATUS_T_DISABLED; | |
1750 | memset(&rx_config->rss_config, 0, | |
1751 | sizeof(rx_config->rss_config)); | |
1752 | } | |
1753 | rx_config->rxp_type = BNA_RXP_SLR; | |
1754 | rx_config->q_depth = bnad->rxq_depth; | |
1755 | ||
1756 | rx_config->small_buff_size = BFI_SMALL_RXBUF_SIZE; | |
1757 | ||
1758 | rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED; | |
1759 | } | |
1760 | ||
1761 | /* Called with mutex_lock(&bnad->conf_mutex) held */ | |
1762 | void | |
1763 | bnad_cleanup_rx(struct bnad *bnad, uint rx_id) | |
1764 | { | |
1765 | struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; | |
1766 | struct bna_rx_config *rx_config = &bnad->rx_config[rx_id]; | |
1767 | struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0]; | |
1768 | unsigned long flags; | |
1769 | int dim_timer_del = 0; | |
1770 | ||
1771 | if (!rx_info->rx) | |
1772 | return; | |
1773 | ||
1774 | if (0 == rx_id) { | |
1775 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1776 | dim_timer_del = bnad_dim_timer_running(bnad); | |
1777 | if (dim_timer_del) | |
1778 | clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags); | |
1779 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1780 | if (dim_timer_del) | |
1781 | del_timer_sync(&bnad->dim_timer); | |
1782 | } | |
1783 | ||
1784 | bnad_napi_disable(bnad, rx_id); | |
1785 | ||
1786 | init_completion(&bnad->bnad_completions.rx_comp); | |
1787 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1788 | bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled); | |
1789 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1790 | wait_for_completion(&bnad->bnad_completions.rx_comp); | |
1791 | ||
1792 | if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX) | |
1793 | bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths); | |
1794 | ||
1795 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1796 | bna_rx_destroy(rx_info->rx); | |
1797 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1798 | ||
1799 | rx_info->rx = NULL; | |
1800 | ||
1801 | bnad_rx_res_free(bnad, res_info); | |
1802 | } | |
1803 | ||
1804 | /* Called with mutex_lock(&bnad->conf_mutex) held */ | |
1805 | int | |
1806 | bnad_setup_rx(struct bnad *bnad, uint rx_id) | |
1807 | { | |
1808 | int err; | |
1809 | struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id]; | |
1810 | struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0]; | |
1811 | struct bna_intr_info *intr_info = | |
1812 | &res_info[BNA_RX_RES_T_INTR].res_u.intr_info; | |
1813 | struct bna_rx_config *rx_config = &bnad->rx_config[rx_id]; | |
1814 | struct bna_rx_event_cbfn rx_cbfn; | |
1815 | struct bna_rx *rx; | |
1816 | unsigned long flags; | |
1817 | ||
1818 | /* Initialize the Rx object configuration */ | |
1819 | bnad_init_rx_config(bnad, rx_config); | |
1820 | ||
1821 | /* Initialize the Rx event handlers */ | |
1822 | rx_cbfn.rcb_setup_cbfn = bnad_cb_rcb_setup; | |
1823 | rx_cbfn.rcb_destroy_cbfn = NULL; | |
1824 | rx_cbfn.ccb_setup_cbfn = bnad_cb_ccb_setup; | |
1825 | rx_cbfn.ccb_destroy_cbfn = bnad_cb_ccb_destroy; | |
1826 | rx_cbfn.rx_cleanup_cbfn = bnad_cb_rx_cleanup; | |
1827 | rx_cbfn.rx_post_cbfn = bnad_cb_rx_post; | |
1828 | ||
1829 | /* Get BNA's resource requirement for one Rx object */ | |
1830 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1831 | bna_rx_res_req(rx_config, res_info); | |
1832 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1833 | ||
1834 | /* Fill Unmap Q memory requirements */ | |
1835 | BNAD_FILL_UNMAPQ_MEM_REQ( | |
1836 | &res_info[BNA_RX_RES_MEM_T_UNMAPQ], | |
1837 | rx_config->num_paths + | |
1838 | ((rx_config->rxp_type == BNA_RXP_SINGLE) ? 0 : | |
1839 | rx_config->num_paths), BNAD_RX_UNMAPQ_DEPTH); | |
1840 | ||
1841 | /* Allocate resource */ | |
1842 | err = bnad_rx_res_alloc(bnad, res_info, rx_id); | |
1843 | if (err) | |
1844 | return err; | |
1845 | ||
1846 | /* Ask BNA to create one Rx object, supplying required resources */ | |
1847 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1848 | rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info, | |
1849 | rx_info); | |
1850 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1851 | if (!rx) | |
1852 | goto err_return; | |
1853 | rx_info->rx = rx; | |
1854 | ||
1855 | /* Register ISR for the Rx object */ | |
1856 | if (intr_info->intr_type == BNA_INTR_T_MSIX) { | |
1857 | err = bnad_rx_msix_register(bnad, rx_info, rx_id, | |
1858 | rx_config->num_paths); | |
1859 | if (err) | |
1860 | goto err_return; | |
1861 | } | |
1862 | ||
1863 | /* Enable NAPI */ | |
1864 | bnad_napi_enable(bnad, rx_id); | |
1865 | ||
1866 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1867 | if (0 == rx_id) { | |
1868 | /* Set up Dynamic Interrupt Moderation Vector */ | |
1869 | if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED) | |
1870 | bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector); | |
1871 | ||
1872 | /* Enable VLAN filtering only on the default Rx */ | |
1873 | bna_rx_vlanfilter_enable(rx); | |
1874 | ||
1875 | /* Start the DIM timer */ | |
1876 | bnad_dim_timer_start(bnad); | |
1877 | } | |
1878 | ||
1879 | bna_rx_enable(rx); | |
1880 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1881 | ||
1882 | return 0; | |
1883 | ||
1884 | err_return: | |
1885 | bnad_cleanup_rx(bnad, rx_id); | |
1886 | return err; | |
1887 | } | |
1888 | ||
1889 | /* Called with conf_lock & bnad->bna_lock held */ | |
1890 | void | |
1891 | bnad_tx_coalescing_timeo_set(struct bnad *bnad) | |
1892 | { | |
1893 | struct bnad_tx_info *tx_info; | |
1894 | ||
1895 | tx_info = &bnad->tx_info[0]; | |
1896 | if (!tx_info->tx) | |
1897 | return; | |
1898 | ||
1899 | bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo); | |
1900 | } | |
1901 | ||
1902 | /* Called with conf_lock & bnad->bna_lock held */ | |
1903 | void | |
1904 | bnad_rx_coalescing_timeo_set(struct bnad *bnad) | |
1905 | { | |
1906 | struct bnad_rx_info *rx_info; | |
1907 | int i; | |
1908 | ||
1909 | for (i = 0; i < bnad->num_rx; i++) { | |
1910 | rx_info = &bnad->rx_info[i]; | |
1911 | if (!rx_info->rx) | |
1912 | continue; | |
1913 | bna_rx_coalescing_timeo_set(rx_info->rx, | |
1914 | bnad->rx_coalescing_timeo); | |
1915 | } | |
1916 | } | |
1917 | ||
1918 | /* | |
1919 | * Called with bnad->bna_lock held | |
1920 | */ | |
1921 | static int | |
1922 | bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr) | |
1923 | { | |
1924 | int ret; | |
1925 | ||
1926 | if (!is_valid_ether_addr(mac_addr)) | |
1927 | return -EADDRNOTAVAIL; | |
1928 | ||
1929 | /* If datapath is down, pretend everything went through */ | |
1930 | if (!bnad->rx_info[0].rx) | |
1931 | return 0; | |
1932 | ||
1933 | ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL); | |
1934 | if (ret != BNA_CB_SUCCESS) | |
1935 | return -EADDRNOTAVAIL; | |
1936 | ||
1937 | return 0; | |
1938 | } | |
1939 | ||
1940 | /* Should be called with conf_lock held */ | |
1941 | static int | |
1942 | bnad_enable_default_bcast(struct bnad *bnad) | |
1943 | { | |
1944 | struct bnad_rx_info *rx_info = &bnad->rx_info[0]; | |
1945 | int ret; | |
1946 | unsigned long flags; | |
1947 | ||
1948 | init_completion(&bnad->bnad_completions.mcast_comp); | |
1949 | ||
1950 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
1951 | ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr, | |
1952 | bnad_cb_rx_mcast_add); | |
1953 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
1954 | ||
1955 | if (ret == BNA_CB_SUCCESS) | |
1956 | wait_for_completion(&bnad->bnad_completions.mcast_comp); | |
1957 | else | |
1958 | return -ENODEV; | |
1959 | ||
1960 | if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS) | |
1961 | return -ENODEV; | |
1962 | ||
1963 | return 0; | |
1964 | } | |
1965 | ||
1966 | /* Statistics utilities */ | |
1967 | void | |
250e061e | 1968 | bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats) |
8b230ed8 | 1969 | { |
8b230ed8 RM |
1970 | int i, j; |
1971 | ||
1972 | for (i = 0; i < bnad->num_rx; i++) { | |
1973 | for (j = 0; j < bnad->num_rxp_per_rx; j++) { | |
1974 | if (bnad->rx_info[i].rx_ctrl[j].ccb) { | |
250e061e | 1975 | stats->rx_packets += bnad->rx_info[i]. |
8b230ed8 | 1976 | rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets; |
250e061e | 1977 | stats->rx_bytes += bnad->rx_info[i]. |
8b230ed8 RM |
1978 | rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes; |
1979 | if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] && | |
1980 | bnad->rx_info[i].rx_ctrl[j].ccb-> | |
1981 | rcb[1]->rxq) { | |
250e061e | 1982 | stats->rx_packets += |
8b230ed8 RM |
1983 | bnad->rx_info[i].rx_ctrl[j]. |
1984 | ccb->rcb[1]->rxq->rx_packets; | |
250e061e | 1985 | stats->rx_bytes += |
8b230ed8 RM |
1986 | bnad->rx_info[i].rx_ctrl[j]. |
1987 | ccb->rcb[1]->rxq->rx_bytes; | |
1988 | } | |
1989 | } | |
1990 | } | |
1991 | } | |
1992 | for (i = 0; i < bnad->num_tx; i++) { | |
1993 | for (j = 0; j < bnad->num_txq_per_tx; j++) { | |
1994 | if (bnad->tx_info[i].tcb[j]) { | |
250e061e | 1995 | stats->tx_packets += |
8b230ed8 | 1996 | bnad->tx_info[i].tcb[j]->txq->tx_packets; |
250e061e | 1997 | stats->tx_bytes += |
8b230ed8 RM |
1998 | bnad->tx_info[i].tcb[j]->txq->tx_bytes; |
1999 | } | |
2000 | } | |
2001 | } | |
2002 | } | |
2003 | ||
2004 | /* | |
2005 | * Must be called with the bna_lock held. | |
2006 | */ | |
2007 | void | |
250e061e | 2008 | bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats) |
8b230ed8 RM |
2009 | { |
2010 | struct bfi_ll_stats_mac *mac_stats; | |
8b230ed8 RM |
2011 | u64 bmap; |
2012 | int i; | |
2013 | ||
2014 | mac_stats = &bnad->stats.bna_stats->hw_stats->mac_stats; | |
250e061e | 2015 | stats->rx_errors = |
8b230ed8 RM |
2016 | mac_stats->rx_fcs_error + mac_stats->rx_alignment_error + |
2017 | mac_stats->rx_frame_length_error + mac_stats->rx_code_error + | |
2018 | mac_stats->rx_undersize; | |
250e061e | 2019 | stats->tx_errors = mac_stats->tx_fcs_error + |
8b230ed8 | 2020 | mac_stats->tx_undersize; |
250e061e ED |
2021 | stats->rx_dropped = mac_stats->rx_drop; |
2022 | stats->tx_dropped = mac_stats->tx_drop; | |
2023 | stats->multicast = mac_stats->rx_multicast; | |
2024 | stats->collisions = mac_stats->tx_total_collision; | |
8b230ed8 | 2025 | |
250e061e | 2026 | stats->rx_length_errors = mac_stats->rx_frame_length_error; |
8b230ed8 RM |
2027 | |
2028 | /* receive ring buffer overflow ?? */ | |
2029 | ||
250e061e ED |
2030 | stats->rx_crc_errors = mac_stats->rx_fcs_error; |
2031 | stats->rx_frame_errors = mac_stats->rx_alignment_error; | |
8b230ed8 RM |
2032 | /* recv'r fifo overrun */ |
2033 | bmap = (u64)bnad->stats.bna_stats->rxf_bmap[0] | | |
2034 | ((u64)bnad->stats.bna_stats->rxf_bmap[1] << 32); | |
2035 | for (i = 0; bmap && (i < BFI_LL_RXF_ID_MAX); i++) { | |
2036 | if (bmap & 1) { | |
250e061e | 2037 | stats->rx_fifo_errors += |
8b230ed8 RM |
2038 | bnad->stats.bna_stats-> |
2039 | hw_stats->rxf_stats[i].frame_drops; | |
2040 | break; | |
2041 | } | |
2042 | bmap >>= 1; | |
2043 | } | |
2044 | } | |
2045 | ||
2046 | static void | |
2047 | bnad_mbox_irq_sync(struct bnad *bnad) | |
2048 | { | |
2049 | u32 irq; | |
2050 | unsigned long flags; | |
2051 | ||
2052 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2053 | if (bnad->cfg_flags & BNAD_CF_MSIX) | |
2054 | irq = bnad->msix_table[bnad->msix_num - 1].vector; | |
2055 | else | |
2056 | irq = bnad->pcidev->irq; | |
2057 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2058 | ||
2059 | synchronize_irq(irq); | |
2060 | } | |
2061 | ||
2062 | /* Utility used by bnad_start_xmit, for doing TSO */ | |
2063 | static int | |
2064 | bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb) | |
2065 | { | |
2066 | int err; | |
2067 | ||
2068 | /* SKB_GSO_TCPV4 and SKB_GSO_TCPV6 is defined since 2.6.18. */ | |
2069 | BUG_ON(!(skb_shinfo(skb)->gso_type == SKB_GSO_TCPV4 || | |
2070 | skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6)); | |
2071 | if (skb_header_cloned(skb)) { | |
2072 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
2073 | if (err) { | |
2074 | BNAD_UPDATE_CTR(bnad, tso_err); | |
2075 | return err; | |
2076 | } | |
2077 | } | |
2078 | ||
2079 | /* | |
2080 | * For TSO, the TCP checksum field is seeded with pseudo-header sum | |
2081 | * excluding the length field. | |
2082 | */ | |
2083 | if (skb->protocol == htons(ETH_P_IP)) { | |
2084 | struct iphdr *iph = ip_hdr(skb); | |
2085 | ||
2086 | /* Do we really need these? */ | |
2087 | iph->tot_len = 0; | |
2088 | iph->check = 0; | |
2089 | ||
2090 | tcp_hdr(skb)->check = | |
2091 | ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, | |
2092 | IPPROTO_TCP, 0); | |
2093 | BNAD_UPDATE_CTR(bnad, tso4); | |
2094 | } else { | |
2095 | struct ipv6hdr *ipv6h = ipv6_hdr(skb); | |
2096 | ||
2097 | BUG_ON(!(skb->protocol == htons(ETH_P_IPV6))); | |
2098 | ipv6h->payload_len = 0; | |
2099 | tcp_hdr(skb)->check = | |
2100 | ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0, | |
2101 | IPPROTO_TCP, 0); | |
2102 | BNAD_UPDATE_CTR(bnad, tso6); | |
2103 | } | |
2104 | ||
2105 | return 0; | |
2106 | } | |
2107 | ||
2108 | /* | |
2109 | * Initialize Q numbers depending on Rx Paths | |
2110 | * Called with bnad->bna_lock held, because of cfg_flags | |
2111 | * access. | |
2112 | */ | |
2113 | static void | |
2114 | bnad_q_num_init(struct bnad *bnad) | |
2115 | { | |
2116 | int rxps; | |
2117 | ||
2118 | rxps = min((uint)num_online_cpus(), | |
2119 | (uint)(BNAD_MAX_RXS * BNAD_MAX_RXPS_PER_RX)); | |
2120 | ||
2121 | if (!(bnad->cfg_flags & BNAD_CF_MSIX)) | |
2122 | rxps = 1; /* INTx */ | |
2123 | ||
2124 | bnad->num_rx = 1; | |
2125 | bnad->num_tx = 1; | |
2126 | bnad->num_rxp_per_rx = rxps; | |
2127 | bnad->num_txq_per_tx = BNAD_TXQ_NUM; | |
2128 | } | |
2129 | ||
2130 | /* | |
2131 | * Adjusts the Q numbers, given a number of msix vectors | |
2132 | * Give preference to RSS as opposed to Tx priority Queues, | |
2133 | * in such a case, just use 1 Tx Q | |
2134 | * Called with bnad->bna_lock held b'cos of cfg_flags access | |
2135 | */ | |
2136 | static void | |
2137 | bnad_q_num_adjust(struct bnad *bnad, int msix_vectors) | |
2138 | { | |
2139 | bnad->num_txq_per_tx = 1; | |
2140 | if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) + | |
2141 | bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) && | |
2142 | (bnad->cfg_flags & BNAD_CF_MSIX)) { | |
2143 | bnad->num_rxp_per_rx = msix_vectors - | |
2144 | (bnad->num_tx * bnad->num_txq_per_tx) - | |
2145 | BNAD_MAILBOX_MSIX_VECTORS; | |
2146 | } else | |
2147 | bnad->num_rxp_per_rx = 1; | |
2148 | } | |
2149 | ||
2150 | static void | |
2151 | bnad_set_netdev_perm_addr(struct bnad *bnad) | |
2152 | { | |
2153 | struct net_device *netdev = bnad->netdev; | |
2154 | ||
2155 | memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len); | |
2156 | if (is_zero_ether_addr(netdev->dev_addr)) | |
2157 | memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len); | |
2158 | } | |
2159 | ||
2160 | /* Enable / disable device */ | |
2161 | static void | |
2162 | bnad_device_disable(struct bnad *bnad) | |
2163 | { | |
2164 | unsigned long flags; | |
2165 | ||
2166 | init_completion(&bnad->bnad_completions.ioc_comp); | |
2167 | ||
2168 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2169 | bna_device_disable(&bnad->bna.device, BNA_HARD_CLEANUP); | |
2170 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2171 | ||
2172 | wait_for_completion(&bnad->bnad_completions.ioc_comp); | |
2173 | ||
2174 | } | |
2175 | ||
2176 | static int | |
2177 | bnad_device_enable(struct bnad *bnad) | |
2178 | { | |
2179 | int err = 0; | |
2180 | unsigned long flags; | |
2181 | ||
2182 | init_completion(&bnad->bnad_completions.ioc_comp); | |
2183 | ||
2184 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2185 | bna_device_enable(&bnad->bna.device); | |
2186 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2187 | ||
2188 | wait_for_completion(&bnad->bnad_completions.ioc_comp); | |
2189 | ||
2190 | if (bnad->bnad_completions.ioc_comp_status) | |
2191 | err = bnad->bnad_completions.ioc_comp_status; | |
2192 | ||
2193 | return err; | |
2194 | } | |
2195 | ||
2196 | /* Free BNA resources */ | |
2197 | static void | |
2198 | bnad_res_free(struct bnad *bnad) | |
2199 | { | |
2200 | int i; | |
2201 | struct bna_res_info *res_info = &bnad->res_info[0]; | |
2202 | ||
2203 | for (i = 0; i < BNA_RES_T_MAX; i++) { | |
2204 | if (res_info[i].res_type == BNA_RES_T_MEM) | |
2205 | bnad_mem_free(bnad, &res_info[i].res_u.mem_info); | |
2206 | else | |
2207 | bnad_mbox_irq_free(bnad, &res_info[i].res_u.intr_info); | |
2208 | } | |
2209 | } | |
2210 | ||
2211 | /* Allocates memory and interrupt resources for BNA */ | |
2212 | static int | |
2213 | bnad_res_alloc(struct bnad *bnad) | |
2214 | { | |
2215 | int i, err; | |
2216 | struct bna_res_info *res_info = &bnad->res_info[0]; | |
2217 | ||
2218 | for (i = 0; i < BNA_RES_T_MAX; i++) { | |
2219 | if (res_info[i].res_type == BNA_RES_T_MEM) | |
2220 | err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info); | |
2221 | else | |
2222 | err = bnad_mbox_irq_alloc(bnad, | |
2223 | &res_info[i].res_u.intr_info); | |
2224 | if (err) | |
2225 | goto err_return; | |
2226 | } | |
2227 | return 0; | |
2228 | ||
2229 | err_return: | |
2230 | bnad_res_free(bnad); | |
2231 | return err; | |
2232 | } | |
2233 | ||
2234 | /* Interrupt enable / disable */ | |
2235 | static void | |
2236 | bnad_enable_msix(struct bnad *bnad) | |
2237 | { | |
2238 | int i, ret; | |
2239 | u32 tot_msix_num; | |
2240 | unsigned long flags; | |
2241 | ||
2242 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2243 | if (!(bnad->cfg_flags & BNAD_CF_MSIX)) { | |
2244 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2245 | return; | |
2246 | } | |
2247 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2248 | ||
2249 | if (bnad->msix_table) | |
2250 | return; | |
2251 | ||
2252 | tot_msix_num = bnad->msix_num + bnad->msix_diag_num; | |
2253 | ||
2254 | bnad->msix_table = | |
2255 | kcalloc(tot_msix_num, sizeof(struct msix_entry), GFP_KERNEL); | |
2256 | ||
2257 | if (!bnad->msix_table) | |
2258 | goto intx_mode; | |
2259 | ||
2260 | for (i = 0; i < tot_msix_num; i++) | |
2261 | bnad->msix_table[i].entry = i; | |
2262 | ||
2263 | ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, tot_msix_num); | |
2264 | if (ret > 0) { | |
2265 | /* Not enough MSI-X vectors. */ | |
2266 | ||
2267 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2268 | /* ret = #of vectors that we got */ | |
2269 | bnad_q_num_adjust(bnad, ret); | |
2270 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2271 | ||
2272 | bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) | |
2273 | + (bnad->num_rx | |
2274 | * bnad->num_rxp_per_rx) + | |
2275 | BNAD_MAILBOX_MSIX_VECTORS; | |
2276 | tot_msix_num = bnad->msix_num + bnad->msix_diag_num; | |
2277 | ||
2278 | /* Try once more with adjusted numbers */ | |
2279 | /* If this fails, fall back to INTx */ | |
2280 | ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, | |
2281 | tot_msix_num); | |
2282 | if (ret) | |
2283 | goto intx_mode; | |
2284 | ||
2285 | } else if (ret < 0) | |
2286 | goto intx_mode; | |
2287 | return; | |
2288 | ||
2289 | intx_mode: | |
2290 | ||
2291 | kfree(bnad->msix_table); | |
2292 | bnad->msix_table = NULL; | |
2293 | bnad->msix_num = 0; | |
2294 | bnad->msix_diag_num = 0; | |
2295 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2296 | bnad->cfg_flags &= ~BNAD_CF_MSIX; | |
2297 | bnad_q_num_init(bnad); | |
2298 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2299 | } | |
2300 | ||
2301 | static void | |
2302 | bnad_disable_msix(struct bnad *bnad) | |
2303 | { | |
2304 | u32 cfg_flags; | |
2305 | unsigned long flags; | |
2306 | ||
2307 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2308 | cfg_flags = bnad->cfg_flags; | |
2309 | if (bnad->cfg_flags & BNAD_CF_MSIX) | |
2310 | bnad->cfg_flags &= ~BNAD_CF_MSIX; | |
2311 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2312 | ||
2313 | if (cfg_flags & BNAD_CF_MSIX) { | |
2314 | pci_disable_msix(bnad->pcidev); | |
2315 | kfree(bnad->msix_table); | |
2316 | bnad->msix_table = NULL; | |
2317 | } | |
2318 | } | |
2319 | ||
2320 | /* Netdev entry points */ | |
2321 | static int | |
2322 | bnad_open(struct net_device *netdev) | |
2323 | { | |
2324 | int err; | |
2325 | struct bnad *bnad = netdev_priv(netdev); | |
2326 | struct bna_pause_config pause_config; | |
2327 | int mtu; | |
2328 | unsigned long flags; | |
2329 | ||
2330 | mutex_lock(&bnad->conf_mutex); | |
2331 | ||
2332 | /* Tx */ | |
2333 | err = bnad_setup_tx(bnad, 0); | |
2334 | if (err) | |
2335 | goto err_return; | |
2336 | ||
2337 | /* Rx */ | |
2338 | err = bnad_setup_rx(bnad, 0); | |
2339 | if (err) | |
2340 | goto cleanup_tx; | |
2341 | ||
2342 | /* Port */ | |
2343 | pause_config.tx_pause = 0; | |
2344 | pause_config.rx_pause = 0; | |
2345 | ||
2346 | mtu = ETH_HLEN + bnad->netdev->mtu + ETH_FCS_LEN; | |
2347 | ||
2348 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2349 | bna_port_mtu_set(&bnad->bna.port, mtu, NULL); | |
2350 | bna_port_pause_config(&bnad->bna.port, &pause_config, NULL); | |
2351 | bna_port_enable(&bnad->bna.port); | |
2352 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2353 | ||
2354 | /* Enable broadcast */ | |
2355 | bnad_enable_default_bcast(bnad); | |
2356 | ||
2357 | /* Set the UCAST address */ | |
2358 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2359 | bnad_mac_addr_set_locked(bnad, netdev->dev_addr); | |
2360 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2361 | ||
2362 | /* Start the stats timer */ | |
2363 | bnad_stats_timer_start(bnad); | |
2364 | ||
2365 | mutex_unlock(&bnad->conf_mutex); | |
2366 | ||
2367 | return 0; | |
2368 | ||
2369 | cleanup_tx: | |
2370 | bnad_cleanup_tx(bnad, 0); | |
2371 | ||
2372 | err_return: | |
2373 | mutex_unlock(&bnad->conf_mutex); | |
2374 | return err; | |
2375 | } | |
2376 | ||
2377 | static int | |
2378 | bnad_stop(struct net_device *netdev) | |
2379 | { | |
2380 | struct bnad *bnad = netdev_priv(netdev); | |
2381 | unsigned long flags; | |
2382 | ||
2383 | mutex_lock(&bnad->conf_mutex); | |
2384 | ||
2385 | /* Stop the stats timer */ | |
2386 | bnad_stats_timer_stop(bnad); | |
2387 | ||
2388 | init_completion(&bnad->bnad_completions.port_comp); | |
2389 | ||
2390 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2391 | bna_port_disable(&bnad->bna.port, BNA_HARD_CLEANUP, | |
2392 | bnad_cb_port_disabled); | |
2393 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2394 | ||
2395 | wait_for_completion(&bnad->bnad_completions.port_comp); | |
2396 | ||
2397 | bnad_cleanup_tx(bnad, 0); | |
2398 | bnad_cleanup_rx(bnad, 0); | |
2399 | ||
2400 | /* Synchronize mailbox IRQ */ | |
2401 | bnad_mbox_irq_sync(bnad); | |
2402 | ||
2403 | mutex_unlock(&bnad->conf_mutex); | |
2404 | ||
2405 | return 0; | |
2406 | } | |
2407 | ||
2408 | /* TX */ | |
2409 | /* | |
2410 | * bnad_start_xmit : Netdev entry point for Transmit | |
2411 | * Called under lock held by net_device | |
2412 | */ | |
2413 | static netdev_tx_t | |
2414 | bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev) | |
2415 | { | |
2416 | struct bnad *bnad = netdev_priv(netdev); | |
2417 | ||
2418 | u16 txq_prod, vlan_tag = 0; | |
2419 | u32 unmap_prod, wis, wis_used, wi_range; | |
2420 | u32 vectors, vect_id, i, acked; | |
2421 | u32 tx_id; | |
2422 | int err; | |
2423 | ||
2424 | struct bnad_tx_info *tx_info; | |
2425 | struct bna_tcb *tcb; | |
2426 | struct bnad_unmap_q *unmap_q; | |
2427 | dma_addr_t dma_addr; | |
2428 | struct bna_txq_entry *txqent; | |
2429 | bna_txq_wi_ctrl_flag_t flags; | |
2430 | ||
2431 | if (unlikely | |
2432 | (skb->len <= ETH_HLEN || skb->len > BFI_TX_MAX_DATA_PER_PKT)) { | |
2433 | dev_kfree_skb(skb); | |
2434 | return NETDEV_TX_OK; | |
2435 | } | |
2436 | ||
2437 | /* | |
2438 | * Takes care of the Tx that is scheduled between clearing the flag | |
2439 | * and the netif_stop_queue() call. | |
2440 | */ | |
2441 | if (unlikely(!test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags))) { | |
2442 | dev_kfree_skb(skb); | |
2443 | return NETDEV_TX_OK; | |
2444 | } | |
2445 | ||
2446 | tx_id = 0; | |
2447 | ||
2448 | tx_info = &bnad->tx_info[tx_id]; | |
2449 | tcb = tx_info->tcb[tx_id]; | |
2450 | unmap_q = tcb->unmap_q; | |
2451 | ||
2452 | vectors = 1 + skb_shinfo(skb)->nr_frags; | |
2453 | if (vectors > BFI_TX_MAX_VECTORS_PER_PKT) { | |
2454 | dev_kfree_skb(skb); | |
2455 | return NETDEV_TX_OK; | |
2456 | } | |
2457 | wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */ | |
2458 | acked = 0; | |
2459 | if (unlikely | |
2460 | (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) || | |
2461 | vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) { | |
2462 | if ((u16) (*tcb->hw_consumer_index) != | |
2463 | tcb->consumer_index && | |
2464 | !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) { | |
2465 | acked = bnad_free_txbufs(bnad, tcb); | |
2466 | bna_ib_ack(tcb->i_dbell, acked); | |
2467 | smp_mb__before_clear_bit(); | |
2468 | clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags); | |
2469 | } else { | |
2470 | netif_stop_queue(netdev); | |
2471 | BNAD_UPDATE_CTR(bnad, netif_queue_stop); | |
2472 | } | |
2473 | ||
2474 | smp_mb(); | |
2475 | /* | |
2476 | * Check again to deal with race condition between | |
2477 | * netif_stop_queue here, and netif_wake_queue in | |
2478 | * interrupt handler which is not inside netif tx lock. | |
2479 | */ | |
2480 | if (likely | |
2481 | (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) || | |
2482 | vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) { | |
2483 | BNAD_UPDATE_CTR(bnad, netif_queue_stop); | |
2484 | return NETDEV_TX_BUSY; | |
2485 | } else { | |
2486 | netif_wake_queue(netdev); | |
2487 | BNAD_UPDATE_CTR(bnad, netif_queue_wakeup); | |
2488 | } | |
2489 | } | |
2490 | ||
2491 | unmap_prod = unmap_q->producer_index; | |
2492 | wis_used = 1; | |
2493 | vect_id = 0; | |
2494 | flags = 0; | |
2495 | ||
2496 | txq_prod = tcb->producer_index; | |
2497 | BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt, txqent, wi_range); | |
2498 | BUG_ON(!(wi_range <= tcb->q_depth)); | |
2499 | txqent->hdr.wi.reserved = 0; | |
2500 | txqent->hdr.wi.num_vectors = vectors; | |
2501 | txqent->hdr.wi.opcode = | |
2502 | htons((skb_is_gso(skb) ? BNA_TXQ_WI_SEND_LSO : | |
2503 | BNA_TXQ_WI_SEND)); | |
2504 | ||
2505 | if (bnad->vlan_grp && vlan_tx_tag_present(skb)) { | |
2506 | vlan_tag = (u16) vlan_tx_tag_get(skb); | |
2507 | flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN); | |
2508 | } | |
2509 | if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) { | |
2510 | vlan_tag = | |
2511 | (tcb->priority & 0x7) << 13 | (vlan_tag & 0x1fff); | |
2512 | flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN); | |
2513 | } | |
2514 | ||
2515 | txqent->hdr.wi.vlan_tag = htons(vlan_tag); | |
2516 | ||
2517 | if (skb_is_gso(skb)) { | |
2518 | err = bnad_tso_prepare(bnad, skb); | |
2519 | if (err) { | |
2520 | dev_kfree_skb(skb); | |
2521 | return NETDEV_TX_OK; | |
2522 | } | |
2523 | txqent->hdr.wi.lso_mss = htons(skb_is_gso(skb)); | |
2524 | flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM); | |
2525 | txqent->hdr.wi.l4_hdr_size_n_offset = | |
2526 | htons(BNA_TXQ_WI_L4_HDR_N_OFFSET | |
2527 | (tcp_hdrlen(skb) >> 2, | |
2528 | skb_transport_offset(skb))); | |
2529 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
2530 | u8 proto = 0; | |
2531 | ||
2532 | txqent->hdr.wi.lso_mss = 0; | |
2533 | ||
2534 | if (skb->protocol == htons(ETH_P_IP)) | |
2535 | proto = ip_hdr(skb)->protocol; | |
2536 | else if (skb->protocol == htons(ETH_P_IPV6)) { | |
2537 | /* nexthdr may not be TCP immediately. */ | |
2538 | proto = ipv6_hdr(skb)->nexthdr; | |
2539 | } | |
2540 | if (proto == IPPROTO_TCP) { | |
2541 | flags |= BNA_TXQ_WI_CF_TCP_CKSUM; | |
2542 | txqent->hdr.wi.l4_hdr_size_n_offset = | |
2543 | htons(BNA_TXQ_WI_L4_HDR_N_OFFSET | |
2544 | (0, skb_transport_offset(skb))); | |
2545 | ||
2546 | BNAD_UPDATE_CTR(bnad, tcpcsum_offload); | |
2547 | ||
2548 | BUG_ON(!(skb_headlen(skb) >= | |
2549 | skb_transport_offset(skb) + tcp_hdrlen(skb))); | |
2550 | ||
2551 | } else if (proto == IPPROTO_UDP) { | |
2552 | flags |= BNA_TXQ_WI_CF_UDP_CKSUM; | |
2553 | txqent->hdr.wi.l4_hdr_size_n_offset = | |
2554 | htons(BNA_TXQ_WI_L4_HDR_N_OFFSET | |
2555 | (0, skb_transport_offset(skb))); | |
2556 | ||
2557 | BNAD_UPDATE_CTR(bnad, udpcsum_offload); | |
2558 | ||
2559 | BUG_ON(!(skb_headlen(skb) >= | |
2560 | skb_transport_offset(skb) + | |
2561 | sizeof(struct udphdr))); | |
2562 | } else { | |
2563 | err = skb_checksum_help(skb); | |
2564 | BNAD_UPDATE_CTR(bnad, csum_help); | |
2565 | if (err) { | |
2566 | dev_kfree_skb(skb); | |
2567 | BNAD_UPDATE_CTR(bnad, csum_help_err); | |
2568 | return NETDEV_TX_OK; | |
2569 | } | |
2570 | } | |
2571 | } else { | |
2572 | txqent->hdr.wi.lso_mss = 0; | |
2573 | txqent->hdr.wi.l4_hdr_size_n_offset = 0; | |
2574 | } | |
2575 | ||
2576 | txqent->hdr.wi.flags = htons(flags); | |
2577 | ||
2578 | txqent->hdr.wi.frame_length = htonl(skb->len); | |
2579 | ||
2580 | unmap_q->unmap_array[unmap_prod].skb = skb; | |
2581 | BUG_ON(!(skb_headlen(skb) <= BFI_TX_MAX_DATA_PER_VECTOR)); | |
2582 | txqent->vector[vect_id].length = htons(skb_headlen(skb)); | |
2583 | dma_addr = pci_map_single(bnad->pcidev, skb->data, skb_headlen(skb), | |
2584 | PCI_DMA_TODEVICE); | |
2585 | pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr, | |
2586 | dma_addr); | |
2587 | ||
2588 | BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr); | |
2589 | BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth); | |
2590 | ||
2591 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
2592 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; | |
2593 | u32 size = frag->size; | |
2594 | ||
2595 | if (++vect_id == BFI_TX_MAX_VECTORS_PER_WI) { | |
2596 | vect_id = 0; | |
2597 | if (--wi_range) | |
2598 | txqent++; | |
2599 | else { | |
2600 | BNA_QE_INDX_ADD(txq_prod, wis_used, | |
2601 | tcb->q_depth); | |
2602 | wis_used = 0; | |
2603 | BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt, | |
2604 | txqent, wi_range); | |
2605 | BUG_ON(!(wi_range <= tcb->q_depth)); | |
2606 | } | |
2607 | wis_used++; | |
2608 | txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION); | |
2609 | } | |
2610 | ||
2611 | BUG_ON(!(size <= BFI_TX_MAX_DATA_PER_VECTOR)); | |
2612 | txqent->vector[vect_id].length = htons(size); | |
2613 | dma_addr = | |
2614 | pci_map_page(bnad->pcidev, frag->page, | |
2615 | frag->page_offset, size, | |
2616 | PCI_DMA_TODEVICE); | |
2617 | pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr, | |
2618 | dma_addr); | |
2619 | BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr); | |
2620 | BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth); | |
2621 | } | |
2622 | ||
2623 | unmap_q->producer_index = unmap_prod; | |
2624 | BNA_QE_INDX_ADD(txq_prod, wis_used, tcb->q_depth); | |
2625 | tcb->producer_index = txq_prod; | |
2626 | ||
2627 | smp_mb(); | |
2628 | bna_txq_prod_indx_doorbell(tcb); | |
2629 | ||
2630 | if ((u16) (*tcb->hw_consumer_index) != tcb->consumer_index) | |
2631 | tasklet_schedule(&bnad->tx_free_tasklet); | |
2632 | ||
2633 | return NETDEV_TX_OK; | |
2634 | } | |
2635 | ||
2636 | /* | |
2637 | * Used spin_lock to synchronize reading of stats structures, which | |
2638 | * is written by BNA under the same lock. | |
2639 | */ | |
250e061e ED |
2640 | static struct rtnl_link_stats64 * |
2641 | bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats) | |
8b230ed8 RM |
2642 | { |
2643 | struct bnad *bnad = netdev_priv(netdev); | |
2644 | unsigned long flags; | |
2645 | ||
2646 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2647 | ||
250e061e ED |
2648 | bnad_netdev_qstats_fill(bnad, stats); |
2649 | bnad_netdev_hwstats_fill(bnad, stats); | |
8b230ed8 RM |
2650 | |
2651 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2652 | ||
250e061e | 2653 | return stats; |
8b230ed8 RM |
2654 | } |
2655 | ||
2656 | static void | |
2657 | bnad_set_rx_mode(struct net_device *netdev) | |
2658 | { | |
2659 | struct bnad *bnad = netdev_priv(netdev); | |
2660 | u32 new_mask, valid_mask; | |
2661 | unsigned long flags; | |
2662 | ||
2663 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2664 | ||
2665 | new_mask = valid_mask = 0; | |
2666 | ||
2667 | if (netdev->flags & IFF_PROMISC) { | |
2668 | if (!(bnad->cfg_flags & BNAD_CF_PROMISC)) { | |
2669 | new_mask = BNAD_RXMODE_PROMISC_DEFAULT; | |
2670 | valid_mask = BNAD_RXMODE_PROMISC_DEFAULT; | |
2671 | bnad->cfg_flags |= BNAD_CF_PROMISC; | |
2672 | } | |
2673 | } else { | |
2674 | if (bnad->cfg_flags & BNAD_CF_PROMISC) { | |
2675 | new_mask = ~BNAD_RXMODE_PROMISC_DEFAULT; | |
2676 | valid_mask = BNAD_RXMODE_PROMISC_DEFAULT; | |
2677 | bnad->cfg_flags &= ~BNAD_CF_PROMISC; | |
2678 | } | |
2679 | } | |
2680 | ||
2681 | if (netdev->flags & IFF_ALLMULTI) { | |
2682 | if (!(bnad->cfg_flags & BNAD_CF_ALLMULTI)) { | |
2683 | new_mask |= BNA_RXMODE_ALLMULTI; | |
2684 | valid_mask |= BNA_RXMODE_ALLMULTI; | |
2685 | bnad->cfg_flags |= BNAD_CF_ALLMULTI; | |
2686 | } | |
2687 | } else { | |
2688 | if (bnad->cfg_flags & BNAD_CF_ALLMULTI) { | |
2689 | new_mask &= ~BNA_RXMODE_ALLMULTI; | |
2690 | valid_mask |= BNA_RXMODE_ALLMULTI; | |
2691 | bnad->cfg_flags &= ~BNAD_CF_ALLMULTI; | |
2692 | } | |
2693 | } | |
2694 | ||
2695 | bna_rx_mode_set(bnad->rx_info[0].rx, new_mask, valid_mask, NULL); | |
2696 | ||
2697 | if (!netdev_mc_empty(netdev)) { | |
2698 | u8 *mcaddr_list; | |
2699 | int mc_count = netdev_mc_count(netdev); | |
2700 | ||
2701 | /* Index 0 holds the broadcast address */ | |
2702 | mcaddr_list = | |
2703 | kzalloc((mc_count + 1) * ETH_ALEN, | |
2704 | GFP_ATOMIC); | |
2705 | if (!mcaddr_list) | |
ca1cef3a | 2706 | goto unlock; |
8b230ed8 RM |
2707 | |
2708 | memcpy(&mcaddr_list[0], &bnad_bcast_addr[0], ETH_ALEN); | |
2709 | ||
2710 | /* Copy rest of the MC addresses */ | |
2711 | bnad_netdev_mc_list_get(netdev, mcaddr_list); | |
2712 | ||
2713 | bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1, | |
2714 | mcaddr_list, NULL); | |
2715 | ||
2716 | /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */ | |
2717 | kfree(mcaddr_list); | |
2718 | } | |
ca1cef3a | 2719 | unlock: |
8b230ed8 RM |
2720 | spin_unlock_irqrestore(&bnad->bna_lock, flags); |
2721 | } | |
2722 | ||
2723 | /* | |
2724 | * bna_lock is used to sync writes to netdev->addr | |
2725 | * conf_lock cannot be used since this call may be made | |
2726 | * in a non-blocking context. | |
2727 | */ | |
2728 | static int | |
2729 | bnad_set_mac_address(struct net_device *netdev, void *mac_addr) | |
2730 | { | |
2731 | int err; | |
2732 | struct bnad *bnad = netdev_priv(netdev); | |
2733 | struct sockaddr *sa = (struct sockaddr *)mac_addr; | |
2734 | unsigned long flags; | |
2735 | ||
2736 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2737 | ||
2738 | err = bnad_mac_addr_set_locked(bnad, sa->sa_data); | |
2739 | ||
2740 | if (!err) | |
2741 | memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len); | |
2742 | ||
2743 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2744 | ||
2745 | return err; | |
2746 | } | |
2747 | ||
2748 | static int | |
2749 | bnad_change_mtu(struct net_device *netdev, int new_mtu) | |
2750 | { | |
2751 | int mtu, err = 0; | |
2752 | unsigned long flags; | |
2753 | ||
2754 | struct bnad *bnad = netdev_priv(netdev); | |
2755 | ||
2756 | if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU) | |
2757 | return -EINVAL; | |
2758 | ||
2759 | mutex_lock(&bnad->conf_mutex); | |
2760 | ||
2761 | netdev->mtu = new_mtu; | |
2762 | ||
2763 | mtu = ETH_HLEN + new_mtu + ETH_FCS_LEN; | |
2764 | ||
2765 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2766 | bna_port_mtu_set(&bnad->bna.port, mtu, NULL); | |
2767 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2768 | ||
2769 | mutex_unlock(&bnad->conf_mutex); | |
2770 | return err; | |
2771 | } | |
2772 | ||
2773 | static void | |
2774 | bnad_vlan_rx_register(struct net_device *netdev, | |
2775 | struct vlan_group *vlan_grp) | |
2776 | { | |
2777 | struct bnad *bnad = netdev_priv(netdev); | |
2778 | ||
2779 | mutex_lock(&bnad->conf_mutex); | |
2780 | bnad->vlan_grp = vlan_grp; | |
2781 | mutex_unlock(&bnad->conf_mutex); | |
2782 | } | |
2783 | ||
2784 | static void | |
2785 | bnad_vlan_rx_add_vid(struct net_device *netdev, | |
2786 | unsigned short vid) | |
2787 | { | |
2788 | struct bnad *bnad = netdev_priv(netdev); | |
2789 | unsigned long flags; | |
2790 | ||
2791 | if (!bnad->rx_info[0].rx) | |
2792 | return; | |
2793 | ||
2794 | mutex_lock(&bnad->conf_mutex); | |
2795 | ||
2796 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2797 | bna_rx_vlan_add(bnad->rx_info[0].rx, vid); | |
2798 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2799 | ||
2800 | mutex_unlock(&bnad->conf_mutex); | |
2801 | } | |
2802 | ||
2803 | static void | |
2804 | bnad_vlan_rx_kill_vid(struct net_device *netdev, | |
2805 | unsigned short vid) | |
2806 | { | |
2807 | struct bnad *bnad = netdev_priv(netdev); | |
2808 | unsigned long flags; | |
2809 | ||
2810 | if (!bnad->rx_info[0].rx) | |
2811 | return; | |
2812 | ||
2813 | mutex_lock(&bnad->conf_mutex); | |
2814 | ||
2815 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2816 | bna_rx_vlan_del(bnad->rx_info[0].rx, vid); | |
2817 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2818 | ||
2819 | mutex_unlock(&bnad->conf_mutex); | |
2820 | } | |
2821 | ||
2822 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2823 | static void | |
2824 | bnad_netpoll(struct net_device *netdev) | |
2825 | { | |
2826 | struct bnad *bnad = netdev_priv(netdev); | |
2827 | struct bnad_rx_info *rx_info; | |
2828 | struct bnad_rx_ctrl *rx_ctrl; | |
2829 | u32 curr_mask; | |
2830 | int i, j; | |
2831 | ||
2832 | if (!(bnad->cfg_flags & BNAD_CF_MSIX)) { | |
2833 | bna_intx_disable(&bnad->bna, curr_mask); | |
2834 | bnad_isr(bnad->pcidev->irq, netdev); | |
2835 | bna_intx_enable(&bnad->bna, curr_mask); | |
2836 | } else { | |
2837 | for (i = 0; i < bnad->num_rx; i++) { | |
2838 | rx_info = &bnad->rx_info[i]; | |
2839 | if (!rx_info->rx) | |
2840 | continue; | |
2841 | for (j = 0; j < bnad->num_rxp_per_rx; j++) { | |
2842 | rx_ctrl = &rx_info->rx_ctrl[j]; | |
2843 | if (rx_ctrl->ccb) { | |
2844 | bnad_disable_rx_irq(bnad, | |
2845 | rx_ctrl->ccb); | |
2846 | bnad_netif_rx_schedule_poll(bnad, | |
2847 | rx_ctrl->ccb); | |
2848 | } | |
2849 | } | |
2850 | } | |
2851 | } | |
2852 | } | |
2853 | #endif | |
2854 | ||
2855 | static const struct net_device_ops bnad_netdev_ops = { | |
2856 | .ndo_open = bnad_open, | |
2857 | .ndo_stop = bnad_stop, | |
2858 | .ndo_start_xmit = bnad_start_xmit, | |
250e061e | 2859 | .ndo_get_stats64 = bnad_get_stats64, |
8b230ed8 RM |
2860 | .ndo_set_rx_mode = bnad_set_rx_mode, |
2861 | .ndo_set_multicast_list = bnad_set_rx_mode, | |
2862 | .ndo_validate_addr = eth_validate_addr, | |
2863 | .ndo_set_mac_address = bnad_set_mac_address, | |
2864 | .ndo_change_mtu = bnad_change_mtu, | |
2865 | .ndo_vlan_rx_register = bnad_vlan_rx_register, | |
2866 | .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid, | |
2867 | .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid, | |
2868 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2869 | .ndo_poll_controller = bnad_netpoll | |
2870 | #endif | |
2871 | }; | |
2872 | ||
2873 | static void | |
2874 | bnad_netdev_init(struct bnad *bnad, bool using_dac) | |
2875 | { | |
2876 | struct net_device *netdev = bnad->netdev; | |
2877 | ||
2878 | netdev->features |= NETIF_F_IPV6_CSUM; | |
2879 | netdev->features |= NETIF_F_TSO; | |
2880 | netdev->features |= NETIF_F_TSO6; | |
2881 | ||
2882 | netdev->features |= NETIF_F_GRO; | |
2883 | pr_warn("bna: GRO enabled, using kernel stack GRO\n"); | |
2884 | ||
2885 | netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; | |
2886 | ||
2887 | if (using_dac) | |
2888 | netdev->features |= NETIF_F_HIGHDMA; | |
2889 | ||
2890 | netdev->features |= | |
2891 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX | | |
2892 | NETIF_F_HW_VLAN_FILTER; | |
2893 | ||
2894 | netdev->vlan_features = netdev->features; | |
2895 | netdev->mem_start = bnad->mmio_start; | |
2896 | netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1; | |
2897 | ||
2898 | netdev->netdev_ops = &bnad_netdev_ops; | |
2899 | bnad_set_ethtool_ops(netdev); | |
2900 | } | |
2901 | ||
2902 | /* | |
2903 | * 1. Initialize the bnad structure | |
2904 | * 2. Setup netdev pointer in pci_dev | |
2905 | * 3. Initialze Tx free tasklet | |
2906 | * 4. Initialize no. of TxQ & CQs & MSIX vectors | |
2907 | */ | |
2908 | static int | |
2909 | bnad_init(struct bnad *bnad, | |
2910 | struct pci_dev *pdev, struct net_device *netdev) | |
2911 | { | |
2912 | unsigned long flags; | |
2913 | ||
2914 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
2915 | pci_set_drvdata(pdev, netdev); | |
2916 | ||
2917 | bnad->netdev = netdev; | |
2918 | bnad->pcidev = pdev; | |
2919 | bnad->mmio_start = pci_resource_start(pdev, 0); | |
2920 | bnad->mmio_len = pci_resource_len(pdev, 0); | |
2921 | bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len); | |
2922 | if (!bnad->bar0) { | |
2923 | dev_err(&pdev->dev, "ioremap for bar0 failed\n"); | |
2924 | pci_set_drvdata(pdev, NULL); | |
2925 | return -ENOMEM; | |
2926 | } | |
2927 | pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0, | |
2928 | (unsigned long long) bnad->mmio_len); | |
2929 | ||
2930 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
2931 | if (!bnad_msix_disable) | |
2932 | bnad->cfg_flags = BNAD_CF_MSIX; | |
2933 | ||
2934 | bnad->cfg_flags |= BNAD_CF_DIM_ENABLED; | |
2935 | ||
2936 | bnad_q_num_init(bnad); | |
2937 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
2938 | ||
2939 | bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) + | |
2940 | (bnad->num_rx * bnad->num_rxp_per_rx) + | |
2941 | BNAD_MAILBOX_MSIX_VECTORS; | |
2942 | bnad->msix_diag_num = 2; /* 1 for Tx, 1 for Rx */ | |
2943 | ||
2944 | bnad->txq_depth = BNAD_TXQ_DEPTH; | |
2945 | bnad->rxq_depth = BNAD_RXQ_DEPTH; | |
2946 | bnad->rx_csum = true; | |
2947 | ||
2948 | bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO; | |
2949 | bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO; | |
2950 | ||
2951 | tasklet_init(&bnad->tx_free_tasklet, bnad_tx_free_tasklet, | |
2952 | (unsigned long)bnad); | |
2953 | ||
2954 | return 0; | |
2955 | } | |
2956 | ||
2957 | /* | |
2958 | * Must be called after bnad_pci_uninit() | |
2959 | * so that iounmap() and pci_set_drvdata(NULL) | |
2960 | * happens only after PCI uninitialization. | |
2961 | */ | |
2962 | static void | |
2963 | bnad_uninit(struct bnad *bnad) | |
2964 | { | |
2965 | if (bnad->bar0) | |
2966 | iounmap(bnad->bar0); | |
2967 | pci_set_drvdata(bnad->pcidev, NULL); | |
2968 | } | |
2969 | ||
2970 | /* | |
2971 | * Initialize locks | |
2972 | a) Per device mutes used for serializing configuration | |
2973 | changes from OS interface | |
2974 | b) spin lock used to protect bna state machine | |
2975 | */ | |
2976 | static void | |
2977 | bnad_lock_init(struct bnad *bnad) | |
2978 | { | |
2979 | spin_lock_init(&bnad->bna_lock); | |
2980 | mutex_init(&bnad->conf_mutex); | |
2981 | } | |
2982 | ||
2983 | static void | |
2984 | bnad_lock_uninit(struct bnad *bnad) | |
2985 | { | |
2986 | mutex_destroy(&bnad->conf_mutex); | |
2987 | } | |
2988 | ||
2989 | /* PCI Initialization */ | |
2990 | static int | |
2991 | bnad_pci_init(struct bnad *bnad, | |
2992 | struct pci_dev *pdev, bool *using_dac) | |
2993 | { | |
2994 | int err; | |
2995 | ||
2996 | err = pci_enable_device(pdev); | |
2997 | if (err) | |
2998 | return err; | |
2999 | err = pci_request_regions(pdev, BNAD_NAME); | |
3000 | if (err) | |
3001 | goto disable_device; | |
3002 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && | |
3003 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
3004 | *using_dac = 1; | |
3005 | } else { | |
3006 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
3007 | if (err) { | |
3008 | err = pci_set_consistent_dma_mask(pdev, | |
3009 | DMA_BIT_MASK(32)); | |
3010 | if (err) | |
3011 | goto release_regions; | |
3012 | } | |
3013 | *using_dac = 0; | |
3014 | } | |
3015 | pci_set_master(pdev); | |
3016 | return 0; | |
3017 | ||
3018 | release_regions: | |
3019 | pci_release_regions(pdev); | |
3020 | disable_device: | |
3021 | pci_disable_device(pdev); | |
3022 | ||
3023 | return err; | |
3024 | } | |
3025 | ||
3026 | static void | |
3027 | bnad_pci_uninit(struct pci_dev *pdev) | |
3028 | { | |
3029 | pci_release_regions(pdev); | |
3030 | pci_disable_device(pdev); | |
3031 | } | |
3032 | ||
3033 | static int __devinit | |
3034 | bnad_pci_probe(struct pci_dev *pdev, | |
3035 | const struct pci_device_id *pcidev_id) | |
3036 | { | |
3037 | bool using_dac; | |
3038 | int err; | |
3039 | struct bnad *bnad; | |
3040 | struct bna *bna; | |
3041 | struct net_device *netdev; | |
3042 | struct bfa_pcidev pcidev_info; | |
3043 | unsigned long flags; | |
3044 | ||
3045 | pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n", | |
3046 | pdev, pcidev_id, PCI_FUNC(pdev->devfn)); | |
3047 | ||
3048 | mutex_lock(&bnad_fwimg_mutex); | |
3049 | if (!cna_get_firmware_buf(pdev)) { | |
3050 | mutex_unlock(&bnad_fwimg_mutex); | |
3051 | pr_warn("Failed to load Firmware Image!\n"); | |
3052 | return -ENODEV; | |
3053 | } | |
3054 | mutex_unlock(&bnad_fwimg_mutex); | |
3055 | ||
3056 | /* | |
3057 | * Allocates sizeof(struct net_device + struct bnad) | |
3058 | * bnad = netdev->priv | |
3059 | */ | |
3060 | netdev = alloc_etherdev(sizeof(struct bnad)); | |
3061 | if (!netdev) { | |
3062 | dev_err(&pdev->dev, "alloc_etherdev failed\n"); | |
3063 | err = -ENOMEM; | |
3064 | return err; | |
3065 | } | |
3066 | bnad = netdev_priv(netdev); | |
3067 | ||
8b230ed8 RM |
3068 | /* |
3069 | * PCI initialization | |
3070 | * Output : using_dac = 1 for 64 bit DMA | |
3071 | * = 0 for 32 bit DMA | |
3072 | */ | |
3073 | err = bnad_pci_init(bnad, pdev, &using_dac); | |
3074 | if (err) | |
3075 | goto free_netdev; | |
3076 | ||
3077 | bnad_lock_init(bnad); | |
3078 | /* | |
3079 | * Initialize bnad structure | |
3080 | * Setup relation between pci_dev & netdev | |
3081 | * Init Tx free tasklet | |
3082 | */ | |
3083 | err = bnad_init(bnad, pdev, netdev); | |
3084 | if (err) | |
3085 | goto pci_uninit; | |
3086 | /* Initialize netdev structure, set up ethtool ops */ | |
3087 | bnad_netdev_init(bnad, using_dac); | |
3088 | ||
3089 | bnad_enable_msix(bnad); | |
3090 | ||
3091 | /* Get resource requirement form bna */ | |
3092 | bna_res_req(&bnad->res_info[0]); | |
3093 | ||
3094 | /* Allocate resources from bna */ | |
3095 | err = bnad_res_alloc(bnad); | |
3096 | if (err) | |
3097 | goto free_netdev; | |
3098 | ||
3099 | bna = &bnad->bna; | |
3100 | ||
3101 | /* Setup pcidev_info for bna_init() */ | |
3102 | pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn); | |
3103 | pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn); | |
3104 | pcidev_info.device_id = bnad->pcidev->device; | |
3105 | pcidev_info.pci_bar_kva = bnad->bar0; | |
3106 | ||
3107 | mutex_lock(&bnad->conf_mutex); | |
3108 | ||
3109 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3110 | bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]); | |
3111 | ||
3112 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3113 | ||
3114 | bnad->stats.bna_stats = &bna->stats; | |
3115 | ||
3116 | /* Set up timers */ | |
3117 | setup_timer(&bnad->bna.device.ioc.ioc_timer, bnad_ioc_timeout, | |
3118 | ((unsigned long)bnad)); | |
3119 | setup_timer(&bnad->bna.device.ioc.hb_timer, bnad_ioc_hb_check, | |
3120 | ((unsigned long)bnad)); | |
3121 | setup_timer(&bnad->bna.device.ioc.sem_timer, bnad_ioc_sem_timeout, | |
3122 | ((unsigned long)bnad)); | |
3123 | ||
3124 | /* Now start the timer before calling IOC */ | |
3125 | mod_timer(&bnad->bna.device.ioc.ioc_timer, | |
3126 | jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ)); | |
3127 | ||
3128 | /* | |
3129 | * Start the chip | |
3130 | * Don't care even if err != 0, bna state machine will | |
3131 | * deal with it | |
3132 | */ | |
3133 | err = bnad_device_enable(bnad); | |
3134 | ||
3135 | /* Get the burnt-in mac */ | |
3136 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3137 | bna_port_mac_get(&bna->port, &bnad->perm_addr); | |
3138 | bnad_set_netdev_perm_addr(bnad); | |
3139 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3140 | ||
3141 | mutex_unlock(&bnad->conf_mutex); | |
3142 | ||
3143 | /* | |
3144 | * Make sure the link appears down to the stack | |
3145 | */ | |
3146 | netif_carrier_off(netdev); | |
3147 | ||
3148 | /* Finally, reguister with net_device layer */ | |
3149 | err = register_netdev(netdev); | |
3150 | if (err) { | |
3151 | pr_err("BNA : Registering with netdev failed\n"); | |
3152 | goto disable_device; | |
3153 | } | |
3154 | ||
3155 | return 0; | |
3156 | ||
3157 | disable_device: | |
3158 | mutex_lock(&bnad->conf_mutex); | |
3159 | bnad_device_disable(bnad); | |
3160 | del_timer_sync(&bnad->bna.device.ioc.ioc_timer); | |
3161 | del_timer_sync(&bnad->bna.device.ioc.sem_timer); | |
3162 | del_timer_sync(&bnad->bna.device.ioc.hb_timer); | |
3163 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3164 | bna_uninit(bna); | |
3165 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3166 | mutex_unlock(&bnad->conf_mutex); | |
3167 | ||
3168 | bnad_res_free(bnad); | |
3169 | bnad_disable_msix(bnad); | |
3170 | pci_uninit: | |
3171 | bnad_pci_uninit(pdev); | |
3172 | bnad_lock_uninit(bnad); | |
3173 | bnad_uninit(bnad); | |
3174 | free_netdev: | |
3175 | free_netdev(netdev); | |
3176 | return err; | |
3177 | } | |
3178 | ||
3179 | static void __devexit | |
3180 | bnad_pci_remove(struct pci_dev *pdev) | |
3181 | { | |
3182 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3183 | struct bnad *bnad; | |
3184 | struct bna *bna; | |
3185 | unsigned long flags; | |
3186 | ||
3187 | if (!netdev) | |
3188 | return; | |
3189 | ||
3190 | pr_info("%s bnad_pci_remove\n", netdev->name); | |
3191 | bnad = netdev_priv(netdev); | |
3192 | bna = &bnad->bna; | |
3193 | ||
3194 | unregister_netdev(netdev); | |
3195 | ||
3196 | mutex_lock(&bnad->conf_mutex); | |
3197 | bnad_device_disable(bnad); | |
3198 | del_timer_sync(&bnad->bna.device.ioc.ioc_timer); | |
3199 | del_timer_sync(&bnad->bna.device.ioc.sem_timer); | |
3200 | del_timer_sync(&bnad->bna.device.ioc.hb_timer); | |
3201 | spin_lock_irqsave(&bnad->bna_lock, flags); | |
3202 | bna_uninit(bna); | |
3203 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | |
3204 | mutex_unlock(&bnad->conf_mutex); | |
3205 | ||
3206 | bnad_res_free(bnad); | |
3207 | bnad_disable_msix(bnad); | |
3208 | bnad_pci_uninit(pdev); | |
3209 | bnad_lock_uninit(bnad); | |
3210 | bnad_uninit(bnad); | |
3211 | free_netdev(netdev); | |
3212 | } | |
3213 | ||
3214 | const struct pci_device_id bnad_pci_id_table[] = { | |
3215 | { | |
3216 | PCI_DEVICE(PCI_VENDOR_ID_BROCADE, | |
3217 | PCI_DEVICE_ID_BROCADE_CT), | |
3218 | .class = PCI_CLASS_NETWORK_ETHERNET << 8, | |
3219 | .class_mask = 0xffff00 | |
3220 | }, {0, } | |
3221 | }; | |
3222 | ||
3223 | MODULE_DEVICE_TABLE(pci, bnad_pci_id_table); | |
3224 | ||
3225 | static struct pci_driver bnad_pci_driver = { | |
3226 | .name = BNAD_NAME, | |
3227 | .id_table = bnad_pci_id_table, | |
3228 | .probe = bnad_pci_probe, | |
3229 | .remove = __devexit_p(bnad_pci_remove), | |
3230 | }; | |
3231 | ||
3232 | static int __init | |
3233 | bnad_module_init(void) | |
3234 | { | |
3235 | int err; | |
3236 | ||
3237 | pr_info("Brocade 10G Ethernet driver\n"); | |
3238 | ||
8a891429 | 3239 | bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover); |
8b230ed8 RM |
3240 | |
3241 | err = pci_register_driver(&bnad_pci_driver); | |
3242 | if (err < 0) { | |
3243 | pr_err("bna : PCI registration failed in module init " | |
3244 | "(%d)\n", err); | |
3245 | return err; | |
3246 | } | |
3247 | ||
3248 | return 0; | |
3249 | } | |
3250 | ||
3251 | static void __exit | |
3252 | bnad_module_exit(void) | |
3253 | { | |
3254 | pci_unregister_driver(&bnad_pci_driver); | |
3255 | ||
3256 | if (bfi_fw) | |
3257 | release_firmware(bfi_fw); | |
3258 | } | |
3259 | ||
3260 | module_init(bnad_module_init); | |
3261 | module_exit(bnad_module_exit); | |
3262 | ||
3263 | MODULE_AUTHOR("Brocade"); | |
3264 | MODULE_LICENSE("GPL"); | |
3265 | MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver"); | |
3266 | MODULE_VERSION(BNAD_VERSION); | |
3267 | MODULE_FIRMWARE(CNA_FW_FILE_CT); |