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be2net: Implement ethtool get_phys_id function.
[net-next-2.6.git] / drivers / net / benet / be_cmds.h
CommitLineData
6b7c5b94
SP		 1/*
2 * Copyright (C) 2005 - 2009 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
54 MCC_STATUS_SUCCESS = 0x0,
55/* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57/* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59/* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61/* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63/* The command is completing with a DMA error */
b31c50a7 64 MCC_STATUS_DMA_FAILED = 0x5,
49643848 65 MCC_STATUS_NOT_SUPPORTED = 66
6b7c5b94
SP		 66};
67
68#define CQE_STATUS_COMPL_MASK 0xFFFF
69#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70#define CQE_STATUS_EXTD_MASK 0xFFFF
71#define CQE_STATUS_EXTD_SHIFT 0 /* bits 0 - 15 */
72
efd2e40a 73struct be_mcc_compl {
6b7c5b94
SP		 74 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
78};
79
a8f447bd
SP		 80/* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
82 */
83#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
85#define ASYNC_EVENT_CODE_LINK_STATE 0x1
86struct be_async_event_trailer {
87 u32 code;
88};
89
90enum {
91 ASYNC_EVENT_LINK_DOWN = 0x0,
92 ASYNC_EVENT_LINK_UP = 0x1
93};
94
95/* When the event code of an async trailer is link-state, the mcc_compl
96 * must be interpreted as follows
97 */
98struct be_async_event_link_state {
99 u8 physical_port;
100 u8 port_link_status;
101 u8 port_duplex;
102 u8 port_speed;
103 u8 port_fault;
104 u8 rsvd0[7];
105 struct be_async_event_trailer trailer;
106} __packed;
107
6b7c5b94
SP		 108struct be_mcc_mailbox {
109 struct be_mcc_wrb wrb;
efd2e40a 110 struct be_mcc_compl compl;
6b7c5b94
SP		 111};
112
113#define CMD_SUBSYSTEM_COMMON 0x1
114#define CMD_SUBSYSTEM_ETH 0x3
115
116#define OPCODE_COMMON_NTWK_MAC_QUERY 1
117#define OPCODE_COMMON_NTWK_MAC_SET 2
118#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
119#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
120#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
84517482 121#define OPCODE_COMMON_WRITE_FLASHROM 7
6b7c5b94
SP		 122#define OPCODE_COMMON_CQ_CREATE 12
123#define OPCODE_COMMON_EQ_CREATE 13
124#define OPCODE_COMMON_MCC_CREATE 21
125#define OPCODE_COMMON_NTWK_RX_FILTER 34
126#define OPCODE_COMMON_GET_FW_VERSION 35
127#define OPCODE_COMMON_SET_FLOW_CONTROL 36
128#define OPCODE_COMMON_GET_FLOW_CONTROL 37
129#define OPCODE_COMMON_SET_FRAME_SIZE 39
130#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
131#define OPCODE_COMMON_FIRMWARE_CONFIG 42
132#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
133#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 134#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 135#define OPCODE_COMMON_CQ_DESTROY 54
136#define OPCODE_COMMON_EQ_DESTROY 55
137#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
138#define OPCODE_COMMON_NTWK_PMAC_ADD 59
139#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 140#define OPCODE_COMMON_FUNCTION_RESET 61
fad9ab2c
SB		 141#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
142#define OPCODE_COMMON_GET_BEACON_STATE 70
6b7c5b94
SP		 143
144#define OPCODE_ETH_ACPI_CONFIG 2
145#define OPCODE_ETH_PROMISCUOUS 3
146#define OPCODE_ETH_GET_STATISTICS 4
147#define OPCODE_ETH_TX_CREATE 7
148#define OPCODE_ETH_RX_CREATE 8
149#define OPCODE_ETH_TX_DESTROY 9
150#define OPCODE_ETH_RX_DESTROY 10
151
152struct be_cmd_req_hdr {
153 u8 opcode; /* dword 0 */
154 u8 subsystem; /* dword 0 */
155 u8 port_number; /* dword 0 */
156 u8 domain; /* dword 0 */
157 u32 timeout; /* dword 1 */
158 u32 request_length; /* dword 2 */
159 u32 rsvd; /* dword 3 */
160};
161
162#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
163#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
164struct be_cmd_resp_hdr {
165 u32 info; /* dword 0 */
166 u32 status; /* dword 1 */
167 u32 response_length; /* dword 2 */
168 u32 actual_resp_len; /* dword 3 */
169};
170
171struct phys_addr {
172 u32 lo;
173 u32 hi;
174};
175
176/**************************
177 * BE Command definitions *
178 **************************/
179
180/* Pseudo amap definition in which each bit of the actual structure is defined
181 * as a byte: used to calculate offset/shift/mask of each field */
182struct amap_eq_context {
183 u8 cidx[13]; /* dword 0*/
184 u8 rsvd0[3]; /* dword 0*/
185 u8 epidx[13]; /* dword 0*/
186 u8 valid; /* dword 0*/
187 u8 rsvd1; /* dword 0*/
188 u8 size; /* dword 0*/
189 u8 pidx[13]; /* dword 1*/
190 u8 rsvd2[3]; /* dword 1*/
191 u8 pd[10]; /* dword 1*/
192 u8 count[3]; /* dword 1*/
193 u8 solevent; /* dword 1*/
194 u8 stalled; /* dword 1*/
195 u8 armed; /* dword 1*/
196 u8 rsvd3[4]; /* dword 2*/
197 u8 func[8]; /* dword 2*/
198 u8 rsvd4; /* dword 2*/
199 u8 delaymult[10]; /* dword 2*/
200 u8 rsvd5[2]; /* dword 2*/
201 u8 phase[2]; /* dword 2*/
202 u8 nodelay; /* dword 2*/
203 u8 rsvd6[4]; /* dword 2*/
204 u8 rsvd7[32]; /* dword 3*/
205} __packed;
206
207struct be_cmd_req_eq_create {
208 struct be_cmd_req_hdr hdr;
209 u16 num_pages; /* sword */
210 u16 rsvd0; /* sword */
211 u8 context[sizeof(struct amap_eq_context) / 8];
212 struct phys_addr pages[8];
213} __packed;
214
215struct be_cmd_resp_eq_create {
216 struct be_cmd_resp_hdr resp_hdr;
217 u16 eq_id; /* sword */
218 u16 rsvd0; /* sword */
219} __packed;
220
221/******************** Mac query ***************************/
222enum {
223 MAC_ADDRESS_TYPE_STORAGE = 0x0,
224 MAC_ADDRESS_TYPE_NETWORK = 0x1,
225 MAC_ADDRESS_TYPE_PD = 0x2,
226 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
227};
228
229struct mac_addr {
230 u16 size_of_struct;
231 u8 addr[ETH_ALEN];
232} __packed;
233
234struct be_cmd_req_mac_query {
235 struct be_cmd_req_hdr hdr;
236 u8 type;
237 u8 permanent;
238 u16 if_id;
239} __packed;
240
241struct be_cmd_resp_mac_query {
242 struct be_cmd_resp_hdr hdr;
243 struct mac_addr mac;
244};
245
246/******************** PMac Add ***************************/
247struct be_cmd_req_pmac_add {
248 struct be_cmd_req_hdr hdr;
249 u32 if_id;
250 u8 mac_address[ETH_ALEN];
251 u8 rsvd0[2];
252} __packed;
253
254struct be_cmd_resp_pmac_add {
255 struct be_cmd_resp_hdr hdr;
256 u32 pmac_id;
257};
258
259/******************** PMac Del ***************************/
260struct be_cmd_req_pmac_del {
261 struct be_cmd_req_hdr hdr;
262 u32 if_id;
263 u32 pmac_id;
264};
265
266/******************** Create CQ ***************************/
267/* Pseudo amap definition in which each bit of the actual structure is defined
268 * as a byte: used to calculate offset/shift/mask of each field */
269struct amap_cq_context {
270 u8 cidx[11]; /* dword 0*/
271 u8 rsvd0; /* dword 0*/
272 u8 coalescwm[2]; /* dword 0*/
273 u8 nodelay; /* dword 0*/
274 u8 epidx[11]; /* dword 0*/
275 u8 rsvd1; /* dword 0*/
276 u8 count[2]; /* dword 0*/
277 u8 valid; /* dword 0*/
278 u8 solevent; /* dword 0*/
279 u8 eventable; /* dword 0*/
280 u8 pidx[11]; /* dword 1*/
281 u8 rsvd2; /* dword 1*/
282 u8 pd[10]; /* dword 1*/
283 u8 eqid[8]; /* dword 1*/
284 u8 stalled; /* dword 1*/
285 u8 armed; /* dword 1*/
286 u8 rsvd3[4]; /* dword 2*/
287 u8 func[8]; /* dword 2*/
288 u8 rsvd4[20]; /* dword 2*/
289 u8 rsvd5[32]; /* dword 3*/
290} __packed;
291
292struct be_cmd_req_cq_create {
293 struct be_cmd_req_hdr hdr;
294 u16 num_pages;
295 u16 rsvd0;
296 u8 context[sizeof(struct amap_cq_context) / 8];
297 struct phys_addr pages[8];
298} __packed;
299
300struct be_cmd_resp_cq_create {
301 struct be_cmd_resp_hdr hdr;
302 u16 cq_id;
303 u16 rsvd0;
304} __packed;
305
5fb379ee
SP		 306/******************** Create MCCQ ***************************/
307/* Pseudo amap definition in which each bit of the actual structure is defined
308 * as a byte: used to calculate offset/shift/mask of each field */
309struct amap_mcc_context {
310 u8 con_index[14];
311 u8 rsvd0[2];
312 u8 ring_size[4];
313 u8 fetch_wrb;
314 u8 fetch_r2t;
315 u8 cq_id[10];
316 u8 prod_index[14];
317 u8 fid[8];
318 u8 pdid[9];
319 u8 valid;
320 u8 rsvd1[32];
321 u8 rsvd2[32];
322} __packed;
323
324struct be_cmd_req_mcc_create {
325 struct be_cmd_req_hdr hdr;
326 u16 num_pages;
327 u16 rsvd0;
328 u8 context[sizeof(struct amap_mcc_context) / 8];
329 struct phys_addr pages[8];
330} __packed;
331
332struct be_cmd_resp_mcc_create {
333 struct be_cmd_resp_hdr hdr;
334 u16 id;
335 u16 rsvd0;
336} __packed;
337
6b7c5b94
SP		 338/******************** Create TxQ ***************************/
339#define BE_ETH_TX_RING_TYPE_STANDARD 2
340#define BE_ULP1_NUM 1
341
342/* Pseudo amap definition in which each bit of the actual structure is defined
343 * as a byte: used to calculate offset/shift/mask of each field */
344struct amap_tx_context {
345 u8 rsvd0[16]; /* dword 0 */
346 u8 tx_ring_size[4]; /* dword 0 */
347 u8 rsvd1[26]; /* dword 0 */
348 u8 pci_func_id[8]; /* dword 1 */
349 u8 rsvd2[9]; /* dword 1 */
350 u8 ctx_valid; /* dword 1 */
351 u8 cq_id_send[16]; /* dword 2 */
352 u8 rsvd3[16]; /* dword 2 */
353 u8 rsvd4[32]; /* dword 3 */
354 u8 rsvd5[32]; /* dword 4 */
355 u8 rsvd6[32]; /* dword 5 */
356 u8 rsvd7[32]; /* dword 6 */
357 u8 rsvd8[32]; /* dword 7 */
358 u8 rsvd9[32]; /* dword 8 */
359 u8 rsvd10[32]; /* dword 9 */
360 u8 rsvd11[32]; /* dword 10 */
361 u8 rsvd12[32]; /* dword 11 */
362 u8 rsvd13[32]; /* dword 12 */
363 u8 rsvd14[32]; /* dword 13 */
364 u8 rsvd15[32]; /* dword 14 */
365 u8 rsvd16[32]; /* dword 15 */
366} __packed;
367
368struct be_cmd_req_eth_tx_create {
369 struct be_cmd_req_hdr hdr;
370 u8 num_pages;
371 u8 ulp_num;
372 u8 type;
373 u8 bound_port;
374 u8 context[sizeof(struct amap_tx_context) / 8];
375 struct phys_addr pages[8];
376} __packed;
377
378struct be_cmd_resp_eth_tx_create {
379 struct be_cmd_resp_hdr hdr;
380 u16 cid;
381 u16 rsvd0;
382} __packed;
383
384/******************** Create RxQ ***************************/
385struct be_cmd_req_eth_rx_create {
386 struct be_cmd_req_hdr hdr;
387 u16 cq_id;
388 u8 frag_size;
389 u8 num_pages;
390 struct phys_addr pages[2];
391 u32 interface_id;
392 u16 max_frame_size;
393 u16 rsvd0;
394 u32 rss_queue;
395} __packed;
396
397struct be_cmd_resp_eth_rx_create {
398 struct be_cmd_resp_hdr hdr;
399 u16 id;
400 u8 cpu_id;
401 u8 rsvd0;
402} __packed;
403
404/******************** Q Destroy ***************************/
405/* Type of Queue to be destroyed */
406enum {
407 QTYPE_EQ = 1,
408 QTYPE_CQ,
409 QTYPE_TXQ,
5fb379ee
SP		 410 QTYPE_RXQ,
411 QTYPE_MCCQ
6b7c5b94
SP		 412};
413
414struct be_cmd_req_q_destroy {
415 struct be_cmd_req_hdr hdr;
416 u16 id;
417 u16 bypass_flush; /* valid only for rx q destroy */
418} __packed;
419
420/************ I/f Create (it's actually I/f Config Create)**********/
421
422/* Capability flags for the i/f */
423enum be_if_flags {
424 BE_IF_FLAGS_RSS = 0x4,
425 BE_IF_FLAGS_PROMISCUOUS = 0x8,
426 BE_IF_FLAGS_BROADCAST = 0x10,
427 BE_IF_FLAGS_UNTAGGED = 0x20,
428 BE_IF_FLAGS_ULP = 0x40,
429 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
430 BE_IF_FLAGS_VLAN = 0x100,
431 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
432 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
433 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
434};
435
436/* An RX interface is an object with one or more MAC addresses and
437 * filtering capabilities. */
438struct be_cmd_req_if_create {
439 struct be_cmd_req_hdr hdr;
440 u32 version; /* ignore currntly */
441 u32 capability_flags;
442 u32 enable_flags;
443 u8 mac_addr[ETH_ALEN];
444 u8 rsvd0;
445 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
446 u32 vlan_tag; /* not used currently */
447} __packed;
448
449struct be_cmd_resp_if_create {
450 struct be_cmd_resp_hdr hdr;
451 u32 interface_id;
452 u32 pmac_id;
453};
454
455/****** I/f Destroy(it's actually I/f Config Destroy )**********/
456struct be_cmd_req_if_destroy {
457 struct be_cmd_req_hdr hdr;
458 u32 interface_id;
459};
460
461/*************** HW Stats Get **********************************/
462struct be_port_rxf_stats {
463 u32 rx_bytes_lsd; /* dword 0*/
464 u32 rx_bytes_msd; /* dword 1*/
465 u32 rx_total_frames; /* dword 2*/
466 u32 rx_unicast_frames; /* dword 3*/
467 u32 rx_multicast_frames; /* dword 4*/
468 u32 rx_broadcast_frames; /* dword 5*/
469 u32 rx_crc_errors; /* dword 6*/
470 u32 rx_alignment_symbol_errors; /* dword 7*/
471 u32 rx_pause_frames; /* dword 8*/
472 u32 rx_control_frames; /* dword 9*/
473 u32 rx_in_range_errors; /* dword 10*/
474 u32 rx_out_range_errors; /* dword 11*/
475 u32 rx_frame_too_long; /* dword 12*/
476 u32 rx_address_match_errors; /* dword 13*/
477 u32 rx_vlan_mismatch; /* dword 14*/
478 u32 rx_dropped_too_small; /* dword 15*/
479 u32 rx_dropped_too_short; /* dword 16*/
480 u32 rx_dropped_header_too_small; /* dword 17*/
481 u32 rx_dropped_tcp_length; /* dword 18*/
482 u32 rx_dropped_runt; /* dword 19*/
483 u32 rx_64_byte_packets; /* dword 20*/
484 u32 rx_65_127_byte_packets; /* dword 21*/
485 u32 rx_128_256_byte_packets; /* dword 22*/
486 u32 rx_256_511_byte_packets; /* dword 23*/
487 u32 rx_512_1023_byte_packets; /* dword 24*/
488 u32 rx_1024_1518_byte_packets; /* dword 25*/
489 u32 rx_1519_2047_byte_packets; /* dword 26*/
490 u32 rx_2048_4095_byte_packets; /* dword 27*/
491 u32 rx_4096_8191_byte_packets; /* dword 28*/
492 u32 rx_8192_9216_byte_packets; /* dword 29*/
493 u32 rx_ip_checksum_errs; /* dword 30*/
494 u32 rx_tcp_checksum_errs; /* dword 31*/
495 u32 rx_udp_checksum_errs; /* dword 32*/
496 u32 rx_non_rss_packets; /* dword 33*/
497 u32 rx_ipv4_packets; /* dword 34*/
498 u32 rx_ipv6_packets; /* dword 35*/
499 u32 rx_ipv4_bytes_lsd; /* dword 36*/
500 u32 rx_ipv4_bytes_msd; /* dword 37*/
501 u32 rx_ipv6_bytes_lsd; /* dword 38*/
502 u32 rx_ipv6_bytes_msd; /* dword 39*/
503 u32 rx_chute1_packets; /* dword 40*/
504 u32 rx_chute2_packets; /* dword 41*/
505 u32 rx_chute3_packets; /* dword 42*/
506 u32 rx_management_packets; /* dword 43*/
507 u32 rx_switched_unicast_packets; /* dword 44*/
508 u32 rx_switched_multicast_packets; /* dword 45*/
509 u32 rx_switched_broadcast_packets; /* dword 46*/
510 u32 tx_bytes_lsd; /* dword 47*/
511 u32 tx_bytes_msd; /* dword 48*/
512 u32 tx_unicastframes; /* dword 49*/
513 u32 tx_multicastframes; /* dword 50*/
514 u32 tx_broadcastframes; /* dword 51*/
515 u32 tx_pauseframes; /* dword 52*/
516 u32 tx_controlframes; /* dword 53*/
517 u32 tx_64_byte_packets; /* dword 54*/
518 u32 tx_65_127_byte_packets; /* dword 55*/
519 u32 tx_128_256_byte_packets; /* dword 56*/
520 u32 tx_256_511_byte_packets; /* dword 57*/
521 u32 tx_512_1023_byte_packets; /* dword 58*/
522 u32 tx_1024_1518_byte_packets; /* dword 59*/
523 u32 tx_1519_2047_byte_packets; /* dword 60*/
524 u32 tx_2048_4095_byte_packets; /* dword 61*/
525 u32 tx_4096_8191_byte_packets; /* dword 62*/
526 u32 tx_8192_9216_byte_packets; /* dword 63*/
527 u32 rx_fifo_overflow; /* dword 64*/
528 u32 rx_input_fifo_overflow; /* dword 65*/
529};
530
531struct be_rxf_stats {
532 struct be_port_rxf_stats port[2];
533 u32 rx_drops_no_pbuf; /* dword 132*/
534 u32 rx_drops_no_txpb; /* dword 133*/
535 u32 rx_drops_no_erx_descr; /* dword 134*/
536 u32 rx_drops_no_tpre_descr; /* dword 135*/
537 u32 management_rx_port_packets; /* dword 136*/
538 u32 management_rx_port_bytes; /* dword 137*/
539 u32 management_rx_port_pause_frames; /* dword 138*/
540 u32 management_rx_port_errors; /* dword 139*/
541 u32 management_tx_port_packets; /* dword 140*/
542 u32 management_tx_port_bytes; /* dword 141*/
543 u32 management_tx_port_pause; /* dword 142*/
544 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
545 u32 rx_drops_too_many_frags; /* dword 144*/
546 u32 rx_drops_invalid_ring; /* dword 145*/
547 u32 forwarded_packets; /* dword 146*/
548 u32 rx_drops_mtu; /* dword 147*/
549 u32 rsvd0[15];
550};
551
552struct be_erx_stats {
553 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
554 u32 debug_wdma_sent_hold; /* dword 44*/
555 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
556 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
557 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
558};
559
560struct be_hw_stats {
561 struct be_rxf_stats rxf;
562 u32 rsvd[48];
563 struct be_erx_stats erx;
564};
565
566struct be_cmd_req_get_stats {
567 struct be_cmd_req_hdr hdr;
568 u8 rsvd[sizeof(struct be_hw_stats)];
569};
570
571struct be_cmd_resp_get_stats {
572 struct be_cmd_resp_hdr hdr;
573 struct be_hw_stats hw_stats;
574};
575
576struct be_cmd_req_vlan_config {
577 struct be_cmd_req_hdr hdr;
578 u8 interface_id;
579 u8 promiscuous;
580 u8 untagged;
581 u8 num_vlan;
582 u16 normal_vlan[64];
583} __packed;
584
585struct be_cmd_req_promiscuous_config {
586 struct be_cmd_req_hdr hdr;
587 u8 port0_promiscuous;
588 u8 port1_promiscuous;
589 u16 rsvd0;
590} __packed;
591
592struct macaddr {
593 u8 byte[ETH_ALEN];
594};
595
596struct be_cmd_req_mcast_mac_config {
597 struct be_cmd_req_hdr hdr;
598 u16 num_mac;
599 u8 promiscuous;
600 u8 interface_id;
601 struct macaddr mac[32];
602} __packed;
603
604static inline struct be_hw_stats *
605hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
606{
607 return &cmd->hw_stats;
608}
609
610/******************** Link Status Query *******************/
611struct be_cmd_req_link_status {
612 struct be_cmd_req_hdr hdr;
613 u32 rsvd;
614};
615
6b7c5b94
SP		 616enum {
617 PHY_LINK_DUPLEX_NONE = 0x0,
618 PHY_LINK_DUPLEX_HALF = 0x1,
619 PHY_LINK_DUPLEX_FULL = 0x2
620};
621
622enum {
623 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
624 PHY_LINK_SPEED_10MBPS = 0x1,
625 PHY_LINK_SPEED_100MBPS = 0x2,
626 PHY_LINK_SPEED_1GBPS = 0x3,
627 PHY_LINK_SPEED_10GBPS = 0x4
628};
629
630struct be_cmd_resp_link_status {
631 struct be_cmd_resp_hdr hdr;
632 u8 physical_port;
633 u8 mac_duplex;
634 u8 mac_speed;
635 u8 mac_fault;
636 u8 mgmt_mac_duplex;
637 u8 mgmt_mac_speed;
638 u16 rsvd0;
639} __packed;
640
641/******************** Get FW Version *******************/
6b7c5b94
SP		 642struct be_cmd_req_get_fw_version {
643 struct be_cmd_req_hdr hdr;
644 u8 rsvd0[FW_VER_LEN];
645 u8 rsvd1[FW_VER_LEN];
646} __packed;
647
648struct be_cmd_resp_get_fw_version {
649 struct be_cmd_resp_hdr hdr;
650 u8 firmware_version_string[FW_VER_LEN];
651 u8 fw_on_flash_version_string[FW_VER_LEN];
652} __packed;
653
654/******************** Set Flow Contrl *******************/
655struct be_cmd_req_set_flow_control {
656 struct be_cmd_req_hdr hdr;
657 u16 tx_flow_control;
658 u16 rx_flow_control;
659} __packed;
660
661/******************** Get Flow Contrl *******************/
662struct be_cmd_req_get_flow_control {
663 struct be_cmd_req_hdr hdr;
664 u32 rsvd;
665};
666
667struct be_cmd_resp_get_flow_control {
668 struct be_cmd_resp_hdr hdr;
669 u16 tx_flow_control;
670 u16 rx_flow_control;
671} __packed;
672
673/******************** Modify EQ Delay *******************/
674struct be_cmd_req_modify_eq_delay {
675 struct be_cmd_req_hdr hdr;
676 u32 num_eq;
677 struct {
678 u32 eq_id;
679 u32 phase;
680 u32 delay_multiplier;
681 } delay[8];
682} __packed;
683
684struct be_cmd_resp_modify_eq_delay {
685 struct be_cmd_resp_hdr hdr;
686 u32 rsvd0;
687} __packed;
688
689/******************** Get FW Config *******************/
690struct be_cmd_req_query_fw_cfg {
691 struct be_cmd_req_hdr hdr;
692 u32 rsvd[30];
693};
694
695struct be_cmd_resp_query_fw_cfg {
696 struct be_cmd_resp_hdr hdr;
697 u32 be_config_number;
698 u32 asic_revision;
699 u32 phys_port;
84517482 700 u32 function_cap;
6b7c5b94
SP		 701 u32 rsvd[26];
702};
703
fad9ab2c
SB		 704/******************** Port Beacon ***************************/
705
706#define BEACON_STATE_ENABLED 0x1
707#define BEACON_STATE_DISABLED 0x0
708
709struct be_cmd_req_enable_disable_beacon {
710 struct be_cmd_req_hdr hdr;
711 u8 port_num;
712 u8 beacon_state;
713 u8 beacon_duration;
714 u8 status_duration;
715} __packed;
716
717struct be_cmd_resp_enable_disable_beacon {
718 struct be_cmd_resp_hdr resp_hdr;
719 u32 rsvd0;
720} __packed;
721
722struct be_cmd_req_get_beacon_state {
723 struct be_cmd_req_hdr hdr;
724 u8 port_num;
725 u8 rsvd0;
726 u16 rsvd1;
727} __packed;
728
729struct be_cmd_resp_get_beacon_state {
730 struct be_cmd_resp_hdr resp_hdr;
731 u8 beacon_state;
732 u8 rsvd0[3];
733} __packed;
734
84517482
AK		 735/****************** Firmware Flash ******************/
736struct flashrom_params {
737 u32 op_code;
738 u32 op_type;
739 u32 data_buf_size;
740 u32 offset;
741 u8 data_buf[4];
742};
743
744struct be_cmd_write_flashrom {
745 struct be_cmd_req_hdr hdr;
746 struct flashrom_params params;
747};
748
8788fdc2
SP		 749extern int be_pci_fnum_get(struct be_adapter *adapter);
750extern int be_cmd_POST(struct be_adapter *adapter);
751extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 752 u8 type, bool permanent, u32 if_handle);
8788fdc2 753extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 754 u32 if_id, u32 *pmac_id);
8788fdc2
SP		 755extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
756extern int be_cmd_if_create(struct be_adapter *adapter, u32 if_flags, u8 *mac,
6b7c5b94 757 bool pmac_invalid, u32 *if_handle, u32 *pmac_id);
8788fdc2
SP		 758extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
759extern int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94 760 struct be_queue_info *eq, int eq_delay);
8788fdc2 761extern int be_cmd_cq_create(struct be_adapter *adapter,
6b7c5b94
SP		 762 struct be_queue_info *cq, struct be_queue_info *eq,
763 bool sol_evts, bool no_delay,
764 int num_cqe_dma_coalesce);
8788fdc2 765extern int be_cmd_mccq_create(struct be_adapter *adapter,
5fb379ee
SP		 766 struct be_queue_info *mccq,
767 struct be_queue_info *cq);
8788fdc2 768extern int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 769 struct be_queue_info *txq,
770 struct be_queue_info *cq);
8788fdc2 771extern int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94
SP		 772 struct be_queue_info *rxq, u16 cq_id,
773 u16 frag_size, u16 max_frame_size, u32 if_id,
774 u32 rss);
8788fdc2 775extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94 776 int type);
8788fdc2 777extern int be_cmd_link_status_query(struct be_adapter *adapter,
a8f447bd 778 bool *link_up);
8788fdc2
SP		 779extern int be_cmd_reset(struct be_adapter *adapter);
780extern int be_cmd_get_stats(struct be_adapter *adapter,
6b7c5b94 781 struct be_dma_mem *nonemb_cmd);
8788fdc2 782extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
6b7c5b94 783
8788fdc2
SP		 784extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
785extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
6b7c5b94
SP		 786 u16 *vtag_array, u32 num, bool untagged,
787 bool promiscuous);
8788fdc2 788extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
6b7c5b94 789 u8 port_num, bool en);
8788fdc2 790extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
24307eef 791 struct dev_mc_list *mc_list, u32 mc_count);
8788fdc2 792extern int be_cmd_set_flow_control(struct be_adapter *adapter,
6b7c5b94 793 u32 tx_fc, u32 rx_fc);
8788fdc2 794extern int be_cmd_get_flow_control(struct be_adapter *adapter,
6b7c5b94 795 u32 *tx_fc, u32 *rx_fc);
dcb9b564
AK		 796extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
797 u32 *port_num, u32 *cap);
14074eab 798extern int be_cmd_reset_function(struct be_adapter *adapter);
b31c50a7 799extern int be_process_mcc(struct be_adapter *adapter);
fad9ab2c
SB		 800extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
801 u8 port_num, u8 beacon, u8 status, u8 state);
802extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
803 u8 port_num, u32 *state);
84517482
AK		 804extern int be_cmd_write_flashrom(struct be_adapter *adapter,
805 struct be_dma_mem *cmd, u32 flash_oper,
806 u32 flash_opcode, u32 buf_size);
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