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be2net: implements ethtool function to read eeprom data.
[net-next-2.6.git] / drivers / net / benet / be_cmds.h
CommitLineData
6b7c5b94
SP		 1/*
2 * Copyright (C) 2005 - 2009 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
54 MCC_STATUS_SUCCESS = 0x0,
55/* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57/* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59/* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61/* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63/* The command is completing with a DMA error */
b31c50a7 64 MCC_STATUS_DMA_FAILED = 0x5,
49643848 65 MCC_STATUS_NOT_SUPPORTED = 66
6b7c5b94
SP		 66};
67
68#define CQE_STATUS_COMPL_MASK 0xFFFF
69#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70#define CQE_STATUS_EXTD_MASK 0xFFFF
f5209b44 71#define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
6b7c5b94 72
efd2e40a 73struct be_mcc_compl {
6b7c5b94
SP		 74 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
78};
79
a8f447bd
SP		 80/* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
82 */
83#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
85#define ASYNC_EVENT_CODE_LINK_STATE 0x1
86struct be_async_event_trailer {
87 u32 code;
88};
89
90enum {
91 ASYNC_EVENT_LINK_DOWN = 0x0,
92 ASYNC_EVENT_LINK_UP = 0x1
93};
94
95/* When the event code of an async trailer is link-state, the mcc_compl
96 * must be interpreted as follows
97 */
98struct be_async_event_link_state {
99 u8 physical_port;
100 u8 port_link_status;
101 u8 port_duplex;
102 u8 port_speed;
103 u8 port_fault;
104 u8 rsvd0[7];
105 struct be_async_event_trailer trailer;
106} __packed;
107
6b7c5b94
SP		 108struct be_mcc_mailbox {
109 struct be_mcc_wrb wrb;
efd2e40a 110 struct be_mcc_compl compl;
6b7c5b94
SP		 111};
112
113#define CMD_SUBSYSTEM_COMMON 0x1
114#define CMD_SUBSYSTEM_ETH 0x3
ff33a6e2 115#define CMD_SUBSYSTEM_LOWLEVEL 0xb
6b7c5b94
SP		 116
117#define OPCODE_COMMON_NTWK_MAC_QUERY 1
118#define OPCODE_COMMON_NTWK_MAC_SET 2
119#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
120#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
121#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
fa9a6fed 122#define OPCODE_COMMON_READ_FLASHROM 6
84517482 123#define OPCODE_COMMON_WRITE_FLASHROM 7
6b7c5b94
SP		 124#define OPCODE_COMMON_CQ_CREATE 12
125#define OPCODE_COMMON_EQ_CREATE 13
126#define OPCODE_COMMON_MCC_CREATE 21
368c0ca2 127#define OPCODE_COMMON_SEEPROM_READ 30
6b7c5b94
SP		 128#define OPCODE_COMMON_NTWK_RX_FILTER 34
129#define OPCODE_COMMON_GET_FW_VERSION 35
130#define OPCODE_COMMON_SET_FLOW_CONTROL 36
131#define OPCODE_COMMON_GET_FLOW_CONTROL 37
132#define OPCODE_COMMON_SET_FRAME_SIZE 39
133#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
134#define OPCODE_COMMON_FIRMWARE_CONFIG 42
135#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
136#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 137#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 138#define OPCODE_COMMON_CQ_DESTROY 54
139#define OPCODE_COMMON_EQ_DESTROY 55
140#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
141#define OPCODE_COMMON_NTWK_PMAC_ADD 59
142#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 143#define OPCODE_COMMON_FUNCTION_RESET 61
fad9ab2c
SB		 144#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
145#define OPCODE_COMMON_GET_BEACON_STATE 70
0388f251 146#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
6b7c5b94
SP		 147
148#define OPCODE_ETH_ACPI_CONFIG 2
149#define OPCODE_ETH_PROMISCUOUS 3
150#define OPCODE_ETH_GET_STATISTICS 4
151#define OPCODE_ETH_TX_CREATE 7
152#define OPCODE_ETH_RX_CREATE 8
153#define OPCODE_ETH_TX_DESTROY 9
154#define OPCODE_ETH_RX_DESTROY 10
71d8d1b5 155#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
6b7c5b94 156
ff33a6e2
S		 157#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
158#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
159
6b7c5b94
SP		 160struct be_cmd_req_hdr {
161 u8 opcode; /* dword 0 */
162 u8 subsystem; /* dword 0 */
163 u8 port_number; /* dword 0 */
164 u8 domain; /* dword 0 */
165 u32 timeout; /* dword 1 */
166 u32 request_length; /* dword 2 */
167 u32 rsvd; /* dword 3 */
168};
169
170#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
171#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
172struct be_cmd_resp_hdr {
173 u32 info; /* dword 0 */
174 u32 status; /* dword 1 */
175 u32 response_length; /* dword 2 */
176 u32 actual_resp_len; /* dword 3 */
177};
178
179struct phys_addr {
180 u32 lo;
181 u32 hi;
182};
183
184/**************************
185 * BE Command definitions *
186 **************************/
187
188/* Pseudo amap definition in which each bit of the actual structure is defined
189 * as a byte: used to calculate offset/shift/mask of each field */
190struct amap_eq_context {
191 u8 cidx[13]; /* dword 0*/
192 u8 rsvd0[3]; /* dword 0*/
193 u8 epidx[13]; /* dword 0*/
194 u8 valid; /* dword 0*/
195 u8 rsvd1; /* dword 0*/
196 u8 size; /* dword 0*/
197 u8 pidx[13]; /* dword 1*/
198 u8 rsvd2[3]; /* dword 1*/
199 u8 pd[10]; /* dword 1*/
200 u8 count[3]; /* dword 1*/
201 u8 solevent; /* dword 1*/
202 u8 stalled; /* dword 1*/
203 u8 armed; /* dword 1*/
204 u8 rsvd3[4]; /* dword 2*/
205 u8 func[8]; /* dword 2*/
206 u8 rsvd4; /* dword 2*/
207 u8 delaymult[10]; /* dword 2*/
208 u8 rsvd5[2]; /* dword 2*/
209 u8 phase[2]; /* dword 2*/
210 u8 nodelay; /* dword 2*/
211 u8 rsvd6[4]; /* dword 2*/
212 u8 rsvd7[32]; /* dword 3*/
213} __packed;
214
215struct be_cmd_req_eq_create {
216 struct be_cmd_req_hdr hdr;
217 u16 num_pages; /* sword */
218 u16 rsvd0; /* sword */
219 u8 context[sizeof(struct amap_eq_context) / 8];
220 struct phys_addr pages[8];
221} __packed;
222
223struct be_cmd_resp_eq_create {
224 struct be_cmd_resp_hdr resp_hdr;
225 u16 eq_id; /* sword */
226 u16 rsvd0; /* sword */
227} __packed;
228
229/******************** Mac query ***************************/
230enum {
231 MAC_ADDRESS_TYPE_STORAGE = 0x0,
232 MAC_ADDRESS_TYPE_NETWORK = 0x1,
233 MAC_ADDRESS_TYPE_PD = 0x2,
234 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
235};
236
237struct mac_addr {
238 u16 size_of_struct;
239 u8 addr[ETH_ALEN];
240} __packed;
241
242struct be_cmd_req_mac_query {
243 struct be_cmd_req_hdr hdr;
244 u8 type;
245 u8 permanent;
246 u16 if_id;
247} __packed;
248
249struct be_cmd_resp_mac_query {
250 struct be_cmd_resp_hdr hdr;
251 struct mac_addr mac;
252};
253
254/******************** PMac Add ***************************/
255struct be_cmd_req_pmac_add {
256 struct be_cmd_req_hdr hdr;
257 u32 if_id;
258 u8 mac_address[ETH_ALEN];
259 u8 rsvd0[2];
260} __packed;
261
262struct be_cmd_resp_pmac_add {
263 struct be_cmd_resp_hdr hdr;
264 u32 pmac_id;
265};
266
267/******************** PMac Del ***************************/
268struct be_cmd_req_pmac_del {
269 struct be_cmd_req_hdr hdr;
270 u32 if_id;
271 u32 pmac_id;
272};
273
274/******************** Create CQ ***************************/
275/* Pseudo amap definition in which each bit of the actual structure is defined
276 * as a byte: used to calculate offset/shift/mask of each field */
277struct amap_cq_context {
278 u8 cidx[11]; /* dword 0*/
279 u8 rsvd0; /* dword 0*/
280 u8 coalescwm[2]; /* dword 0*/
281 u8 nodelay; /* dword 0*/
282 u8 epidx[11]; /* dword 0*/
283 u8 rsvd1; /* dword 0*/
284 u8 count[2]; /* dword 0*/
285 u8 valid; /* dword 0*/
286 u8 solevent; /* dword 0*/
287 u8 eventable; /* dword 0*/
288 u8 pidx[11]; /* dword 1*/
289 u8 rsvd2; /* dword 1*/
290 u8 pd[10]; /* dword 1*/
291 u8 eqid[8]; /* dword 1*/
292 u8 stalled; /* dword 1*/
293 u8 armed; /* dword 1*/
294 u8 rsvd3[4]; /* dword 2*/
295 u8 func[8]; /* dword 2*/
296 u8 rsvd4[20]; /* dword 2*/
297 u8 rsvd5[32]; /* dword 3*/
298} __packed;
299
300struct be_cmd_req_cq_create {
301 struct be_cmd_req_hdr hdr;
302 u16 num_pages;
303 u16 rsvd0;
304 u8 context[sizeof(struct amap_cq_context) / 8];
305 struct phys_addr pages[8];
306} __packed;
307
308struct be_cmd_resp_cq_create {
309 struct be_cmd_resp_hdr hdr;
310 u16 cq_id;
311 u16 rsvd0;
312} __packed;
313
5fb379ee
SP		 314/******************** Create MCCQ ***************************/
315/* Pseudo amap definition in which each bit of the actual structure is defined
316 * as a byte: used to calculate offset/shift/mask of each field */
317struct amap_mcc_context {
318 u8 con_index[14];
319 u8 rsvd0[2];
320 u8 ring_size[4];
321 u8 fetch_wrb;
322 u8 fetch_r2t;
323 u8 cq_id[10];
324 u8 prod_index[14];
325 u8 fid[8];
326 u8 pdid[9];
327 u8 valid;
328 u8 rsvd1[32];
329 u8 rsvd2[32];
330} __packed;
331
332struct be_cmd_req_mcc_create {
333 struct be_cmd_req_hdr hdr;
334 u16 num_pages;
335 u16 rsvd0;
336 u8 context[sizeof(struct amap_mcc_context) / 8];
337 struct phys_addr pages[8];
338} __packed;
339
340struct be_cmd_resp_mcc_create {
341 struct be_cmd_resp_hdr hdr;
342 u16 id;
343 u16 rsvd0;
344} __packed;
345
6b7c5b94
SP		 346/******************** Create TxQ ***************************/
347#define BE_ETH_TX_RING_TYPE_STANDARD 2
348#define BE_ULP1_NUM 1
349
350/* Pseudo amap definition in which each bit of the actual structure is defined
351 * as a byte: used to calculate offset/shift/mask of each field */
352struct amap_tx_context {
353 u8 rsvd0[16]; /* dword 0 */
354 u8 tx_ring_size[4]; /* dword 0 */
355 u8 rsvd1[26]; /* dword 0 */
356 u8 pci_func_id[8]; /* dword 1 */
357 u8 rsvd2[9]; /* dword 1 */
358 u8 ctx_valid; /* dword 1 */
359 u8 cq_id_send[16]; /* dword 2 */
360 u8 rsvd3[16]; /* dword 2 */
361 u8 rsvd4[32]; /* dword 3 */
362 u8 rsvd5[32]; /* dword 4 */
363 u8 rsvd6[32]; /* dword 5 */
364 u8 rsvd7[32]; /* dword 6 */
365 u8 rsvd8[32]; /* dword 7 */
366 u8 rsvd9[32]; /* dword 8 */
367 u8 rsvd10[32]; /* dword 9 */
368 u8 rsvd11[32]; /* dword 10 */
369 u8 rsvd12[32]; /* dword 11 */
370 u8 rsvd13[32]; /* dword 12 */
371 u8 rsvd14[32]; /* dword 13 */
372 u8 rsvd15[32]; /* dword 14 */
373 u8 rsvd16[32]; /* dword 15 */
374} __packed;
375
376struct be_cmd_req_eth_tx_create {
377 struct be_cmd_req_hdr hdr;
378 u8 num_pages;
379 u8 ulp_num;
380 u8 type;
381 u8 bound_port;
382 u8 context[sizeof(struct amap_tx_context) / 8];
383 struct phys_addr pages[8];
384} __packed;
385
386struct be_cmd_resp_eth_tx_create {
387 struct be_cmd_resp_hdr hdr;
388 u16 cid;
389 u16 rsvd0;
390} __packed;
391
392/******************** Create RxQ ***************************/
393struct be_cmd_req_eth_rx_create {
394 struct be_cmd_req_hdr hdr;
395 u16 cq_id;
396 u8 frag_size;
397 u8 num_pages;
398 struct phys_addr pages[2];
399 u32 interface_id;
400 u16 max_frame_size;
401 u16 rsvd0;
402 u32 rss_queue;
403} __packed;
404
405struct be_cmd_resp_eth_rx_create {
406 struct be_cmd_resp_hdr hdr;
407 u16 id;
408 u8 cpu_id;
409 u8 rsvd0;
410} __packed;
411
412/******************** Q Destroy ***************************/
413/* Type of Queue to be destroyed */
414enum {
415 QTYPE_EQ = 1,
416 QTYPE_CQ,
417 QTYPE_TXQ,
5fb379ee
SP		 418 QTYPE_RXQ,
419 QTYPE_MCCQ
6b7c5b94
SP		 420};
421
422struct be_cmd_req_q_destroy {
423 struct be_cmd_req_hdr hdr;
424 u16 id;
425 u16 bypass_flush; /* valid only for rx q destroy */
426} __packed;
427
428/************ I/f Create (it's actually I/f Config Create)**********/
429
430/* Capability flags for the i/f */
431enum be_if_flags {
432 BE_IF_FLAGS_RSS = 0x4,
433 BE_IF_FLAGS_PROMISCUOUS = 0x8,
434 BE_IF_FLAGS_BROADCAST = 0x10,
435 BE_IF_FLAGS_UNTAGGED = 0x20,
436 BE_IF_FLAGS_ULP = 0x40,
437 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
438 BE_IF_FLAGS_VLAN = 0x100,
439 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
440 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
441 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
442};
443
444/* An RX interface is an object with one or more MAC addresses and
445 * filtering capabilities. */
446struct be_cmd_req_if_create {
447 struct be_cmd_req_hdr hdr;
af901ca1 448 u32 version; /* ignore currently */
6b7c5b94
SP		 449 u32 capability_flags;
450 u32 enable_flags;
451 u8 mac_addr[ETH_ALEN];
452 u8 rsvd0;
453 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
454 u32 vlan_tag; /* not used currently */
455} __packed;
456
457struct be_cmd_resp_if_create {
458 struct be_cmd_resp_hdr hdr;
459 u32 interface_id;
460 u32 pmac_id;
461};
462
463/****** I/f Destroy(it's actually I/f Config Destroy )**********/
464struct be_cmd_req_if_destroy {
465 struct be_cmd_req_hdr hdr;
466 u32 interface_id;
467};
468
469/*************** HW Stats Get **********************************/
470struct be_port_rxf_stats {
471 u32 rx_bytes_lsd; /* dword 0*/
472 u32 rx_bytes_msd; /* dword 1*/
473 u32 rx_total_frames; /* dword 2*/
474 u32 rx_unicast_frames; /* dword 3*/
475 u32 rx_multicast_frames; /* dword 4*/
476 u32 rx_broadcast_frames; /* dword 5*/
477 u32 rx_crc_errors; /* dword 6*/
478 u32 rx_alignment_symbol_errors; /* dword 7*/
479 u32 rx_pause_frames; /* dword 8*/
480 u32 rx_control_frames; /* dword 9*/
481 u32 rx_in_range_errors; /* dword 10*/
482 u32 rx_out_range_errors; /* dword 11*/
483 u32 rx_frame_too_long; /* dword 12*/
484 u32 rx_address_match_errors; /* dword 13*/
485 u32 rx_vlan_mismatch; /* dword 14*/
486 u32 rx_dropped_too_small; /* dword 15*/
487 u32 rx_dropped_too_short; /* dword 16*/
488 u32 rx_dropped_header_too_small; /* dword 17*/
489 u32 rx_dropped_tcp_length; /* dword 18*/
490 u32 rx_dropped_runt; /* dword 19*/
491 u32 rx_64_byte_packets; /* dword 20*/
492 u32 rx_65_127_byte_packets; /* dword 21*/
493 u32 rx_128_256_byte_packets; /* dword 22*/
494 u32 rx_256_511_byte_packets; /* dword 23*/
495 u32 rx_512_1023_byte_packets; /* dword 24*/
496 u32 rx_1024_1518_byte_packets; /* dword 25*/
497 u32 rx_1519_2047_byte_packets; /* dword 26*/
498 u32 rx_2048_4095_byte_packets; /* dword 27*/
499 u32 rx_4096_8191_byte_packets; /* dword 28*/
500 u32 rx_8192_9216_byte_packets; /* dword 29*/
501 u32 rx_ip_checksum_errs; /* dword 30*/
502 u32 rx_tcp_checksum_errs; /* dword 31*/
503 u32 rx_udp_checksum_errs; /* dword 32*/
504 u32 rx_non_rss_packets; /* dword 33*/
505 u32 rx_ipv4_packets; /* dword 34*/
506 u32 rx_ipv6_packets; /* dword 35*/
507 u32 rx_ipv4_bytes_lsd; /* dword 36*/
508 u32 rx_ipv4_bytes_msd; /* dword 37*/
509 u32 rx_ipv6_bytes_lsd; /* dword 38*/
510 u32 rx_ipv6_bytes_msd; /* dword 39*/
511 u32 rx_chute1_packets; /* dword 40*/
512 u32 rx_chute2_packets; /* dword 41*/
513 u32 rx_chute3_packets; /* dword 42*/
514 u32 rx_management_packets; /* dword 43*/
515 u32 rx_switched_unicast_packets; /* dword 44*/
516 u32 rx_switched_multicast_packets; /* dword 45*/
517 u32 rx_switched_broadcast_packets; /* dword 46*/
518 u32 tx_bytes_lsd; /* dword 47*/
519 u32 tx_bytes_msd; /* dword 48*/
520 u32 tx_unicastframes; /* dword 49*/
521 u32 tx_multicastframes; /* dword 50*/
522 u32 tx_broadcastframes; /* dword 51*/
523 u32 tx_pauseframes; /* dword 52*/
524 u32 tx_controlframes; /* dword 53*/
525 u32 tx_64_byte_packets; /* dword 54*/
526 u32 tx_65_127_byte_packets; /* dword 55*/
527 u32 tx_128_256_byte_packets; /* dword 56*/
528 u32 tx_256_511_byte_packets; /* dword 57*/
529 u32 tx_512_1023_byte_packets; /* dword 58*/
530 u32 tx_1024_1518_byte_packets; /* dword 59*/
531 u32 tx_1519_2047_byte_packets; /* dword 60*/
532 u32 tx_2048_4095_byte_packets; /* dword 61*/
533 u32 tx_4096_8191_byte_packets; /* dword 62*/
534 u32 tx_8192_9216_byte_packets; /* dword 63*/
535 u32 rx_fifo_overflow; /* dword 64*/
536 u32 rx_input_fifo_overflow; /* dword 65*/
537};
538
539struct be_rxf_stats {
540 struct be_port_rxf_stats port[2];
541 u32 rx_drops_no_pbuf; /* dword 132*/
542 u32 rx_drops_no_txpb; /* dword 133*/
543 u32 rx_drops_no_erx_descr; /* dword 134*/
544 u32 rx_drops_no_tpre_descr; /* dword 135*/
545 u32 management_rx_port_packets; /* dword 136*/
546 u32 management_rx_port_bytes; /* dword 137*/
547 u32 management_rx_port_pause_frames; /* dword 138*/
548 u32 management_rx_port_errors; /* dword 139*/
549 u32 management_tx_port_packets; /* dword 140*/
550 u32 management_tx_port_bytes; /* dword 141*/
551 u32 management_tx_port_pause; /* dword 142*/
552 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
553 u32 rx_drops_too_many_frags; /* dword 144*/
554 u32 rx_drops_invalid_ring; /* dword 145*/
555 u32 forwarded_packets; /* dword 146*/
556 u32 rx_drops_mtu; /* dword 147*/
557 u32 rsvd0[15];
558};
559
560struct be_erx_stats {
561 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
562 u32 debug_wdma_sent_hold; /* dword 44*/
563 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
564 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
565 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
566};
567
568struct be_hw_stats {
569 struct be_rxf_stats rxf;
570 u32 rsvd[48];
571 struct be_erx_stats erx;
572};
573
574struct be_cmd_req_get_stats {
575 struct be_cmd_req_hdr hdr;
576 u8 rsvd[sizeof(struct be_hw_stats)];
577};
578
579struct be_cmd_resp_get_stats {
580 struct be_cmd_resp_hdr hdr;
581 struct be_hw_stats hw_stats;
582};
583
584struct be_cmd_req_vlan_config {
585 struct be_cmd_req_hdr hdr;
586 u8 interface_id;
587 u8 promiscuous;
588 u8 untagged;
589 u8 num_vlan;
590 u16 normal_vlan[64];
591} __packed;
592
593struct be_cmd_req_promiscuous_config {
594 struct be_cmd_req_hdr hdr;
595 u8 port0_promiscuous;
596 u8 port1_promiscuous;
597 u16 rsvd0;
598} __packed;
599
e7b909a6
SP		 600/******************** Multicast MAC Config *******************/
601#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
6b7c5b94
SP		 602struct macaddr {
603 u8 byte[ETH_ALEN];
604};
605
606struct be_cmd_req_mcast_mac_config {
607 struct be_cmd_req_hdr hdr;
608 u16 num_mac;
609 u8 promiscuous;
610 u8 interface_id;
e7b909a6 611 struct macaddr mac[BE_MAX_MC];
6b7c5b94
SP		 612} __packed;
613
614static inline struct be_hw_stats *
615hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
616{
617 return &cmd->hw_stats;
618}
619
620/******************** Link Status Query *******************/
621struct be_cmd_req_link_status {
622 struct be_cmd_req_hdr hdr;
623 u32 rsvd;
624};
625
6b7c5b94
SP		 626enum {
627 PHY_LINK_DUPLEX_NONE = 0x0,
628 PHY_LINK_DUPLEX_HALF = 0x1,
629 PHY_LINK_DUPLEX_FULL = 0x2
630};
631
632enum {
633 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
634 PHY_LINK_SPEED_10MBPS = 0x1,
635 PHY_LINK_SPEED_100MBPS = 0x2,
636 PHY_LINK_SPEED_1GBPS = 0x3,
637 PHY_LINK_SPEED_10GBPS = 0x4
638};
639
640struct be_cmd_resp_link_status {
641 struct be_cmd_resp_hdr hdr;
642 u8 physical_port;
643 u8 mac_duplex;
644 u8 mac_speed;
645 u8 mac_fault;
646 u8 mgmt_mac_duplex;
647 u8 mgmt_mac_speed;
0388f251
SB		 648 u16 link_speed;
649 u32 rsvd0;
6b7c5b94
SP		 650} __packed;
651
0388f251
SB		 652/******************** Port Identification ***************************/
653/* Identifies the type of port attached to NIC */
654struct be_cmd_req_port_type {
655 struct be_cmd_req_hdr hdr;
656 u32 page_num;
657 u32 port;
658};
659
660enum {
661 TR_PAGE_A0 = 0xa0,
662 TR_PAGE_A2 = 0xa2
663};
664
665struct be_cmd_resp_port_type {
666 struct be_cmd_resp_hdr hdr;
667 u32 page_num;
668 u32 port;
669 struct data {
670 u8 identifier;
671 u8 identifier_ext;
672 u8 connector;
673 u8 transceiver[8];
674 u8 rsvd0[3];
675 u8 length_km;
676 u8 length_hm;
677 u8 length_om1;
678 u8 length_om2;
679 u8 length_cu;
680 u8 length_cu_m;
681 u8 vendor_name[16];
682 u8 rsvd;
683 u8 vendor_oui[3];
684 u8 vendor_pn[16];
685 u8 vendor_rev[4];
686 } data;
687};
688
6b7c5b94 689/******************** Get FW Version *******************/
6b7c5b94
SP		 690struct be_cmd_req_get_fw_version {
691 struct be_cmd_req_hdr hdr;
692 u8 rsvd0[FW_VER_LEN];
693 u8 rsvd1[FW_VER_LEN];
694} __packed;
695
696struct be_cmd_resp_get_fw_version {
697 struct be_cmd_resp_hdr hdr;
698 u8 firmware_version_string[FW_VER_LEN];
699 u8 fw_on_flash_version_string[FW_VER_LEN];
700} __packed;
701
702/******************** Set Flow Contrl *******************/
703struct be_cmd_req_set_flow_control {
704 struct be_cmd_req_hdr hdr;
705 u16 tx_flow_control;
706 u16 rx_flow_control;
707} __packed;
708
709/******************** Get Flow Contrl *******************/
710struct be_cmd_req_get_flow_control {
711 struct be_cmd_req_hdr hdr;
712 u32 rsvd;
713};
714
715struct be_cmd_resp_get_flow_control {
716 struct be_cmd_resp_hdr hdr;
717 u16 tx_flow_control;
718 u16 rx_flow_control;
719} __packed;
720
721/******************** Modify EQ Delay *******************/
722struct be_cmd_req_modify_eq_delay {
723 struct be_cmd_req_hdr hdr;
724 u32 num_eq;
725 struct {
726 u32 eq_id;
727 u32 phase;
728 u32 delay_multiplier;
729 } delay[8];
730} __packed;
731
732struct be_cmd_resp_modify_eq_delay {
733 struct be_cmd_resp_hdr hdr;
734 u32 rsvd0;
735} __packed;
736
737/******************** Get FW Config *******************/
738struct be_cmd_req_query_fw_cfg {
739 struct be_cmd_req_hdr hdr;
740 u32 rsvd[30];
741};
742
743struct be_cmd_resp_query_fw_cfg {
744 struct be_cmd_resp_hdr hdr;
745 u32 be_config_number;
746 u32 asic_revision;
747 u32 phys_port;
84517482 748 u32 function_cap;
6b7c5b94
SP		 749 u32 rsvd[26];
750};
751
fad9ab2c
SB		 752/******************** Port Beacon ***************************/
753
754#define BEACON_STATE_ENABLED 0x1
755#define BEACON_STATE_DISABLED 0x0
756
757struct be_cmd_req_enable_disable_beacon {
758 struct be_cmd_req_hdr hdr;
759 u8 port_num;
760 u8 beacon_state;
761 u8 beacon_duration;
762 u8 status_duration;
763} __packed;
764
765struct be_cmd_resp_enable_disable_beacon {
766 struct be_cmd_resp_hdr resp_hdr;
767 u32 rsvd0;
768} __packed;
769
770struct be_cmd_req_get_beacon_state {
771 struct be_cmd_req_hdr hdr;
772 u8 port_num;
773 u8 rsvd0;
774 u16 rsvd1;
775} __packed;
776
777struct be_cmd_resp_get_beacon_state {
778 struct be_cmd_resp_hdr resp_hdr;
779 u8 beacon_state;
780 u8 rsvd0[3];
781} __packed;
782
84517482
AK		 783/****************** Firmware Flash ******************/
784struct flashrom_params {
785 u32 op_code;
786 u32 op_type;
787 u32 data_buf_size;
788 u32 offset;
789 u8 data_buf[4];
790};
791
792struct be_cmd_write_flashrom {
793 struct be_cmd_req_hdr hdr;
794 struct flashrom_params params;
795};
796
71d8d1b5
AK		 797/************************ WOL *******************************/
798struct be_cmd_req_acpi_wol_magic_config{
799 struct be_cmd_req_hdr hdr;
800 u32 rsvd0[145];
801 u8 magic_mac[6];
802 u8 rsvd2[2];
803} __packed;
804
ff33a6e2
S		 805/********************** LoopBack test *********************/
806struct be_cmd_req_loopback_test {
807 struct be_cmd_req_hdr hdr;
808 u32 loopback_type;
809 u32 num_pkts;
810 u64 pattern;
811 u32 src_port;
812 u32 dest_port;
813 u32 pkt_size;
814};
815
816struct be_cmd_resp_loopback_test {
817 struct be_cmd_resp_hdr resp_hdr;
818 u32 status;
819 u32 num_txfer;
820 u32 num_rx;
821 u32 miscomp_off;
822 u32 ticks_compl;
823};
824
825/********************** DDR DMA test *********************/
826struct be_cmd_req_ddrdma_test {
827 struct be_cmd_req_hdr hdr;
828 u64 pattern;
829 u32 byte_count;
830 u32 rsvd0;
831 u8 snd_buff[4096];
832 u8 rsvd1[4096];
833};
834
835struct be_cmd_resp_ddrdma_test {
836 struct be_cmd_resp_hdr hdr;
837 u64 pattern;
838 u32 byte_cnt;
839 u32 snd_err;
840 u8 rsvd0[4096];
841 u8 rcv_buff[4096];
842};
843
368c0ca2
SB		 844/*********************** SEEPROM Read ***********************/
845
846#define BE_READ_SEEPROM_LEN 1024
847struct be_cmd_req_seeprom_read {
848 struct be_cmd_req_hdr hdr;
849 u8 rsvd0[BE_READ_SEEPROM_LEN];
850};
851
852struct be_cmd_resp_seeprom_read {
853 struct be_cmd_req_hdr hdr;
854 u8 seeprom_data[BE_READ_SEEPROM_LEN];
855};
856
8788fdc2
SP		 857extern int be_pci_fnum_get(struct be_adapter *adapter);
858extern int be_cmd_POST(struct be_adapter *adapter);
859extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 860 u8 type, bool permanent, u32 if_handle);
8788fdc2 861extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
6b7c5b94 862 u32 if_id, u32 *pmac_id);
8788fdc2 863extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
73d540f2
SP		 864extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
865 u32 en_flags, u8 *mac, bool pmac_invalid,
866 u32 *if_handle, u32 *pmac_id);
8788fdc2
SP		 867extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
868extern int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94 869 struct be_queue_info *eq, int eq_delay);
8788fdc2 870extern int be_cmd_cq_create(struct be_adapter *adapter,
6b7c5b94
SP		 871 struct be_queue_info *cq, struct be_queue_info *eq,
872 bool sol_evts, bool no_delay,
873 int num_cqe_dma_coalesce);
8788fdc2 874extern int be_cmd_mccq_create(struct be_adapter *adapter,
5fb379ee
SP		 875 struct be_queue_info *mccq,
876 struct be_queue_info *cq);
8788fdc2 877extern int be_cmd_txq_create(struct be_adapter *adapter,
6b7c5b94
SP		 878 struct be_queue_info *txq,
879 struct be_queue_info *cq);
8788fdc2 880extern int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94
SP		 881 struct be_queue_info *rxq, u16 cq_id,
882 u16 frag_size, u16 max_frame_size, u32 if_id,
883 u32 rss);
8788fdc2 884extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94 885 int type);
8788fdc2 886extern int be_cmd_link_status_query(struct be_adapter *adapter,
0388f251 887 bool *link_up, u8 *mac_speed, u16 *link_speed);
8788fdc2
SP		 888extern int be_cmd_reset(struct be_adapter *adapter);
889extern int be_cmd_get_stats(struct be_adapter *adapter,
6b7c5b94 890 struct be_dma_mem *nonemb_cmd);
8788fdc2 891extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
6b7c5b94 892
8788fdc2
SP		 893extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
894extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
6b7c5b94
SP		 895 u16 *vtag_array, u32 num, bool untagged,
896 bool promiscuous);
8788fdc2 897extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
6b7c5b94 898 u8 port_num, bool en);
8788fdc2 899extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
e7b909a6
SP		 900 struct dev_mc_list *mc_list, u32 mc_count,
901 struct be_dma_mem *mem);
8788fdc2 902extern int be_cmd_set_flow_control(struct be_adapter *adapter,
6b7c5b94 903 u32 tx_fc, u32 rx_fc);
8788fdc2 904extern int be_cmd_get_flow_control(struct be_adapter *adapter,
6b7c5b94 905 u32 *tx_fc, u32 *rx_fc);
dcb9b564
AK		 906extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
907 u32 *port_num, u32 *cap);
14074eab 908extern int be_cmd_reset_function(struct be_adapter *adapter);
b31c50a7 909extern int be_process_mcc(struct be_adapter *adapter);
fad9ab2c
SB		 910extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
911 u8 port_num, u8 beacon, u8 status, u8 state);
912extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
913 u8 port_num, u32 *state);
0388f251
SB		 914extern int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
915 u8 *connector);
84517482
AK		 916extern int be_cmd_write_flashrom(struct be_adapter *adapter,
917 struct be_dma_mem *cmd, u32 flash_oper,
918 u32 flash_opcode, u32 buf_size);
fa9a6fed 919extern int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc);
71d8d1b5
AK		 920extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
921 struct be_dma_mem *nonemb_cmd);
2243e2e9
SP		 922extern int be_cmd_fw_init(struct be_adapter *adapter);
923extern int be_cmd_fw_clean(struct be_adapter *adapter);
ff33a6e2
S		 924extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
925 u32 loopback_type, u32 pkt_size,
926 u32 num_pkts, u64 pattern);
927extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
928 u32 byte_cnt, struct be_dma_mem *cmd);
368c0ca2
SB		 929extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
930 struct be_dma_mem *nonemb_cmd);
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