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6b7c5b94 | 1 | /* |
294aedcf | 2 | * Copyright (C) 2005 - 2010 ServerEngines |
6b7c5b94 SP |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
11 | * linux-drivers@serverengines.com | |
12 | * | |
13 | * ServerEngines | |
14 | * 209 N. Fair Oaks Ave | |
15 | * Sunnyvale, CA 94085 | |
16 | */ | |
17 | ||
18 | #include "be.h" | |
8788fdc2 | 19 | #include "be_cmds.h" |
6b7c5b94 | 20 | |
8788fdc2 | 21 | static void be_mcc_notify(struct be_adapter *adapter) |
5fb379ee | 22 | { |
8788fdc2 | 23 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
5fb379ee SP |
24 | u32 val = 0; |
25 | ||
26 | val |= mccq->id & DB_MCCQ_RING_ID_MASK; | |
27 | val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; | |
8788fdc2 | 28 | iowrite32(val, adapter->db + DB_MCCQ_OFFSET); |
5fb379ee SP |
29 | } |
30 | ||
31 | /* To check if valid bit is set, check the entire word as we don't know | |
32 | * the endianness of the data (old entry is host endian while a new entry is | |
33 | * little endian) */ | |
efd2e40a | 34 | static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) |
5fb379ee SP |
35 | { |
36 | if (compl->flags != 0) { | |
37 | compl->flags = le32_to_cpu(compl->flags); | |
38 | BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0); | |
39 | return true; | |
40 | } else { | |
41 | return false; | |
42 | } | |
43 | } | |
44 | ||
45 | /* Need to reset the entire word that houses the valid bit */ | |
efd2e40a | 46 | static inline void be_mcc_compl_use(struct be_mcc_compl *compl) |
5fb379ee SP |
47 | { |
48 | compl->flags = 0; | |
49 | } | |
50 | ||
8788fdc2 | 51 | static int be_mcc_compl_process(struct be_adapter *adapter, |
efd2e40a | 52 | struct be_mcc_compl *compl) |
5fb379ee SP |
53 | { |
54 | u16 compl_status, extd_status; | |
55 | ||
56 | /* Just swap the status to host endian; mcc tag is opaquely copied | |
57 | * from mcc_wrb */ | |
58 | be_dws_le_to_cpu(compl, 4); | |
59 | ||
60 | compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & | |
61 | CQE_STATUS_COMPL_MASK; | |
b31c50a7 SP |
62 | if (compl_status == MCC_STATUS_SUCCESS) { |
63 | if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) { | |
64 | struct be_cmd_resp_get_stats *resp = | |
65 | adapter->stats.cmd.va; | |
66 | be_dws_le_to_cpu(&resp->hw_stats, | |
67 | sizeof(resp->hw_stats)); | |
68 | netdev_stats_update(adapter); | |
69 | } | |
70 | } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) { | |
5fb379ee SP |
71 | extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & |
72 | CQE_STATUS_EXTD_MASK; | |
5f0b849e | 73 | dev_warn(&adapter->pdev->dev, |
d744b44e AK |
74 | "Error in cmd completion - opcode %d, compl %d, extd %d\n", |
75 | compl->tag0, compl_status, extd_status); | |
5fb379ee | 76 | } |
b31c50a7 | 77 | return compl_status; |
5fb379ee SP |
78 | } |
79 | ||
a8f447bd | 80 | /* Link state evt is a string of bytes; no need for endian swapping */ |
8788fdc2 | 81 | static void be_async_link_state_process(struct be_adapter *adapter, |
a8f447bd SP |
82 | struct be_async_event_link_state *evt) |
83 | { | |
8788fdc2 SP |
84 | be_link_status_update(adapter, |
85 | evt->port_link_status == ASYNC_EVENT_LINK_UP); | |
a8f447bd SP |
86 | } |
87 | ||
88 | static inline bool is_link_state_evt(u32 trailer) | |
89 | { | |
90 | return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & | |
91 | ASYNC_TRAILER_EVENT_CODE_MASK) == | |
92 | ASYNC_EVENT_CODE_LINK_STATE); | |
93 | } | |
5fb379ee | 94 | |
efd2e40a | 95 | static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter) |
5fb379ee | 96 | { |
8788fdc2 | 97 | struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq; |
efd2e40a | 98 | struct be_mcc_compl *compl = queue_tail_node(mcc_cq); |
5fb379ee SP |
99 | |
100 | if (be_mcc_compl_is_new(compl)) { | |
101 | queue_tail_inc(mcc_cq); | |
102 | return compl; | |
103 | } | |
104 | return NULL; | |
105 | } | |
106 | ||
7a1e9b20 SP |
107 | void be_async_mcc_enable(struct be_adapter *adapter) |
108 | { | |
109 | spin_lock_bh(&adapter->mcc_cq_lock); | |
110 | ||
111 | be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0); | |
112 | adapter->mcc_obj.rearm_cq = true; | |
113 | ||
114 | spin_unlock_bh(&adapter->mcc_cq_lock); | |
115 | } | |
116 | ||
117 | void be_async_mcc_disable(struct be_adapter *adapter) | |
118 | { | |
119 | adapter->mcc_obj.rearm_cq = false; | |
120 | } | |
121 | ||
f31e50a8 | 122 | int be_process_mcc(struct be_adapter *adapter, int *status) |
5fb379ee | 123 | { |
efd2e40a | 124 | struct be_mcc_compl *compl; |
f31e50a8 | 125 | int num = 0; |
7a1e9b20 | 126 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; |
5fb379ee | 127 | |
8788fdc2 SP |
128 | spin_lock_bh(&adapter->mcc_cq_lock); |
129 | while ((compl = be_mcc_compl_get(adapter))) { | |
a8f447bd SP |
130 | if (compl->flags & CQE_FLAGS_ASYNC_MASK) { |
131 | /* Interpret flags as an async trailer */ | |
132 | BUG_ON(!is_link_state_evt(compl->flags)); | |
133 | ||
134 | /* Interpret compl as a async link evt */ | |
8788fdc2 | 135 | be_async_link_state_process(adapter, |
a8f447bd | 136 | (struct be_async_event_link_state *) compl); |
b31c50a7 | 137 | } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { |
f31e50a8 | 138 | *status = be_mcc_compl_process(adapter, compl); |
7a1e9b20 | 139 | atomic_dec(&mcc_obj->q.used); |
5fb379ee SP |
140 | } |
141 | be_mcc_compl_use(compl); | |
142 | num++; | |
143 | } | |
b31c50a7 | 144 | |
8788fdc2 | 145 | spin_unlock_bh(&adapter->mcc_cq_lock); |
f31e50a8 | 146 | return num; |
5fb379ee SP |
147 | } |
148 | ||
6ac7b687 | 149 | /* Wait till no more pending mcc requests are present */ |
b31c50a7 | 150 | static int be_mcc_wait_compl(struct be_adapter *adapter) |
6ac7b687 | 151 | { |
b31c50a7 | 152 | #define mcc_timeout 120000 /* 12s timeout */ |
f31e50a8 SP |
153 | int i, num, status = 0; |
154 | struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; | |
155 | ||
6ac7b687 | 156 | for (i = 0; i < mcc_timeout; i++) { |
f31e50a8 SP |
157 | num = be_process_mcc(adapter, &status); |
158 | if (num) | |
159 | be_cq_notify(adapter, mcc_obj->cq.id, | |
160 | mcc_obj->rearm_cq, num); | |
b31c50a7 | 161 | |
f31e50a8 | 162 | if (atomic_read(&mcc_obj->q.used) == 0) |
6ac7b687 SP |
163 | break; |
164 | udelay(100); | |
165 | } | |
b31c50a7 | 166 | if (i == mcc_timeout) { |
5f0b849e | 167 | dev_err(&adapter->pdev->dev, "mccq poll timed out\n"); |
b31c50a7 SP |
168 | return -1; |
169 | } | |
f31e50a8 | 170 | return status; |
6ac7b687 SP |
171 | } |
172 | ||
173 | /* Notify MCC requests and wait for completion */ | |
b31c50a7 | 174 | static int be_mcc_notify_wait(struct be_adapter *adapter) |
6ac7b687 | 175 | { |
8788fdc2 | 176 | be_mcc_notify(adapter); |
b31c50a7 | 177 | return be_mcc_wait_compl(adapter); |
6ac7b687 SP |
178 | } |
179 | ||
5f0b849e | 180 | static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) |
6b7c5b94 SP |
181 | { |
182 | int cnt = 0, wait = 5; | |
183 | u32 ready; | |
184 | ||
185 | do { | |
cf588477 SP |
186 | ready = ioread32(db); |
187 | if (ready == 0xffffffff) { | |
188 | dev_err(&adapter->pdev->dev, | |
189 | "pci slot disconnected\n"); | |
190 | return -1; | |
191 | } | |
192 | ||
193 | ready &= MPU_MAILBOX_DB_RDY_MASK; | |
6b7c5b94 SP |
194 | if (ready) |
195 | break; | |
196 | ||
84517482 | 197 | if (cnt > 4000000) { |
5f0b849e | 198 | dev_err(&adapter->pdev->dev, "mbox poll timed out\n"); |
6b7c5b94 SP |
199 | return -1; |
200 | } | |
201 | ||
202 | if (cnt > 50) | |
203 | wait = 200; | |
204 | cnt += wait; | |
205 | udelay(wait); | |
206 | } while (true); | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | /* | |
212 | * Insert the mailbox address into the doorbell in two steps | |
5fb379ee | 213 | * Polls on the mbox doorbell till a command completion (or a timeout) occurs |
6b7c5b94 | 214 | */ |
b31c50a7 | 215 | static int be_mbox_notify_wait(struct be_adapter *adapter) |
6b7c5b94 SP |
216 | { |
217 | int status; | |
6b7c5b94 | 218 | u32 val = 0; |
8788fdc2 SP |
219 | void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET; |
220 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; | |
6b7c5b94 | 221 | struct be_mcc_mailbox *mbox = mbox_mem->va; |
efd2e40a | 222 | struct be_mcc_compl *compl = &mbox->compl; |
6b7c5b94 | 223 | |
cf588477 SP |
224 | /* wait for ready to be set */ |
225 | status = be_mbox_db_ready_wait(adapter, db); | |
226 | if (status != 0) | |
227 | return status; | |
228 | ||
6b7c5b94 SP |
229 | val |= MPU_MAILBOX_DB_HI_MASK; |
230 | /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ | |
231 | val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; | |
232 | iowrite32(val, db); | |
233 | ||
234 | /* wait for ready to be set */ | |
5f0b849e | 235 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
236 | if (status != 0) |
237 | return status; | |
238 | ||
239 | val = 0; | |
6b7c5b94 SP |
240 | /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ |
241 | val |= (u32)(mbox_mem->dma >> 4) << 2; | |
242 | iowrite32(val, db); | |
243 | ||
5f0b849e | 244 | status = be_mbox_db_ready_wait(adapter, db); |
6b7c5b94 SP |
245 | if (status != 0) |
246 | return status; | |
247 | ||
5fb379ee | 248 | /* A cq entry has been made now */ |
efd2e40a SP |
249 | if (be_mcc_compl_is_new(compl)) { |
250 | status = be_mcc_compl_process(adapter, &mbox->compl); | |
251 | be_mcc_compl_use(compl); | |
5fb379ee SP |
252 | if (status) |
253 | return status; | |
254 | } else { | |
5f0b849e | 255 | dev_err(&adapter->pdev->dev, "invalid mailbox completion\n"); |
6b7c5b94 SP |
256 | return -1; |
257 | } | |
5fb379ee | 258 | return 0; |
6b7c5b94 SP |
259 | } |
260 | ||
8788fdc2 | 261 | static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage) |
6b7c5b94 | 262 | { |
8788fdc2 | 263 | u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET); |
6b7c5b94 SP |
264 | |
265 | *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK; | |
266 | if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK) | |
267 | return -1; | |
268 | else | |
269 | return 0; | |
270 | } | |
271 | ||
8788fdc2 | 272 | int be_cmd_POST(struct be_adapter *adapter) |
6b7c5b94 | 273 | { |
43a04fdc SP |
274 | u16 stage; |
275 | int status, timeout = 0; | |
6b7c5b94 | 276 | |
43a04fdc SP |
277 | do { |
278 | status = be_POST_stage_get(adapter, &stage); | |
279 | if (status) { | |
280 | dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n", | |
281 | stage); | |
282 | return -1; | |
283 | } else if (stage != POST_STAGE_ARMFW_RDY) { | |
284 | set_current_state(TASK_INTERRUPTIBLE); | |
285 | schedule_timeout(2 * HZ); | |
286 | timeout += 2; | |
287 | } else { | |
288 | return 0; | |
289 | } | |
290 | } while (timeout < 20); | |
6b7c5b94 | 291 | |
43a04fdc SP |
292 | dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage); |
293 | return -1; | |
6b7c5b94 SP |
294 | } |
295 | ||
296 | static inline void *embedded_payload(struct be_mcc_wrb *wrb) | |
297 | { | |
298 | return wrb->payload.embedded_payload; | |
299 | } | |
300 | ||
301 | static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) | |
302 | { | |
303 | return &wrb->payload.sgl[0]; | |
304 | } | |
305 | ||
306 | /* Don't touch the hdr after it's prepared */ | |
307 | static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, | |
d744b44e | 308 | bool embedded, u8 sge_cnt, u32 opcode) |
6b7c5b94 SP |
309 | { |
310 | if (embedded) | |
311 | wrb->embedded |= MCC_WRB_EMBEDDED_MASK; | |
312 | else | |
313 | wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << | |
314 | MCC_WRB_SGE_CNT_SHIFT; | |
315 | wrb->payload_length = payload_len; | |
d744b44e | 316 | wrb->tag0 = opcode; |
fa4281bb | 317 | be_dws_cpu_to_le(wrb, 8); |
6b7c5b94 SP |
318 | } |
319 | ||
320 | /* Don't touch the hdr after it's prepared */ | |
321 | static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, | |
322 | u8 subsystem, u8 opcode, int cmd_len) | |
323 | { | |
324 | req_hdr->opcode = opcode; | |
325 | req_hdr->subsystem = subsystem; | |
326 | req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); | |
07793d33 | 327 | req_hdr->version = 0; |
6b7c5b94 SP |
328 | } |
329 | ||
330 | static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, | |
331 | struct be_dma_mem *mem) | |
332 | { | |
333 | int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); | |
334 | u64 dma = (u64)mem->dma; | |
335 | ||
336 | for (i = 0; i < buf_pages; i++) { | |
337 | pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); | |
338 | pages[i].hi = cpu_to_le32(upper_32_bits(dma)); | |
339 | dma += PAGE_SIZE_4K; | |
340 | } | |
341 | } | |
342 | ||
343 | /* Converts interrupt delay in microseconds to multiplier value */ | |
344 | static u32 eq_delay_to_mult(u32 usec_delay) | |
345 | { | |
346 | #define MAX_INTR_RATE 651042 | |
347 | const u32 round = 10; | |
348 | u32 multiplier; | |
349 | ||
350 | if (usec_delay == 0) | |
351 | multiplier = 0; | |
352 | else { | |
353 | u32 interrupt_rate = 1000000 / usec_delay; | |
354 | /* Max delay, corresponding to the lowest interrupt rate */ | |
355 | if (interrupt_rate == 0) | |
356 | multiplier = 1023; | |
357 | else { | |
358 | multiplier = (MAX_INTR_RATE - interrupt_rate) * round; | |
359 | multiplier /= interrupt_rate; | |
360 | /* Round the multiplier to the closest value.*/ | |
361 | multiplier = (multiplier + round/2) / round; | |
362 | multiplier = min(multiplier, (u32)1023); | |
363 | } | |
364 | } | |
365 | return multiplier; | |
366 | } | |
367 | ||
b31c50a7 | 368 | static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter) |
6b7c5b94 | 369 | { |
b31c50a7 SP |
370 | struct be_dma_mem *mbox_mem = &adapter->mbox_mem; |
371 | struct be_mcc_wrb *wrb | |
372 | = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; | |
373 | memset(wrb, 0, sizeof(*wrb)); | |
374 | return wrb; | |
6b7c5b94 SP |
375 | } |
376 | ||
b31c50a7 | 377 | static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter) |
5fb379ee | 378 | { |
b31c50a7 SP |
379 | struct be_queue_info *mccq = &adapter->mcc_obj.q; |
380 | struct be_mcc_wrb *wrb; | |
381 | ||
713d0394 SP |
382 | if (atomic_read(&mccq->used) >= mccq->len) { |
383 | dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n"); | |
384 | return NULL; | |
385 | } | |
386 | ||
b31c50a7 SP |
387 | wrb = queue_head_node(mccq); |
388 | queue_head_inc(mccq); | |
389 | atomic_inc(&mccq->used); | |
390 | memset(wrb, 0, sizeof(*wrb)); | |
5fb379ee SP |
391 | return wrb; |
392 | } | |
393 | ||
2243e2e9 SP |
394 | /* Tell fw we're about to start firing cmds by writing a |
395 | * special pattern across the wrb hdr; uses mbox | |
396 | */ | |
397 | int be_cmd_fw_init(struct be_adapter *adapter) | |
398 | { | |
399 | u8 *wrb; | |
400 | int status; | |
401 | ||
402 | spin_lock(&adapter->mbox_lock); | |
403 | ||
404 | wrb = (u8 *)wrb_from_mbox(adapter); | |
405 | *wrb++ = 0xFF; | |
406 | *wrb++ = 0x12; | |
407 | *wrb++ = 0x34; | |
408 | *wrb++ = 0xFF; | |
409 | *wrb++ = 0xFF; | |
410 | *wrb++ = 0x56; | |
411 | *wrb++ = 0x78; | |
412 | *wrb = 0xFF; | |
413 | ||
414 | status = be_mbox_notify_wait(adapter); | |
415 | ||
416 | spin_unlock(&adapter->mbox_lock); | |
417 | return status; | |
418 | } | |
419 | ||
420 | /* Tell fw we're done with firing cmds by writing a | |
421 | * special pattern across the wrb hdr; uses mbox | |
422 | */ | |
423 | int be_cmd_fw_clean(struct be_adapter *adapter) | |
424 | { | |
425 | u8 *wrb; | |
426 | int status; | |
427 | ||
cf588477 SP |
428 | if (adapter->eeh_err) |
429 | return -EIO; | |
430 | ||
2243e2e9 SP |
431 | spin_lock(&adapter->mbox_lock); |
432 | ||
433 | wrb = (u8 *)wrb_from_mbox(adapter); | |
434 | *wrb++ = 0xFF; | |
435 | *wrb++ = 0xAA; | |
436 | *wrb++ = 0xBB; | |
437 | *wrb++ = 0xFF; | |
438 | *wrb++ = 0xFF; | |
439 | *wrb++ = 0xCC; | |
440 | *wrb++ = 0xDD; | |
441 | *wrb = 0xFF; | |
442 | ||
443 | status = be_mbox_notify_wait(adapter); | |
444 | ||
445 | spin_unlock(&adapter->mbox_lock); | |
446 | return status; | |
447 | } | |
8788fdc2 | 448 | int be_cmd_eq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
449 | struct be_queue_info *eq, int eq_delay) |
450 | { | |
b31c50a7 SP |
451 | struct be_mcc_wrb *wrb; |
452 | struct be_cmd_req_eq_create *req; | |
6b7c5b94 SP |
453 | struct be_dma_mem *q_mem = &eq->dma_mem; |
454 | int status; | |
455 | ||
8788fdc2 | 456 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
457 | |
458 | wrb = wrb_from_mbox(adapter); | |
459 | req = embedded_payload(wrb); | |
6b7c5b94 | 460 | |
d744b44e | 461 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE); |
6b7c5b94 SP |
462 | |
463 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
464 | OPCODE_COMMON_EQ_CREATE, sizeof(*req)); | |
465 | ||
466 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
467 | ||
6b7c5b94 SP |
468 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); |
469 | /* 4byte eqe*/ | |
470 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); | |
471 | AMAP_SET_BITS(struct amap_eq_context, count, req->context, | |
472 | __ilog2_u32(eq->len/256)); | |
473 | AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, | |
474 | eq_delay_to_mult(eq_delay)); | |
475 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | |
476 | ||
477 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
478 | ||
b31c50a7 | 479 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 480 | if (!status) { |
b31c50a7 | 481 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
482 | eq->id = le16_to_cpu(resp->eq_id); |
483 | eq->created = true; | |
484 | } | |
b31c50a7 | 485 | |
8788fdc2 | 486 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
487 | return status; |
488 | } | |
489 | ||
b31c50a7 | 490 | /* Uses mbox */ |
8788fdc2 | 491 | int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, |
6b7c5b94 SP |
492 | u8 type, bool permanent, u32 if_handle) |
493 | { | |
b31c50a7 SP |
494 | struct be_mcc_wrb *wrb; |
495 | struct be_cmd_req_mac_query *req; | |
6b7c5b94 SP |
496 | int status; |
497 | ||
8788fdc2 | 498 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
499 | |
500 | wrb = wrb_from_mbox(adapter); | |
501 | req = embedded_payload(wrb); | |
6b7c5b94 | 502 | |
d744b44e AK |
503 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
504 | OPCODE_COMMON_NTWK_MAC_QUERY); | |
6b7c5b94 SP |
505 | |
506 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
507 | OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req)); | |
508 | ||
509 | req->type = type; | |
510 | if (permanent) { | |
511 | req->permanent = 1; | |
512 | } else { | |
b31c50a7 | 513 | req->if_id = cpu_to_le16((u16) if_handle); |
6b7c5b94 SP |
514 | req->permanent = 0; |
515 | } | |
516 | ||
b31c50a7 SP |
517 | status = be_mbox_notify_wait(adapter); |
518 | if (!status) { | |
519 | struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); | |
6b7c5b94 | 520 | memcpy(mac_addr, resp->mac.addr, ETH_ALEN); |
b31c50a7 | 521 | } |
6b7c5b94 | 522 | |
8788fdc2 | 523 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
524 | return status; |
525 | } | |
526 | ||
b31c50a7 | 527 | /* Uses synchronous MCCQ */ |
8788fdc2 | 528 | int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, |
6b7c5b94 SP |
529 | u32 if_id, u32 *pmac_id) |
530 | { | |
b31c50a7 SP |
531 | struct be_mcc_wrb *wrb; |
532 | struct be_cmd_req_pmac_add *req; | |
6b7c5b94 SP |
533 | int status; |
534 | ||
b31c50a7 SP |
535 | spin_lock_bh(&adapter->mcc_lock); |
536 | ||
537 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
538 | if (!wrb) { |
539 | status = -EBUSY; | |
540 | goto err; | |
541 | } | |
b31c50a7 | 542 | req = embedded_payload(wrb); |
6b7c5b94 | 543 | |
d744b44e AK |
544 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
545 | OPCODE_COMMON_NTWK_PMAC_ADD); | |
6b7c5b94 SP |
546 | |
547 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
548 | OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req)); | |
549 | ||
550 | req->if_id = cpu_to_le32(if_id); | |
551 | memcpy(req->mac_address, mac_addr, ETH_ALEN); | |
552 | ||
b31c50a7 | 553 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
554 | if (!status) { |
555 | struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); | |
556 | *pmac_id = le32_to_cpu(resp->pmac_id); | |
557 | } | |
558 | ||
713d0394 | 559 | err: |
b31c50a7 | 560 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
561 | return status; |
562 | } | |
563 | ||
b31c50a7 | 564 | /* Uses synchronous MCCQ */ |
8788fdc2 | 565 | int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id) |
6b7c5b94 | 566 | { |
b31c50a7 SP |
567 | struct be_mcc_wrb *wrb; |
568 | struct be_cmd_req_pmac_del *req; | |
6b7c5b94 SP |
569 | int status; |
570 | ||
b31c50a7 SP |
571 | spin_lock_bh(&adapter->mcc_lock); |
572 | ||
573 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
574 | if (!wrb) { |
575 | status = -EBUSY; | |
576 | goto err; | |
577 | } | |
b31c50a7 | 578 | req = embedded_payload(wrb); |
6b7c5b94 | 579 | |
d744b44e AK |
580 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
581 | OPCODE_COMMON_NTWK_PMAC_DEL); | |
6b7c5b94 SP |
582 | |
583 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
584 | OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req)); | |
585 | ||
586 | req->if_id = cpu_to_le32(if_id); | |
587 | req->pmac_id = cpu_to_le32(pmac_id); | |
588 | ||
b31c50a7 SP |
589 | status = be_mcc_notify_wait(adapter); |
590 | ||
713d0394 | 591 | err: |
b31c50a7 | 592 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
593 | return status; |
594 | } | |
595 | ||
b31c50a7 | 596 | /* Uses Mbox */ |
8788fdc2 | 597 | int be_cmd_cq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
598 | struct be_queue_info *cq, struct be_queue_info *eq, |
599 | bool sol_evts, bool no_delay, int coalesce_wm) | |
600 | { | |
b31c50a7 SP |
601 | struct be_mcc_wrb *wrb; |
602 | struct be_cmd_req_cq_create *req; | |
6b7c5b94 | 603 | struct be_dma_mem *q_mem = &cq->dma_mem; |
b31c50a7 | 604 | void *ctxt; |
6b7c5b94 SP |
605 | int status; |
606 | ||
8788fdc2 | 607 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
608 | |
609 | wrb = wrb_from_mbox(adapter); | |
610 | req = embedded_payload(wrb); | |
611 | ctxt = &req->context; | |
6b7c5b94 | 612 | |
d744b44e AK |
613 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
614 | OPCODE_COMMON_CQ_CREATE); | |
6b7c5b94 SP |
615 | |
616 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
617 | OPCODE_COMMON_CQ_CREATE, sizeof(*req)); | |
618 | ||
619 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | |
620 | ||
621 | AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm); | |
622 | AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay); | |
623 | AMAP_SET_BITS(struct amap_cq_context, count, ctxt, | |
624 | __ilog2_u32(cq->len/256)); | |
625 | AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1); | |
626 | AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts); | |
627 | AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); | |
628 | AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); | |
5fb379ee | 629 | AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); |
6b7c5b94 SP |
630 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); |
631 | ||
632 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
633 | ||
b31c50a7 | 634 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 | 635 | if (!status) { |
b31c50a7 | 636 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); |
6b7c5b94 SP |
637 | cq->id = le16_to_cpu(resp->cq_id); |
638 | cq->created = true; | |
639 | } | |
b31c50a7 | 640 | |
8788fdc2 | 641 | spin_unlock(&adapter->mbox_lock); |
5fb379ee SP |
642 | |
643 | return status; | |
644 | } | |
645 | ||
646 | static u32 be_encoded_q_len(int q_len) | |
647 | { | |
648 | u32 len_encoded = fls(q_len); /* log2(len) + 1 */ | |
649 | if (len_encoded == 16) | |
650 | len_encoded = 0; | |
651 | return len_encoded; | |
652 | } | |
653 | ||
8788fdc2 | 654 | int be_cmd_mccq_create(struct be_adapter *adapter, |
5fb379ee SP |
655 | struct be_queue_info *mccq, |
656 | struct be_queue_info *cq) | |
657 | { | |
b31c50a7 SP |
658 | struct be_mcc_wrb *wrb; |
659 | struct be_cmd_req_mcc_create *req; | |
5fb379ee | 660 | struct be_dma_mem *q_mem = &mccq->dma_mem; |
b31c50a7 | 661 | void *ctxt; |
5fb379ee SP |
662 | int status; |
663 | ||
8788fdc2 | 664 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
665 | |
666 | wrb = wrb_from_mbox(adapter); | |
667 | req = embedded_payload(wrb); | |
668 | ctxt = &req->context; | |
5fb379ee | 669 | |
d744b44e AK |
670 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
671 | OPCODE_COMMON_MCC_CREATE); | |
5fb379ee SP |
672 | |
673 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
674 | OPCODE_COMMON_MCC_CREATE, sizeof(*req)); | |
675 | ||
d4a2ac3e | 676 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); |
5fb379ee | 677 | |
5fb379ee SP |
678 | AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); |
679 | AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, | |
680 | be_encoded_q_len(mccq->len)); | |
681 | AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id); | |
682 | ||
683 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
684 | ||
685 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
686 | ||
b31c50a7 | 687 | status = be_mbox_notify_wait(adapter); |
5fb379ee SP |
688 | if (!status) { |
689 | struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); | |
690 | mccq->id = le16_to_cpu(resp->id); | |
691 | mccq->created = true; | |
692 | } | |
8788fdc2 | 693 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
694 | |
695 | return status; | |
696 | } | |
697 | ||
8788fdc2 | 698 | int be_cmd_txq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
699 | struct be_queue_info *txq, |
700 | struct be_queue_info *cq) | |
701 | { | |
b31c50a7 SP |
702 | struct be_mcc_wrb *wrb; |
703 | struct be_cmd_req_eth_tx_create *req; | |
6b7c5b94 | 704 | struct be_dma_mem *q_mem = &txq->dma_mem; |
b31c50a7 | 705 | void *ctxt; |
6b7c5b94 | 706 | int status; |
6b7c5b94 | 707 | |
8788fdc2 | 708 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
709 | |
710 | wrb = wrb_from_mbox(adapter); | |
711 | req = embedded_payload(wrb); | |
712 | ctxt = &req->context; | |
6b7c5b94 | 713 | |
d744b44e AK |
714 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
715 | OPCODE_ETH_TX_CREATE); | |
6b7c5b94 SP |
716 | |
717 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE, | |
718 | sizeof(*req)); | |
719 | ||
720 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | |
721 | req->ulp_num = BE_ULP1_NUM; | |
722 | req->type = BE_ETH_TX_RING_TYPE_STANDARD; | |
723 | ||
b31c50a7 SP |
724 | AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, |
725 | be_encoded_q_len(txq->len)); | |
6b7c5b94 SP |
726 | AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); |
727 | AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); | |
728 | ||
729 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | |
730 | ||
731 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
732 | ||
b31c50a7 | 733 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
734 | if (!status) { |
735 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); | |
736 | txq->id = le16_to_cpu(resp->cid); | |
737 | txq->created = true; | |
738 | } | |
b31c50a7 | 739 | |
8788fdc2 | 740 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
741 | |
742 | return status; | |
743 | } | |
744 | ||
b31c50a7 | 745 | /* Uses mbox */ |
8788fdc2 | 746 | int be_cmd_rxq_create(struct be_adapter *adapter, |
6b7c5b94 SP |
747 | struct be_queue_info *rxq, u16 cq_id, u16 frag_size, |
748 | u16 max_frame_size, u32 if_id, u32 rss) | |
749 | { | |
b31c50a7 SP |
750 | struct be_mcc_wrb *wrb; |
751 | struct be_cmd_req_eth_rx_create *req; | |
6b7c5b94 SP |
752 | struct be_dma_mem *q_mem = &rxq->dma_mem; |
753 | int status; | |
754 | ||
8788fdc2 | 755 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
756 | |
757 | wrb = wrb_from_mbox(adapter); | |
758 | req = embedded_payload(wrb); | |
6b7c5b94 | 759 | |
d744b44e AK |
760 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
761 | OPCODE_ETH_RX_CREATE); | |
6b7c5b94 SP |
762 | |
763 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE, | |
764 | sizeof(*req)); | |
765 | ||
766 | req->cq_id = cpu_to_le16(cq_id); | |
767 | req->frag_size = fls(frag_size) - 1; | |
768 | req->num_pages = 2; | |
769 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | |
770 | req->interface_id = cpu_to_le32(if_id); | |
771 | req->max_frame_size = cpu_to_le16(max_frame_size); | |
772 | req->rss_queue = cpu_to_le32(rss); | |
773 | ||
b31c50a7 | 774 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
775 | if (!status) { |
776 | struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); | |
777 | rxq->id = le16_to_cpu(resp->id); | |
778 | rxq->created = true; | |
779 | } | |
b31c50a7 | 780 | |
8788fdc2 | 781 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
782 | |
783 | return status; | |
784 | } | |
785 | ||
b31c50a7 SP |
786 | /* Generic destroyer function for all types of queues |
787 | * Uses Mbox | |
788 | */ | |
8788fdc2 | 789 | int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, |
6b7c5b94 SP |
790 | int queue_type) |
791 | { | |
b31c50a7 SP |
792 | struct be_mcc_wrb *wrb; |
793 | struct be_cmd_req_q_destroy *req; | |
6b7c5b94 SP |
794 | u8 subsys = 0, opcode = 0; |
795 | int status; | |
796 | ||
cf588477 SP |
797 | if (adapter->eeh_err) |
798 | return -EIO; | |
799 | ||
8788fdc2 | 800 | spin_lock(&adapter->mbox_lock); |
6b7c5b94 | 801 | |
b31c50a7 SP |
802 | wrb = wrb_from_mbox(adapter); |
803 | req = embedded_payload(wrb); | |
804 | ||
6b7c5b94 SP |
805 | switch (queue_type) { |
806 | case QTYPE_EQ: | |
807 | subsys = CMD_SUBSYSTEM_COMMON; | |
808 | opcode = OPCODE_COMMON_EQ_DESTROY; | |
809 | break; | |
810 | case QTYPE_CQ: | |
811 | subsys = CMD_SUBSYSTEM_COMMON; | |
812 | opcode = OPCODE_COMMON_CQ_DESTROY; | |
813 | break; | |
814 | case QTYPE_TXQ: | |
815 | subsys = CMD_SUBSYSTEM_ETH; | |
816 | opcode = OPCODE_ETH_TX_DESTROY; | |
817 | break; | |
818 | case QTYPE_RXQ: | |
819 | subsys = CMD_SUBSYSTEM_ETH; | |
820 | opcode = OPCODE_ETH_RX_DESTROY; | |
821 | break; | |
5fb379ee SP |
822 | case QTYPE_MCCQ: |
823 | subsys = CMD_SUBSYSTEM_COMMON; | |
824 | opcode = OPCODE_COMMON_MCC_DESTROY; | |
825 | break; | |
6b7c5b94 | 826 | default: |
5f0b849e | 827 | BUG(); |
6b7c5b94 | 828 | } |
d744b44e AK |
829 | |
830 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode); | |
831 | ||
6b7c5b94 SP |
832 | be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); |
833 | req->id = cpu_to_le16(q->id); | |
834 | ||
b31c50a7 | 835 | status = be_mbox_notify_wait(adapter); |
5f0b849e | 836 | |
8788fdc2 | 837 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
838 | |
839 | return status; | |
840 | } | |
841 | ||
b31c50a7 SP |
842 | /* Create an rx filtering policy configuration on an i/f |
843 | * Uses mbox | |
844 | */ | |
73d540f2 | 845 | int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, |
ba343c77 SB |
846 | u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id, |
847 | u32 domain) | |
6b7c5b94 | 848 | { |
b31c50a7 SP |
849 | struct be_mcc_wrb *wrb; |
850 | struct be_cmd_req_if_create *req; | |
6b7c5b94 SP |
851 | int status; |
852 | ||
8788fdc2 | 853 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
854 | |
855 | wrb = wrb_from_mbox(adapter); | |
856 | req = embedded_payload(wrb); | |
6b7c5b94 | 857 | |
d744b44e AK |
858 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
859 | OPCODE_COMMON_NTWK_INTERFACE_CREATE); | |
6b7c5b94 SP |
860 | |
861 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
862 | OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req)); | |
863 | ||
ba343c77 | 864 | req->hdr.domain = domain; |
73d540f2 SP |
865 | req->capability_flags = cpu_to_le32(cap_flags); |
866 | req->enable_flags = cpu_to_le32(en_flags); | |
b31c50a7 | 867 | req->pmac_invalid = pmac_invalid; |
6b7c5b94 SP |
868 | if (!pmac_invalid) |
869 | memcpy(req->mac_addr, mac, ETH_ALEN); | |
870 | ||
b31c50a7 | 871 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
872 | if (!status) { |
873 | struct be_cmd_resp_if_create *resp = embedded_payload(wrb); | |
874 | *if_handle = le32_to_cpu(resp->interface_id); | |
875 | if (!pmac_invalid) | |
876 | *pmac_id = le32_to_cpu(resp->pmac_id); | |
877 | } | |
878 | ||
8788fdc2 | 879 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
880 | return status; |
881 | } | |
882 | ||
b31c50a7 | 883 | /* Uses mbox */ |
8788fdc2 | 884 | int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id) |
6b7c5b94 | 885 | { |
b31c50a7 SP |
886 | struct be_mcc_wrb *wrb; |
887 | struct be_cmd_req_if_destroy *req; | |
6b7c5b94 SP |
888 | int status; |
889 | ||
cf588477 SP |
890 | if (adapter->eeh_err) |
891 | return -EIO; | |
892 | ||
8788fdc2 | 893 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
894 | |
895 | wrb = wrb_from_mbox(adapter); | |
896 | req = embedded_payload(wrb); | |
6b7c5b94 | 897 | |
d744b44e AK |
898 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
899 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY); | |
6b7c5b94 SP |
900 | |
901 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
902 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req)); | |
903 | ||
904 | req->interface_id = cpu_to_le32(interface_id); | |
b31c50a7 SP |
905 | |
906 | status = be_mbox_notify_wait(adapter); | |
6b7c5b94 | 907 | |
8788fdc2 | 908 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
909 | |
910 | return status; | |
911 | } | |
912 | ||
913 | /* Get stats is a non embedded command: the request is not embedded inside | |
914 | * WRB but is a separate dma memory block | |
b31c50a7 | 915 | * Uses asynchronous MCC |
6b7c5b94 | 916 | */ |
8788fdc2 | 917 | int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd) |
6b7c5b94 | 918 | { |
b31c50a7 SP |
919 | struct be_mcc_wrb *wrb; |
920 | struct be_cmd_req_get_stats *req; | |
921 | struct be_sge *sge; | |
713d0394 | 922 | int status = 0; |
6b7c5b94 | 923 | |
b31c50a7 | 924 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 925 | |
b31c50a7 | 926 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
927 | if (!wrb) { |
928 | status = -EBUSY; | |
929 | goto err; | |
930 | } | |
b31c50a7 SP |
931 | req = nonemb_cmd->va; |
932 | sge = nonembedded_sgl(wrb); | |
6b7c5b94 | 933 | |
d744b44e AK |
934 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, |
935 | OPCODE_ETH_GET_STATISTICS); | |
6b7c5b94 SP |
936 | |
937 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
938 | OPCODE_ETH_GET_STATISTICS, sizeof(*req)); | |
939 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
940 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
941 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
942 | ||
b31c50a7 | 943 | be_mcc_notify(adapter); |
6b7c5b94 | 944 | |
713d0394 | 945 | err: |
b31c50a7 | 946 | spin_unlock_bh(&adapter->mcc_lock); |
713d0394 | 947 | return status; |
6b7c5b94 SP |
948 | } |
949 | ||
b31c50a7 | 950 | /* Uses synchronous mcc */ |
8788fdc2 | 951 | int be_cmd_link_status_query(struct be_adapter *adapter, |
0388f251 | 952 | bool *link_up, u8 *mac_speed, u16 *link_speed) |
6b7c5b94 | 953 | { |
b31c50a7 SP |
954 | struct be_mcc_wrb *wrb; |
955 | struct be_cmd_req_link_status *req; | |
6b7c5b94 SP |
956 | int status; |
957 | ||
b31c50a7 SP |
958 | spin_lock_bh(&adapter->mcc_lock); |
959 | ||
960 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
961 | if (!wrb) { |
962 | status = -EBUSY; | |
963 | goto err; | |
964 | } | |
b31c50a7 | 965 | req = embedded_payload(wrb); |
a8f447bd SP |
966 | |
967 | *link_up = false; | |
6b7c5b94 | 968 | |
d744b44e AK |
969 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
970 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY); | |
6b7c5b94 SP |
971 | |
972 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
973 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req)); | |
974 | ||
b31c50a7 | 975 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
976 | if (!status) { |
977 | struct be_cmd_resp_link_status *resp = embedded_payload(wrb); | |
0388f251 | 978 | if (resp->mac_speed != PHY_LINK_SPEED_ZERO) { |
a8f447bd | 979 | *link_up = true; |
0388f251 SB |
980 | *link_speed = le16_to_cpu(resp->link_speed); |
981 | *mac_speed = resp->mac_speed; | |
982 | } | |
6b7c5b94 SP |
983 | } |
984 | ||
713d0394 | 985 | err: |
b31c50a7 | 986 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
987 | return status; |
988 | } | |
989 | ||
b31c50a7 | 990 | /* Uses Mbox */ |
8788fdc2 | 991 | int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver) |
6b7c5b94 | 992 | { |
b31c50a7 SP |
993 | struct be_mcc_wrb *wrb; |
994 | struct be_cmd_req_get_fw_version *req; | |
6b7c5b94 SP |
995 | int status; |
996 | ||
8788fdc2 | 997 | spin_lock(&adapter->mbox_lock); |
b31c50a7 SP |
998 | |
999 | wrb = wrb_from_mbox(adapter); | |
1000 | req = embedded_payload(wrb); | |
6b7c5b94 | 1001 | |
d744b44e AK |
1002 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1003 | OPCODE_COMMON_GET_FW_VERSION); | |
6b7c5b94 SP |
1004 | |
1005 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1006 | OPCODE_COMMON_GET_FW_VERSION, sizeof(*req)); | |
1007 | ||
b31c50a7 | 1008 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
1009 | if (!status) { |
1010 | struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); | |
1011 | strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN); | |
1012 | } | |
1013 | ||
8788fdc2 | 1014 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1015 | return status; |
1016 | } | |
1017 | ||
b31c50a7 SP |
1018 | /* set the EQ delay interval of an EQ to specified value |
1019 | * Uses async mcc | |
1020 | */ | |
8788fdc2 | 1021 | int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd) |
6b7c5b94 | 1022 | { |
b31c50a7 SP |
1023 | struct be_mcc_wrb *wrb; |
1024 | struct be_cmd_req_modify_eq_delay *req; | |
713d0394 | 1025 | int status = 0; |
6b7c5b94 | 1026 | |
b31c50a7 SP |
1027 | spin_lock_bh(&adapter->mcc_lock); |
1028 | ||
1029 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1030 | if (!wrb) { |
1031 | status = -EBUSY; | |
1032 | goto err; | |
1033 | } | |
b31c50a7 | 1034 | req = embedded_payload(wrb); |
6b7c5b94 | 1035 | |
d744b44e AK |
1036 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1037 | OPCODE_COMMON_MODIFY_EQ_DELAY); | |
6b7c5b94 SP |
1038 | |
1039 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1040 | OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req)); | |
1041 | ||
1042 | req->num_eq = cpu_to_le32(1); | |
1043 | req->delay[0].eq_id = cpu_to_le32(eq_id); | |
1044 | req->delay[0].phase = 0; | |
1045 | req->delay[0].delay_multiplier = cpu_to_le32(eqd); | |
1046 | ||
b31c50a7 | 1047 | be_mcc_notify(adapter); |
6b7c5b94 | 1048 | |
713d0394 | 1049 | err: |
b31c50a7 | 1050 | spin_unlock_bh(&adapter->mcc_lock); |
713d0394 | 1051 | return status; |
6b7c5b94 SP |
1052 | } |
1053 | ||
b31c50a7 | 1054 | /* Uses sycnhronous mcc */ |
8788fdc2 | 1055 | int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, |
6b7c5b94 SP |
1056 | u32 num, bool untagged, bool promiscuous) |
1057 | { | |
b31c50a7 SP |
1058 | struct be_mcc_wrb *wrb; |
1059 | struct be_cmd_req_vlan_config *req; | |
6b7c5b94 SP |
1060 | int status; |
1061 | ||
b31c50a7 SP |
1062 | spin_lock_bh(&adapter->mcc_lock); |
1063 | ||
1064 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1065 | if (!wrb) { |
1066 | status = -EBUSY; | |
1067 | goto err; | |
1068 | } | |
b31c50a7 | 1069 | req = embedded_payload(wrb); |
6b7c5b94 | 1070 | |
d744b44e AK |
1071 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1072 | OPCODE_COMMON_NTWK_VLAN_CONFIG); | |
6b7c5b94 SP |
1073 | |
1074 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1075 | OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req)); | |
1076 | ||
1077 | req->interface_id = if_id; | |
1078 | req->promiscuous = promiscuous; | |
1079 | req->untagged = untagged; | |
1080 | req->num_vlan = num; | |
1081 | if (!promiscuous) { | |
1082 | memcpy(req->normal_vlan, vtag_array, | |
1083 | req->num_vlan * sizeof(vtag_array[0])); | |
1084 | } | |
1085 | ||
b31c50a7 | 1086 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1087 | |
713d0394 | 1088 | err: |
b31c50a7 | 1089 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1090 | return status; |
1091 | } | |
1092 | ||
b31c50a7 SP |
1093 | /* Uses MCC for this command as it may be called in BH context |
1094 | * Uses synchronous mcc | |
1095 | */ | |
8788fdc2 | 1096 | int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en) |
6b7c5b94 | 1097 | { |
6ac7b687 SP |
1098 | struct be_mcc_wrb *wrb; |
1099 | struct be_cmd_req_promiscuous_config *req; | |
b31c50a7 | 1100 | int status; |
6b7c5b94 | 1101 | |
8788fdc2 | 1102 | spin_lock_bh(&adapter->mcc_lock); |
6ac7b687 | 1103 | |
b31c50a7 | 1104 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1105 | if (!wrb) { |
1106 | status = -EBUSY; | |
1107 | goto err; | |
1108 | } | |
6ac7b687 | 1109 | req = embedded_payload(wrb); |
6b7c5b94 | 1110 | |
d744b44e | 1111 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS); |
6b7c5b94 SP |
1112 | |
1113 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
1114 | OPCODE_ETH_PROMISCUOUS, sizeof(*req)); | |
1115 | ||
1116 | if (port_num) | |
1117 | req->port1_promiscuous = en; | |
1118 | else | |
1119 | req->port0_promiscuous = en; | |
1120 | ||
b31c50a7 | 1121 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1122 | |
713d0394 | 1123 | err: |
8788fdc2 | 1124 | spin_unlock_bh(&adapter->mcc_lock); |
b31c50a7 | 1125 | return status; |
6b7c5b94 SP |
1126 | } |
1127 | ||
6ac7b687 | 1128 | /* |
b31c50a7 | 1129 | * Uses MCC for this command as it may be called in BH context |
6ac7b687 SP |
1130 | * (mc == NULL) => multicast promiscous |
1131 | */ | |
8788fdc2 | 1132 | int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id, |
0ddf477b | 1133 | struct net_device *netdev, struct be_dma_mem *mem) |
6b7c5b94 | 1134 | { |
6ac7b687 | 1135 | struct be_mcc_wrb *wrb; |
e7b909a6 SP |
1136 | struct be_cmd_req_mcast_mac_config *req = mem->va; |
1137 | struct be_sge *sge; | |
1138 | int status; | |
6b7c5b94 | 1139 | |
8788fdc2 | 1140 | spin_lock_bh(&adapter->mcc_lock); |
6ac7b687 | 1141 | |
b31c50a7 | 1142 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1143 | if (!wrb) { |
1144 | status = -EBUSY; | |
1145 | goto err; | |
1146 | } | |
e7b909a6 SP |
1147 | sge = nonembedded_sgl(wrb); |
1148 | memset(req, 0, sizeof(*req)); | |
6b7c5b94 | 1149 | |
d744b44e AK |
1150 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, |
1151 | OPCODE_COMMON_NTWK_MULTICAST_SET); | |
e7b909a6 SP |
1152 | sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma)); |
1153 | sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF); | |
1154 | sge->len = cpu_to_le32(mem->size); | |
6b7c5b94 SP |
1155 | |
1156 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1157 | OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req)); | |
1158 | ||
1159 | req->interface_id = if_id; | |
0ddf477b | 1160 | if (netdev) { |
24307eef SP |
1161 | int i; |
1162 | struct dev_mc_list *mc; | |
1163 | ||
0ddf477b | 1164 | req->num_mac = cpu_to_le16(netdev_mc_count(netdev)); |
24307eef | 1165 | |
0ddf477b JP |
1166 | i = 0; |
1167 | netdev_for_each_mc_addr(mc, netdev) | |
24307eef SP |
1168 | memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN); |
1169 | } else { | |
1170 | req->promiscuous = 1; | |
6b7c5b94 SP |
1171 | } |
1172 | ||
e7b909a6 | 1173 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1174 | |
713d0394 | 1175 | err: |
8788fdc2 | 1176 | spin_unlock_bh(&adapter->mcc_lock); |
e7b909a6 | 1177 | return status; |
6b7c5b94 SP |
1178 | } |
1179 | ||
b31c50a7 | 1180 | /* Uses synchrounous mcc */ |
8788fdc2 | 1181 | int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc) |
6b7c5b94 | 1182 | { |
b31c50a7 SP |
1183 | struct be_mcc_wrb *wrb; |
1184 | struct be_cmd_req_set_flow_control *req; | |
6b7c5b94 SP |
1185 | int status; |
1186 | ||
b31c50a7 | 1187 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1188 | |
b31c50a7 | 1189 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1190 | if (!wrb) { |
1191 | status = -EBUSY; | |
1192 | goto err; | |
1193 | } | |
b31c50a7 | 1194 | req = embedded_payload(wrb); |
6b7c5b94 | 1195 | |
d744b44e AK |
1196 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1197 | OPCODE_COMMON_SET_FLOW_CONTROL); | |
6b7c5b94 SP |
1198 | |
1199 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1200 | OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req)); | |
1201 | ||
1202 | req->tx_flow_control = cpu_to_le16((u16)tx_fc); | |
1203 | req->rx_flow_control = cpu_to_le16((u16)rx_fc); | |
1204 | ||
b31c50a7 | 1205 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 | 1206 | |
713d0394 | 1207 | err: |
b31c50a7 | 1208 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1209 | return status; |
1210 | } | |
1211 | ||
b31c50a7 | 1212 | /* Uses sycn mcc */ |
8788fdc2 | 1213 | int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) |
6b7c5b94 | 1214 | { |
b31c50a7 SP |
1215 | struct be_mcc_wrb *wrb; |
1216 | struct be_cmd_req_get_flow_control *req; | |
6b7c5b94 SP |
1217 | int status; |
1218 | ||
b31c50a7 | 1219 | spin_lock_bh(&adapter->mcc_lock); |
6b7c5b94 | 1220 | |
b31c50a7 | 1221 | wrb = wrb_from_mccq(adapter); |
713d0394 SP |
1222 | if (!wrb) { |
1223 | status = -EBUSY; | |
1224 | goto err; | |
1225 | } | |
b31c50a7 | 1226 | req = embedded_payload(wrb); |
6b7c5b94 | 1227 | |
d744b44e AK |
1228 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1229 | OPCODE_COMMON_GET_FLOW_CONTROL); | |
6b7c5b94 SP |
1230 | |
1231 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1232 | OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req)); | |
1233 | ||
b31c50a7 | 1234 | status = be_mcc_notify_wait(adapter); |
6b7c5b94 SP |
1235 | if (!status) { |
1236 | struct be_cmd_resp_get_flow_control *resp = | |
1237 | embedded_payload(wrb); | |
1238 | *tx_fc = le16_to_cpu(resp->tx_flow_control); | |
1239 | *rx_fc = le16_to_cpu(resp->rx_flow_control); | |
1240 | } | |
1241 | ||
713d0394 | 1242 | err: |
b31c50a7 | 1243 | spin_unlock_bh(&adapter->mcc_lock); |
6b7c5b94 SP |
1244 | return status; |
1245 | } | |
1246 | ||
b31c50a7 | 1247 | /* Uses mbox */ |
dcb9b564 | 1248 | int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap) |
6b7c5b94 | 1249 | { |
b31c50a7 SP |
1250 | struct be_mcc_wrb *wrb; |
1251 | struct be_cmd_req_query_fw_cfg *req; | |
6b7c5b94 SP |
1252 | int status; |
1253 | ||
8788fdc2 | 1254 | spin_lock(&adapter->mbox_lock); |
6b7c5b94 | 1255 | |
b31c50a7 SP |
1256 | wrb = wrb_from_mbox(adapter); |
1257 | req = embedded_payload(wrb); | |
6b7c5b94 | 1258 | |
d744b44e AK |
1259 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1260 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG); | |
6b7c5b94 SP |
1261 | |
1262 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1263 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req)); | |
1264 | ||
b31c50a7 | 1265 | status = be_mbox_notify_wait(adapter); |
6b7c5b94 SP |
1266 | if (!status) { |
1267 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); | |
1268 | *port_num = le32_to_cpu(resp->phys_port); | |
dcb9b564 | 1269 | *cap = le32_to_cpu(resp->function_cap); |
6b7c5b94 SP |
1270 | } |
1271 | ||
8788fdc2 | 1272 | spin_unlock(&adapter->mbox_lock); |
6b7c5b94 SP |
1273 | return status; |
1274 | } | |
14074eab | 1275 | |
b31c50a7 | 1276 | /* Uses mbox */ |
14074eab | 1277 | int be_cmd_reset_function(struct be_adapter *adapter) |
1278 | { | |
b31c50a7 SP |
1279 | struct be_mcc_wrb *wrb; |
1280 | struct be_cmd_req_hdr *req; | |
14074eab | 1281 | int status; |
1282 | ||
1283 | spin_lock(&adapter->mbox_lock); | |
1284 | ||
b31c50a7 SP |
1285 | wrb = wrb_from_mbox(adapter); |
1286 | req = embedded_payload(wrb); | |
14074eab | 1287 | |
d744b44e AK |
1288 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1289 | OPCODE_COMMON_FUNCTION_RESET); | |
14074eab | 1290 | |
1291 | be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON, | |
1292 | OPCODE_COMMON_FUNCTION_RESET, sizeof(*req)); | |
1293 | ||
b31c50a7 | 1294 | status = be_mbox_notify_wait(adapter); |
14074eab | 1295 | |
1296 | spin_unlock(&adapter->mbox_lock); | |
1297 | return status; | |
1298 | } | |
84517482 | 1299 | |
fad9ab2c SB |
1300 | /* Uses sync mcc */ |
1301 | int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, | |
1302 | u8 bcn, u8 sts, u8 state) | |
1303 | { | |
1304 | struct be_mcc_wrb *wrb; | |
1305 | struct be_cmd_req_enable_disable_beacon *req; | |
1306 | int status; | |
1307 | ||
1308 | spin_lock_bh(&adapter->mcc_lock); | |
1309 | ||
1310 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1311 | if (!wrb) { |
1312 | status = -EBUSY; | |
1313 | goto err; | |
1314 | } | |
fad9ab2c SB |
1315 | req = embedded_payload(wrb); |
1316 | ||
d744b44e AK |
1317 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1318 | OPCODE_COMMON_ENABLE_DISABLE_BEACON); | |
fad9ab2c SB |
1319 | |
1320 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1321 | OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req)); | |
1322 | ||
1323 | req->port_num = port_num; | |
1324 | req->beacon_state = state; | |
1325 | req->beacon_duration = bcn; | |
1326 | req->status_duration = sts; | |
1327 | ||
1328 | status = be_mcc_notify_wait(adapter); | |
1329 | ||
713d0394 | 1330 | err: |
fad9ab2c SB |
1331 | spin_unlock_bh(&adapter->mcc_lock); |
1332 | return status; | |
1333 | } | |
1334 | ||
1335 | /* Uses sync mcc */ | |
1336 | int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state) | |
1337 | { | |
1338 | struct be_mcc_wrb *wrb; | |
1339 | struct be_cmd_req_get_beacon_state *req; | |
1340 | int status; | |
1341 | ||
1342 | spin_lock_bh(&adapter->mcc_lock); | |
1343 | ||
1344 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1345 | if (!wrb) { |
1346 | status = -EBUSY; | |
1347 | goto err; | |
1348 | } | |
fad9ab2c SB |
1349 | req = embedded_payload(wrb); |
1350 | ||
d744b44e AK |
1351 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, |
1352 | OPCODE_COMMON_GET_BEACON_STATE); | |
fad9ab2c SB |
1353 | |
1354 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1355 | OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req)); | |
1356 | ||
1357 | req->port_num = port_num; | |
1358 | ||
1359 | status = be_mcc_notify_wait(adapter); | |
1360 | if (!status) { | |
1361 | struct be_cmd_resp_get_beacon_state *resp = | |
1362 | embedded_payload(wrb); | |
1363 | *state = resp->beacon_state; | |
1364 | } | |
1365 | ||
713d0394 | 1366 | err: |
fad9ab2c SB |
1367 | spin_unlock_bh(&adapter->mcc_lock); |
1368 | return status; | |
1369 | } | |
1370 | ||
0388f251 SB |
1371 | /* Uses sync mcc */ |
1372 | int be_cmd_read_port_type(struct be_adapter *adapter, u32 port, | |
1373 | u8 *connector) | |
1374 | { | |
1375 | struct be_mcc_wrb *wrb; | |
1376 | struct be_cmd_req_port_type *req; | |
1377 | int status; | |
1378 | ||
1379 | spin_lock_bh(&adapter->mcc_lock); | |
1380 | ||
1381 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1382 | if (!wrb) { |
1383 | status = -EBUSY; | |
1384 | goto err; | |
1385 | } | |
0388f251 SB |
1386 | req = embedded_payload(wrb); |
1387 | ||
d744b44e AK |
1388 | be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0, |
1389 | OPCODE_COMMON_READ_TRANSRECV_DATA); | |
0388f251 SB |
1390 | |
1391 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1392 | OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req)); | |
1393 | ||
1394 | req->port = cpu_to_le32(port); | |
1395 | req->page_num = cpu_to_le32(TR_PAGE_A0); | |
1396 | status = be_mcc_notify_wait(adapter); | |
1397 | if (!status) { | |
1398 | struct be_cmd_resp_port_type *resp = embedded_payload(wrb); | |
1399 | *connector = resp->data.connector; | |
1400 | } | |
1401 | ||
713d0394 | 1402 | err: |
0388f251 SB |
1403 | spin_unlock_bh(&adapter->mcc_lock); |
1404 | return status; | |
1405 | } | |
1406 | ||
84517482 AK |
1407 | int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, |
1408 | u32 flash_type, u32 flash_opcode, u32 buf_size) | |
1409 | { | |
b31c50a7 | 1410 | struct be_mcc_wrb *wrb; |
3f0d4560 | 1411 | struct be_cmd_write_flashrom *req; |
b31c50a7 | 1412 | struct be_sge *sge; |
84517482 AK |
1413 | int status; |
1414 | ||
b31c50a7 SP |
1415 | spin_lock_bh(&adapter->mcc_lock); |
1416 | ||
1417 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1418 | if (!wrb) { |
1419 | status = -EBUSY; | |
1420 | goto err; | |
1421 | } | |
1422 | req = cmd->va; | |
b31c50a7 SP |
1423 | sge = nonembedded_sgl(wrb); |
1424 | ||
d744b44e AK |
1425 | be_wrb_hdr_prepare(wrb, cmd->size, false, 1, |
1426 | OPCODE_COMMON_WRITE_FLASHROM); | |
84517482 AK |
1427 | |
1428 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1429 | OPCODE_COMMON_WRITE_FLASHROM, cmd->size); | |
1430 | sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma)); | |
1431 | sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF); | |
1432 | sge->len = cpu_to_le32(cmd->size); | |
1433 | ||
1434 | req->params.op_type = cpu_to_le32(flash_type); | |
1435 | req->params.op_code = cpu_to_le32(flash_opcode); | |
1436 | req->params.data_buf_size = cpu_to_le32(buf_size); | |
1437 | ||
b31c50a7 | 1438 | status = be_mcc_notify_wait(adapter); |
84517482 | 1439 | |
713d0394 | 1440 | err: |
b31c50a7 | 1441 | spin_unlock_bh(&adapter->mcc_lock); |
84517482 AK |
1442 | return status; |
1443 | } | |
fa9a6fed | 1444 | |
3f0d4560 AK |
1445 | int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, |
1446 | int offset) | |
fa9a6fed SB |
1447 | { |
1448 | struct be_mcc_wrb *wrb; | |
1449 | struct be_cmd_write_flashrom *req; | |
1450 | int status; | |
1451 | ||
1452 | spin_lock_bh(&adapter->mcc_lock); | |
1453 | ||
1454 | wrb = wrb_from_mccq(adapter); | |
713d0394 SP |
1455 | if (!wrb) { |
1456 | status = -EBUSY; | |
1457 | goto err; | |
1458 | } | |
fa9a6fed SB |
1459 | req = embedded_payload(wrb); |
1460 | ||
d744b44e AK |
1461 | be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0, |
1462 | OPCODE_COMMON_READ_FLASHROM); | |
fa9a6fed SB |
1463 | |
1464 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1465 | OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4); | |
1466 | ||
3f0d4560 | 1467 | req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT); |
fa9a6fed | 1468 | req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); |
3f0d4560 | 1469 | req->params.offset = offset; |
fa9a6fed SB |
1470 | req->params.data_buf_size = 0x4; |
1471 | ||
1472 | status = be_mcc_notify_wait(adapter); | |
1473 | if (!status) | |
1474 | memcpy(flashed_crc, req->params.data_buf, 4); | |
1475 | ||
713d0394 | 1476 | err: |
fa9a6fed SB |
1477 | spin_unlock_bh(&adapter->mcc_lock); |
1478 | return status; | |
1479 | } | |
71d8d1b5 AK |
1480 | |
1481 | extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, | |
1482 | struct be_dma_mem *nonemb_cmd) | |
1483 | { | |
1484 | struct be_mcc_wrb *wrb; | |
1485 | struct be_cmd_req_acpi_wol_magic_config *req; | |
1486 | struct be_sge *sge; | |
1487 | int status; | |
1488 | ||
1489 | spin_lock_bh(&adapter->mcc_lock); | |
1490 | ||
1491 | wrb = wrb_from_mccq(adapter); | |
1492 | if (!wrb) { | |
1493 | status = -EBUSY; | |
1494 | goto err; | |
1495 | } | |
1496 | req = nonemb_cmd->va; | |
1497 | sge = nonembedded_sgl(wrb); | |
1498 | ||
1499 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, | |
1500 | OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG); | |
1501 | ||
1502 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | |
1503 | OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req)); | |
1504 | memcpy(req->magic_mac, mac, ETH_ALEN); | |
1505 | ||
1506 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
1507 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
1508 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
1509 | ||
1510 | status = be_mcc_notify_wait(adapter); | |
1511 | ||
1512 | err: | |
1513 | spin_unlock_bh(&adapter->mcc_lock); | |
1514 | return status; | |
1515 | } | |
ff33a6e2 | 1516 | |
fced9999 SB |
1517 | int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, |
1518 | u8 loopback_type, u8 enable) | |
1519 | { | |
1520 | struct be_mcc_wrb *wrb; | |
1521 | struct be_cmd_req_set_lmode *req; | |
1522 | int status; | |
1523 | ||
1524 | spin_lock_bh(&adapter->mcc_lock); | |
1525 | ||
1526 | wrb = wrb_from_mccq(adapter); | |
1527 | if (!wrb) { | |
1528 | status = -EBUSY; | |
1529 | goto err; | |
1530 | } | |
1531 | ||
1532 | req = embedded_payload(wrb); | |
1533 | ||
1534 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
1535 | OPCODE_LOWLEVEL_SET_LOOPBACK_MODE); | |
1536 | ||
1537 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
1538 | OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, | |
1539 | sizeof(*req)); | |
1540 | ||
1541 | req->src_port = port_num; | |
1542 | req->dest_port = port_num; | |
1543 | req->loopback_type = loopback_type; | |
1544 | req->loopback_state = enable; | |
1545 | ||
1546 | status = be_mcc_notify_wait(adapter); | |
1547 | err: | |
1548 | spin_unlock_bh(&adapter->mcc_lock); | |
1549 | return status; | |
1550 | } | |
1551 | ||
ff33a6e2 S |
1552 | int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, |
1553 | u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern) | |
1554 | { | |
1555 | struct be_mcc_wrb *wrb; | |
1556 | struct be_cmd_req_loopback_test *req; | |
1557 | int status; | |
1558 | ||
1559 | spin_lock_bh(&adapter->mcc_lock); | |
1560 | ||
1561 | wrb = wrb_from_mccq(adapter); | |
1562 | if (!wrb) { | |
1563 | status = -EBUSY; | |
1564 | goto err; | |
1565 | } | |
1566 | ||
1567 | req = embedded_payload(wrb); | |
1568 | ||
1569 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, | |
1570 | OPCODE_LOWLEVEL_LOOPBACK_TEST); | |
1571 | ||
1572 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
1573 | OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req)); | |
d7b90141 | 1574 | req->hdr.timeout = 4; |
ff33a6e2 S |
1575 | |
1576 | req->pattern = cpu_to_le64(pattern); | |
1577 | req->src_port = cpu_to_le32(port_num); | |
1578 | req->dest_port = cpu_to_le32(port_num); | |
1579 | req->pkt_size = cpu_to_le32(pkt_size); | |
1580 | req->num_pkts = cpu_to_le32(num_pkts); | |
1581 | req->loopback_type = cpu_to_le32(loopback_type); | |
1582 | ||
1583 | status = be_mcc_notify_wait(adapter); | |
1584 | if (!status) { | |
1585 | struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb); | |
1586 | status = le32_to_cpu(resp->status); | |
1587 | } | |
1588 | ||
1589 | err: | |
1590 | spin_unlock_bh(&adapter->mcc_lock); | |
1591 | return status; | |
1592 | } | |
1593 | ||
1594 | int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, | |
1595 | u32 byte_cnt, struct be_dma_mem *cmd) | |
1596 | { | |
1597 | struct be_mcc_wrb *wrb; | |
1598 | struct be_cmd_req_ddrdma_test *req; | |
1599 | struct be_sge *sge; | |
1600 | int status; | |
1601 | int i, j = 0; | |
1602 | ||
1603 | spin_lock_bh(&adapter->mcc_lock); | |
1604 | ||
1605 | wrb = wrb_from_mccq(adapter); | |
1606 | if (!wrb) { | |
1607 | status = -EBUSY; | |
1608 | goto err; | |
1609 | } | |
1610 | req = cmd->va; | |
1611 | sge = nonembedded_sgl(wrb); | |
1612 | be_wrb_hdr_prepare(wrb, cmd->size, false, 1, | |
1613 | OPCODE_LOWLEVEL_HOST_DDR_DMA); | |
1614 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL, | |
1615 | OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size); | |
1616 | ||
1617 | sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma)); | |
1618 | sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF); | |
1619 | sge->len = cpu_to_le32(cmd->size); | |
1620 | ||
1621 | req->pattern = cpu_to_le64(pattern); | |
1622 | req->byte_count = cpu_to_le32(byte_cnt); | |
1623 | for (i = 0; i < byte_cnt; i++) { | |
1624 | req->snd_buff[i] = (u8)(pattern >> (j*8)); | |
1625 | j++; | |
1626 | if (j > 7) | |
1627 | j = 0; | |
1628 | } | |
1629 | ||
1630 | status = be_mcc_notify_wait(adapter); | |
1631 | ||
1632 | if (!status) { | |
1633 | struct be_cmd_resp_ddrdma_test *resp; | |
1634 | resp = cmd->va; | |
1635 | if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) || | |
1636 | resp->snd_err) { | |
1637 | status = -1; | |
1638 | } | |
1639 | } | |
1640 | ||
1641 | err: | |
1642 | spin_unlock_bh(&adapter->mcc_lock); | |
1643 | return status; | |
1644 | } | |
368c0ca2 SB |
1645 | |
1646 | extern int be_cmd_get_seeprom_data(struct be_adapter *adapter, | |
1647 | struct be_dma_mem *nonemb_cmd) | |
1648 | { | |
1649 | struct be_mcc_wrb *wrb; | |
1650 | struct be_cmd_req_seeprom_read *req; | |
1651 | struct be_sge *sge; | |
1652 | int status; | |
1653 | ||
1654 | spin_lock_bh(&adapter->mcc_lock); | |
1655 | ||
1656 | wrb = wrb_from_mccq(adapter); | |
1657 | req = nonemb_cmd->va; | |
1658 | sge = nonembedded_sgl(wrb); | |
1659 | ||
1660 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, | |
1661 | OPCODE_COMMON_SEEPROM_READ); | |
1662 | ||
1663 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | |
1664 | OPCODE_COMMON_SEEPROM_READ, sizeof(*req)); | |
1665 | ||
1666 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | |
1667 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | |
1668 | sge->len = cpu_to_le32(nonemb_cmd->size); | |
1669 | ||
1670 | status = be_mcc_notify_wait(adapter); | |
1671 | ||
1672 | spin_unlock_bh(&adapter->mcc_lock); | |
1673 | return status; | |
1674 | } |