[net-next-2.6.git] / drivers / net / benet / be.h

/*
 * Copyright (C) 2005 - 2009 ServerEngines
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.  The full GNU General
 * Public License is included in this distribution in the file called COPYING.
 *
 * Contact Information:
 * linux-drivers@serverengines.com
 *
 * ServerEngines
 * 209 N. Fair Oaks Ave
 * Sunnyvale, CA 94085
 */

#ifndef BE_H
#define BE_H

#include <linux/pci.h>
#include <linux/etherdevice.h>
#include <linux/version.h>
#include <linux/delay.h>
#include <net/tcp.h>
#include <net/ip.h>
#include <net/ipv6.h>
#include <linux/if_vlan.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/firmware.h>

#include "be_hw.h"

#define DRV_VER			"2.101.346u"
#define DRV_NAME		"be2net"
#define BE_NAME			"ServerEngines BladeEngine2 10Gbps NIC"
#define BE3_NAME		"ServerEngines BladeEngine3 10Gbps NIC"
#define OC_NAME			"Emulex OneConnect 10Gbps NIC"
#define OC_NAME1		"Emulex OneConnect 10Gbps NIC (be3)"
#define DRV_DESC		BE_NAME "Driver"

#define BE_VENDOR_ID 		0x19a2
#define BE_DEVICE_ID1		0x211
#define BE_DEVICE_ID2		0x221
#define OC_DEVICE_ID1		0x700
#define OC_DEVICE_ID2		0x701
#define OC_DEVICE_ID3		0x710

static inline char *nic_name(struct pci_dev *pdev)
{
	switch (pdev->device) {
	case OC_DEVICE_ID1:
	case OC_DEVICE_ID2:
		return OC_NAME;
	case OC_DEVICE_ID3:
		return OC_NAME1;
	case BE_DEVICE_ID2:
		return BE3_NAME;
	default:
		return BE_NAME;
	}
}

/* Number of bytes of an RX frame that are copied to skb->data */
#define BE_HDR_LEN 		64
#define BE_MAX_JUMBO_FRAME_SIZE	9018
#define BE_MIN_MTU		256

#define BE_NUM_VLANS_SUPPORTED	64
#define BE_MAX_EQD		96
#define	BE_MAX_TX_FRAG_COUNT	30

#define EVNT_Q_LEN		1024
#define TX_Q_LEN		2048
#define TX_CQ_LEN		1024
#define RX_Q_LEN		1024	/* Does not support any other value */
#define RX_CQ_LEN		1024
#define MCC_Q_LEN		128	/* total size not to exceed 8 pages */
#define MCC_CQ_LEN		256

#define BE_NAPI_WEIGHT		64
#define MAX_RX_POST 		BE_NAPI_WEIGHT /* Frags posted at a time */
#define RX_FRAGS_REFILL_WM	(RX_Q_LEN - MAX_RX_POST)

#define FW_VER_LEN		32

struct be_dma_mem {
	void *va;
	dma_addr_t dma;
	u32 size;
};

struct be_queue_info {
	struct be_dma_mem dma_mem;
	u16 len;
	u16 entry_size;	/* Size of an element in the queue */
	u16 id;
	u16 tail, head;
	bool created;
	atomic_t used;	/* Number of valid elements in the queue */
};

static inline u32 MODULO(u16 val, u16 limit)
{
	BUG_ON(limit & (limit - 1));
	return val & (limit - 1);
}

static inline void index_adv(u16 *index, u16 val, u16 limit)
{
	*index = MODULO((*index + val), limit);
}

static inline void index_inc(u16 *index, u16 limit)
{
	*index = MODULO((*index + 1), limit);
}

static inline void *queue_head_node(struct be_queue_info *q)
{
	return q->dma_mem.va + q->head * q->entry_size;
}

static inline void *queue_tail_node(struct be_queue_info *q)
{
	return q->dma_mem.va + q->tail * q->entry_size;
}

static inline void queue_head_inc(struct be_queue_info *q)
{
	index_inc(&q->head, q->len);
}

static inline void queue_tail_inc(struct be_queue_info *q)
{
	index_inc(&q->tail, q->len);
}

struct be_eq_obj {
	struct be_queue_info q;
	char desc[32];

	/* Adaptive interrupt coalescing (AIC) info */
	bool enable_aic;
	u16 min_eqd;		/* in usecs */
	u16 max_eqd;		/* in usecs */
	u16 cur_eqd;		/* in usecs */

	struct napi_struct napi;
};

struct be_mcc_obj {
	struct be_queue_info q;
	struct be_queue_info cq;
};

struct be_drvr_stats {
	u32 be_tx_reqs;		/* number of TX requests initiated */
	u32 be_tx_stops;	/* number of times TX Q was stopped */
	u32 be_fwd_reqs;	/* number of send reqs through forwarding i/f */
	u32 be_tx_wrbs;		/* number of tx WRBs used */
	u32 be_tx_events;	/* number of tx completion events  */
	u32 be_tx_compl;	/* number of tx completion entries processed */
	ulong be_tx_jiffies;
	u64 be_tx_bytes;
	u64 be_tx_bytes_prev;
	u32 be_tx_rate;

	u32 cache_barrier[16];

	u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
	u32 be_rx_polls;	/* number of times NAPI called poll function */
	u32 be_rx_events;	/* number of ucast rx completion events  */
	u32 be_rx_compl;	/* number of rx completion entries processed */
	ulong be_rx_jiffies;
	u64 be_rx_bytes;
	u64 be_rx_bytes_prev;
	u32 be_rx_rate;
	/* number of non ether type II frames dropped where
	 * frame len > length field of Mac Hdr */
	u32 be_802_3_dropped_frames;
	/* number of non ether type II frames malformed where
	 * in frame len < length field of Mac Hdr */
	u32 be_802_3_malformed_frames;
	u32 be_rxcp_err;	/* Num rx completion entries w/ err set. */
	ulong rx_fps_jiffies;	/* jiffies at last FPS calc */
	u32 be_rx_frags;
	u32 be_prev_rx_frags;
	u32 be_rx_fps;		/* Rx frags per second */
};

struct be_stats_obj {
	struct be_drvr_stats drvr_stats;
	struct be_dma_mem cmd;
};

struct be_tx_obj {
	struct be_queue_info q;
	struct be_queue_info cq;
	/* Remember the skbs that were transmitted */
	struct sk_buff *sent_skb_list[TX_Q_LEN];
};

/* Struct to remember the pages posted for rx frags */
struct be_rx_page_info {
	struct page *page;
	dma_addr_t bus;
	u16 page_offset;
	bool last_page_user;
};

struct be_rx_obj {
	struct be_queue_info q;
	struct be_queue_info cq;
	struct be_rx_page_info page_info_tbl[RX_Q_LEN];
};

#define BE_NUM_MSIX_VECTORS		2	/* 1 each for Tx and Rx */
struct be_adapter {
	struct pci_dev *pdev;
	struct net_device *netdev;

	u8 __iomem *csr;
	u8 __iomem *db;		/* Door Bell */
	u8 __iomem *pcicfg;	/* PCI config space */

	spinlock_t mbox_lock;	/* For serializing mbox cmds to BE card */
	struct be_dma_mem mbox_mem;
	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
	 * is stored for freeing purpose */
	struct be_dma_mem mbox_mem_alloced;

	struct be_mcc_obj mcc_obj;
	spinlock_t mcc_lock;	/* For serializing mcc cmds to BE card */
	spinlock_t mcc_cq_lock;

	struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
	bool msix_enabled;
	bool isr_registered;

	/* TX Rings */
	struct be_eq_obj tx_eq;
	struct be_tx_obj tx_obj;

	u32 cache_line_break[8];

	/* Rx rings */
	struct be_eq_obj rx_eq;
	struct be_rx_obj rx_obj;
	u32 big_page_size;	/* Compounded page size shared by rx wrbs */
	bool rx_post_starved;	/* Zero rx frags have been posted to BE */

	struct vlan_group *vlan_grp;
	u16 num_vlans;
	u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
	struct be_dma_mem mc_cmd_mem;

	struct be_stats_obj stats;
	/* Work queue used to perform periodic tasks like getting statistics */
	struct delayed_work work;

	/* Ethtool knobs and info */
	bool rx_csum; 		/* BE card must perform rx-checksumming */
	char fw_ver[FW_VER_LEN];
	u32 if_handle;		/* Used to configure filtering */
	u32 pmac_id;		/* MAC addr handle used by BE card */

	bool link_up;
	u32 port_num;
	bool promiscuous;
	bool wol;
	u32 cap;
	u32 rx_fc;		/* Rx flow control */
	u32 tx_fc;		/* Tx flow control */
	int link_speed;
	u8 port_type;
	u8 transceiver;
};

extern const struct ethtool_ops be_ethtool_ops;

#define drvr_stats(adapter)		(&adapter->stats.drvr_stats)

static inline unsigned int be_pci_func(struct be_adapter *adapter)
{
	return PCI_FUNC(adapter->pdev->devfn);
}

#define BE_SET_NETDEV_OPS(netdev, ops)	(netdev->netdev_ops = ops)

#define PAGE_SHIFT_4K		12
#define PAGE_SIZE_4K		(1 << PAGE_SHIFT_4K)

/* Returns number of pages spanned by the data starting at the given addr */
#define PAGES_4K_SPANNED(_address, size) 				\
		((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + 	\
			(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))

/* Byte offset into the page corresponding to given address */
#define OFFSET_IN_PAGE(addr)						\
		 ((size_t)(addr) & (PAGE_SIZE_4K-1))

/* Returns bit offset within a DWORD of a bitfield */
#define AMAP_BIT_OFFSET(_struct, field)  				\
		(((size_t)&(((_struct *)0)->field))%32)

/* Returns the bit mask of the field that is NOT shifted into location. */
static inline u32 amap_mask(u32 bitsize)
{
	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
}

static inline void
amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
{
	u32 *dw = (u32 *) ptr + dw_offset;
	*dw &= ~(mask << offset);
	*dw |= (mask & value) << offset;
}

#define AMAP_SET_BITS(_struct, field, ptr, val)				\
		amap_set(ptr,						\
			offsetof(_struct, field)/32,			\
			amap_mask(sizeof(((_struct *)0)->field)),	\
			AMAP_BIT_OFFSET(_struct, field),		\
			val)

static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
{
	u32 *dw = (u32 *) ptr;
	return mask & (*(dw + dw_offset) >> offset);
}

#define AMAP_GET_BITS(_struct, field, ptr)				\
		amap_get(ptr,						\
			offsetof(_struct, field)/32,			\
			amap_mask(sizeof(((_struct *)0)->field)),	\
			AMAP_BIT_OFFSET(_struct, field))

#define be_dws_cpu_to_le(wrb, len)	swap_dws(wrb, len)
#define be_dws_le_to_cpu(wrb, len)	swap_dws(wrb, len)
static inline void swap_dws(void *wrb, int len)
{
#ifdef __BIG_ENDIAN
	u32 *dw = wrb;
	BUG_ON(len % 4);
	do {
		*dw = cpu_to_le32(*dw);
		dw++;
		len -= 4;
	} while (len);
#endif				/* __BIG_ENDIAN */
}

static inline u8 is_tcp_pkt(struct sk_buff *skb)
{
	u8 val = 0;

	if (ip_hdr(skb)->version == 4)
		val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
	else if (ip_hdr(skb)->version == 6)
		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);

	return val;
}

static inline u8 is_udp_pkt(struct sk_buff *skb)
{
	u8 val = 0;

	if (ip_hdr(skb)->version == 4)
		val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
	else if (ip_hdr(skb)->version == 6)
		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);

	return val;
}

extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
		u16 num_popped);
extern void be_link_status_update(struct be_adapter *adapter, bool link_up);
extern void netdev_stats_update(struct be_adapter *adapter);
extern int be_load_fw(struct be_adapter *adapter, u8 *func);
#endif				/* BE_H */
Commit	Line	Data
6b7c5b94 SP	1	/*
	2	* Copyright (C) 2005 - 2009 ServerEngines
	3	* All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License version 2
	7	* as published by the Free Software Foundation. The full GNU General
	8	* Public License is included in this distribution in the file called COPYING.
	9	*
	10	* Contact Information:
	11	* linux-drivers@serverengines.com
	12	*
	13	* ServerEngines
	14	* 209 N. Fair Oaks Ave
	15	* Sunnyvale, CA 94085
	16	*/
	17
	18	#ifndef BE_H
	19	#define BE_H
	20
	21	#include <linux/pci.h>
	22	#include <linux/etherdevice.h>
	23	#include <linux/version.h>
	24	#include <linux/delay.h>
	25	#include <net/tcp.h>
	26	#include <net/ip.h>
	27	#include <net/ipv6.h>
	28	#include <linux/if_vlan.h>
	29	#include <linux/workqueue.h>
	30	#include <linux/interrupt.h>
84517482	31	#include <linux/firmware.h>
6b7c5b94 SP	32
	33	#include "be_hw.h"
	34
3454f835	35	#define DRV_VER "2.101.346u"
6b7c5b94 SP	36	#define DRV_NAME "be2net"
6b7c5b94 SP	37	#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
12d7ea2c	38	#define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
c4ca2374	39	#define OC_NAME "Emulex OneConnect 10Gbps NIC"
12d7ea2c	40	#define OC_NAME1 "Emulex OneConnect 10Gbps NIC (be3)"
6b7c5b94 SP	41	#define DRV_DESC BE_NAME "Driver"
6b7c5b94 SP	42
c4ca2374 AK	43	#define BE_VENDOR_ID 0x19a2
c4ca2374 AK	44	#define BE_DEVICE_ID1 0x211
12d7ea2c	45	#define BE_DEVICE_ID2 0x221
c4ca2374 AK	46	#define OC_DEVICE_ID1 0x700
c4ca2374 AK	47	#define OC_DEVICE_ID2 0x701
12d7ea2c	48	#define OC_DEVICE_ID3 0x710
c4ca2374 AK	49
	50	static inline char nic_name(struct pci_dev pdev)
	51	{
12d7ea2c AK	52	switch (pdev->device) {
	53	case OC_DEVICE_ID1:
	54	case OC_DEVICE_ID2:
c4ca2374	55	return OC_NAME;
12d7ea2c AK	56	case OC_DEVICE_ID3:
	57	return OC_NAME1;
	58	case BE_DEVICE_ID2:
	59	return BE3_NAME;
	60	default:
c4ca2374	61	return BE_NAME;
12d7ea2c	62	}
c4ca2374 AK	63	}
c4ca2374 AK	64
6b7c5b94 SP	65	/* Number of bytes of an RX frame that are copied to skb->data */
	66	#define BE_HDR_LEN 64
	67	#define BE_MAX_JUMBO_FRAME_SIZE 9018
	68	#define BE_MIN_MTU 256
	69
	70	#define BE_NUM_VLANS_SUPPORTED 64
	71	#define BE_MAX_EQD 96
	72	#define BE_MAX_TX_FRAG_COUNT 30
	73
	74	#define EVNT_Q_LEN 1024
	75	#define TX_Q_LEN 2048
	76	#define TX_CQ_LEN 1024
	77	#define RX_Q_LEN 1024 /* Does not support any other value */
	78	#define RX_CQ_LEN 1024
5fb379ee	79	#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
6b7c5b94 SP	80	#define MCC_CQ_LEN 256
	81
	82	#define BE_NAPI_WEIGHT 64
	83	#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
	84	#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
	85
8788fdc2 SP	86	#define FW_VER_LEN 32
8788fdc2 SP	87
6b7c5b94 SP	88	struct be_dma_mem {
	89	void *va;
	90	dma_addr_t dma;
	91	u32 size;
	92	};
	93
	94	struct be_queue_info {
	95	struct be_dma_mem dma_mem;
	96	u16 len;
	97	u16 entry_size; /* Size of an element in the queue */
	98	u16 id;
	99	u16 tail, head;
	100	bool created;
	101	atomic_t used; /* Number of valid elements in the queue */
	102	};
	103
5fb379ee SP	104	static inline u32 MODULO(u16 val, u16 limit)
	105	{
	106	BUG_ON(limit & (limit - 1));
	107	return val & (limit - 1);
	108	}
	109
	110	static inline void index_adv(u16 *index, u16 val, u16 limit)
	111	{
	112	index = MODULO((index + val), limit);
	113	}
	114
	115	static inline void index_inc(u16 *index, u16 limit)
	116	{
	117	index = MODULO((index + 1), limit);
	118	}
	119
	120	static inline void queue_head_node(struct be_queue_info q)
	121	{
	122	return q->dma_mem.va + q->head * q->entry_size;
	123	}
	124
	125	static inline void queue_tail_node(struct be_queue_info q)
	126	{
	127	return q->dma_mem.va + q->tail * q->entry_size;
	128	}
	129
	130	static inline void queue_head_inc(struct be_queue_info *q)
	131	{
	132	index_inc(&q->head, q->len);
	133	}
	134
	135	static inline void queue_tail_inc(struct be_queue_info *q)
	136	{
	137	index_inc(&q->tail, q->len);
	138	}
	139
5fb379ee SP	140	struct be_eq_obj {
	141	struct be_queue_info q;
	142	char desc[32];
	143
	144	/* Adaptive interrupt coalescing (AIC) info */
	145	bool enable_aic;
	146	u16 min_eqd; /* in usecs */
	147	u16 max_eqd; /* in usecs */
	148	u16 cur_eqd; /* in usecs */
	149
	150	struct napi_struct napi;
	151	};
	152
	153	struct be_mcc_obj {
	154	struct be_queue_info q;
	155	struct be_queue_info cq;
	156	};
	157
6b7c5b94 SP	158	struct be_drvr_stats {
	159	u32 be_tx_reqs; /* number of TX requests initiated */
	160	u32 be_tx_stops; /* number of times TX Q was stopped */
	161	u32 be_fwd_reqs; /* number of send reqs through forwarding i/f */
	162	u32 be_tx_wrbs; /* number of tx WRBs used */
	163	u32 be_tx_events; /* number of tx completion events */
	164	u32 be_tx_compl; /* number of tx completion entries processed */
4097f663 SP	165	ulong be_tx_jiffies;
	166	u64 be_tx_bytes;
	167	u64 be_tx_bytes_prev;
6b7c5b94 SP	168	u32 be_tx_rate;
	169
	170	u32 cache_barrier[16];
	171
	172	u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
b7b83ac3	173	u32 be_rx_polls; /* number of times NAPI called poll function */
6b7c5b94 SP	174	u32 be_rx_events; /* number of ucast rx completion events */
6b7c5b94 SP	175	u32 be_rx_compl; /* number of rx completion entries processed */
4097f663 SP	176	ulong be_rx_jiffies;
	177	u64 be_rx_bytes;
	178	u64 be_rx_bytes_prev;
6b7c5b94 SP	179	u32 be_rx_rate;
	180	/* number of non ether type II frames dropped where
	181	* frame len > length field of Mac Hdr */
	182	u32 be_802_3_dropped_frames;
	183	/* number of non ether type II frames malformed where
	184	* in frame len < length field of Mac Hdr */
	185	u32 be_802_3_malformed_frames;
	186	u32 be_rxcp_err; /* Num rx completion entries w/ err set. */
	187	ulong rx_fps_jiffies; /* jiffies at last FPS calc */
	188	u32 be_rx_frags;
	189	u32 be_prev_rx_frags;
	190	u32 be_rx_fps; /* Rx frags per second */
	191	};
	192
	193	struct be_stats_obj {
	194	struct be_drvr_stats drvr_stats;
6b7c5b94 SP	195	struct be_dma_mem cmd;
	196	};
	197
6b7c5b94 SP	198	struct be_tx_obj {
	199	struct be_queue_info q;
	200	struct be_queue_info cq;
	201	/* Remember the skbs that were transmitted */
	202	struct sk_buff *sent_skb_list[TX_Q_LEN];
	203	};
	204
	205	/* Struct to remember the pages posted for rx frags */
	206	struct be_rx_page_info {
	207	struct page *page;
	208	dma_addr_t bus;
	209	u16 page_offset;
	210	bool last_page_user;
	211	};
	212
	213	struct be_rx_obj {
	214	struct be_queue_info q;
	215	struct be_queue_info cq;
	216	struct be_rx_page_info page_info_tbl[RX_Q_LEN];
6b7c5b94 SP	217	};
	218
	219	#define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */
	220	struct be_adapter {
	221	struct pci_dev *pdev;
	222	struct net_device *netdev;
	223
8788fdc2 SP	224	u8 __iomem *csr;
	225	u8 __iomem db; / Door Bell */
	226	u8 __iomem pcicfg; / PCI config space */
8788fdc2 SP	227
	228	spinlock_t mbox_lock; /* For serializing mbox cmds to BE card */
	229	struct be_dma_mem mbox_mem;
	230	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
	231	* is stored for freeing purpose */
	232	struct be_dma_mem mbox_mem_alloced;
	233
	234	struct be_mcc_obj mcc_obj;
	235	spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
	236	spinlock_t mcc_cq_lock;
6b7c5b94 SP	237
	238	struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
	239	bool msix_enabled;
	240	bool isr_registered;
	241
	242	/* TX Rings */
	243	struct be_eq_obj tx_eq;
	244	struct be_tx_obj tx_obj;
	245
	246	u32 cache_line_break[8];
	247
	248	/* Rx rings */
	249	struct be_eq_obj rx_eq;
	250	struct be_rx_obj rx_obj;
	251	u32 big_page_size; /* Compounded page size shared by rx wrbs */
ea1dae11	252	bool rx_post_starved; /* Zero rx frags have been posted to BE */
6b7c5b94 SP	253
	254	struct vlan_group *vlan_grp;
	255	u16 num_vlans;
	256	u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
e7b909a6	257	struct be_dma_mem mc_cmd_mem;
6b7c5b94 SP	258
	259	struct be_stats_obj stats;
	260	/* Work queue used to perform periodic tasks like getting statistics */
	261	struct delayed_work work;
	262
	263	/* Ethtool knobs and info */
	264	bool rx_csum; /* BE card must perform rx-checksumming */
6b7c5b94 SP	265	char fw_ver[FW_VER_LEN];
	266	u32 if_handle; /* Used to configure filtering */
	267	u32 pmac_id; /* MAC addr handle used by BE card */
	268
a8f447bd	269	bool link_up;
6b7c5b94	270	u32 port_num;
24307eef	271	bool promiscuous;
71d8d1b5	272	bool wol;
dcb9b564	273	u32 cap;
9e90c961 AK	274	u32 rx_fc; /* Rx flow control */
9e90c961 AK	275	u32 tx_fc; /* Tx flow control */
0dffc83e AK	276	int link_speed;
0dffc83e AK	277	u8 port_type;
16c02145	278	u8 transceiver;
6b7c5b94 SP	279	};
6b7c5b94 SP	280
0fc0b732	281	extern const struct ethtool_ops be_ethtool_ops;
6b7c5b94 SP	282
	283	#define drvr_stats(adapter) (&adapter->stats.drvr_stats)
	284
eec368fb SP	285	static inline unsigned int be_pci_func(struct be_adapter *adapter)
	286	{
	287	return PCI_FUNC(adapter->pdev->devfn);
	288	}
	289
6b7c5b94 SP	290	#define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
6b7c5b94 SP	291
6b7c5b94 SP	292	#define PAGE_SHIFT_4K 12
	293	#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
	294
	295	/* Returns number of pages spanned by the data starting at the given addr */
	296	#define PAGES_4K_SPANNED(_address, size) \
	297	((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
	298	(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
	299
	300	/* Byte offset into the page corresponding to given address */
	301	#define OFFSET_IN_PAGE(addr) \
	302	((size_t)(addr) & (PAGE_SIZE_4K-1))
	303
	304	/* Returns bit offset within a DWORD of a bitfield */
	305	#define AMAP_BIT_OFFSET(_struct, field) \
	306	(((size_t)&(((_struct *)0)->field))%32)
	307
	308	/* Returns the bit mask of the field that is NOT shifted into location. */
	309	static inline u32 amap_mask(u32 bitsize)
	310	{
	311	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
	312	}
	313
	314	static inline void
	315	amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
	316	{
	317	u32 dw = (u32 ) ptr + dw_offset;
	318	*dw &= ~(mask << offset);
	319	*dw \|= (mask & value) << offset;
	320	}
	321
	322	#define AMAP_SET_BITS(_struct, field, ptr, val) \
	323	amap_set(ptr, \
	324	offsetof(_struct, field)/32, \
	325	amap_mask(sizeof(((_struct *)0)->field)), \
	326	AMAP_BIT_OFFSET(_struct, field), \
	327	val)
	328
	329	static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
	330	{
	331	u32 dw = (u32 ) ptr;
	332	return mask & (*(dw + dw_offset) >> offset);
	333	}
	334
	335	#define AMAP_GET_BITS(_struct, field, ptr) \
	336	amap_get(ptr, \
	337	offsetof(_struct, field)/32, \
	338	amap_mask(sizeof(((_struct *)0)->field)), \
	339	AMAP_BIT_OFFSET(_struct, field))
	340
	341	#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
	342	#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
	343	static inline void swap_dws(void *wrb, int len)
	344	{
	345	#ifdef __BIG_ENDIAN
	346	u32 *dw = wrb;
	347	BUG_ON(len % 4);
	348	do {
	349	dw = cpu_to_le32(dw);
	350	dw++;
	351	len -= 4;
	352	} while (len);
	353	#endif /* __BIG_ENDIAN */
	354	}
	355
356	static inline u8 is_tcp_pkt(struct sk_buff *skb)
357	{
358	u8 val = 0;
359
360	if (ip_hdr(skb)->version == 4)
361	val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
362	else if (ip_hdr(skb)->version == 6)
363	val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
364
365	return val;
366	}
367
368	static inline u8 is_udp_pkt(struct sk_buff *skb)
369	{
370	u8 val = 0;
371
372	if (ip_hdr(skb)->version == 4)
373	val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
374	else if (ip_hdr(skb)->version == 6)
375	val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
376
377	return val;
378	}
379
8788fdc2	380	extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
5fb379ee	381	u16 num_popped);
8788fdc2	382	extern void be_link_status_update(struct be_adapter *adapter, bool link_up);
b31c50a7	383	extern void netdev_stats_update(struct be_adapter *adapter);
84517482	384	extern int be_load_fw(struct be_adapter adapter, u8 func);
6b7c5b94	385	#endif /* BE_H */