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ARM: SAMSUNG: MMC: fix build error when both DMA and PIO mode selected
[net-next-2.6.git] / drivers / mmc / host / s3cmci.c
CommitLineData
be518018
TK		 1/*
2 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
3 *
4 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
5 *
08c55e22 6 * Current driver maintained by Ben Dooks and Simtec Electronics
7 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
8 *
be518018
TK		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/dma-mapping.h>
16#include <linux/clk.h>
17#include <linux/mmc/host.h>
18#include <linux/platform_device.h>
f87e6d00 19#include <linux/cpufreq.h>
9bdd203b
BD		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
ec976d6e 22#include <linux/gpio.h>
be518018
TK		 23#include <linux/irq.h>
24#include <linux/io.h>
25
7ad14f83 26#include <mach/dma.h>
be518018 27
a09e64fb
RK		 28#include <mach/regs-sdi.h>
29#include <mach/regs-gpio.h>
be518018 30
e3bd9ec5 31#include <plat/mci.h>
edb5a98e 32
be518018
TK		 33#include "s3cmci.h"
34
35#define DRIVER_NAME "s3c-mci"
36
37enum dbg_channels {
38 dbg_err = (1 << 0),
39 dbg_debug = (1 << 1),
40 dbg_info = (1 << 2),
41 dbg_irq = (1 << 3),
42 dbg_sg = (1 << 4),
43 dbg_dma = (1 << 5),
44 dbg_pio = (1 << 6),
45 dbg_fail = (1 << 7),
46 dbg_conf = (1 << 8),
47};
48
9c2e7e40 49static const int dbgmap_err = dbg_fail;
be518018 50static const int dbgmap_info = dbg_info | dbg_conf;
9c2e7e40 51static const int dbgmap_debug = dbg_err | dbg_debug;
be518018
TK		 52
53#define dbg(host, channels, args...) \
54 do { \
55 if (dbgmap_err & channels) \
56 dev_err(&host->pdev->dev, args); \
57 else if (dbgmap_info & channels) \
58 dev_info(&host->pdev->dev, args); \
59 else if (dbgmap_debug & channels) \
60 dev_dbg(&host->pdev->dev, args); \
61 } while (0)
62
be518018
TK		 63static struct s3c2410_dma_client s3cmci_dma_client = {
64 .name = "s3c-mci",
65};
66
67static void finalize_request(struct s3cmci_host *host);
68static void s3cmci_send_request(struct mmc_host *mmc);
69static void s3cmci_reset(struct s3cmci_host *host);
70
71#ifdef CONFIG_MMC_DEBUG
72
73static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
74{
75 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
76 u32 datcon, datcnt, datsta, fsta, imask;
77
78 con = readl(host->base + S3C2410_SDICON);
79 pre = readl(host->base + S3C2410_SDIPRE);
80 cmdarg = readl(host->base + S3C2410_SDICMDARG);
81 cmdcon = readl(host->base + S3C2410_SDICMDCON);
82 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
83 r0 = readl(host->base + S3C2410_SDIRSP0);
84 r1 = readl(host->base + S3C2410_SDIRSP1);
85 r2 = readl(host->base + S3C2410_SDIRSP2);
86 r3 = readl(host->base + S3C2410_SDIRSP3);
87 timer = readl(host->base + S3C2410_SDITIMER);
88 bsize = readl(host->base + S3C2410_SDIBSIZE);
89 datcon = readl(host->base + S3C2410_SDIDCON);
90 datcnt = readl(host->base + S3C2410_SDIDCNT);
91 datsta = readl(host->base + S3C2410_SDIDSTA);
92 fsta = readl(host->base + S3C2410_SDIFSTA);
93 imask = readl(host->base + host->sdiimsk);
94
95 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
96 prefix, con, pre, timer);
97
98 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
99 prefix, cmdcon, cmdarg, cmdsta);
100
101 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
102 " DSTA:[%08x] DCNT:[%08x]\n",
103 prefix, datcon, fsta, datsta, datcnt);
104
105 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
106 " R2:[%08x] R3:[%08x]\n",
107 prefix, r0, r1, r2, r3);
108}
109
110static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
111 int stop)
112{
113 snprintf(host->dbgmsg_cmd, 300,
114 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
115 host->ccnt, (stop ? " (STOP)" : ""),
116 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
117
118 if (cmd->data) {
119 snprintf(host->dbgmsg_dat, 300,
120 "#%u bsize:%u blocks:%u bytes:%u",
121 host->dcnt, cmd->data->blksz,
122 cmd->data->blocks,
123 cmd->data->blocks * cmd->data->blksz);
124 } else {
125 host->dbgmsg_dat[0] = '\0';
126 }
127}
128
129static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
130 int fail)
131{
132 unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
133
134 if (!cmd)
135 return;
136
137 if (cmd->error == 0) {
138 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
139 host->dbgmsg_cmd, cmd->resp[0]);
140 } else {
141 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
142 cmd->error, host->dbgmsg_cmd, host->status);
143 }
144
145 if (!cmd->data)
146 return;
147
148 if (cmd->data->error == 0) {
149 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
150 } else {
151 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
152 cmd->data->error, host->dbgmsg_dat,
153 readl(host->base + S3C2410_SDIDCNT));
154 }
155}
156#else
157static void dbg_dumpcmd(struct s3cmci_host *host,
158 struct mmc_command *cmd, int fail) { }
159
160static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
161 int stop) { }
162
163static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
164
165#endif /* CONFIG_MMC_DEBUG */
166
26f14947
BD		 167/**
168 * s3cmci_host_usedma - return whether the host is using dma or pio
169 * @host: The host state
170 *
171 * Return true if the host is using DMA to transfer data, else false
172 * to use PIO mode. Will return static data depending on the driver
173 * configuration.
174 */
175static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
176{
177#ifdef CONFIG_MMC_S3C_PIO
178 return false;
179#elif defined(CONFIG_MMC_S3C_DMA)
180 return true;
181#else
182 return host->dodma;
183#endif
184}
185
68c5ed59
BD		 186/**
187 * s3cmci_host_canpio - return true if host has pio code available
188 *
189 * Return true if the driver has been compiled with the PIO support code
190 * available.
191 */
192static inline bool s3cmci_host_canpio(void)
193{
194#ifdef CONFIG_MMC_S3C_PIO
195 return true;
196#else
197 return false;
198#endif
199}
200
be518018
TK		 201static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
202{
203 u32 newmask;
204
205 newmask = readl(host->base + host->sdiimsk);
206 newmask |= imask;
207
208 writel(newmask, host->base + host->sdiimsk);
209
210 return newmask;
211}
212
213static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
214{
215 u32 newmask;
216
217 newmask = readl(host->base + host->sdiimsk);
218 newmask &= ~imask;
219
220 writel(newmask, host->base + host->sdiimsk);
221
222 return newmask;
223}
224
225static inline void clear_imask(struct s3cmci_host *host)
226{
c2258893
BD		 227 u32 mask = readl(host->base + host->sdiimsk);
228
229 /* preserve the SDIO IRQ mask state */
230 mask &= S3C2410_SDIIMSK_SDIOIRQ;
231 writel(mask, host->base + host->sdiimsk);
232}
233
234/**
235 * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
236 * @host: The host to check.
237 *
238 * Test to see if the SDIO interrupt is being signalled in case the
239 * controller has failed to re-detect a card interrupt. Read GPE8 and
240 * see if it is low and if so, signal a SDIO interrupt.
241 *
242 * This is currently called if a request is finished (we assume that the
243 * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
244 * already being indicated.
245*/
246static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
247{
248 if (host->sdio_irqen) {
249 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
250 printk(KERN_DEBUG "%s: signalling irq\n", __func__);
251 mmc_signal_sdio_irq(host->mmc);
252 }
253 }
be518018
TK		 254}
255
256static inline int get_data_buffer(struct s3cmci_host *host,
088a78af 257 u32 *bytes, u32 **pointer)
be518018
TK		 258{
259 struct scatterlist *sg;
260
261 if (host->pio_active == XFER_NONE)
262 return -EINVAL;
263
264 if ((!host->mrq) || (!host->mrq->data))
265 return -EINVAL;
266
267 if (host->pio_sgptr >= host->mrq->data->sg_len) {
268 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
269 host->pio_sgptr, host->mrq->data->sg_len);
270 return -EBUSY;
271 }
272 sg = &host->mrq->data->sg[host->pio_sgptr];
273
088a78af 274 *bytes = sg->length;
be518018
TK		 275 *pointer = sg_virt(sg);
276
277 host->pio_sgptr++;
278
279 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
280 host->pio_sgptr, host->mrq->data->sg_len);
281
282 return 0;
283}
284
285static inline u32 fifo_count(struct s3cmci_host *host)
286{
287 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
288
289 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
088a78af 290 return fifostat;
be518018
TK		 291}
292
293static inline u32 fifo_free(struct s3cmci_host *host)
294{
295 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
296
297 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
088a78af 298 return 63 - fifostat;
be518018
TK		 299}
300
c2258893
BD		 301/**
302 * s3cmci_enable_irq - enable IRQ, after having disabled it.
303 * @host: The device state.
304 * @more: True if more IRQs are expected from transfer.
305 *
306 * Enable the main IRQ if needed after it has been disabled.
307 *
308 * The IRQ can be one of the following states:
309 * - disabled during IDLE
310 * - disabled whilst processing data
311 * - enabled during transfer
312 * - enabled whilst awaiting SDIO interrupt detection
313 */
314static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
315{
316 unsigned long flags;
317 bool enable = false;
318
319 local_irq_save(flags);
320
321 host->irq_enabled = more;
322 host->irq_disabled = false;
323
324 enable = more | host->sdio_irqen;
325
326 if (host->irq_state != enable) {
327 host->irq_state = enable;
328
329 if (enable)
330 enable_irq(host->irq);
331 else
332 disable_irq(host->irq);
333 }
334
335 local_irq_restore(flags);
336}
337
338/**
339 *
340 */
341static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
342{
343 unsigned long flags;
344
345 local_irq_save(flags);
346
347 //printk(KERN_DEBUG "%s: transfer %d\n", __func__, transfer);
348
349 host->irq_disabled = transfer;
350
351 if (transfer && host->irq_state) {
352 host->irq_state = false;
353 disable_irq(host->irq);
354 }
355
356 local_irq_restore(flags);
357}
358
be518018
TK		 359static void do_pio_read(struct s3cmci_host *host)
360{
361 int res;
362 u32 fifo;
18280fff 363 u32 *ptr;
088a78af 364 u32 fifo_words;
be518018
TK		 365 void __iomem *from_ptr;
366
367 /* write real prescaler to host, it might be set slow to fix */
368 writel(host->prescaler, host->base + S3C2410_SDIPRE);
369
370 from_ptr = host->base + host->sdidata;
371
372 while ((fifo = fifo_count(host))) {
088a78af
CW		 373 if (!host->pio_bytes) {
374 res = get_data_buffer(host, &host->pio_bytes,
be518018
TK		 375 &host->pio_ptr);
376 if (res) {
377 host->pio_active = XFER_NONE;
378 host->complete_what = COMPLETION_FINALIZE;
379
380 dbg(host, dbg_pio, "pio_read(): "
381 "complete (no more data).\n");
382 return;
383 }
384
385 dbg(host, dbg_pio,
386 "pio_read(): new target: [%i]@[%p]\n",
088a78af 387 host->pio_bytes, host->pio_ptr);
be518018
TK		 388 }
389
390 dbg(host, dbg_pio,
391 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
088a78af 392 fifo, host->pio_bytes,
be518018
TK		 393 readl(host->base + S3C2410_SDIDCNT));
394
088a78af
CW		 395 /* If we have reached the end of the block, we can
396 * read a word and get 1 to 3 bytes. If we in the
397 * middle of the block, we have to read full words,
398 * otherwise we will write garbage, so round down to
399 * an even multiple of 4. */
400 if (fifo >= host->pio_bytes)
401 fifo = host->pio_bytes;
402 else
403 fifo -= fifo & 3;
404
405 host->pio_bytes -= fifo;
be518018
TK		 406 host->pio_count += fifo;
407
088a78af 408 fifo_words = fifo >> 2;
18280fff 409 ptr = host->pio_ptr;
088a78af 410 while (fifo_words--)
18280fff 411 *ptr++ = readl(from_ptr);
412 host->pio_ptr = ptr;
088a78af
CW		 413
414 if (fifo & 3) {
415 u32 n = fifo & 3;
416 u32 data = readl(from_ptr);
417 u8 *p = (u8 *)host->pio_ptr;
418
419 while (n--) {
420 *p++ = data;
421 data >>= 8;
422 }
423 }
be518018
TK		 424 }
425
088a78af
CW		 426 if (!host->pio_bytes) {
427 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
be518018
TK		 428 if (res) {
429 dbg(host, dbg_pio,
430 "pio_read(): complete (no more buffers).\n");
431 host->pio_active = XFER_NONE;
432 host->complete_what = COMPLETION_FINALIZE;
433
434 return;
435 }
436 }
437
438 enable_imask(host,
439 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
440}
441
442static void do_pio_write(struct s3cmci_host *host)
443{
444 void __iomem *to_ptr;
445 int res;
446 u32 fifo;
18280fff 447 u32 *ptr;
be518018
TK		 448
449 to_ptr = host->base + host->sdidata;
450
99424488 451 while ((fifo = fifo_free(host)) > 3) {
088a78af
CW		 452 if (!host->pio_bytes) {
453 res = get_data_buffer(host, &host->pio_bytes,
be518018
TK		 454 &host->pio_ptr);
455 if (res) {
456 dbg(host, dbg_pio,
457 "pio_write(): complete (no more data).\n");
458 host->pio_active = XFER_NONE;
459
460 return;
461 }
462
463 dbg(host, dbg_pio,
464 "pio_write(): new source: [%i]@[%p]\n",
088a78af 465 host->pio_bytes, host->pio_ptr);
be518018
TK		 466
467 }
468
088a78af
CW		 469 /* If we have reached the end of the block, we have to
470 * write exactly the remaining number of bytes. If we
471 * in the middle of the block, we have to write full
472 * words, so round down to an even multiple of 4. */
473 if (fifo >= host->pio_bytes)
474 fifo = host->pio_bytes;
475 else
476 fifo -= fifo & 3;
be518018 477
088a78af 478 host->pio_bytes -= fifo;
be518018
TK		 479 host->pio_count += fifo;
480
088a78af 481 fifo = (fifo + 3) >> 2;
18280fff 482 ptr = host->pio_ptr;
be518018 483 while (fifo--)
18280fff 484 writel(*ptr++, to_ptr);
485 host->pio_ptr = ptr;
be518018
TK		 486 }
487
488 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
489}
490
491static void pio_tasklet(unsigned long data)
492{
493 struct s3cmci_host *host = (struct s3cmci_host *) data;
494
c2258893 495 s3cmci_disable_irq(host, true);
d643b5f7 496
be518018
TK		 497 if (host->pio_active == XFER_WRITE)
498 do_pio_write(host);
499
500 if (host->pio_active == XFER_READ)
501 do_pio_read(host);
502
503 if (host->complete_what == COMPLETION_FINALIZE) {
504 clear_imask(host);
505 if (host->pio_active != XFER_NONE) {
506 dbg(host, dbg_err, "unfinished %s "
088a78af 507 "- pio_count:[%u] pio_bytes:[%u]\n",
be518018 508 (host->pio_active == XFER_READ) ? "read" : "write",
088a78af 509 host->pio_count, host->pio_bytes);
be518018 510
7c14450e
BD		 511 if (host->mrq->data)
512 host->mrq->data->error = -EINVAL;
be518018
TK		 513 }
514
c2258893 515 s3cmci_enable_irq(host, false);
be518018 516 finalize_request(host);
d643b5f7 517 } else
c2258893 518 s3cmci_enable_irq(host, true);
be518018
TK		 519}
520
521/*
522 * ISR for SDI Interface IRQ
523 * Communication between driver and ISR works as follows:
524 * host->mrq points to current request
525 * host->complete_what Indicates when the request is considered done
526 * COMPLETION_CMDSENT when the command was sent
527 * COMPLETION_RSPFIN when a response was received
528 * COMPLETION_XFERFINISH when the data transfer is finished
529 * COMPLETION_XFERFINISH_RSPFIN both of the above.
530 * host->complete_request is the completion-object the driver waits for
531 *
532 * 1) Driver sets up host->mrq and host->complete_what
533 * 2) Driver prepares the transfer
534 * 3) Driver enables interrupts
535 * 4) Driver starts transfer
536 * 5) Driver waits for host->complete_rquest
537 * 6) ISR checks for request status (errors and success)
538 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
539 * 7) ISR completes host->complete_request
540 * 8) ISR disables interrupts
541 * 9) Driver wakes up and takes care of the request
542 *
543 * Note: "->error"-fields are expected to be set to 0 before the request
544 * was issued by mmc.c - therefore they are only set, when an error
545 * contition comes up
546 */
547
548static irqreturn_t s3cmci_irq(int irq, void *dev_id)
549{
550 struct s3cmci_host *host = dev_id;
551 struct mmc_command *cmd;
552 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
c2258893 553 u32 mci_cclear = 0, mci_dclear;
be518018
TK		 554 unsigned long iflags;
555
c2258893
BD		 556 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
557 mci_imsk = readl(host->base + host->sdiimsk);
558
559 if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
560 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
561 mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
562 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
563
564 mmc_signal_sdio_irq(host->mmc);
565 return IRQ_HANDLED;
566 }
567 }
568
be518018
TK		 569 spin_lock_irqsave(&host->complete_lock, iflags);
570
571 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
be518018
TK		 572 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
573 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
be518018
TK		 574 mci_dclear = 0;
575
576 if ((host->complete_what == COMPLETION_NONE) ||
577 (host->complete_what == COMPLETION_FINALIZE)) {
578 host->status = "nothing to complete";
579 clear_imask(host);
580 goto irq_out;
581 }
582
583 if (!host->mrq) {
584 host->status = "no active mrq";
585 clear_imask(host);
586 goto irq_out;
587 }
588
589 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
590
591 if (!cmd) {
592 host->status = "no active cmd";
593 clear_imask(host);
594 goto irq_out;
595 }
596
26f14947 597 if (!s3cmci_host_usedma(host)) {
be518018
TK		 598 if ((host->pio_active == XFER_WRITE) &&
599 (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
600
601 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
602 tasklet_schedule(&host->pio_tasklet);
603 host->status = "pio tx";
604 }
605
606 if ((host->pio_active == XFER_READ) &&
607 (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
608
609 disable_imask(host,
610 S3C2410_SDIIMSK_RXFIFOHALF |
611 S3C2410_SDIIMSK_RXFIFOLAST);
612
613 tasklet_schedule(&host->pio_tasklet);
614 host->status = "pio rx";
615 }
616 }
617
618 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
ff8c804f 619 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
be518018
TK		 620 cmd->error = -ETIMEDOUT;
621 host->status = "error: command timeout";
622 goto fail_transfer;
623 }
624
625 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
626 if (host->complete_what == COMPLETION_CMDSENT) {
627 host->status = "ok: command sent";
628 goto close_transfer;
629 }
630
631 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
632 }
633
634 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
635 if (cmd->flags & MMC_RSP_CRC) {
679f0f8a
HW		 636 if (host->mrq->cmd->flags & MMC_RSP_136) {
637 dbg(host, dbg_irq,
638 "fixup: ignore CRC fail with long rsp\n");
639 } else {
640 /* note, we used to fail the transfer
641 * here, but it seems that this is just
642 * the hardware getting it wrong.
643 *
644 * cmd->error = -EILSEQ;
645 * host->status = "error: bad command crc";
646 * goto fail_transfer;
647 */
648 }
be518018
TK		 649 }
650
651 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
652 }
653
654 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
655 if (host->complete_what == COMPLETION_RSPFIN) {
656 host->status = "ok: command response received";
657 goto close_transfer;
658 }
659
660 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
661 host->complete_what = COMPLETION_XFERFINISH;
662
663 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
664 }
665
666 /* errors handled after this point are only relevant
667 when a data transfer is in progress */
668
669 if (!cmd->data)
670 goto clear_status_bits;
671
672 /* Check for FIFO failure */
673 if (host->is2440) {
674 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
ff8c804f 675 dbg(host, dbg_err, "FIFO failure\n");
be518018
TK		 676 host->mrq->data->error = -EILSEQ;
677 host->status = "error: 2440 fifo failure";
678 goto fail_transfer;
679 }
680 } else {
681 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
ff8c804f 682 dbg(host, dbg_err, "FIFO failure\n");
be518018
TK		 683 cmd->data->error = -EILSEQ;
684 host->status = "error: fifo failure";
685 goto fail_transfer;
686 }
687 }
688
689 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
ff8c804f 690 dbg(host, dbg_err, "bad data crc (outgoing)\n");
be518018
TK		 691 cmd->data->error = -EILSEQ;
692 host->status = "error: bad data crc (outgoing)";
693 goto fail_transfer;
694 }
695
696 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
ff8c804f 697 dbg(host, dbg_err, "bad data crc (incoming)\n");
be518018
TK		 698 cmd->data->error = -EILSEQ;
699 host->status = "error: bad data crc (incoming)";
700 goto fail_transfer;
701 }
702
703 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
ff8c804f 704 dbg(host, dbg_err, "data timeout\n");
be518018
TK		 705 cmd->data->error = -ETIMEDOUT;
706 host->status = "error: data timeout";
707 goto fail_transfer;
708 }
709
710 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
711 if (host->complete_what == COMPLETION_XFERFINISH) {
712 host->status = "ok: data transfer completed";
713 goto close_transfer;
714 }
715
716 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
717 host->complete_what = COMPLETION_RSPFIN;
718
719 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
720 }
721
722clear_status_bits:
723 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
724 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
725
726 goto irq_out;
727
728fail_transfer:
729 host->pio_active = XFER_NONE;
730
731close_transfer:
732 host->complete_what = COMPLETION_FINALIZE;
733
734 clear_imask(host);
735 tasklet_schedule(&host->pio_tasklet);
736
737 goto irq_out;
738
739irq_out:
740 dbg(host, dbg_irq,
741 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
742 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
743
744 spin_unlock_irqrestore(&host->complete_lock, iflags);
745 return IRQ_HANDLED;
746
747}
748
749/*
750 * ISR for the CardDetect Pin
751*/
752
753static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
754{
755 struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
756
757 dbg(host, dbg_irq, "card detect\n");
758
2de5f79d 759 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
be518018
TK		 760
761 return IRQ_HANDLED;
762}
763
5d304400
BD		 764static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
765 void *buf_id, int size,
766 enum s3c2410_dma_buffresult result)
be518018
TK		 767{
768 struct s3cmci_host *host = buf_id;
769 unsigned long iflags;
770 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
771
772 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
773 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
774 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
775 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
776
777 BUG_ON(!host->mrq);
778 BUG_ON(!host->mrq->data);
779 BUG_ON(!host->dmatogo);
780
781 spin_lock_irqsave(&host->complete_lock, iflags);
782
783 if (result != S3C2410_RES_OK) {
784 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
785 "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
786 mci_csta, mci_dsta, mci_fsta,
787 mci_dcnt, result, host->dmatogo);
788
789 goto fail_request;
790 }
791
792 host->dmatogo--;
793 if (host->dmatogo) {
794 dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] "
795 "DCNT:[%08x] toGo:%u\n",
796 size, mci_dsta, mci_dcnt, host->dmatogo);
797
798 goto out;
799 }
800
801 dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
802 size, mci_dsta, mci_dcnt);
803
68c5ed59 804 host->dma_complete = 1;
be518018
TK		 805 host->complete_what = COMPLETION_FINALIZE;
806
807out:
808 tasklet_schedule(&host->pio_tasklet);
809 spin_unlock_irqrestore(&host->complete_lock, iflags);
810 return;
811
be518018
TK		 812fail_request:
813 host->mrq->data->error = -EINVAL;
814 host->complete_what = COMPLETION_FINALIZE;
e6130aef 815 clear_imask(host);
be518018 816
e6130aef 817 goto out;
be518018
TK		 818}
819
820static void finalize_request(struct s3cmci_host *host)
821{
822 struct mmc_request *mrq = host->mrq;
3423d80a 823 struct mmc_command *cmd;
be518018
TK		 824 int debug_as_failure = 0;
825
826 if (host->complete_what != COMPLETION_FINALIZE)
827 return;
828
829 if (!mrq)
830 return;
3423d80a 831 cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
be518018
TK		 832
833 if (cmd->data && (cmd->error == 0) &&
834 (cmd->data->error == 0)) {
26f14947 835 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
68c5ed59
BD		 836 dbg(host, dbg_dma, "DMA Missing (%d)!\n",
837 host->dma_complete);
be518018
TK		 838 return;
839 }
840 }
841
842 /* Read response from controller. */
843 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
844 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
845 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
846 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
847
848 writel(host->prescaler, host->base + S3C2410_SDIPRE);
849
850 if (cmd->error)
851 debug_as_failure = 1;
852
853 if (cmd->data && cmd->data->error)
854 debug_as_failure = 1;
855
856 dbg_dumpcmd(host, cmd, debug_as_failure);
857
858 /* Cleanup controller */
859 writel(0, host->base + S3C2410_SDICMDARG);
bdbc9c3a 860 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
be518018 861 writel(0, host->base + S3C2410_SDICMDCON);
e6130aef 862 clear_imask(host);
be518018
TK		 863
864 if (cmd->data && cmd->error)
865 cmd->data->error = cmd->error;
866
867 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
868 host->cmd_is_stop = 1;
869 s3cmci_send_request(host->mmc);
870 return;
871 }
872
873 /* If we have no data transfer we are finished here */
874 if (!mrq->data)
875 goto request_done;
876
877 /* Calulate the amout of bytes transfer if there was no error */
878 if (mrq->data->error == 0) {
879 mrq->data->bytes_xfered =
880 (mrq->data->blocks * mrq->data->blksz);
881 } else {
882 mrq->data->bytes_xfered = 0;
883 }
884
885 /* If we had an error while transfering data we flush the
886 * DMA channel and the fifo to clear out any garbage. */
887 if (mrq->data->error != 0) {
26f14947 888 if (s3cmci_host_usedma(host))
be518018
TK		 889 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
890
891 if (host->is2440) {
892 /* Clear failure register and reset fifo. */
893 writel(S3C2440_SDIFSTA_FIFORESET |
894 S3C2440_SDIFSTA_FIFOFAIL,
895 host->base + S3C2410_SDIFSTA);
896 } else {
897 u32 mci_con;
898
899 /* reset fifo */
900 mci_con = readl(host->base + S3C2410_SDICON);
901 mci_con |= S3C2410_SDICON_FIFORESET;
902
903 writel(mci_con, host->base + S3C2410_SDICON);
904 }
905 }
906
907request_done:
908 host->complete_what = COMPLETION_NONE;
909 host->mrq = NULL;
c2258893
BD		 910
911 s3cmci_check_sdio_irq(host);
be518018
TK		 912 mmc_request_done(host->mmc, mrq);
913}
914
5d304400
BD		 915static void s3cmci_dma_setup(struct s3cmci_host *host,
916 enum s3c2410_dmasrc source)
be518018
TK		 917{
918 static enum s3c2410_dmasrc last_source = -1;
919 static int setup_ok;
920
921 if (last_source == source)
922 return;
923
924 last_source = source;
925
8970ef47 926 s3c2410_dma_devconfig(host->dma, source,
be518018
TK		 927 host->mem->start + host->sdidata);
928
929 if (!setup_ok) {
fe9db6cb 930 s3c2410_dma_config(host->dma, 4);
be518018
TK		 931 s3c2410_dma_set_buffdone_fn(host->dma,
932 s3cmci_dma_done_callback);
933 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
934 setup_ok = 1;
935 }
936}
937
938static void s3cmci_send_command(struct s3cmci_host *host,
939 struct mmc_command *cmd)
940{
941 u32 ccon, imsk;
942
943 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
944 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
945 S3C2410_SDIIMSK_RESPONSECRC;
946
947 enable_imask(host, imsk);
948
949 if (cmd->data)
950 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
951 else if (cmd->flags & MMC_RSP_PRESENT)
952 host->complete_what = COMPLETION_RSPFIN;
953 else
954 host->complete_what = COMPLETION_CMDSENT;
955
956 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
957
958 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
959 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
960
961 if (cmd->flags & MMC_RSP_PRESENT)
962 ccon |= S3C2410_SDICMDCON_WAITRSP;
963
964 if (cmd->flags & MMC_RSP_136)
965 ccon |= S3C2410_SDICMDCON_LONGRSP;
966
967 writel(ccon, host->base + S3C2410_SDICMDCON);
968}
969
970static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
971{
972 u32 dcon, imsk, stoptries = 3;
973
974 /* write DCON register */
975
976 if (!data) {
977 writel(0, host->base + S3C2410_SDIDCON);
978 return 0;
979 }
980
7e9c7b64
BD		 981 if ((data->blksz & 3) != 0) {
982 /* We cannot deal with unaligned blocks with more than
983 * one block being transfered. */
984
088a78af
CW		 985 if (data->blocks > 1) {
986 pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz);
7e9c7b64 987 return -EINVAL;
088a78af 988 }
7e9c7b64
BD		 989 }
990
be518018
TK		 991 while (readl(host->base + S3C2410_SDIDSTA) &
992 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
993
994 dbg(host, dbg_err,
995 "mci_setup_data() transfer stillin progress.\n");
996
bdbc9c3a 997 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
be518018
TK		 998 s3cmci_reset(host);
999
1000 if ((stoptries--) == 0) {
1001 dbg_dumpregs(host, "DRF");
1002 return -EINVAL;
1003 }
1004 }
1005
1006 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
1007
26f14947 1008 if (s3cmci_host_usedma(host))
be518018
TK		 1009 dcon |= S3C2410_SDIDCON_DMAEN;
1010
1011 if (host->bus_width == MMC_BUS_WIDTH_4)
1012 dcon |= S3C2410_SDIDCON_WIDEBUS;
1013
1014 if (!(data->flags & MMC_DATA_STREAM))
1015 dcon |= S3C2410_SDIDCON_BLOCKMODE;
1016
1017 if (data->flags & MMC_DATA_WRITE) {
1018 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1019 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1020 }
1021
1022 if (data->flags & MMC_DATA_READ) {
1023 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1024 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1025 }
1026
1027 if (host->is2440) {
1028 dcon |= S3C2440_SDIDCON_DS_WORD;
1029 dcon |= S3C2440_SDIDCON_DATSTART;
1030 }
1031
1032 writel(dcon, host->base + S3C2410_SDIDCON);
1033
1034 /* write BSIZE register */
1035
1036 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1037
1038 /* add to IMASK register */
1039 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1040 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1041
1042 enable_imask(host, imsk);
1043
1044 /* write TIMER register */
1045
1046 if (host->is2440) {
1047 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1048 } else {
1049 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1050
1051 /* FIX: set slow clock to prevent timeouts on read */
1052 if (data->flags & MMC_DATA_READ)
1053 writel(0xFF, host->base + S3C2410_SDIPRE);
1054 }
1055
1056 return 0;
1057}
1058
1059#define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1060
1061static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1062{
1063 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1064
1065 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1066
1067 host->pio_sgptr = 0;
088a78af 1068 host->pio_bytes = 0;
be518018
TK		 1069 host->pio_count = 0;
1070 host->pio_active = rw ? XFER_WRITE : XFER_READ;
1071
1072 if (rw) {
1073 do_pio_write(host);
1074 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1075 } else {
1076 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1077 | S3C2410_SDIIMSK_RXFIFOLAST);
1078 }
1079
1080 return 0;
1081}
1082
1083static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1084{
1085 int dma_len, i;
68c5ed59 1086 int rw = data->flags & MMC_DATA_WRITE;
be518018
TK		 1087
1088 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1089
1090 s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW);
1091 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1092
1093 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
68c5ed59 1094 rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
be518018
TK		 1095
1096 if (dma_len == 0)
1097 return -ENOMEM;
1098
1099 host->dma_complete = 0;
1100 host->dmatogo = dma_len;
1101
1102 for (i = 0; i < dma_len; i++) {
1103 int res;
1104
68c5ed59
BD		 1105 dbg(host, dbg_dma, "enqueue %i: %08x@%u\n", i,
1106 sg_dma_address(&data->sg[i]),
1107 sg_dma_len(&data->sg[i]));
be518018 1108
68c5ed59 1109 res = s3c2410_dma_enqueue(host->dma, host,
be518018
TK		 1110 sg_dma_address(&data->sg[i]),
1111 sg_dma_len(&data->sg[i]));
1112
1113 if (res) {
1114 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1115 return -EBUSY;
1116 }
1117 }
1118
1119 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
1120
1121 return 0;
1122}
1123
1124static void s3cmci_send_request(struct mmc_host *mmc)
1125{
1126 struct s3cmci_host *host = mmc_priv(mmc);
1127 struct mmc_request *mrq = host->mrq;
1128 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1129
1130 host->ccnt++;
1131 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1132
1133 /* Clear command, data and fifo status registers
1134 Fifo clear only necessary on 2440, but doesn't hurt on 2410
1135 */
1136 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1137 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1138 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1139
1140 if (cmd->data) {
1141 int res = s3cmci_setup_data(host, cmd->data);
1142
1143 host->dcnt++;
1144
1145 if (res) {
ff8c804f
BD		 1146 dbg(host, dbg_err, "setup data error %d\n", res);
1147 cmd->error = res;
1148 cmd->data->error = res;
be518018
TK		 1149
1150 mmc_request_done(mmc, mrq);
1151 return;
1152 }
1153
26f14947 1154 if (s3cmci_host_usedma(host))
be518018
TK		 1155 res = s3cmci_prepare_dma(host, cmd->data);
1156 else
1157 res = s3cmci_prepare_pio(host, cmd->data);
1158
1159 if (res) {
ff8c804f 1160 dbg(host, dbg_err, "data prepare error %d\n", res);
be518018
TK		 1161 cmd->error = res;
1162 cmd->data->error = res;
1163
1164 mmc_request_done(mmc, mrq);
1165 return;
1166 }
1167 }
1168
1169 /* Send command */
1170 s3cmci_send_command(host, cmd);
1171
1172 /* Enable Interrupt */
c2258893 1173 s3cmci_enable_irq(host, true);
be518018
TK		 1174}
1175
87dd9803 1176static int s3cmci_card_present(struct mmc_host *mmc)
50a84570 1177{
87dd9803 1178 struct s3cmci_host *host = mmc_priv(mmc);
50a84570
BD		 1179 struct s3c24xx_mci_pdata *pdata = host->pdata;
1180 int ret;
1181
dc2ed552 1182 if (pdata->no_detect)
50a84570
BD		 1183 return -ENOSYS;
1184
916a3077 1185 ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
50a84570
BD		 1186 return ret ^ pdata->detect_invert;
1187}
1188
be518018
TK		 1189static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1190{
1191 struct s3cmci_host *host = mmc_priv(mmc);
1192
1193 host->status = "mmc request";
1194 host->cmd_is_stop = 0;
1195 host->mrq = mrq;
1196
87dd9803 1197 if (s3cmci_card_present(mmc) == 0) {
50a84570
BD		 1198 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1199 host->mrq->cmd->error = -ENOMEDIUM;
1200 mmc_request_done(mmc, mrq);
1201 } else
1202 s3cmci_send_request(mmc);
be518018
TK		 1203}
1204
f87e6d00 1205static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1206{
1207 u32 mci_psc;
1208
1209 /* Set clock */
1210 for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1211 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1212
1213 if (host->real_rate <= ios->clock)
1214 break;
1215 }
1216
1217 if (mci_psc > 255)
1218 mci_psc = 255;
1219
1220 host->prescaler = mci_psc;
1221 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1222
1223 /* If requested clock is 0, real_rate will be 0, too */
1224 if (ios->clock == 0)
1225 host->real_rate = 0;
1226}
1227
be518018
TK		 1228static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1229{
1230 struct s3cmci_host *host = mmc_priv(mmc);
f87e6d00 1231 u32 mci_con;
be518018
TK		 1232
1233 /* Set the power state */
1234
1235 mci_con = readl(host->base + S3C2410_SDICON);
1236
1237 switch (ios->power_mode) {
1238 case MMC_POWER_ON:
1239 case MMC_POWER_UP:
916a3077
BD		 1240 s3c2410_gpio_cfgpin(S3C2410_GPE(5), S3C2410_GPE5_SDCLK);
1241 s3c2410_gpio_cfgpin(S3C2410_GPE(6), S3C2410_GPE6_SDCMD);
1242 s3c2410_gpio_cfgpin(S3C2410_GPE(7), S3C2410_GPE7_SDDAT0);
1243 s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
1244 s3c2410_gpio_cfgpin(S3C2410_GPE(9), S3C2410_GPE9_SDDAT2);
1245 s3c2410_gpio_cfgpin(S3C2410_GPE(10), S3C2410_GPE10_SDDAT3);
be518018 1246
edb5a98e
BD		 1247 if (host->pdata->set_power)
1248 host->pdata->set_power(ios->power_mode, ios->vdd);
1249
be518018
TK		 1250 if (!host->is2440)
1251 mci_con |= S3C2410_SDICON_FIFORESET;
1252
1253 break;
1254
1255 case MMC_POWER_OFF:
1256 default:
916a3077 1257 gpio_direction_output(S3C2410_GPE(5), 0);
be518018
TK		 1258
1259 if (host->is2440)
1260 mci_con |= S3C2440_SDICON_SDRESET;
1261
edb5a98e
BD		 1262 if (host->pdata->set_power)
1263 host->pdata->set_power(ios->power_mode, ios->vdd);
1264
be518018
TK		 1265 break;
1266 }
1267
f87e6d00 1268 s3cmci_set_clk(host, ios);
be518018
TK		 1269
1270 /* Set CLOCK_ENABLE */
1271 if (ios->clock)
1272 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1273 else
1274 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1275
1276 writel(mci_con, host->base + S3C2410_SDICON);
1277
1278 if ((ios->power_mode == MMC_POWER_ON) ||
1279 (ios->power_mode == MMC_POWER_UP)) {
1280 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1281 host->real_rate/1000, ios->clock/1000);
1282 } else {
1283 dbg(host, dbg_conf, "powered down.\n");
1284 }
1285
1286 host->bus_width = ios->bus_width;
1287}
1288
1289static void s3cmci_reset(struct s3cmci_host *host)
1290{
1291 u32 con = readl(host->base + S3C2410_SDICON);
1292
1293 con |= S3C2440_SDICON_SDRESET;
1294 writel(con, host->base + S3C2410_SDICON);
1295}
1296
edb5a98e
BD		 1297static int s3cmci_get_ro(struct mmc_host *mmc)
1298{
1299 struct s3cmci_host *host = mmc_priv(mmc);
cf0984c8
BD		 1300 struct s3c24xx_mci_pdata *pdata = host->pdata;
1301 int ret;
edb5a98e 1302
00acfaee 1303 if (pdata->no_wprotect)
edb5a98e
BD		 1304 return 0;
1305
c78402e9
BD		 1306 ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
1307 ret ^= pdata->wprotect_invert;
cf0984c8
BD		 1308
1309 return ret;
edb5a98e
BD		 1310}
1311
c2258893
BD		 1312static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1313{
1314 struct s3cmci_host *host = mmc_priv(mmc);
1315 unsigned long flags;
1316 u32 con;
1317
1318 local_irq_save(flags);
1319
1320 con = readl(host->base + S3C2410_SDICON);
1321 host->sdio_irqen = enable;
1322
1323 if (enable == host->sdio_irqen)
1324 goto same_state;
1325
1326 if (enable) {
1327 con |= S3C2410_SDICON_SDIOIRQ;
1328 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1329
1330 if (!host->irq_state && !host->irq_disabled) {
1331 host->irq_state = true;
1332 enable_irq(host->irq);
1333 }
1334 } else {
1335 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1336 con &= ~S3C2410_SDICON_SDIOIRQ;
1337
1338 if (!host->irq_enabled && host->irq_state) {
1339 disable_irq_nosync(host->irq);
1340 host->irq_state = false;
1341 }
1342 }
1343
1344 writel(con, host->base + S3C2410_SDICON);
1345
1346 same_state:
1347 local_irq_restore(flags);
1348
1349 s3cmci_check_sdio_irq(host);
1350}
1351
be518018
TK		 1352static struct mmc_host_ops s3cmci_ops = {
1353 .request = s3cmci_request,
1354 .set_ios = s3cmci_set_ios,
edb5a98e 1355 .get_ro = s3cmci_get_ro,
87dd9803 1356 .get_cd = s3cmci_card_present,
c2258893 1357 .enable_sdio_irq = s3cmci_enable_sdio_irq,
edb5a98e
BD		 1358};
1359
1360static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1361 /* This is currently here to avoid a number of if (host->pdata)
af901ca1 1362 * checks. Any zero fields to ensure reasonable defaults are picked. */
c212808a
LPC		 1363 .no_wprotect = 1,
1364 .no_detect = 1,
be518018
TK		 1365};
1366
f87e6d00 1367#ifdef CONFIG_CPU_FREQ
1368
1369static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1370 unsigned long val, void *data)
1371{
1372 struct s3cmci_host *host;
1373 struct mmc_host *mmc;
1374 unsigned long newclk;
1375 unsigned long flags;
1376
1377 host = container_of(nb, struct s3cmci_host, freq_transition);
1378 newclk = clk_get_rate(host->clk);
1379 mmc = host->mmc;
1380
1381 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1382 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1383 spin_lock_irqsave(&mmc->lock, flags);
1384
1385 host->clk_rate = newclk;
1386
1387 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1388 mmc->ios.clock != 0)
1389 s3cmci_set_clk(host, &mmc->ios);
1390
1391 spin_unlock_irqrestore(&mmc->lock, flags);
1392 }
1393
1394 return 0;
1395}
1396
1397static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1398{
1399 host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1400
1401 return cpufreq_register_notifier(&host->freq_transition,
1402 CPUFREQ_TRANSITION_NOTIFIER);
1403}
1404
1405static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1406{
1407 cpufreq_unregister_notifier(&host->freq_transition,
1408 CPUFREQ_TRANSITION_NOTIFIER);
1409}
1410
1411#else
1412static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1413{
1414 return 0;
1415}
1416
1417static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1418{
1419}
1420#endif
1421
916a3077 1422
9bdd203b
BD		 1423#ifdef CONFIG_DEBUG_FS
1424
1425static int s3cmci_state_show(struct seq_file *seq, void *v)
1426{
1427 struct s3cmci_host *host = seq->private;
1428
1429 seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1430 seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1431 seq_printf(seq, "Prescale = %d\n", host->prescaler);
1432 seq_printf(seq, "is2440 = %d\n", host->is2440);
1433 seq_printf(seq, "IRQ = %d\n", host->irq);
c2258893
BD		 1434 seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1435 seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1436 seq_printf(seq, "IRQ state = %d\n", host->irq_state);
9bdd203b 1437 seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
26f14947 1438 seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
9bdd203b
BD		 1439 seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1440 seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1441
1442 return 0;
1443}
1444
1445static int s3cmci_state_open(struct inode *inode, struct file *file)
1446{
1447 return single_open(file, s3cmci_state_show, inode->i_private);
1448}
1449
1450static const struct file_operations s3cmci_fops_state = {
1451 .owner = THIS_MODULE,
1452 .open = s3cmci_state_open,
1453 .read = seq_read,
1454 .llseek = seq_lseek,
1455 .release = single_release,
1456};
1457
1458#define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1459
1460struct s3cmci_reg {
1461 unsigned short addr;
1462 unsigned char *name;
1463} debug_regs[] = {
1464 DBG_REG(CON),
1465 DBG_REG(PRE),
1466 DBG_REG(CMDARG),
1467 DBG_REG(CMDCON),
1468 DBG_REG(CMDSTAT),
1469 DBG_REG(RSP0),
1470 DBG_REG(RSP1),
1471 DBG_REG(RSP2),
1472 DBG_REG(RSP3),
1473 DBG_REG(TIMER),
1474 DBG_REG(BSIZE),
1475 DBG_REG(DCON),
1476 DBG_REG(DCNT),
1477 DBG_REG(DSTA),
1478 DBG_REG(FSTA),
1479 {}
1480};
1481
1482static int s3cmci_regs_show(struct seq_file *seq, void *v)
1483{
1484 struct s3cmci_host *host = seq->private;
1485 struct s3cmci_reg *rptr = debug_regs;
1486
1487 for (; rptr->name; rptr++)
1488 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1489 readl(host->base + rptr->addr));
1490
1491 seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1492
1493 return 0;
1494}
1495
1496static int s3cmci_regs_open(struct inode *inode, struct file *file)
1497{
1498 return single_open(file, s3cmci_regs_show, inode->i_private);
1499}
1500
1501static const struct file_operations s3cmci_fops_regs = {
1502 .owner = THIS_MODULE,
1503 .open = s3cmci_regs_open,
1504 .read = seq_read,
1505 .llseek = seq_lseek,
1506 .release = single_release,
1507};
1508
1509static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1510{
1511 struct device *dev = &host->pdev->dev;
1512
1513 host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1514 if (IS_ERR(host->debug_root)) {
1515 dev_err(dev, "failed to create debugfs root\n");
1516 return;
1517 }
1518
1519 host->debug_state = debugfs_create_file("state", 0444,
1520 host->debug_root, host,
1521 &s3cmci_fops_state);
1522
1523 if (IS_ERR(host->debug_state))
1524 dev_err(dev, "failed to create debug state file\n");
1525
1526 host->debug_regs = debugfs_create_file("regs", 0444,
1527 host->debug_root, host,
1528 &s3cmci_fops_regs);
1529
1530 if (IS_ERR(host->debug_regs))
1531 dev_err(dev, "failed to create debug regs file\n");
1532}
1533
1534static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1535{
1536 debugfs_remove(host->debug_regs);
1537 debugfs_remove(host->debug_state);
1538 debugfs_remove(host->debug_root);
1539}
1540
1541#else
1542static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1543static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1544
1545#endif /* CONFIG_DEBUG_FS */
1546
44d0e199 1547static int __devinit s3cmci_probe(struct platform_device *pdev)
be518018
TK		 1548{
1549 struct s3cmci_host *host;
1550 struct mmc_host *mmc;
1551 int ret;
44d0e199 1552 int is2440;
916a3077 1553 int i;
44d0e199
BD		 1554
1555 is2440 = platform_get_device_id(pdev)->driver_data;
be518018
TK		 1556
1557 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1558 if (!mmc) {
1559 ret = -ENOMEM;
1560 goto probe_out;
1561 }
1562
916a3077
BD		 1563 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1564 ret = gpio_request(i, dev_name(&pdev->dev));
1565 if (ret) {
1566 dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1567
1568 for (i--; i >= S3C2410_GPE(5); i--)
1569 gpio_free(i);
1570
1571 goto probe_free_host;
1572 }
1573 }
1574
be518018
TK		 1575 host = mmc_priv(mmc);
1576 host->mmc = mmc;
1577 host->pdev = pdev;
1578 host->is2440 = is2440;
1579
edb5a98e
BD		 1580 host->pdata = pdev->dev.platform_data;
1581 if (!host->pdata) {
1582 pdev->dev.platform_data = &s3cmci_def_pdata;
1583 host->pdata = &s3cmci_def_pdata;
1584 }
1585
be518018
TK		 1586 spin_lock_init(&host->complete_lock);
1587 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1588
1589 if (is2440) {
1590 host->sdiimsk = S3C2440_SDIIMSK;
1591 host->sdidata = S3C2440_SDIDATA;
1592 host->clk_div = 1;
1593 } else {
1594 host->sdiimsk = S3C2410_SDIIMSK;
1595 host->sdidata = S3C2410_SDIDATA;
1596 host->clk_div = 2;
1597 }
1598
be518018
TK		 1599 host->complete_what = COMPLETION_NONE;
1600 host->pio_active = XFER_NONE;
1601
26f14947 1602#ifdef CONFIG_MMC_S3C_PIODMA
60c2c0d5 1603 host->dodma = host->pdata->use_dma;
26f14947
BD		 1604#endif
1605
be518018
TK		 1606 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1607 if (!host->mem) {
1608 dev_err(&pdev->dev,
1609 "failed to get io memory region resouce.\n");
1610
1611 ret = -ENOENT;
916a3077 1612 goto probe_free_gpio;
be518018
TK		 1613 }
1614
1615 host->mem = request_mem_region(host->mem->start,
da52a7ca 1616 resource_size(host->mem), pdev->name);
be518018
TK		 1617
1618 if (!host->mem) {
1619 dev_err(&pdev->dev, "failed to request io memory region.\n");
1620 ret = -ENOENT;
916a3077 1621 goto probe_free_gpio;
be518018
TK		 1622 }
1623
da52a7ca 1624 host->base = ioremap(host->mem->start, resource_size(host->mem));
5d304400 1625 if (!host->base) {
be518018
TK		 1626 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1627 ret = -EINVAL;
1628 goto probe_free_mem_region;
1629 }
1630
1631 host->irq = platform_get_irq(pdev, 0);
1632 if (host->irq == 0) {
1633 dev_err(&pdev->dev, "failed to get interrupt resouce.\n");
1634 ret = -EINVAL;
1635 goto probe_iounmap;
1636 }
1637
1638 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1639 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1640 ret = -ENOENT;
1641 goto probe_iounmap;
1642 }
1643
1644 /* We get spurious interrupts even when we have set the IMSK
1645 * register to ignore everything, so use disable_irq() to make
1646 * ensure we don't lock the system with un-serviceable requests. */
1647
1648 disable_irq(host->irq);
c2258893 1649 host->irq_state = false;
be518018 1650
00acfaee 1651 if (!host->pdata->no_detect) {
916a3077
BD		 1652 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
1653 if (ret) {
1654 dev_err(&pdev->dev, "failed to get detect gpio\n");
1655 goto probe_free_irq;
1656 }
be518018 1657
c78402e9 1658 host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
00acfaee
BD		 1659
1660 if (host->irq_cd >= 0) {
1661 if (request_irq(host->irq_cd, s3cmci_irq_cd,
1662 IRQF_TRIGGER_RISING |
1663 IRQF_TRIGGER_FALLING,
1664 DRIVER_NAME, host)) {
1665 dev_err(&pdev->dev,
1666 "can't get card detect irq.\n");
1667 ret = -ENOENT;
1668 goto probe_free_gpio_cd;
1669 }
1670 } else {
1671 dev_warn(&pdev->dev,
1672 "host detect has no irq available\n");
1673 gpio_direction_input(host->pdata->gpio_detect);
55d70f5a 1674 }
00acfaee
BD		 1675 } else
1676 host->irq_cd = -1;
be518018 1677
00acfaee 1678 if (!host->pdata->no_wprotect) {
916a3077
BD		 1679 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
1680 if (ret) {
1681 dev_err(&pdev->dev, "failed to get writeprotect\n");
1682 goto probe_free_irq_cd;
1683 }
1684
1685 gpio_direction_input(host->pdata->gpio_wprotect);
1686 }
edb5a98e 1687
68c5ed59
BD		 1688 /* depending on the dma state, get a dma channel to use. */
1689
1690 if (s3cmci_host_usedma(host)) {
1691 host->dma = s3c2410_dma_request(DMACH_SDI, &s3cmci_dma_client,
1692 host);
1693 if (host->dma < 0) {
1694 dev_err(&pdev->dev, "cannot get DMA channel.\n");
1695 if (!s3cmci_host_canpio()) {
1696 ret = -EBUSY;
1697 goto probe_free_gpio_wp;
1698 } else {
1699 dev_warn(&pdev->dev, "falling back to PIO.\n");
1700 host->dodma = 0;
1701 }
1702 }
be518018
TK		 1703 }
1704
1705 host->clk = clk_get(&pdev->dev, "sdi");
1706 if (IS_ERR(host->clk)) {
1707 dev_err(&pdev->dev, "failed to find clock source.\n");
1708 ret = PTR_ERR(host->clk);
1709 host->clk = NULL;
68c5ed59 1710 goto probe_free_dma;
be518018
TK		 1711 }
1712
1713 ret = clk_enable(host->clk);
1714 if (ret) {
1715 dev_err(&pdev->dev, "failed to enable clock source.\n");
1716 goto clk_free;
1717 }
1718
1719 host->clk_rate = clk_get_rate(host->clk);
1720
1721 mmc->ops = &s3cmci_ops;
edb5a98e 1722 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
5a2c4fe0 1723#ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
c2258893 1724 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
5a2c4fe0
BD		 1725#else
1726 mmc->caps = MMC_CAP_4_BIT_DATA;
1727#endif
be518018
TK		 1728 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1729 mmc->f_max = host->clk_rate / host->clk_div;
1730
edb5a98e
BD		 1731 if (host->pdata->ocr_avail)
1732 mmc->ocr_avail = host->pdata->ocr_avail;
1733
be518018
TK		 1734 mmc->max_blk_count = 4095;
1735 mmc->max_blk_size = 4095;
1736 mmc->max_req_size = 4095 * 512;
1737 mmc->max_seg_size = mmc->max_req_size;
1738
1739 mmc->max_phys_segs = 128;
1740 mmc->max_hw_segs = 128;
1741
1742 dbg(host, dbg_debug,
1743 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1744 (host->is2440?"2440":""),
1745 host->base, host->irq, host->irq_cd, host->dma);
1746
f87e6d00 1747 ret = s3cmci_cpufreq_register(host);
1748 if (ret) {
1749 dev_err(&pdev->dev, "failed to register cpufreq\n");
1750 goto free_dmabuf;
1751 }
1752
be518018
TK		 1753 ret = mmc_add_host(mmc);
1754 if (ret) {
1755 dev_err(&pdev->dev, "failed to add mmc host.\n");
f87e6d00 1756 goto free_cpufreq;
be518018
TK		 1757 }
1758
9bdd203b
BD		 1759 s3cmci_debugfs_attach(host);
1760
be518018 1761 platform_set_drvdata(pdev, mmc);
5a2c4fe0
BD		 1762 dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1763 s3cmci_host_usedma(host) ? "dma" : "pio",
1764 mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
be518018
TK		 1765
1766 return 0;
1767
f87e6d00 1768 free_cpufreq:
1769 s3cmci_cpufreq_deregister(host);
1770
be518018
TK		 1771 free_dmabuf:
1772 clk_disable(host->clk);
1773
1774 clk_free:
1775 clk_put(host->clk);
1776
68c5ed59
BD		 1777 probe_free_dma:
1778 if (s3cmci_host_usedma(host))
1779 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
1780
916a3077 1781 probe_free_gpio_wp:
00acfaee 1782 if (!host->pdata->no_wprotect)
916a3077
BD		 1783 gpio_free(host->pdata->gpio_wprotect);
1784
1785 probe_free_gpio_cd:
00acfaee 1786 if (!host->pdata->no_detect)
916a3077
BD		 1787 gpio_free(host->pdata->gpio_detect);
1788
be518018 1789 probe_free_irq_cd:
55d70f5a
BD		 1790 if (host->irq_cd >= 0)
1791 free_irq(host->irq_cd, host);
be518018
TK		 1792
1793 probe_free_irq:
1794 free_irq(host->irq, host);
1795
1796 probe_iounmap:
1797 iounmap(host->base);
1798
1799 probe_free_mem_region:
da52a7ca 1800 release_mem_region(host->mem->start, resource_size(host->mem));
be518018 1801
916a3077
BD		 1802 probe_free_gpio:
1803 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1804 gpio_free(i);
1805
be518018
TK		 1806 probe_free_host:
1807 mmc_free_host(mmc);
916a3077 1808
be518018
TK		 1809 probe_out:
1810 return ret;
1811}
1812
907b2cd6
BD		 1813static void s3cmci_shutdown(struct platform_device *pdev)
1814{
1815 struct mmc_host *mmc = platform_get_drvdata(pdev);
1816 struct s3cmci_host *host = mmc_priv(mmc);
1817
1818 if (host->irq_cd >= 0)
1819 free_irq(host->irq_cd, host);
1820
9bdd203b 1821 s3cmci_debugfs_remove(host);
f87e6d00 1822 s3cmci_cpufreq_deregister(host);
907b2cd6
BD		 1823 mmc_remove_host(mmc);
1824 clk_disable(host->clk);
1825}
1826
be518018
TK		 1827static int __devexit s3cmci_remove(struct platform_device *pdev)
1828{
1829 struct mmc_host *mmc = platform_get_drvdata(pdev);
1830 struct s3cmci_host *host = mmc_priv(mmc);
916a3077
BD		 1831 struct s3c24xx_mci_pdata *pd = host->pdata;
1832 int i;
be518018 1833
907b2cd6 1834 s3cmci_shutdown(pdev);
be518018 1835
be518018
TK		 1836 clk_put(host->clk);
1837
1838 tasklet_disable(&host->pio_tasklet);
68c5ed59
BD		 1839
1840 if (s3cmci_host_usedma(host))
1841 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
be518018 1842
be518018
TK		 1843 free_irq(host->irq, host);
1844
00acfaee 1845 if (!pd->no_wprotect)
916a3077
BD		 1846 gpio_free(pd->gpio_wprotect);
1847
00acfaee 1848 if (!pd->no_detect)
916a3077
BD		 1849 gpio_free(pd->gpio_detect);
1850
1851 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1852 gpio_free(i);
1853
1854
be518018 1855 iounmap(host->base);
da52a7ca 1856 release_mem_region(host->mem->start, resource_size(host->mem));
be518018
TK		 1857
1858 mmc_free_host(mmc);
1859 return 0;
1860}
1861
44d0e199
BD		 1862static struct platform_device_id s3cmci_driver_ids[] = {
1863 {
1864 .name = "s3c2410-sdi",
1865 .driver_data = 0,
1866 }, {
1867 .name = "s3c2412-sdi",
1868 .driver_data = 1,
1869 }, {
1870 .name = "s3c2440-sdi",
1871 .driver_data = 1,
1872 },
1873 { }
1874};
be518018 1875
44d0e199 1876MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
be518018 1877
be518018
TK		 1878
1879#ifdef CONFIG_PM
1880
50d7fa9a 1881static int s3cmci_suspend(struct device *dev)
be518018 1882{
50d7fa9a 1883 struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
be518018 1884
1a13f8fa 1885 return mmc_suspend_host(mmc);
be518018
TK		 1886}
1887
50d7fa9a 1888static int s3cmci_resume(struct device *dev)
be518018 1889{
50d7fa9a 1890 struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
be518018
TK		 1891
1892 return mmc_resume_host(mmc);
1893}
1894
47145210 1895static const struct dev_pm_ops s3cmci_pm = {
50d7fa9a
BD		 1896 .suspend = s3cmci_suspend,
1897 .resume = s3cmci_resume,
1898};
1899
1900#define s3cmci_pm_ops &s3cmci_pm
be518018 1901#else /* CONFIG_PM */
50d7fa9a 1902#define s3cmci_pm_ops NULL
be518018
TK		 1903#endif /* CONFIG_PM */
1904
1905
44d0e199 1906static struct platform_driver s3cmci_driver = {
50d7fa9a
BD		 1907 .driver = {
1908 .name = "s3c-sdi",
1909 .owner = THIS_MODULE,
1910 .pm = s3cmci_pm_ops,
1911 },
44d0e199
BD		 1912 .id_table = s3cmci_driver_ids,
1913 .probe = s3cmci_probe,
be518018 1914 .remove = __devexit_p(s3cmci_remove),
907b2cd6 1915 .shutdown = s3cmci_shutdown,
be518018
TK		 1916};
1917
be518018
TK		 1918static int __init s3cmci_init(void)
1919{
44d0e199 1920 return platform_driver_register(&s3cmci_driver);
be518018
TK		 1921}
1922
1923static void __exit s3cmci_exit(void)
1924{
44d0e199 1925 platform_driver_unregister(&s3cmci_driver);
be518018
TK		 1926}
1927
1928module_init(s3cmci_init);
1929module_exit(s3cmci_exit);
1930
1931MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1932MODULE_LICENSE("GPL v2");
08c55e22 1933MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
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