[net-next-2.6.git] / drivers / hwmon / coretemp.c

/*
 * coretemp.c - Linux kernel module for hardware monitoring
 *
 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
 *
 * Inspired from many hwmon drivers
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301 USA.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/hwmon.h>
#include <linux/sysfs.h>
#include <linux/hwmon-sysfs.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/cpu.h>
#include <linux/pci.h>
#include <asm/msr.h>
#include <asm/processor.h>

#define DRVNAME	"coretemp"

typedef enum { SHOW_TEMP, SHOW_TJMAX, SHOW_TTARGET, SHOW_LABEL,
		SHOW_NAME } SHOW;

/*
 * Functions declaration
 */

static struct coretemp_data *coretemp_update_device(struct device *dev);

struct coretemp_data {
	struct device *hwmon_dev;
	struct mutex update_lock;
	const char *name;
	u32 id;
	char valid;		/* zero until following fields are valid */
	unsigned long last_updated;	/* in jiffies */
	int temp;
	int tjmax;
	int ttarget;
	u8 alarm;
};

/*
 * Sysfs stuff
 */

static ssize_t show_name(struct device *dev, struct device_attribute
			  *devattr, char *buf)
{
	int ret;
	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	struct coretemp_data *data = dev_get_drvdata(dev);

	if (attr->index == SHOW_NAME)
		ret = sprintf(buf, "%s\n", data->name);
	else	/* show label */
		ret = sprintf(buf, "Core %d\n", data->id);
	return ret;
}

static ssize_t show_alarm(struct device *dev, struct device_attribute
			  *devattr, char *buf)
{
	struct coretemp_data *data = coretemp_update_device(dev);
	/* read the Out-of-spec log, never clear */
	return sprintf(buf, "%d\n", data->alarm);
}

static ssize_t show_temp(struct device *dev,
			 struct device_attribute *devattr, char *buf)
{
	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	struct coretemp_data *data = coretemp_update_device(dev);
	int err;

	if (attr->index == SHOW_TEMP)
		err = data->valid ? sprintf(buf, "%d\n", data->temp) : -EAGAIN;
	else if (attr->index == SHOW_TJMAX)
		err = sprintf(buf, "%d\n", data->tjmax);
	else
		err = sprintf(buf, "%d\n", data->ttarget);
	return err;
}

static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL,
			  SHOW_TEMP);
static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, NULL,
			  SHOW_TJMAX);
static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, NULL,
			  SHOW_TTARGET);
static DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL);
static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_name, NULL, SHOW_LABEL);
static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, SHOW_NAME);

static struct attribute *coretemp_attributes[] = {
	&sensor_dev_attr_name.dev_attr.attr,
	&sensor_dev_attr_temp1_label.dev_attr.attr,
	&dev_attr_temp1_crit_alarm.attr,
	&sensor_dev_attr_temp1_input.dev_attr.attr,
	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	NULL
};

static const struct attribute_group coretemp_group = {
	.attrs = coretemp_attributes,
};

static struct coretemp_data *coretemp_update_device(struct device *dev)
{
	struct coretemp_data *data = dev_get_drvdata(dev);

	mutex_lock(&data->update_lock);

	if (!data->valid || time_after(jiffies, data->last_updated + HZ)) {
		u32 eax, edx;

		data->valid = 0;
		rdmsr_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
		data->alarm = (eax >> 5) & 1;
		/* update only if data has been valid */
		if (eax & 0x80000000) {
			data->temp = data->tjmax - (((eax >> 16)
							& 0x7f) * 1000);
			data->valid = 1;
		} else {
			dev_dbg(dev, "Temperature data invalid (0x%x)\n", eax);
		}
		data->last_updated = jiffies;
	}

	mutex_unlock(&data->update_lock);
	return data;
}

static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
{
	/* The 100C is default for both mobile and non mobile CPUs */

	int tjmax = 100000;
	int tjmax_ee = 85000;
	int usemsr_ee = 1;
	int err;
	u32 eax, edx;
	struct pci_dev *host_bridge;

	/* Early chips have no MSR for TjMax */

	if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
		usemsr_ee = 0;
	}

	/* Atom CPUs */

	if (c->x86_model == 0x1c) {
		usemsr_ee = 0;

		host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));

		if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
		    && (host_bridge->device == 0xa000	/* NM10 based nettop */
		    || host_bridge->device == 0xa010))	/* NM10 based netbook */
			tjmax = 100000;
		else
			tjmax = 90000;

		pci_dev_put(host_bridge);
	}

	if ((c->x86_model > 0xe) && (usemsr_ee)) {
		u8 platform_id;

		/* Now we can detect the mobile CPU using Intel provided table
		   http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
		   For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
		*/

		err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
		if (err) {
			dev_warn(dev,
				 "Unable to access MSR 0x17, assuming desktop"
				 " CPU\n");
			usemsr_ee = 0;
		} else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
			/* Trust bit 28 up to Penryn, I could not find any
			   documentation on that; if you happen to know
			   someone at Intel please ask */
			usemsr_ee = 0;
		} else {
			/* Platform ID bits 52:50 (EDX starts at bit 32) */
			platform_id = (edx >> 18) & 0x7;

			/* Mobile Penryn CPU seems to be platform ID 7 or 5
			  (guesswork) */
			if ((c->x86_model == 0x17) &&
			    ((platform_id == 5) || (platform_id == 7))) {
				/* If MSR EE bit is set, set it to 90 degrees C,
				   otherwise 105 degrees C */
				tjmax_ee = 90000;
				tjmax = 105000;
			}
		}
	}

	if (usemsr_ee) {

		err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
		if (err) {
			dev_warn(dev,
				 "Unable to access MSR 0xEE, for Tjmax, left"
				 " at default\n");
		} else if (eax & 0x40000000) {
			tjmax = tjmax_ee;
		}
	/* if we dont use msr EE it means we are desktop CPU (with exeception
	   of Atom) */
	} else if (tjmax == 100000) {
		dev_warn(dev, "Using relative temperature scale!\n");
	}

	return tjmax;
}

static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id,
			       struct device *dev)
{
	/* The 100C is default for both mobile and non mobile CPUs */
	int err;
	u32 eax, edx;
	u32 val;

	/* A new feature of current Intel(R) processors, the
	   IA32_TEMPERATURE_TARGET contains the TjMax value */
	err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
	if (err) {
		dev_warn(dev, "Unable to read TjMax from CPU.\n");
	} else {
		val = (eax >> 16) & 0xff;
		/*
		 * If the TjMax is not plausible, an assumption
		 * will be used
		 */
		if ((val > 80) && (val < 120)) {
			dev_info(dev, "TjMax is %d C.\n", val);
			return val * 1000;
		}
	}

	/*
	 * An assumption is made for early CPUs and unreadable MSR.
	 * NOTE: the given value may not be correct.
	 */

	switch (c->x86_model) {
	case 0xe:
	case 0xf:
	case 0x16:
	case 0x1a:
		dev_warn(dev, "TjMax is assumed as 100 C!\n");
		return 100000;
		break;
	case 0x17:
	case 0x1c:		/* Atom CPUs */
		return adjust_tjmax(c, id, dev);
		break;
	default:
		dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
			" using default TjMax of 100C.\n", c->x86_model);
		return 100000;
	}
}

static int __devinit coretemp_probe(struct platform_device *pdev)
{
	struct coretemp_data *data;
	struct cpuinfo_x86 *c = &cpu_data(pdev->id);
	int err;
	u32 eax, edx;

	if (!(data = kzalloc(sizeof(struct coretemp_data), GFP_KERNEL))) {
		err = -ENOMEM;
		dev_err(&pdev->dev, "Out of memory\n");
		goto exit;
	}

	data->id = pdev->id;
	data->name = "coretemp";
	mutex_init(&data->update_lock);

	/* test if we can access the THERM_STATUS MSR */
	err = rdmsr_safe_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
	if (err) {
		dev_err(&pdev->dev,
			"Unable to access THERM_STATUS MSR, giving up\n");
		goto exit_free;
	}

	/* Check if we have problem with errata AE18 of Core processors:
	   Readings might stop update when processor visited too deep sleep,
	   fixed for stepping D0 (6EC).
	*/

	if ((c->x86_model == 0xe) && (c->x86_mask < 0xc)) {
		/* check for microcode update */
		rdmsr_on_cpu(data->id, MSR_IA32_UCODE_REV, &eax, &edx);
		if (edx < 0x39) {
			err = -ENODEV;
			dev_err(&pdev->dev,
				"Errata AE18 not fixed, update BIOS or "
				"microcode of the CPU!\n");
			goto exit_free;
		}
	}

	data->tjmax = get_tjmax(c, data->id, &pdev->dev);
	platform_set_drvdata(pdev, data);

	/*
	 * read the still undocumented IA32_TEMPERATURE_TARGET. It exists
	 * on older CPUs but not in this register,
	 * Atoms don't have it either.
	 */

	if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
		err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET,
		    &eax, &edx);
		if (err) {
			dev_warn(&pdev->dev, "Unable to read"
					" IA32_TEMPERATURE_TARGET MSR\n");
		} else {
			data->ttarget = data->tjmax -
					(((eax >> 8) & 0xff) * 1000);
			err = device_create_file(&pdev->dev,
					&sensor_dev_attr_temp1_max.dev_attr);
			if (err)
				goto exit_free;
		}
	}

	if ((err = sysfs_create_group(&pdev->dev.kobj, &coretemp_group)))
		goto exit_dev;

	data->hwmon_dev = hwmon_device_register(&pdev->dev);
	if (IS_ERR(data->hwmon_dev)) {
		err = PTR_ERR(data->hwmon_dev);
		dev_err(&pdev->dev, "Class registration failed (%d)\n",
			err);
		goto exit_class;
	}

	return 0;

exit_class:
	sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
exit_dev:
	device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
exit_free:
	kfree(data);
exit:
	return err;
}

static int __devexit coretemp_remove(struct platform_device *pdev)
{
	struct coretemp_data *data = platform_get_drvdata(pdev);

	hwmon_device_unregister(data->hwmon_dev);
	sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
	device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
	platform_set_drvdata(pdev, NULL);
	kfree(data);
	return 0;
}

static struct platform_driver coretemp_driver = {
	.driver = {
		.owner = THIS_MODULE,
		.name = DRVNAME,
	},
	.probe = coretemp_probe,
	.remove = __devexit_p(coretemp_remove),
};

struct pdev_entry {
	struct list_head list;
	struct platform_device *pdev;
	unsigned int cpu;
#ifdef CONFIG_SMP
	u16 phys_proc_id;
	u16 cpu_core_id;
#endif
};

static LIST_HEAD(pdev_list);
static DEFINE_MUTEX(pdev_list_mutex);

static int __cpuinit coretemp_device_add(unsigned int cpu)
{
	int err;
	struct platform_device *pdev;
	struct pdev_entry *pdev_entry;
#ifdef CONFIG_SMP
	struct cpuinfo_x86 *c = &cpu_data(cpu);
#endif

	mutex_lock(&pdev_list_mutex);

#ifdef CONFIG_SMP
	/* Skip second HT entry of each core */
	list_for_each_entry(pdev_entry, &pdev_list, list) {
		if (c->phys_proc_id == pdev_entry->phys_proc_id &&
		    c->cpu_core_id == pdev_entry->cpu_core_id) {
			err = 0;	/* Not an error */
			goto exit;
		}
	}
#endif

	pdev = platform_device_alloc(DRVNAME, cpu);
	if (!pdev) {
		err = -ENOMEM;
		printk(KERN_ERR DRVNAME ": Device allocation failed\n");
		goto exit;
	}

	pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL);
	if (!pdev_entry) {
		err = -ENOMEM;
		goto exit_device_put;
	}

	err = platform_device_add(pdev);
	if (err) {
		printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
		       err);
		goto exit_device_free;
	}

	pdev_entry->pdev = pdev;
	pdev_entry->cpu = cpu;
#ifdef CONFIG_SMP
	pdev_entry->phys_proc_id = c->phys_proc_id;
	pdev_entry->cpu_core_id = c->cpu_core_id;
#endif
	list_add_tail(&pdev_entry->list, &pdev_list);
	mutex_unlock(&pdev_list_mutex);

	return 0;

exit_device_free:
	kfree(pdev_entry);
exit_device_put:
	platform_device_put(pdev);
exit:
	mutex_unlock(&pdev_list_mutex);
	return err;
}

#ifdef CONFIG_HOTPLUG_CPU
static void coretemp_device_remove(unsigned int cpu)
{
	struct pdev_entry *p, *n;
	mutex_lock(&pdev_list_mutex);
	list_for_each_entry_safe(p, n, &pdev_list, list) {
		if (p->cpu == cpu) {
			platform_device_unregister(p->pdev);
			list_del(&p->list);
			kfree(p);
		}
	}
	mutex_unlock(&pdev_list_mutex);
}

static int __cpuinit coretemp_cpu_callback(struct notifier_block *nfb,
				 unsigned long action, void *hcpu)
{
	unsigned int cpu = (unsigned long) hcpu;

	switch (action) {
	case CPU_ONLINE:
	case CPU_DOWN_FAILED:
		coretemp_device_add(cpu);
		break;
	case CPU_DOWN_PREPARE:
		coretemp_device_remove(cpu);
		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block coretemp_cpu_notifier __refdata = {
	.notifier_call = coretemp_cpu_callback,
};
#endif				/* !CONFIG_HOTPLUG_CPU */

static int __init coretemp_init(void)
{
	int i, err = -ENODEV;
	struct pdev_entry *p, *n;

	/* quick check if we run Intel */
	if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
		goto exit;

	err = platform_driver_register(&coretemp_driver);
	if (err)
		goto exit;

	for_each_online_cpu(i) {
		struct cpuinfo_x86 *c = &cpu_data(i);
		/*
		 * CPUID.06H.EAX[0] indicates whether the CPU has thermal
		 * sensors. We check this bit only, all the early CPUs
		 * without thermal sensors will be filtered out.
		 */
		if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
			err = coretemp_device_add(i);
			if (err)
				goto exit_devices_unreg;

		} else {
			printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
				" has no thermal sensor.\n", c->x86_model);
		}
	}
	if (list_empty(&pdev_list)) {
		err = -ENODEV;
		goto exit_driver_unreg;
	}

#ifdef CONFIG_HOTPLUG_CPU
	register_hotcpu_notifier(&coretemp_cpu_notifier);
#endif
	return 0;

exit_devices_unreg:
	mutex_lock(&pdev_list_mutex);
	list_for_each_entry_safe(p, n, &pdev_list, list) {
		platform_device_unregister(p->pdev);
		list_del(&p->list);
		kfree(p);
	}
	mutex_unlock(&pdev_list_mutex);
exit_driver_unreg:
	platform_driver_unregister(&coretemp_driver);
exit:
	return err;
}

static void __exit coretemp_exit(void)
{
	struct pdev_entry *p, *n;
#ifdef CONFIG_HOTPLUG_CPU
	unregister_hotcpu_notifier(&coretemp_cpu_notifier);
#endif
	mutex_lock(&pdev_list_mutex);
	list_for_each_entry_safe(p, n, &pdev_list, list) {
		platform_device_unregister(p->pdev);
		list_del(&p->list);
		kfree(p);
	}
	mutex_unlock(&pdev_list_mutex);
	platform_driver_unregister(&coretemp_driver);
}

MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
MODULE_DESCRIPTION("Intel Core temperature monitor");
MODULE_LICENSE("GPL");

module_init(coretemp_init)
module_exit(coretemp_exit)
Commit	Line	Data
bebe4678 RM	1	/*
	2	* coretemp.c - Linux kernel module for hardware monitoring
	3	*
	4	* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
	5	*
	6	* Inspired from many hwmon drivers
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	20	* 02110-1301 USA.
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/delay.h>
	25	#include <linux/init.h>
	26	#include <linux/slab.h>
	27	#include <linux/jiffies.h>
	28	#include <linux/hwmon.h>
	29	#include <linux/sysfs.h>
	30	#include <linux/hwmon-sysfs.h>
	31	#include <linux/err.h>
	32	#include <linux/mutex.h>
	33	#include <linux/list.h>
	34	#include <linux/platform_device.h>
	35	#include <linux/cpu.h>
1fe63ab4	36	#include <linux/pci.h>
bebe4678 RM	37	#include <asm/msr.h>
	38	#include <asm/processor.h>
	39
	40	#define DRVNAME "coretemp"
	41
6369a288 RM	42	typedef enum { SHOW_TEMP, SHOW_TJMAX, SHOW_TTARGET, SHOW_LABEL,
6369a288 RM	43	SHOW_NAME } SHOW;
bebe4678 RM	44
	45	/*
	46	* Functions declaration
	47	*/
	48
	49	static struct coretemp_data coretemp_update_device(struct device dev);
	50
	51	struct coretemp_data {
1beeffe4	52	struct device *hwmon_dev;
bebe4678 RM	53	struct mutex update_lock;
	54	const char *name;
	55	u32 id;
	56	char valid; /* zero until following fields are valid */
	57	unsigned long last_updated; /* in jiffies */
	58	int temp;
	59	int tjmax;
6369a288	60	int ttarget;
bebe4678 RM	61	u8 alarm;
	62	};
	63
bebe4678 RM	64	/*
	65	* Sysfs stuff
	66	*/
	67
	68	static ssize_t show_name(struct device *dev, struct device_attribute
	69	devattr, char buf)
	70	{
	71	int ret;
	72	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	73	struct coretemp_data *data = dev_get_drvdata(dev);
	74
	75	if (attr->index == SHOW_NAME)
	76	ret = sprintf(buf, "%s\n", data->name);
	77	else /* show label */
	78	ret = sprintf(buf, "Core %d\n", data->id);
	79	return ret;
	80	}
	81
	82	static ssize_t show_alarm(struct device *dev, struct device_attribute
	83	devattr, char buf)
	84	{
	85	struct coretemp_data *data = coretemp_update_device(dev);
	86	/* read the Out-of-spec log, never clear */
	87	return sprintf(buf, "%d\n", data->alarm);
	88	}
	89
	90	static ssize_t show_temp(struct device *dev,
	91	struct device_attribute devattr, char buf)
	92	{
	93	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
	94	struct coretemp_data *data = coretemp_update_device(dev);
	95	int err;
	96
	97	if (attr->index == SHOW_TEMP)
	98	err = data->valid ? sprintf(buf, "%d\n", data->temp) : -EAGAIN;
6369a288	99	else if (attr->index == SHOW_TJMAX)
bebe4678	100	err = sprintf(buf, "%d\n", data->tjmax);
6369a288 RM	101	else
6369a288 RM	102	err = sprintf(buf, "%d\n", data->ttarget);
bebe4678 RM	103	return err;
	104	}
	105
	106	static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL,
	107	SHOW_TEMP);
	108	static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, NULL,
	109	SHOW_TJMAX);
6369a288 RM	110	static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, NULL,
6369a288 RM	111	SHOW_TTARGET);
bebe4678 RM	112	static DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL);
	113	static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_name, NULL, SHOW_LABEL);
	114	static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, SHOW_NAME);
	115
	116	static struct attribute *coretemp_attributes[] = {
	117	&sensor_dev_attr_name.dev_attr.attr,
	118	&sensor_dev_attr_temp1_label.dev_attr.attr,
	119	&dev_attr_temp1_crit_alarm.attr,
	120	&sensor_dev_attr_temp1_input.dev_attr.attr,
	121	&sensor_dev_attr_temp1_crit.dev_attr.attr,
	122	NULL
	123	};
	124
	125	static const struct attribute_group coretemp_group = {
	126	.attrs = coretemp_attributes,
	127	};
	128
	129	static struct coretemp_data coretemp_update_device(struct device dev)
	130	{
	131	struct coretemp_data *data = dev_get_drvdata(dev);
	132
	133	mutex_lock(&data->update_lock);
	134
	135	if (!data->valid \|\| time_after(jiffies, data->last_updated + HZ)) {
	136	u32 eax, edx;
	137
	138	data->valid = 0;
	139	rdmsr_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
	140	data->alarm = (eax >> 5) & 1;
	141	/* update only if data has been valid */
	142	if (eax & 0x80000000) {
	143	data->temp = data->tjmax - (((eax >> 16)
	144	& 0x7f) * 1000);
	145	data->valid = 1;
	146	} else {
	147	dev_dbg(dev, "Temperature data invalid (0x%x)\n", eax);
	148	}
	149	data->last_updated = jiffies;
	150	}
	151
	152	mutex_unlock(&data->update_lock);
	153	return data;
	154	}
	155
118a8871 RM	156	static int __devinit adjust_tjmax(struct cpuinfo_x86 c, u32 id, struct device dev)
	157	{
	158	/* The 100C is default for both mobile and non mobile CPUs */
	159
	160	int tjmax = 100000;
eccfed42	161	int tjmax_ee = 85000;
708a62bc	162	int usemsr_ee = 1;
118a8871 RM	163	int err;
118a8871 RM	164	u32 eax, edx;
1fe63ab4	165	struct pci_dev *host_bridge;
118a8871 RM	166
	167	/* Early chips have no MSR for TjMax */
	168
	169	if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
708a62bc	170	usemsr_ee = 0;
118a8871 RM	171	}
118a8871 RM	172
1fe63ab4	173	/* Atom CPUs */
708a62bc RM	174
	175	if (c->x86_model == 0x1c) {
	176	usemsr_ee = 0;
1fe63ab4 YW	177
	178	host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
	179
	180	if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
	181	&& (host_bridge->device == 0xa000 /* NM10 based nettop */
	182	\|\| host_bridge->device == 0xa010)) /* NM10 based netbook */
	183	tjmax = 100000;
	184	else
	185	tjmax = 90000;
	186
	187	pci_dev_put(host_bridge);
708a62bc RM	188	}
	189
	190	if ((c->x86_model > 0xe) && (usemsr_ee)) {
eccfed42	191	u8 platform_id;
118a8871 RM	192
	193	/* Now we can detect the mobile CPU using Intel provided table
	194	http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
	195	For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
	196	*/
	197
	198	err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
	199	if (err) {
	200	dev_warn(dev,
	201	"Unable to access MSR 0x17, assuming desktop"
	202	" CPU\n");
708a62bc	203	usemsr_ee = 0;
eccfed42 RM	204	} else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
	205	/* Trust bit 28 up to Penryn, I could not find any
	206	documentation on that; if you happen to know
	207	someone at Intel please ask */
708a62bc	208	usemsr_ee = 0;
eccfed42 RM	209	} else {
	210	/* Platform ID bits 52:50 (EDX starts at bit 32) */
	211	platform_id = (edx >> 18) & 0x7;
	212
	213	/* Mobile Penryn CPU seems to be platform ID 7 or 5
	214	(guesswork) */
	215	if ((c->x86_model == 0x17) &&
	216	((platform_id == 5) \|\| (platform_id == 7))) {
	217	/* If MSR EE bit is set, set it to 90 degrees C,
	218	otherwise 105 degrees C */
	219	tjmax_ee = 90000;
	220	tjmax = 105000;
	221	}
118a8871 RM	222	}
	223	}
	224
708a62bc	225	if (usemsr_ee) {
118a8871 RM	226
	227	err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
	228	if (err) {
	229	dev_warn(dev,
	230	"Unable to access MSR 0xEE, for Tjmax, left"
4d7a5644	231	" at default\n");
118a8871	232	} else if (eax & 0x40000000) {
eccfed42	233	tjmax = tjmax_ee;
118a8871	234	}
708a62bc RM	235	/* if we dont use msr EE it means we are desktop CPU (with exeception
	236	of Atom) */
	237	} else if (tjmax == 100000) {
118a8871 RM	238	dev_warn(dev, "Using relative temperature scale!\n");
	239	}
	240
	241	return tjmax;
	242	}
	243
a321cedb CE	244	static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id,
	245	struct device *dev)
	246	{
	247	/* The 100C is default for both mobile and non mobile CPUs */
	248	int err;
	249	u32 eax, edx;
	250	u32 val;
	251
	252	/* A new feature of current Intel(R) processors, the
	253	IA32_TEMPERATURE_TARGET contains the TjMax value */
	254	err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
	255	if (err) {
	256	dev_warn(dev, "Unable to read TjMax from CPU.\n");
	257	} else {
	258	val = (eax >> 16) & 0xff;
	259	/*
	260	* If the TjMax is not plausible, an assumption
	261	* will be used
	262	*/
	263	if ((val > 80) && (val < 120)) {
	264	dev_info(dev, "TjMax is %d C.\n", val);
	265	return val * 1000;
	266	}
	267	}
	268
	269	/*
	270	* An assumption is made for early CPUs and unreadable MSR.
	271	* NOTE: the given value may not be correct.
	272	*/
	273
	274	switch (c->x86_model) {
	275	case 0xe:
	276	case 0xf:
	277	case 0x16:
	278	case 0x1a:
	279	dev_warn(dev, "TjMax is assumed as 100 C!\n");
	280	return 100000;
	281	break;
	282	case 0x17:
	283	case 0x1c: /* Atom CPUs */
	284	return adjust_tjmax(c, id, dev);
	285	break;
	286	default:
	287	dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
	288	" using default TjMax of 100C.\n", c->x86_model);
	289	return 100000;
	290	}
	291	}
	292
bebe4678 RM	293	static int __devinit coretemp_probe(struct platform_device *pdev)
	294	{
	295	struct coretemp_data *data;
92cb7612	296	struct cpuinfo_x86 *c = &cpu_data(pdev->id);
bebe4678 RM	297	int err;
	298	u32 eax, edx;
	299
	300	if (!(data = kzalloc(sizeof(struct coretemp_data), GFP_KERNEL))) {
	301	err = -ENOMEM;
	302	dev_err(&pdev->dev, "Out of memory\n");
	303	goto exit;
	304	}
	305
	306	data->id = pdev->id;
	307	data->name = "coretemp";
	308	mutex_init(&data->update_lock);
bebe4678 RM	309
	310	/* test if we can access the THERM_STATUS MSR */
	311	err = rdmsr_safe_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
	312	if (err) {
	313	dev_err(&pdev->dev,
	314	"Unable to access THERM_STATUS MSR, giving up\n");
	315	goto exit_free;
	316	}
	317
67f363b1 RM	318	/* Check if we have problem with errata AE18 of Core processors:
	319	Readings might stop update when processor visited too deep sleep,
	320	fixed for stepping D0 (6EC).
	321	*/
	322
	323	if ((c->x86_model == 0xe) && (c->x86_mask < 0xc)) {
	324	/* check for microcode update */
	325	rdmsr_on_cpu(data->id, MSR_IA32_UCODE_REV, &eax, &edx);
	326	if (edx < 0x39) {
6d79af70	327	err = -ENODEV;
67f363b1 RM	328	dev_err(&pdev->dev,
	329	"Errata AE18 not fixed, update BIOS or "
	330	"microcode of the CPU!\n");
	331	goto exit_free;
	332	}
	333	}
	334
a321cedb	335	data->tjmax = get_tjmax(c, data->id, &pdev->dev);
bebe4678 RM	336	platform_set_drvdata(pdev, data);
bebe4678 RM	337
a321cedb CE	338	/*
	339	* read the still undocumented IA32_TEMPERATURE_TARGET. It exists
	340	* on older CPUs but not in this register,
	341	* Atoms don't have it either.
	342	*/
6369a288	343
708a62bc	344	if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
a321cedb CE	345	err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET,
a321cedb CE	346	&eax, &edx);
6369a288 RM	347	if (err) {
	348	dev_warn(&pdev->dev, "Unable to read"
	349	" IA32_TEMPERATURE_TARGET MSR\n");
	350	} else {
	351	data->ttarget = data->tjmax -
	352	(((eax >> 8) & 0xff) * 1000);
	353	err = device_create_file(&pdev->dev,
	354	&sensor_dev_attr_temp1_max.dev_attr);
	355	if (err)
	356	goto exit_free;
	357	}
	358	}
	359
bebe4678	360	if ((err = sysfs_create_group(&pdev->dev.kobj, &coretemp_group)))
6369a288	361	goto exit_dev;
bebe4678	362
1beeffe4 TJ	363	data->hwmon_dev = hwmon_device_register(&pdev->dev);
	364	if (IS_ERR(data->hwmon_dev)) {
	365	err = PTR_ERR(data->hwmon_dev);
bebe4678 RM	366	dev_err(&pdev->dev, "Class registration failed (%d)\n",
	367	err);
	368	goto exit_class;
	369	}
	370
	371	return 0;
	372
	373	exit_class:
	374	sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
6369a288 RM	375	exit_dev:
6369a288 RM	376	device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
bebe4678 RM	377	exit_free:
	378	kfree(data);
	379	exit:
	380	return err;
	381	}
	382
	383	static int __devexit coretemp_remove(struct platform_device *pdev)
	384	{
	385	struct coretemp_data *data = platform_get_drvdata(pdev);
	386
1beeffe4	387	hwmon_device_unregister(data->hwmon_dev);
bebe4678	388	sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
6369a288	389	device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
bebe4678 RM	390	platform_set_drvdata(pdev, NULL);
	391	kfree(data);
	392	return 0;
	393	}
	394
	395	static struct platform_driver coretemp_driver = {
	396	.driver = {
	397	.owner = THIS_MODULE,
	398	.name = DRVNAME,
	399	},
	400	.probe = coretemp_probe,
	401	.remove = __devexit_p(coretemp_remove),
	402	};
	403
	404	struct pdev_entry {
	405	struct list_head list;
	406	struct platform_device *pdev;
	407	unsigned int cpu;
d883b9f0 JD	408	#ifdef CONFIG_SMP
	409	u16 phys_proc_id;
	410	u16 cpu_core_id;
	411	#endif
bebe4678 RM	412	};
	413
	414	static LIST_HEAD(pdev_list);
	415	static DEFINE_MUTEX(pdev_list_mutex);
	416
	417	static int __cpuinit coretemp_device_add(unsigned int cpu)
	418	{
	419	int err;
	420	struct platform_device *pdev;
	421	struct pdev_entry *pdev_entry;
d883b9f0 JD	422	#ifdef CONFIG_SMP
	423	struct cpuinfo_x86 *c = &cpu_data(cpu);
	424	#endif
	425
	426	mutex_lock(&pdev_list_mutex);
	427
	428	#ifdef CONFIG_SMP
	429	/* Skip second HT entry of each core */
	430	list_for_each_entry(pdev_entry, &pdev_list, list) {
	431	if (c->phys_proc_id == pdev_entry->phys_proc_id &&
	432	c->cpu_core_id == pdev_entry->cpu_core_id) {
	433	err = 0; /* Not an error */
	434	goto exit;
	435	}
	436	}
	437	#endif
bebe4678 RM	438
	439	pdev = platform_device_alloc(DRVNAME, cpu);
	440	if (!pdev) {
	441	err = -ENOMEM;
	442	printk(KERN_ERR DRVNAME ": Device allocation failed\n");
	443	goto exit;
	444	}
	445
	446	pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL);
	447	if (!pdev_entry) {
	448	err = -ENOMEM;
	449	goto exit_device_put;
	450	}
	451
	452	err = platform_device_add(pdev);
	453	if (err) {
	454	printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
	455	err);
	456	goto exit_device_free;
	457	}
	458
	459	pdev_entry->pdev = pdev;
	460	pdev_entry->cpu = cpu;
d883b9f0 JD	461	#ifdef CONFIG_SMP
	462	pdev_entry->phys_proc_id = c->phys_proc_id;
	463	pdev_entry->cpu_core_id = c->cpu_core_id;
	464	#endif
bebe4678 RM	465	list_add_tail(&pdev_entry->list, &pdev_list);
	466	mutex_unlock(&pdev_list_mutex);
	467
	468	return 0;
	469
	470	exit_device_free:
	471	kfree(pdev_entry);
	472	exit_device_put:
	473	platform_device_put(pdev);
	474	exit:
d883b9f0	475	mutex_unlock(&pdev_list_mutex);
bebe4678 RM	476	return err;
	477	}
	478
	479	#ifdef CONFIG_HOTPLUG_CPU
d2bc7b13	480	static void coretemp_device_remove(unsigned int cpu)
bebe4678 RM	481	{
	482	struct pdev_entry p, n;
	483	mutex_lock(&pdev_list_mutex);
	484	list_for_each_entry_safe(p, n, &pdev_list, list) {
	485	if (p->cpu == cpu) {
	486	platform_device_unregister(p->pdev);
	487	list_del(&p->list);
	488	kfree(p);
	489	}
	490	}
	491	mutex_unlock(&pdev_list_mutex);
	492	}
	493
ba7c1927	494	static int __cpuinit coretemp_cpu_callback(struct notifier_block *nfb,
bebe4678 RM	495	unsigned long action, void *hcpu)
	496	{
	497	unsigned int cpu = (unsigned long) hcpu;
	498
	499	switch (action) {
	500	case CPU_ONLINE:
561d9a96	501	case CPU_DOWN_FAILED:
bebe4678 RM	502	coretemp_device_add(cpu);
bebe4678 RM	503	break;
561d9a96	504	case CPU_DOWN_PREPARE:
bebe4678 RM	505	coretemp_device_remove(cpu);
	506	break;
	507	}
	508	return NOTIFY_OK;
	509	}
	510
ba7c1927	511	static struct notifier_block coretemp_cpu_notifier __refdata = {
bebe4678 RM	512	.notifier_call = coretemp_cpu_callback,
	513	};
	514	#endif /* !CONFIG_HOTPLUG_CPU */
	515
	516	static int __init coretemp_init(void)
	517	{
	518	int i, err = -ENODEV;
	519	struct pdev_entry p, n;
	520
bebe4678	521	/* quick check if we run Intel */
92cb7612	522	if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
bebe4678 RM	523	goto exit;
	524
	525	err = platform_driver_register(&coretemp_driver);
	526	if (err)
	527	goto exit;
	528
	529	for_each_online_cpu(i) {
92cb7612	530	struct cpuinfo_x86 *c = &cpu_data(i);
5db47b00 CE	531	/*
	532	* CPUID.06H.EAX[0] indicates whether the CPU has thermal
	533	* sensors. We check this bit only, all the early CPUs
	534	* without thermal sensors will be filtered out.
	535	*/
	536	if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
	537	err = coretemp_device_add(i);
	538	if (err)
	539	goto exit_devices_unreg;
bebe4678	540
5db47b00 CE	541	} else {
	542	printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
	543	" has no thermal sensor.\n", c->x86_model);
bebe4678	544	}
bebe4678 RM	545	}
	546	if (list_empty(&pdev_list)) {
	547	err = -ENODEV;
	548	goto exit_driver_unreg;
	549	}
	550
	551	#ifdef CONFIG_HOTPLUG_CPU
	552	register_hotcpu_notifier(&coretemp_cpu_notifier);
	553	#endif
	554	return 0;
	555
	556	exit_devices_unreg:
	557	mutex_lock(&pdev_list_mutex);
	558	list_for_each_entry_safe(p, n, &pdev_list, list) {
	559	platform_device_unregister(p->pdev);
	560	list_del(&p->list);
	561	kfree(p);
	562	}
	563	mutex_unlock(&pdev_list_mutex);
	564	exit_driver_unreg:
	565	platform_driver_unregister(&coretemp_driver);
	566	exit:
	567	return err;
	568	}
	569
	570	static void __exit coretemp_exit(void)
	571	{
	572	struct pdev_entry p, n;
	573	#ifdef CONFIG_HOTPLUG_CPU
	574	unregister_hotcpu_notifier(&coretemp_cpu_notifier);
	575	#endif
	576	mutex_lock(&pdev_list_mutex);
	577	list_for_each_entry_safe(p, n, &pdev_list, list) {
	578	platform_device_unregister(p->pdev);
	579	list_del(&p->list);
	580	kfree(p);
	581	}
	582	mutex_unlock(&pdev_list_mutex);
	583	platform_driver_unregister(&coretemp_driver);
	584	}
	585
	586	MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
	587	MODULE_DESCRIPTION("Intel Core temperature monitor");
	588	MODULE_LICENSE("GPL");
	589
	590	module_init(coretemp_init)
	591	module_exit(coretemp_exit)