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drm/radeon/kms: fix bandwidth calculation when sideport is present
[net-next-2.6.git] / drivers / gpu / drm / radeon / rs690.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
771fe6b9 29#include "radeon.h"
e6990375 30#include "radeon_asic.h"
c93bb85b 31#include "atom.h"
3bc68535 32#include "rs690d.h"
771fe6b9 33
3bc68535 34static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9
JG		 35{
36 unsigned i;
37 uint32_t tmp;
38
39 for (i = 0; i < rdev->usec_timeout; i++) {
40 /* read MC_STATUS */
3bc68535
JG		 41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
771fe6b9 43 return 0;
3bc68535 44 udelay(1);
771fe6b9
JG		 45 }
46 return -1;
47}
48
3bc68535 49static void rs690_gpu_init(struct radeon_device *rdev)
771fe6b9 50{
771fe6b9
JG		 51 /* FIXME: is this correct ? */
52 r420_pipes_init(rdev);
53 if (rs690_mc_wait_for_idle(rdev)) {
54 printk(KERN_WARNING "Failed to wait MC idle while "
55 "programming pipes. Bad things might happen.\n");
56 }
57}
58
a084e6ee
AD		 59union igp_info {
60 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
61 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
62};
63
c93bb85b
JG		 64void rs690_pm_info(struct radeon_device *rdev)
65{
66 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
a084e6ee 67 union igp_info *info;
c93bb85b
JG		 68 uint16_t data_offset;
69 uint8_t frev, crev;
70 fixed20_12 tmp;
71
a084e6ee
AD		 72 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
73 &frev, &crev, &data_offset)) {
74 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
75
76 /* Get various system informations from bios */
77 switch (crev) {
78 case 1:
68adac5e
BS		 79 tmp.full = dfixed_const(100);
80 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock);
81 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
82 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
83 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
84 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
a084e6ee
AD		 85 break;
86 case 2:
68adac5e
BS		 87 tmp.full = dfixed_const(100);
88 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock);
89 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
90 rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);
91 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
92 rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq);
93 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
94 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
a084e6ee
AD		 95 break;
96 default:
68adac5e 97 tmp.full = dfixed_const(100);
a084e6ee
AD		 98 /* We assume the slower possible clock ie worst case */
99 /* DDR 333Mhz */
68adac5e 100 rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
a084e6ee 101 /* FIXME: system clock ? */
68adac5e
BS		 102 rdev->pm.igp_system_mclk.full = dfixed_const(100);
103 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
104 rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
105 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
a084e6ee
AD		 106 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
107 break;
108 }
109 } else {
68adac5e 110 tmp.full = dfixed_const(100);
c93bb85b
JG		 111 /* We assume the slower possible clock ie worst case */
112 /* DDR 333Mhz */
68adac5e 113 rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
c93bb85b 114 /* FIXME: system clock ? */
68adac5e
BS		 115 rdev->pm.igp_system_mclk.full = dfixed_const(100);
116 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
117 rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
118 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
c93bb85b 119 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
c93bb85b
JG		 120 }
121 /* Compute various bandwidth */
122 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
68adac5e
BS		 123 tmp.full = dfixed_const(4);
124 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
c93bb85b
JG		 125 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
126 * = ht_clk * ht_width / 5
127 */
68adac5e
BS		 128 tmp.full = dfixed_const(5);
129 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
c93bb85b 130 rdev->pm.igp_ht_link_width);
68adac5e 131 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
c93bb85b
JG		 132 if (tmp.full < rdev->pm.max_bandwidth.full) {
133 /* HT link is a limiting factor */
134 rdev->pm.max_bandwidth.full = tmp.full;
135 }
136 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
137 * = (sideport_clk * 14) / 10
138 */
68adac5e
BS		 139 tmp.full = dfixed_const(14);
140 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
141 tmp.full = dfixed_const(10);
142 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
c93bb85b
JG		 143}
144
d594e46a 145void rs690_mc_init(struct radeon_device *rdev)
771fe6b9 146{
d594e46a 147 u64 base;
771fe6b9
JG		 148
149 rs400_gart_adjust_size(rdev);
771fe6b9 150 rdev->mc.vram_is_ddr = true;
722f2943 151 rdev->mc.vram_width = 128;
7a50f01a
DA		 152 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
153 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 154 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
155 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
51e5fcd3 156 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a
JG		 157 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
158 base = G_000100_MC_FB_START(base) << 16;
c93bb85b 159 rs690_pm_info(rdev);
06b6476d 160 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
d594e46a
JG		 161 radeon_vram_location(rdev, &rdev->mc, base);
162 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 163 radeon_update_bandwidth_info(rdev);
22dd5013
AD		 164}
165
c93bb85b
JG		 166void rs690_line_buffer_adjust(struct radeon_device *rdev,
167 struct drm_display_mode *mode1,
168 struct drm_display_mode *mode2)
169{
170 u32 tmp;
171
172 /*
173 * Line Buffer Setup
174 * There is a single line buffer shared by both display controllers.
3bc68535 175 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
c93bb85b
JG		 176 * the display controllers. The paritioning can either be done
177 * manually or via one of four preset allocations specified in bits 1:0:
178 * 0 - line buffer is divided in half and shared between crtc
179 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
180 * 2 - D1 gets the whole buffer
181 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
3bc68535 182 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
c93bb85b
JG		 183 * allocation mode. In manual allocation mode, D1 always starts at 0,
184 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
185 */
3bc68535
JG		 186 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
187 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
c93bb85b
JG		 188 /* auto */
189 if (mode1 && mode2) {
190 if (mode1->hdisplay > mode2->hdisplay) {
191 if (mode1->hdisplay > 2560)
3bc68535 192 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
c93bb85b 193 else
3bc68535 194 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b
JG		 195 } else if (mode2->hdisplay > mode1->hdisplay) {
196 if (mode2->hdisplay > 2560)
3bc68535 197 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
c93bb85b 198 else
3bc68535 199 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b 200 } else
3bc68535 201 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b 202 } else if (mode1) {
3bc68535 203 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
c93bb85b 204 } else if (mode2) {
3bc68535 205 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
c93bb85b 206 }
3bc68535 207 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
771fe6b9
JG		 208}
209
c93bb85b
JG		 210struct rs690_watermark {
211 u32 lb_request_fifo_depth;
212 fixed20_12 num_line_pair;
213 fixed20_12 estimated_width;
214 fixed20_12 worst_case_latency;
215 fixed20_12 consumption_rate;
216 fixed20_12 active_time;
217 fixed20_12 dbpp;
218 fixed20_12 priority_mark_max;
219 fixed20_12 priority_mark;
220 fixed20_12 sclk;
221};
222
223void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
224 struct radeon_crtc *crtc,
225 struct rs690_watermark *wm)
226{
227 struct drm_display_mode *mode = &crtc->base.mode;
228 fixed20_12 a, b, c;
229 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
230 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
c93bb85b
JG		 231
232 if (!crtc->base.enabled) {
233 /* FIXME: wouldn't it better to set priority mark to maximum */
234 wm->lb_request_fifo_depth = 4;
235 return;
236 }
237
68adac5e
BS		 238 if (crtc->vsc.full > dfixed_const(2))
239 wm->num_line_pair.full = dfixed_const(2);
c93bb85b 240 else
68adac5e
BS		 241 wm->num_line_pair.full = dfixed_const(1);
242
243 b.full = dfixed_const(mode->crtc_hdisplay);
244 c.full = dfixed_const(256);
245 a.full = dfixed_div(b, c);
246 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
247 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
248 if (a.full < dfixed_const(4)) {
c93bb85b
JG		 249 wm->lb_request_fifo_depth = 4;
250 } else {
68adac5e 251 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
c93bb85b
JG		 252 }
253
254 /* Determine consumption rate
255 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
256 * vtaps = number of vertical taps,
257 * vsc = vertical scaling ratio, defined as source/destination
258 * hsc = horizontal scaling ration, defined as source/destination
259 */
68adac5e
BS		 260 a.full = dfixed_const(mode->clock);
261 b.full = dfixed_const(1000);
262 a.full = dfixed_div(a, b);
263 pclk.full = dfixed_div(b, a);
c93bb85b 264 if (crtc->rmx_type != RMX_OFF) {
68adac5e 265 b.full = dfixed_const(2);
c93bb85b
JG		 266 if (crtc->vsc.full > b.full)
267 b.full = crtc->vsc.full;
68adac5e
BS		 268 b.full = dfixed_mul(b, crtc->hsc);
269 c.full = dfixed_const(2);
270 b.full = dfixed_div(b, c);
271 consumption_time.full = dfixed_div(pclk, b);
c93bb85b
JG		 272 } else {
273 consumption_time.full = pclk.full;
274 }
68adac5e
BS		 275 a.full = dfixed_const(1);
276 wm->consumption_rate.full = dfixed_div(a, consumption_time);
c93bb85b
JG		 277
278
279 /* Determine line time
280 * LineTime = total time for one line of displayhtotal
281 * LineTime = total number of horizontal pixels
282 * pclk = pixel clock period(ns)
283 */
68adac5e
BS		 284 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
285 line_time.full = dfixed_mul(a, pclk);
c93bb85b
JG		 286
287 /* Determine active time
288 * ActiveTime = time of active region of display within one line,
289 * hactive = total number of horizontal active pixels
290 * htotal = total number of horizontal pixels
291 */
68adac5e
BS		 292 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
293 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
294 wm->active_time.full = dfixed_mul(line_time, b);
295 wm->active_time.full = dfixed_div(wm->active_time, a);
c93bb85b
JG		 296
297 /* Maximun bandwidth is the minimun bandwidth of all component */
298 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
0888e883 299 if (rdev->mc.igp_sideport_enabled) {
c93bb85b
JG		 300 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
301 rdev->pm.sideport_bandwidth.full)
302 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
68adac5e
BS		 303 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
304 read_delay_latency.full = dfixed_div(read_delay_latency,
c93bb85b
JG		 305 rdev->pm.igp_sideport_mclk);
306 } else {
307 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
308 rdev->pm.k8_bandwidth.full)
309 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
310 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
311 rdev->pm.ht_bandwidth.full)
312 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
68adac5e 313 read_delay_latency.full = dfixed_const(5000);
c93bb85b
JG		 314 }
315
316 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
68adac5e
BS		 317 a.full = dfixed_const(16);
318 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
319 a.full = dfixed_const(1000);
320 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
c93bb85b
JG		 321 /* Determine chunk time
322 * ChunkTime = the time it takes the DCP to send one chunk of data
323 * to the LB which consists of pipeline delay and inter chunk gap
324 * sclk = system clock(ns)
325 */
68adac5e
BS		 326 a.full = dfixed_const(256 * 13);
327 chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
328 a.full = dfixed_const(10);
329 chunk_time.full = dfixed_div(chunk_time, a);
c93bb85b
JG		 330
331 /* Determine the worst case latency
332 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
333 * WorstCaseLatency = worst case time from urgent to when the MC starts
334 * to return data
335 * READ_DELAY_IDLE_MAX = constant of 1us
336 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
337 * which consists of pipeline delay and inter chunk gap
338 */
68adac5e
BS		 339 if (dfixed_trunc(wm->num_line_pair) > 1) {
340 a.full = dfixed_const(3);
341 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
c93bb85b
JG		 342 wm->worst_case_latency.full += read_delay_latency.full;
343 } else {
68adac5e
BS		 344 a.full = dfixed_const(2);
345 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
c93bb85b
JG		 346 wm->worst_case_latency.full += read_delay_latency.full;
347 }
348
349 /* Determine the tolerable latency
350 * TolerableLatency = Any given request has only 1 line time
351 * for the data to be returned
352 * LBRequestFifoDepth = Number of chunk requests the LB can
353 * put into the request FIFO for a display
354 * LineTime = total time for one line of display
355 * ChunkTime = the time it takes the DCP to send one chunk
356 * of data to the LB which consists of
357 * pipeline delay and inter chunk gap
358 */
68adac5e 359 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
c93bb85b
JG		 360 tolerable_latency.full = line_time.full;
361 } else {
68adac5e 362 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
c93bb85b 363 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
68adac5e 364 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
c93bb85b
JG		 365 tolerable_latency.full = line_time.full - tolerable_latency.full;
366 }
367 /* We assume worst case 32bits (4 bytes) */
68adac5e 368 wm->dbpp.full = dfixed_const(4 * 8);
c93bb85b
JG		 369
370 /* Determine the maximum priority mark
371 * width = viewport width in pixels
372 */
68adac5e
BS		 373 a.full = dfixed_const(16);
374 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
375 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
376 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
c93bb85b
JG		 377
378 /* Determine estimated width */
379 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
68adac5e
BS		 380 estimated_width.full = dfixed_div(estimated_width, consumption_time);
381 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
382 wm->priority_mark.full = dfixed_const(10);
c93bb85b 383 } else {
68adac5e
BS		 384 a.full = dfixed_const(16);
385 wm->priority_mark.full = dfixed_div(estimated_width, a);
386 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
c93bb85b
JG		 387 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
388 }
389}
390
391void rs690_bandwidth_update(struct radeon_device *rdev)
392{
393 struct drm_display_mode *mode0 = NULL;
394 struct drm_display_mode *mode1 = NULL;
395 struct rs690_watermark wm0;
396 struct rs690_watermark wm1;
f46c0120 397 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
c93bb85b
JG		 398 fixed20_12 priority_mark02, priority_mark12, fill_rate;
399 fixed20_12 a, b;
400
f46c0120
AD		 401 radeon_update_display_priority(rdev);
402
c93bb85b
JG		 403 if (rdev->mode_info.crtcs[0]->base.enabled)
404 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
405 if (rdev->mode_info.crtcs[1]->base.enabled)
406 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
407 /*
408 * Set display0/1 priority up in the memory controller for
409 * modes if the user specifies HIGH for displaypriority
410 * option.
411 */
f46c0120
AD		 412 if ((rdev->disp_priority == 2) &&
413 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
3bc68535
JG		 414 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
415 tmp &= C_000104_MC_DISP0R_INIT_LAT;
416 tmp &= C_000104_MC_DISP1R_INIT_LAT;
c93bb85b 417 if (mode0)
3bc68535
JG		 418 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
419 if (mode1)
420 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
421 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
c93bb85b
JG		 422 }
423 rs690_line_buffer_adjust(rdev, mode0, mode1);
424
425 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
3bc68535 426 WREG32(R_006C9C_DCP_CONTROL, 0);
c93bb85b 427 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
3bc68535 428 WREG32(R_006C9C_DCP_CONTROL, 2);
c93bb85b
JG		 429
430 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
431 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
432
433 tmp = (wm0.lb_request_fifo_depth - 1);
434 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
3bc68535 435 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
c93bb85b
JG		 436
437 if (mode0 && mode1) {
68adac5e
BS		 438 if (dfixed_trunc(wm0.dbpp) > 64)
439 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
c93bb85b
JG		 440 else
441 a.full = wm0.num_line_pair.full;
68adac5e
BS		 442 if (dfixed_trunc(wm1.dbpp) > 64)
443 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
c93bb85b
JG		 444 else
445 b.full = wm1.num_line_pair.full;
446 a.full += b.full;
68adac5e 447 fill_rate.full = dfixed_div(wm0.sclk, a);
c93bb85b
JG		 448 if (wm0.consumption_rate.full > fill_rate.full) {
449 b.full = wm0.consumption_rate.full - fill_rate.full;
68adac5e
BS		 450 b.full = dfixed_mul(b, wm0.active_time);
451 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b
JG		 452 wm0.consumption_rate);
453 a.full = a.full + b.full;
68adac5e
BS		 454 b.full = dfixed_const(16 * 1000);
455 priority_mark02.full = dfixed_div(a, b);
c93bb85b 456 } else {
68adac5e 457 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b 458 wm0.consumption_rate);
68adac5e
BS		 459 b.full = dfixed_const(16 * 1000);
460 priority_mark02.full = dfixed_div(a, b);
c93bb85b
JG		 461 }
462 if (wm1.consumption_rate.full > fill_rate.full) {
463 b.full = wm1.consumption_rate.full - fill_rate.full;
68adac5e
BS		 464 b.full = dfixed_mul(b, wm1.active_time);
465 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b
JG		 466 wm1.consumption_rate);
467 a.full = a.full + b.full;
68adac5e
BS		 468 b.full = dfixed_const(16 * 1000);
469 priority_mark12.full = dfixed_div(a, b);
c93bb85b 470 } else {
68adac5e 471 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b 472 wm1.consumption_rate);
68adac5e
BS		 473 b.full = dfixed_const(16 * 1000);
474 priority_mark12.full = dfixed_div(a, b);
c93bb85b
JG		 475 }
476 if (wm0.priority_mark.full > priority_mark02.full)
477 priority_mark02.full = wm0.priority_mark.full;
68adac5e 478 if (dfixed_trunc(priority_mark02) < 0)
c93bb85b
JG		 479 priority_mark02.full = 0;
480 if (wm0.priority_mark_max.full > priority_mark02.full)
481 priority_mark02.full = wm0.priority_mark_max.full;
482 if (wm1.priority_mark.full > priority_mark12.full)
483 priority_mark12.full = wm1.priority_mark.full;
68adac5e 484 if (dfixed_trunc(priority_mark12) < 0)
c93bb85b
JG		 485 priority_mark12.full = 0;
486 if (wm1.priority_mark_max.full > priority_mark12.full)
487 priority_mark12.full = wm1.priority_mark_max.full;
68adac5e
BS		 488 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
489 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
f46c0120
AD		 490 if (rdev->disp_priority == 2) {
491 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
492 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
493 }
494 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
495 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
496 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
497 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
c93bb85b 498 } else if (mode0) {
68adac5e
BS		 499 if (dfixed_trunc(wm0.dbpp) > 64)
500 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
c93bb85b
JG		 501 else
502 a.full = wm0.num_line_pair.full;
68adac5e 503 fill_rate.full = dfixed_div(wm0.sclk, a);
c93bb85b
JG		 504 if (wm0.consumption_rate.full > fill_rate.full) {
505 b.full = wm0.consumption_rate.full - fill_rate.full;
68adac5e
BS		 506 b.full = dfixed_mul(b, wm0.active_time);
507 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b
JG		 508 wm0.consumption_rate);
509 a.full = a.full + b.full;
68adac5e
BS		 510 b.full = dfixed_const(16 * 1000);
511 priority_mark02.full = dfixed_div(a, b);
c93bb85b 512 } else {
68adac5e 513 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b 514 wm0.consumption_rate);
68adac5e
BS		 515 b.full = dfixed_const(16 * 1000);
516 priority_mark02.full = dfixed_div(a, b);
c93bb85b
JG		 517 }
518 if (wm0.priority_mark.full > priority_mark02.full)
519 priority_mark02.full = wm0.priority_mark.full;
68adac5e 520 if (dfixed_trunc(priority_mark02) < 0)
c93bb85b
JG		 521 priority_mark02.full = 0;
522 if (wm0.priority_mark_max.full > priority_mark02.full)
523 priority_mark02.full = wm0.priority_mark_max.full;
68adac5e 524 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
f46c0120
AD		 525 if (rdev->disp_priority == 2)
526 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
527 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
528 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
3bc68535
JG		 529 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
530 S_006D48_D2MODE_PRIORITY_A_OFF(1));
531 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
532 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
c93bb85b 533 } else {
68adac5e
BS		 534 if (dfixed_trunc(wm1.dbpp) > 64)
535 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
c93bb85b
JG		 536 else
537 a.full = wm1.num_line_pair.full;
68adac5e 538 fill_rate.full = dfixed_div(wm1.sclk, a);
c93bb85b
JG		 539 if (wm1.consumption_rate.full > fill_rate.full) {
540 b.full = wm1.consumption_rate.full - fill_rate.full;
68adac5e
BS		 541 b.full = dfixed_mul(b, wm1.active_time);
542 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b
JG		 543 wm1.consumption_rate);
544 a.full = a.full + b.full;
68adac5e
BS		 545 b.full = dfixed_const(16 * 1000);
546 priority_mark12.full = dfixed_div(a, b);
c93bb85b 547 } else {
68adac5e 548 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b 549 wm1.consumption_rate);
68adac5e
BS		 550 b.full = dfixed_const(16 * 1000);
551 priority_mark12.full = dfixed_div(a, b);
c93bb85b
JG		 552 }
553 if (wm1.priority_mark.full > priority_mark12.full)
554 priority_mark12.full = wm1.priority_mark.full;
68adac5e 555 if (dfixed_trunc(priority_mark12) < 0)
c93bb85b
JG		 556 priority_mark12.full = 0;
557 if (wm1.priority_mark_max.full > priority_mark12.full)
558 priority_mark12.full = wm1.priority_mark_max.full;
68adac5e 559 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
f46c0120
AD		 560 if (rdev->disp_priority == 2)
561 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
3bc68535
JG		 562 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
563 S_006548_D1MODE_PRIORITY_A_OFF(1));
564 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
565 S_00654C_D1MODE_PRIORITY_B_OFF(1));
f46c0120
AD		 566 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
567 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
c93bb85b
JG		 568 }
569}
771fe6b9 570
771fe6b9
JG		 571uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
572{
573 uint32_t r;
574
3bc68535
JG		 575 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
576 r = RREG32(R_00007C_MC_DATA);
577 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
771fe6b9
JG		 578 return r;
579}
580
581void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
582{
3bc68535
JG		 583 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
584 S_000078_MC_IND_WR_EN(1));
585 WREG32(R_00007C_MC_DATA, v);
586 WREG32(R_000078_MC_INDEX, 0x7F);
587}
588
589void rs690_mc_program(struct radeon_device *rdev)
590{
591 struct rv515_mc_save save;
592
593 /* Stops all mc clients */
594 rv515_mc_stop(rdev, &save);
595
596 /* Wait for mc idle */
597 if (rs690_mc_wait_for_idle(rdev))
598 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
599 /* Program MC, should be a 32bits limited address space */
600 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
601 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
602 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
603 WREG32(R_000134_HDP_FB_LOCATION,
604 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
605
606 rv515_mc_resume(rdev, &save);
607}
608
609static int rs690_startup(struct radeon_device *rdev)
610{
611 int r;
612
613 rs690_mc_program(rdev);
614 /* Resume clock */
615 rv515_clock_startup(rdev);
616 /* Initialize GPU configuration (# pipes, ...) */
617 rs690_gpu_init(rdev);
618 /* Initialize GART (initialize after TTM so we can allocate
619 * memory through TTM but finalize after TTM) */
620 r = rs400_gart_enable(rdev);
621 if (r)
622 return r;
623 /* Enable IRQ */
ac447df4 624 rs600_irq_set(rdev);
cafe6609 625 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3bc68535
JG		 626 /* 1M ring buffer */
627 r = r100_cp_init(rdev, 1024 * 1024);
628 if (r) {
629 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
630 return r;
631 }
632 r = r100_wb_init(rdev);
633 if (r)
634 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
635 r = r100_ib_init(rdev);
636 if (r) {
637 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
638 return r;
639 }
640 return 0;
641}
642
643int rs690_resume(struct radeon_device *rdev)
644{
645 /* Make sur GART are not working */
646 rs400_gart_disable(rdev);
647 /* Resume clock before doing reset */
648 rv515_clock_startup(rdev);
649 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 650 if (radeon_asic_reset(rdev)) {
3bc68535
JG		 651 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
652 RREG32(R_000E40_RBBM_STATUS),
653 RREG32(R_0007C0_CP_STAT));
654 }
655 /* post */
656 atom_asic_init(rdev->mode_info.atom_context);
657 /* Resume clock after posting */
658 rv515_clock_startup(rdev);
550e2d92
DA		 659 /* Initialize surface registers */
660 radeon_surface_init(rdev);
3bc68535
JG		 661 return rs690_startup(rdev);
662}
663
664int rs690_suspend(struct radeon_device *rdev)
665{
666 r100_cp_disable(rdev);
667 r100_wb_disable(rdev);
ac447df4 668 rs600_irq_disable(rdev);
3bc68535
JG		 669 rs400_gart_disable(rdev);
670 return 0;
671}
672
673void rs690_fini(struct radeon_device *rdev)
674{
3bc68535
JG		 675 r100_cp_fini(rdev);
676 r100_wb_fini(rdev);
677 r100_ib_fini(rdev);
678 radeon_gem_fini(rdev);
679 rs400_gart_fini(rdev);
680 radeon_irq_kms_fini(rdev);
681 radeon_fence_driver_fini(rdev);
4c788679 682 radeon_bo_fini(rdev);
3bc68535
JG		 683 radeon_atombios_fini(rdev);
684 kfree(rdev->bios);
685 rdev->bios = NULL;
686}
687
688int rs690_init(struct radeon_device *rdev)
689{
690 int r;
691
3bc68535
JG		 692 /* Disable VGA */
693 rv515_vga_render_disable(rdev);
694 /* Initialize scratch registers */
695 radeon_scratch_init(rdev);
696 /* Initialize surface registers */
697 radeon_surface_init(rdev);
698 /* TODO: disable VGA need to use VGA request */
699 /* BIOS*/
700 if (!radeon_get_bios(rdev)) {
701 if (ASIC_IS_AVIVO(rdev))
702 return -EINVAL;
703 }
704 if (rdev->is_atom_bios) {
705 r = radeon_atombios_init(rdev);
706 if (r)
707 return r;
708 } else {
709 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
710 return -EINVAL;
711 }
712 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 713 if (radeon_asic_reset(rdev)) {
3bc68535
JG		 714 dev_warn(rdev->dev,
715 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
716 RREG32(R_000E40_RBBM_STATUS),
717 RREG32(R_0007C0_CP_STAT));
718 }
719 /* check if cards are posted or not */
72542d77
DA		 720 if (radeon_boot_test_post_card(rdev) == false)
721 return -EINVAL;
722
3bc68535
JG		 723 /* Initialize clocks */
724 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 725 /* initialize memory controller */
726 rs690_mc_init(rdev);
3bc68535
JG		 727 rv515_debugfs(rdev);
728 /* Fence driver */
729 r = radeon_fence_driver_init(rdev);
730 if (r)
731 return r;
732 r = radeon_irq_kms_init(rdev);
733 if (r)
734 return r;
735 /* Memory manager */
4c788679 736 r = radeon_bo_init(rdev);
3bc68535
JG		 737 if (r)
738 return r;
739 r = rs400_gart_init(rdev);
740 if (r)
741 return r;
742 rs600_set_safe_registers(rdev);
743 rdev->accel_working = true;
744 r = rs690_startup(rdev);
745 if (r) {
746 /* Somethings want wront with the accel init stop accel */
747 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3bc68535
JG		 748 r100_cp_fini(rdev);
749 r100_wb_fini(rdev);
750 r100_ib_fini(rdev);
751 rs400_gart_fini(rdev);
752 radeon_irq_kms_fini(rdev);
753 rdev->accel_working = false;
754 }
755 return 0;
771fe6b9 756}
Clone of davem's net-next-2.6 tree