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DRM / radeon / KMS: Fix hibernation regression related to radeon PM (was: Re: [Regres...
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e
RM		 22 */
23#include "drmP.h"
24#include "radeon.h"
f735261b 25#include "avivod.h"
ce8f5370
AD		 26#ifdef CONFIG_ACPI
27#include <linux/acpi.h>
28#endif
29#include <linux/power_supply.h>
7433874e 30
c913e23a
RM		 31#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c 34#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a 35
f712d0c7
RM		 36static const char *radeon_pm_state_type_name[5] = {
37 "Default",
38 "Powersave",
39 "Battery",
40 "Balanced",
41 "Performance",
42};
43
ce8f5370 44static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 45static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 46static bool radeon_pm_in_vbl(struct radeon_device *rdev);
47static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
48static void radeon_pm_update_profile(struct radeon_device *rdev);
49static void radeon_pm_set_clocks(struct radeon_device *rdev);
50
51#define ACPI_AC_CLASS "ac_adapter"
52
53#ifdef CONFIG_ACPI
54static int radeon_acpi_event(struct notifier_block *nb,
55 unsigned long val,
56 void *data)
57{
58 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
59 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
60
61 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
62 if (power_supply_is_system_supplied() > 0)
ce8a3eb2 63 DRM_DEBUG("pm: AC\n");
ce8f5370 64 else
ce8a3eb2 65 DRM_DEBUG("pm: DC\n");
ce8f5370
AD		 66
67 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
68 if (rdev->pm.profile == PM_PROFILE_AUTO) {
69 mutex_lock(&rdev->pm.mutex);
70 radeon_pm_update_profile(rdev);
71 radeon_pm_set_clocks(rdev);
72 mutex_unlock(&rdev->pm.mutex);
73 }
74 }
75 }
76
77 return NOTIFY_OK;
78}
79#endif
80
81static void radeon_pm_update_profile(struct radeon_device *rdev)
82{
83 switch (rdev->pm.profile) {
84 case PM_PROFILE_DEFAULT:
85 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
86 break;
87 case PM_PROFILE_AUTO:
88 if (power_supply_is_system_supplied() > 0) {
89 if (rdev->pm.active_crtc_count > 1)
90 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
91 else
92 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
93 } else {
94 if (rdev->pm.active_crtc_count > 1)
c9e75b21 95 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 96 else
c9e75b21 97 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 98 }
99 break;
100 case PM_PROFILE_LOW:
101 if (rdev->pm.active_crtc_count > 1)
102 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
103 else
104 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
105 break;
c9e75b21
AD		 106 case PM_PROFILE_MID:
107 if (rdev->pm.active_crtc_count > 1)
108 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
109 else
110 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
111 break;
ce8f5370
AD		 112 case PM_PROFILE_HIGH:
113 if (rdev->pm.active_crtc_count > 1)
114 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
115 else
116 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
117 break;
118 }
119
120 if (rdev->pm.active_crtc_count == 0) {
121 rdev->pm.requested_power_state_index =
122 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
123 rdev->pm.requested_clock_mode_index =
124 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
125 } else {
126 rdev->pm.requested_power_state_index =
127 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
128 rdev->pm.requested_clock_mode_index =
129 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
130 }
131}
c913e23a 132
5876dd24
MG		 133static void radeon_unmap_vram_bos(struct radeon_device *rdev)
134{
135 struct radeon_bo *bo, *n;
136
137 if (list_empty(&rdev->gem.objects))
138 return;
139
140 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
141 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
142 ttm_bo_unmap_virtual(&bo->tbo);
143 }
5876dd24
MG		 144}
145
ce8f5370 146static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 147{
ce8f5370
AD		 148 if (rdev->pm.active_crtcs) {
149 rdev->pm.vblank_sync = false;
150 wait_event_timeout(
151 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
152 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
153 }
154}
155
156static void radeon_set_power_state(struct radeon_device *rdev)
157{
158 u32 sclk, mclk;
92645879 159 bool misc_after = false;
ce8f5370
AD		 160
161 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
162 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
163 return;
164
165 if (radeon_gui_idle(rdev)) {
166 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
167 clock_info[rdev->pm.requested_clock_mode_index].sclk;
168 if (sclk > rdev->clock.default_sclk)
169 sclk = rdev->clock.default_sclk;
170
171 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
172 clock_info[rdev->pm.requested_clock_mode_index].mclk;
173 if (mclk > rdev->clock.default_mclk)
174 mclk = rdev->clock.default_mclk;
175
92645879
AD		 176 /* upvolt before raising clocks, downvolt after lowering clocks */
177 if (sclk < rdev->pm.current_sclk)
178 misc_after = true;
ce8f5370 179
92645879 180 radeon_sync_with_vblank(rdev);
ce8f5370 181
92645879 182 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 183 if (!radeon_pm_in_vbl(rdev))
184 return;
92645879 185 }
ce8f5370 186
92645879 187 radeon_pm_prepare(rdev);
ce8f5370 188
92645879
AD		 189 if (!misc_after)
190 /* voltage, pcie lanes, etc.*/
191 radeon_pm_misc(rdev);
192
193 /* set engine clock */
194 if (sclk != rdev->pm.current_sclk) {
195 radeon_pm_debug_check_in_vbl(rdev, false);
196 radeon_set_engine_clock(rdev, sclk);
197 radeon_pm_debug_check_in_vbl(rdev, true);
198 rdev->pm.current_sclk = sclk;
199 DRM_DEBUG("Setting: e: %d\n", sclk);
200 }
201
202 /* set memory clock */
203 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
204 radeon_pm_debug_check_in_vbl(rdev, false);
205 radeon_set_memory_clock(rdev, mclk);
206 radeon_pm_debug_check_in_vbl(rdev, true);
207 rdev->pm.current_mclk = mclk;
208 DRM_DEBUG("Setting: m: %d\n", mclk);
ce8f5370 209 }
2aba631c 210
92645879
AD		 211 if (misc_after)
212 /* voltage, pcie lanes, etc.*/
213 radeon_pm_misc(rdev);
214
215 radeon_pm_finish(rdev);
216
ce8f5370
AD		 217 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
218 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
219 } else
ce8a3eb2 220 DRM_DEBUG("pm: GUI not idle!!!\n");
ce8f5370
AD		 221}
222
223static void radeon_pm_set_clocks(struct radeon_device *rdev)
224{
225 int i;
c37d230a 226
612e06ce
MG		 227 mutex_lock(&rdev->ddev->struct_mutex);
228 mutex_lock(&rdev->vram_mutex);
a424816f 229 mutex_lock(&rdev->cp.mutex);
4f3218cb
AD		 230
231 /* gui idle int has issues on older chips it seems */
232 if (rdev->family >= CHIP_R600) {
ce8f5370
AD		 233 if (rdev->irq.installed) {
234 /* wait for GPU idle */
235 rdev->pm.gui_idle = false;
236 rdev->irq.gui_idle = true;
237 radeon_irq_set(rdev);
238 wait_event_interruptible_timeout(
239 rdev->irq.idle_queue, rdev->pm.gui_idle,
240 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
241 rdev->irq.gui_idle = false;
242 radeon_irq_set(rdev);
243 }
01434b4b 244 } else {
ce8f5370
AD		 245 if (rdev->cp.ready) {
246 struct radeon_fence *fence;
247 radeon_ring_alloc(rdev, 64);
248 radeon_fence_create(rdev, &fence);
249 radeon_fence_emit(rdev, fence);
250 radeon_ring_commit(rdev);
251 radeon_fence_wait(fence, false);
252 radeon_fence_unref(&fence);
253 }
4f3218cb 254 }
5876dd24
MG		 255 radeon_unmap_vram_bos(rdev);
256
ce8f5370 257 if (rdev->irq.installed) {
2aba631c
MG		 258 for (i = 0; i < rdev->num_crtc; i++) {
259 if (rdev->pm.active_crtcs & (1 << i)) {
260 rdev->pm.req_vblank |= (1 << i);
261 drm_vblank_get(rdev->ddev, i);
262 }
263 }
264 }
539d2418 265
ce8f5370 266 radeon_set_power_state(rdev);
2aba631c 267
ce8f5370 268 if (rdev->irq.installed) {
2aba631c
MG		 269 for (i = 0; i < rdev->num_crtc; i++) {
270 if (rdev->pm.req_vblank & (1 << i)) {
271 rdev->pm.req_vblank &= ~(1 << i);
272 drm_vblank_put(rdev->ddev, i);
273 }
274 }
275 }
5876dd24 276
a424816f
AD		 277 /* update display watermarks based on new power state */
278 radeon_update_bandwidth_info(rdev);
279 if (rdev->pm.active_crtc_count)
280 radeon_bandwidth_update(rdev);
281
ce8f5370 282 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 283
a424816f 284 mutex_unlock(&rdev->cp.mutex);
612e06ce
MG		 285 mutex_unlock(&rdev->vram_mutex);
286 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 287}
288
f712d0c7
RM		 289static void radeon_pm_print_states(struct radeon_device *rdev)
290{
291 int i, j;
292 struct radeon_power_state *power_state;
293 struct radeon_pm_clock_info *clock_info;
294
295 DRM_DEBUG("%d Power State(s)\n", rdev->pm.num_power_states);
296 for (i = 0; i < rdev->pm.num_power_states; i++) {
297 power_state = &rdev->pm.power_state[i];
298 DRM_DEBUG("State %d: %s\n", i,
299 radeon_pm_state_type_name[power_state->type]);
300 if (i == rdev->pm.default_power_state_index)
301 DRM_DEBUG("\tDefault");
302 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
303 DRM_DEBUG("\t%d PCIE Lanes\n", power_state->pcie_lanes);
304 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
305 DRM_DEBUG("\tSingle display only\n");
306 DRM_DEBUG("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
307 for (j = 0; j < power_state->num_clock_modes; j++) {
308 clock_info = &(power_state->clock_info[j]);
309 if (rdev->flags & RADEON_IS_IGP)
310 DRM_DEBUG("\t\t%d e: %d%s\n",
311 j,
312 clock_info->sclk * 10,
313 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
314 else
315 DRM_DEBUG("\t\t%d e: %d\tm: %d\tv: %d%s\n",
316 j,
317 clock_info->sclk * 10,
318 clock_info->mclk * 10,
319 clock_info->voltage.voltage,
320 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
321 }
322 }
323}
324
ce8f5370
AD		 325static ssize_t radeon_get_pm_profile(struct device *dev,
326 struct device_attribute *attr,
327 char *buf)
a424816f
AD		 328{
329 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
330 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 331 int cp = rdev->pm.profile;
a424816f 332
ce8f5370
AD		 333 return snprintf(buf, PAGE_SIZE, "%s\n",
334 (cp == PM_PROFILE_AUTO) ? "auto" :
335 (cp == PM_PROFILE_LOW) ? "low" :
336 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 337}
338
ce8f5370
AD		 339static ssize_t radeon_set_pm_profile(struct device *dev,
340 struct device_attribute *attr,
341 const char *buf,
342 size_t count)
a424816f
AD		 343{
344 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
345 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 346
347 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 348 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
349 if (strncmp("default", buf, strlen("default")) == 0)
350 rdev->pm.profile = PM_PROFILE_DEFAULT;
351 else if (strncmp("auto", buf, strlen("auto")) == 0)
352 rdev->pm.profile = PM_PROFILE_AUTO;
353 else if (strncmp("low", buf, strlen("low")) == 0)
354 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 355 else if (strncmp("mid", buf, strlen("mid")) == 0)
356 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 357 else if (strncmp("high", buf, strlen("high")) == 0)
358 rdev->pm.profile = PM_PROFILE_HIGH;
359 else {
360 DRM_ERROR("invalid power profile!\n");
361 goto fail;
a424816f 362 }
ce8f5370
AD		 363 radeon_pm_update_profile(rdev);
364 radeon_pm_set_clocks(rdev);
365 }
366fail:
a424816f
AD		 367 mutex_unlock(&rdev->pm.mutex);
368
369 return count;
370}
371
ce8f5370
AD		 372static ssize_t radeon_get_pm_method(struct device *dev,
373 struct device_attribute *attr,
374 char *buf)
a424816f
AD		 375{
376 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
377 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 378 int pm = rdev->pm.pm_method;
a424816f
AD		 379
380 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 381 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 382}
383
ce8f5370
AD		 384static ssize_t radeon_set_pm_method(struct device *dev,
385 struct device_attribute *attr,
386 const char *buf,
387 size_t count)
a424816f
AD		 388{
389 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
390 struct radeon_device *rdev = ddev->dev_private;
a424816f 391
ce8f5370
AD		 392
393 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 394 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 395 rdev->pm.pm_method = PM_METHOD_DYNPM;
396 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
397 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 398 mutex_unlock(&rdev->pm.mutex);
ce8f5370 399 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
3f53eb6f
RW		 400 bool flush_wq = false;
401
ce8f5370 402 mutex_lock(&rdev->pm.mutex);
3f53eb6f
RW		 403 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
404 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
405 flush_wq = true;
406 }
ce8f5370
AD		 407 /* disable dynpm */
408 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
409 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 410 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 411 mutex_unlock(&rdev->pm.mutex);
3f53eb6f
RW		 412 if (flush_wq)
413 flush_workqueue(rdev->wq);
ce8f5370
AD		 414 } else {
415 DRM_ERROR("invalid power method!\n");
416 goto fail;
417 }
418 radeon_pm_compute_clocks(rdev);
419fail:
a424816f
AD		 420 return count;
421}
422
ce8f5370
AD		 423static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
424static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 425
ce8f5370 426void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 427{
3f53eb6f
RW		 428 bool flush_wq = false;
429
ce8f5370 430 mutex_lock(&rdev->pm.mutex);
3f53eb6f
RW		 431 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
432 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
433 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
434 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
435 flush_wq = true;
436 }
ce8f5370 437 mutex_unlock(&rdev->pm.mutex);
3f53eb6f
RW		 438 if (flush_wq)
439 flush_workqueue(rdev->wq);
56278a8e
AD		 440}
441
ce8f5370 442void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 443{
f8ed8b4c
AD		 444 /* asic init will reset the default power state */
445 mutex_lock(&rdev->pm.mutex);
446 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
447 rdev->pm.current_clock_mode_index = 0;
448 rdev->pm.current_sclk = rdev->clock.default_sclk;
449 rdev->pm.current_mclk = rdev->clock.default_mclk;
4d60173f 450 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
3f53eb6f
RW		 451 if (rdev->pm.pm_method == PM_METHOD_DYNPM
452 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
453 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
454 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
455 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
456 }
f8ed8b4c 457 mutex_unlock(&rdev->pm.mutex);
ce8f5370 458 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 459}
460
7433874e
RM		 461int radeon_pm_init(struct radeon_device *rdev)
462{
26481fb1 463 int ret;
ce8f5370
AD		 464 /* default to profile method */
465 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 466 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 467 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
468 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
469 rdev->pm.dynpm_can_upclock = true;
470 rdev->pm.dynpm_can_downclock = true;
f8ed8b4c
AD		 471 rdev->pm.current_sclk = rdev->clock.default_sclk;
472 rdev->pm.current_mclk = rdev->clock.default_mclk;
c913e23a 473
56278a8e
AD		 474 if (rdev->bios) {
475 if (rdev->is_atom_bios)
476 radeon_atombios_get_power_modes(rdev);
477 else
478 radeon_combios_get_power_modes(rdev);
f712d0c7 479 radeon_pm_print_states(rdev);
ce8f5370 480 radeon_pm_init_profile(rdev);
56278a8e
AD		 481 }
482
ce8f5370 483 if (rdev->pm.num_power_states > 1) {
ce8f5370 484 /* where's the best place to put these? */
26481fb1
DA		 485 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
486 if (ret)
487 DRM_ERROR("failed to create device file for power profile\n");
488 ret = device_create_file(rdev->dev, &dev_attr_power_method);
489 if (ret)
490 DRM_ERROR("failed to create device file for power method\n");
a424816f 491
ce8f5370
AD		 492#ifdef CONFIG_ACPI
493 rdev->acpi_nb.notifier_call = radeon_acpi_event;
494 register_acpi_notifier(&rdev->acpi_nb);
495#endif
496 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
c913e23a 497
ce8f5370
AD		 498 if (radeon_debugfs_pm_init(rdev)) {
499 DRM_ERROR("Failed to register debugfs file for PM!\n");
500 }
c913e23a 501
ce8f5370
AD		 502 DRM_INFO("radeon: power management initialized\n");
503 }
c913e23a 504
7433874e
RM		 505 return 0;
506}
507
29fb52ca
AD		 508void radeon_pm_fini(struct radeon_device *rdev)
509{
ce8f5370 510 if (rdev->pm.num_power_states > 1) {
3f53eb6f
RW		 511 bool flush_wq = false;
512
a424816f 513 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 514 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
515 rdev->pm.profile = PM_PROFILE_DEFAULT;
516 radeon_pm_update_profile(rdev);
517 radeon_pm_set_clocks(rdev);
518 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
519 /* cancel work */
3f53eb6f
RW		 520 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
521 flush_wq = true;
ce8f5370
AD		 522 /* reset default clocks */
523 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
524 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
525 radeon_pm_set_clocks(rdev);
526 }
a424816f 527 mutex_unlock(&rdev->pm.mutex);
3f53eb6f
RW		 528 if (flush_wq)
529 flush_workqueue(rdev->wq);
58e21dff 530
ce8f5370
AD		 531 device_remove_file(rdev->dev, &dev_attr_power_profile);
532 device_remove_file(rdev->dev, &dev_attr_power_method);
533#ifdef CONFIG_ACPI
534 unregister_acpi_notifier(&rdev->acpi_nb);
535#endif
536 }
a424816f 537
29fb52ca
AD		 538 if (rdev->pm.i2c_bus)
539 radeon_i2c_destroy(rdev->pm.i2c_bus);
540}
541
c913e23a
RM		 542void radeon_pm_compute_clocks(struct radeon_device *rdev)
543{
544 struct drm_device *ddev = rdev->ddev;
a48b9b4e 545 struct drm_crtc *crtc;
c913e23a 546 struct radeon_crtc *radeon_crtc;
c913e23a 547
ce8f5370
AD		 548 if (rdev->pm.num_power_states < 2)
549 return;
550
c913e23a
RM		 551 mutex_lock(&rdev->pm.mutex);
552
553 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 554 rdev->pm.active_crtc_count = 0;
555 list_for_each_entry(crtc,
556 &ddev->mode_config.crtc_list, head) {
557 radeon_crtc = to_radeon_crtc(crtc);
558 if (radeon_crtc->enabled) {
c913e23a 559 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 560 rdev->pm.active_crtc_count++;
c913e23a
RM		 561 }
562 }
563
ce8f5370
AD		 564 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
565 radeon_pm_update_profile(rdev);
566 radeon_pm_set_clocks(rdev);
567 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
568 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
569 if (rdev->pm.active_crtc_count > 1) {
570 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
571 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
572
573 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
574 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
575 radeon_pm_get_dynpm_state(rdev);
576 radeon_pm_set_clocks(rdev);
577
578 DRM_DEBUG("radeon: dynamic power management deactivated\n");
579 }
580 } else if (rdev->pm.active_crtc_count == 1) {
581 /* TODO: Increase clocks if needed for current mode */
582
583 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
584 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
585 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
586 radeon_pm_get_dynpm_state(rdev);
587 radeon_pm_set_clocks(rdev);
588
589 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
590 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
591 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
592 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
593 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
594 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
595 DRM_DEBUG("radeon: dynamic power management activated\n");
596 }
597 } else { /* count == 0 */
598 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
599 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
600
601 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
602 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
603 radeon_pm_get_dynpm_state(rdev);
604 radeon_pm_set_clocks(rdev);
605 }
606 }
c913e23a 607 }
c913e23a 608 }
73a6d3fc
RM		 609
610 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 611}
612
ce8f5370 613static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 614{
539d2418 615 u32 stat_crtc = 0, vbl = 0, position = 0;
f735261b
DA		 616 bool in_vbl = true;
617
bae6b562
AD		 618 if (ASIC_IS_DCE4(rdev)) {
619 if (rdev->pm.active_crtcs & (1 << 0)) {
539d2418
AD		 620 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
621 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
622 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
623 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 624 }
625 if (rdev->pm.active_crtcs & (1 << 1)) {
539d2418
AD		 626 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
627 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
628 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
629 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 630 }
631 if (rdev->pm.active_crtcs & (1 << 2)) {
539d2418
AD		 632 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
633 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
634 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
635 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 636 }
637 if (rdev->pm.active_crtcs & (1 << 3)) {
539d2418
AD		 638 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
639 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
640 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
641 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 642 }
643 if (rdev->pm.active_crtcs & (1 << 4)) {
539d2418
AD		 644 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
645 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
646 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
647 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 648 }
649 if (rdev->pm.active_crtcs & (1 << 5)) {
539d2418
AD		 650 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
651 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
652 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
653 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 654 }
655 } else if (ASIC_IS_AVIVO(rdev)) {
656 if (rdev->pm.active_crtcs & (1 << 0)) {
539d2418
AD		 657 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
658 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
bae6b562
AD		 659 }
660 if (rdev->pm.active_crtcs & (1 << 1)) {
539d2418
AD		 661 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
662 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
bae6b562 663 }
539d2418
AD		 664 if (position < vbl && position > 1)
665 in_vbl = false;
bae6b562 666 } else {
f735261b 667 if (rdev->pm.active_crtcs & (1 << 0)) {
bae6b562
AD		 668 stat_crtc = RREG32(RADEON_CRTC_STATUS);
669 if (!(stat_crtc & 1))
f735261b
DA		 670 in_vbl = false;
671 }
672 if (rdev->pm.active_crtcs & (1 << 1)) {
bae6b562
AD		 673 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
674 if (!(stat_crtc & 1))
f735261b
DA		 675 in_vbl = false;
676 }
677 }
f81f2024 678
539d2418
AD		 679 if (position < vbl && position > 1)
680 in_vbl = false;
681
f81f2024
MG		 682 return in_vbl;
683}
684
ce8f5370 685static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 686{
687 u32 stat_crtc = 0;
688 bool in_vbl = radeon_pm_in_vbl(rdev);
689
f735261b 690 if (in_vbl == false)
ce8a3eb2 691 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 692 finish ? "exit" : "entry");
f735261b
DA		 693 return in_vbl;
694}
c913e23a 695
ce8f5370 696static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 697{
698 struct radeon_device *rdev;
d9932a32 699 int resched;
c913e23a 700 rdev = container_of(work, struct radeon_device,
ce8f5370 701 pm.dynpm_idle_work.work);
c913e23a 702
d9932a32 703 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 704 mutex_lock(&rdev->pm.mutex);
ce8f5370 705 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a
RM		 706 unsigned long irq_flags;
707 int not_processed = 0;
708
709 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
710 if (!list_empty(&rdev->fence_drv.emited)) {
711 struct list_head *ptr;
712 list_for_each(ptr, &rdev->fence_drv.emited) {
713 /* count up to 3, that's enought info */
714 if (++not_processed >= 3)
715 break;
716 }
717 }
718 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
719
720 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 721 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
722 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
723 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
724 rdev->pm.dynpm_can_upclock) {
725 rdev->pm.dynpm_planned_action =
726 DYNPM_ACTION_UPCLOCK;
727 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 728 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
729 }
730 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 731 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
732 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
733 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
734 rdev->pm.dynpm_can_downclock) {
735 rdev->pm.dynpm_planned_action =
736 DYNPM_ACTION_DOWNCLOCK;
737 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 738 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
739 }
740 }
741
d7311171
AD		 742 /* Note, radeon_pm_set_clocks is called with static_switch set
743 * to false since we want to wait for vbl to avoid flicker.
744 */
ce8f5370
AD		 745 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
746 jiffies > rdev->pm.dynpm_action_timeout) {
747 radeon_pm_get_dynpm_state(rdev);
748 radeon_pm_set_clocks(rdev);
c913e23a 749 }
3f53eb6f
RW		 750
751 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
752 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 753 }
754 mutex_unlock(&rdev->pm.mutex);
d9932a32 755 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 756}
757
7433874e
RM		 758/*
759 * Debugfs info
760 */
761#if defined(CONFIG_DEBUG_FS)
762
763static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
764{
765 struct drm_info_node *node = (struct drm_info_node *) m->private;
766 struct drm_device *dev = node->minor->dev;
767 struct radeon_device *rdev = dev->dev_private;
768
6234077d
RM		 769 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
770 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
771 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
772 if (rdev->asic->get_memory_clock)
773 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 774 if (rdev->pm.current_vddc)
775 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
aa5120d2
RM		 776 if (rdev->asic->get_pcie_lanes)
777 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 778
779 return 0;
780}
781
782static struct drm_info_list radeon_pm_info_list[] = {
783 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
784};
785#endif
786
c913e23a 787static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 788{
789#if defined(CONFIG_DEBUG_FS)
790 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
791#else
792 return 0;
793#endif
794}
Clone of davem's net-next-2.6 tree