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drm/radeon: add fake RN50 table for powerpc
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_mode.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
746c1aa4 36#include <drm_dp_helper.h>
68adac5e 37#include <drm_fixed.h>
771fe6b9
JG		 38#include <linux/i2c.h>
39#include <linux/i2c-id.h>
40#include <linux/i2c-algo-bit.h>
c93bb85b 41
38651674 42struct radeon_bo;
c93bb85b 43struct radeon_device;
771fe6b9
JG		 44
45#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
46#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
47#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
48#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
49
771fe6b9
JG		 50enum radeon_rmx_type {
51 RMX_OFF,
52 RMX_FULL,
53 RMX_CENTER,
54 RMX_ASPECT
55};
56
57enum radeon_tv_std {
58 TV_STD_NTSC,
59 TV_STD_PAL,
60 TV_STD_PAL_M,
61 TV_STD_PAL_60,
62 TV_STD_NTSC_J,
63 TV_STD_SCART_PAL,
64 TV_STD_SECAM,
65 TV_STD_PAL_CN,
d79766fa 66 TV_STD_PAL_N,
771fe6b9
JG		 67};
68
8e36ed00
AD		 69enum radeon_hpd_id {
70 RADEON_HPD_1 = 0,
71 RADEON_HPD_2,
72 RADEON_HPD_3,
73 RADEON_HPD_4,
74 RADEON_HPD_5,
75 RADEON_HPD_6,
76 RADEON_HPD_NONE = 0xff,
77};
78
9b9fe724
AD		 79/* radeon gpio-based i2c
80 * 1. "mask" reg and bits
81 * grabs the gpio pins for software use
82 * 0=not held 1=held
83 * 2. "a" reg and bits
84 * output pin value
85 * 0=low 1=high
86 * 3. "en" reg and bits
87 * sets the pin direction
88 * 0=input 1=output
89 * 4. "y" reg and bits
90 * input pin value
91 * 0=low 1=high
92 */
771fe6b9
JG		 93struct radeon_i2c_bus_rec {
94 bool valid;
6a93cb25
AD		 95 /* id used by atom */
96 uint8_t i2c_id;
bcc1c2a1 97 /* id used by atom */
8e36ed00 98 enum radeon_hpd_id hpd;
6a93cb25
AD		 99 /* can be used with hw i2c engine */
100 bool hw_capable;
101 /* uses multi-media i2c engine */
102 bool mm_i2c;
103 /* regs and bits */
771fe6b9
JG		 104 uint32_t mask_clk_reg;
105 uint32_t mask_data_reg;
106 uint32_t a_clk_reg;
107 uint32_t a_data_reg;
9b9fe724
AD		 108 uint32_t en_clk_reg;
109 uint32_t en_data_reg;
110 uint32_t y_clk_reg;
111 uint32_t y_data_reg;
771fe6b9
JG		 112 uint32_t mask_clk_mask;
113 uint32_t mask_data_mask;
771fe6b9
JG		 114 uint32_t a_clk_mask;
115 uint32_t a_data_mask;
9b9fe724
AD		 116 uint32_t en_clk_mask;
117 uint32_t en_data_mask;
118 uint32_t y_clk_mask;
119 uint32_t y_data_mask;
771fe6b9
JG		 120};
121
122struct radeon_tmds_pll {
123 uint32_t freq;
124 uint32_t value;
125};
126
127#define RADEON_MAX_BIOS_CONNECTOR 16
128
7c27f87d 129/* pll flags */
771fe6b9
JG		 130#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
131#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
132#define RADEON_PLL_USE_REF_DIV (1 << 2)
133#define RADEON_PLL_LEGACY (1 << 3)
134#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
135#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
136#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
137#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
138#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
139#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
140#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
d0e275a9 141#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
fc10332b 142#define RADEON_PLL_USE_POST_DIV (1 << 12)
86cb2bbf 143#define RADEON_PLL_IS_LCD (1 << 13)
771fe6b9 144
7c27f87d
AD		 145/* pll algo */
146enum radeon_pll_algo {
147 PLL_ALGO_LEGACY,
383be5d1 148 PLL_ALGO_NEW
7c27f87d
AD		 149};
150
771fe6b9 151struct radeon_pll {
fc10332b
AD		 152 /* reference frequency */
153 uint32_t reference_freq;
154
155 /* fixed dividers */
156 uint32_t reference_div;
157 uint32_t post_div;
158
159 /* pll in/out limits */
771fe6b9
JG		 160 uint32_t pll_in_min;
161 uint32_t pll_in_max;
162 uint32_t pll_out_min;
163 uint32_t pll_out_max;
86cb2bbf
AD		 164 uint32_t lcd_pll_out_min;
165 uint32_t lcd_pll_out_max;
fc10332b 166 uint32_t best_vco;
771fe6b9 167
fc10332b 168 /* divider limits */
771fe6b9
JG		 169 uint32_t min_ref_div;
170 uint32_t max_ref_div;
171 uint32_t min_post_div;
172 uint32_t max_post_div;
173 uint32_t min_feedback_div;
174 uint32_t max_feedback_div;
175 uint32_t min_frac_feedback_div;
176 uint32_t max_frac_feedback_div;
fc10332b
AD		 177
178 /* flags for the current clock */
179 uint32_t flags;
180
181 /* pll id */
182 uint32_t id;
7c27f87d
AD		 183 /* pll algo */
184 enum radeon_pll_algo algo;
771fe6b9
JG		 185};
186
187struct radeon_i2c_chan {
771fe6b9 188 struct i2c_adapter adapter;
746c1aa4
DA		 189 struct drm_device *dev;
190 union {
ac1aade6 191 struct i2c_algo_bit_data bit;
746c1aa4 192 struct i2c_algo_dp_aux_data dp;
746c1aa4 193 } algo;
771fe6b9
JG		 194 struct radeon_i2c_bus_rec rec;
195};
196
197/* mostly for macs, but really any system without connector tables */
198enum radeon_connector_table {
199 CT_NONE,
200 CT_GENERIC,
201 CT_IBOOK,
202 CT_POWERBOOK_EXTERNAL,
203 CT_POWERBOOK_INTERNAL,
204 CT_POWERBOOK_VGA,
205 CT_MINI_EXTERNAL,
206 CT_MINI_INTERNAL,
207 CT_IMAC_G5_ISIGHT,
208 CT_EMAC,
76a7142a 209 CT_RN50_POWER,
771fe6b9
JG		 210};
211
fcec570b
AD		 212enum radeon_dvo_chip {
213 DVO_SIL164,
214 DVO_SIL1178,
215};
216
8be48d92 217struct radeon_fbdev;
38651674 218
771fe6b9
JG		 219struct radeon_mode_info {
220 struct atom_context *atom_context;
61c4b24b 221 struct card_info *atom_card_info;
771fe6b9
JG		 222 enum radeon_connector_table connector_table;
223 bool mode_config_initialized;
bcc1c2a1 224 struct radeon_crtc *crtcs[6];
445282db
DA		 225 /* DVI-I properties */
226 struct drm_property *coherent_mode_property;
227 /* DAC enable load detect */
228 struct drm_property *load_detect_property;
229 /* TV standard load detect */
230 struct drm_property *tv_std_property;
231 /* legacy TMDS PLL detect */
232 struct drm_property *tmds_pll_property;
3c537889
AD		 233 /* hardcoded DFP edid from BIOS */
234 struct edid *bios_hardcoded_edid;
38651674
DA		 235
236 /* pointer to fbdev info structure */
8be48d92 237 struct radeon_fbdev *rfbdev;
c93bb85b
JG		 238};
239
4ce001ab
DA		 240#define MAX_H_CODE_TIMING_LEN 32
241#define MAX_V_CODE_TIMING_LEN 32
242
243/* need to store these as reading
244 back code tables is excessive */
245struct radeon_tv_regs {
246 uint32_t tv_uv_adr;
247 uint32_t timing_cntl;
248 uint32_t hrestart;
249 uint32_t vrestart;
250 uint32_t frestart;
251 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
252 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
253};
254
771fe6b9
JG		 255struct radeon_crtc {
256 struct drm_crtc base;
257 int crtc_id;
258 u16 lut_r[256], lut_g[256], lut_b[256];
259 bool enabled;
260 bool can_tile;
261 uint32_t crtc_offset;
771fe6b9
JG		 262 struct drm_gem_object *cursor_bo;
263 uint64_t cursor_addr;
264 int cursor_width;
265 int cursor_height;
4162338a 266 uint32_t legacy_display_base_addr;
c836e862 267 uint32_t legacy_cursor_offset;
c93bb85b 268 enum radeon_rmx_type rmx_type;
c93bb85b
JG		 269 fixed20_12 vsc;
270 fixed20_12 hsc;
de2103e4 271 struct drm_display_mode native_mode;
bcc1c2a1 272 int pll_id;
771fe6b9
JG		 273};
274
275struct radeon_encoder_primary_dac {
276 /* legacy primary dac */
277 uint32_t ps2_pdac_adj;
278};
279
280struct radeon_encoder_lvds {
281 /* legacy lvds */
282 uint16_t panel_vcc_delay;
283 uint8_t panel_pwr_delay;
284 uint8_t panel_digon_delay;
285 uint8_t panel_blon_delay;
286 uint16_t panel_ref_divider;
287 uint8_t panel_post_divider;
288 uint16_t panel_fb_divider;
289 bool use_bios_dividers;
290 uint32_t lvds_gen_cntl;
291 /* panel mode */
de2103e4 292 struct drm_display_mode native_mode;
771fe6b9
JG		 293};
294
295struct radeon_encoder_tv_dac {
296 /* legacy tv dac */
297 uint32_t ps2_tvdac_adj;
298 uint32_t ntsc_tvdac_adj;
299 uint32_t pal_tvdac_adj;
300
4ce001ab
DA		 301 int h_pos;
302 int v_pos;
303 int h_size;
304 int supported_tv_stds;
305 bool tv_on;
771fe6b9 306 enum radeon_tv_std tv_std;
4ce001ab 307 struct radeon_tv_regs tv;
771fe6b9
JG		 308};
309
310struct radeon_encoder_int_tmds {
311 /* legacy int tmds */
312 struct radeon_tmds_pll tmds_pll[4];
313};
314
fcec570b
AD		 315struct radeon_encoder_ext_tmds {
316 /* tmds over dvo */
317 struct radeon_i2c_chan *i2c_bus;
318 uint8_t slave_addr;
319 enum radeon_dvo_chip dvo_chip;
320};
321
ebbe1cb9
AD		 322/* spread spectrum */
323struct radeon_atom_ss {
324 uint16_t percentage;
325 uint8_t type;
326 uint8_t step;
327 uint8_t delay;
328 uint8_t range;
329 uint8_t refdiv;
330};
331
771fe6b9
JG		 332struct radeon_encoder_atom_dig {
333 /* atom dig */
334 bool coherent_mode;
f28cf339 335 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
771fe6b9
JG		 336 /* atom lvds */
337 uint32_t lvds_misc;
338 uint16_t panel_pwr_delay;
7c27f87d 339 enum radeon_pll_algo pll_algo;
ebbe1cb9 340 struct radeon_atom_ss *ss;
771fe6b9 341 /* panel mode */
de2103e4 342 struct drm_display_mode native_mode;
771fe6b9
JG		 343};
344
4ce001ab
DA		 345struct radeon_encoder_atom_dac {
346 enum radeon_tv_std tv_std;
347};
348
771fe6b9
JG		 349struct radeon_encoder {
350 struct drm_encoder base;
351 uint32_t encoder_id;
352 uint32_t devices;
4ce001ab 353 uint32_t active_device;
771fe6b9
JG		 354 uint32_t flags;
355 uint32_t pixel_clock;
356 enum radeon_rmx_type rmx_type;
de2103e4 357 struct drm_display_mode native_mode;
771fe6b9 358 void *enc_priv;
58bd0863 359 int audio_polling_active;
dafc3bd5 360 int hdmi_offset;
808032ee 361 int hdmi_config_offset;
dafc3bd5
CK		 362 int hdmi_audio_workaround;
363 int hdmi_buffer_status;
771fe6b9
JG		 364};
365
366struct radeon_connector_atom_dig {
367 uint32_t igp_lane_info;
368 bool linkb;
4143e919 369 /* displayport */
746c1aa4 370 struct radeon_i2c_chan *dp_i2c_bus;
1a66c95a 371 u8 dpcd[8];
4143e919 372 u8 dp_sink_type;
5801ead6
AD		 373 int dp_clock;
374 int dp_lane_count;
771fe6b9
JG		 375};
376
eed45b30
AD		 377struct radeon_gpio_rec {
378 bool valid;
379 u8 id;
380 u32 reg;
381 u32 mask;
382};
383
eed45b30
AD		 384struct radeon_hpd {
385 enum radeon_hpd_id hpd;
386 u8 plugged_state;
387 struct radeon_gpio_rec gpio;
388};
389
771fe6b9
JG		 390struct radeon_connector {
391 struct drm_connector base;
392 uint32_t connector_id;
393 uint32_t devices;
394 struct radeon_i2c_chan *ddc_bus;
0294cf4f
AD		 395 /* some systems have a an hdmi and vga port with a shared ddc line */
396 bool shared_ddc;
4ce001ab
DA		 397 bool use_digital;
398 /* we need to mind the EDID between detect
399 and get modes due to analog/digital/tvencoder */
400 struct edid *edid;
771fe6b9 401 void *con_priv;
445282db 402 bool dac_load_detect;
b75fad06 403 uint16_t connector_object_id;
eed45b30 404 struct radeon_hpd hpd;
771fe6b9
JG		 405};
406
407struct radeon_framebuffer {
408 struct drm_framebuffer base;
409 struct drm_gem_object *obj;
410};
411
d79766fa
AD		 412extern enum radeon_tv_std
413radeon_combios_get_tv_info(struct radeon_device *rdev);
414extern enum radeon_tv_std
415radeon_atombios_get_tv_info(struct radeon_device *rdev);
416
d4877cf2
AD		 417extern void radeon_connector_hotplug(struct drm_connector *connector);
418extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
5801ead6
AD		 419extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
420 struct drm_display_mode *mode);
421extern void radeon_dp_set_link_config(struct drm_connector *connector,
422 struct drm_display_mode *mode);
423extern void dp_link_train(struct drm_encoder *encoder,
424 struct drm_connector *connector);
4143e919 425extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
9fa05c98 426extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
bcc1c2a1 427extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
5801ead6
AD		 428extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
429 int action, uint8_t lane_num,
430 uint8_t lane_set);
746c1aa4
DA		 431extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
432 uint8_t write_byte, uint8_t *read_byte);
433
434extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
6a93cb25
AD		 435 struct radeon_i2c_bus_rec *rec,
436 const char *name);
771fe6b9
JG		 437extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
438 struct radeon_i2c_bus_rec *rec,
439 const char *name);
440extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
5a6f98f5
AD		 441extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
442 u8 slave_addr,
443 u8 addr,
444 u8 *val);
445extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
446 u8 slave_addr,
447 u8 addr,
448 u8 val);
771fe6b9
JG		 449extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
450extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
451
452extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
453
454extern void radeon_compute_pll(struct radeon_pll *pll,
455 uint64_t freq,
456 uint32_t *dot_clock_p,
457 uint32_t *fb_div_p,
458 uint32_t *frac_fb_div_p,
459 uint32_t *ref_div_p,
fc10332b 460 uint32_t *post_div_p);
771fe6b9 461
1f3b6a45
DA		 462extern void radeon_setup_encoder_clones(struct drm_device *dev);
463
771fe6b9
JG		 464struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
465struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
466struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
467struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
468struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
469extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
32f48ffe 470extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
771fe6b9 471extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
4ce001ab 472extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
771fe6b9
JG		 473
474extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
475extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
476 struct drm_framebuffer *old_fb);
477extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
478 struct drm_display_mode *mode,
479 struct drm_display_mode *adjusted_mode,
480 int x, int y,
481 struct drm_framebuffer *old_fb);
482extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
483
484extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
485 struct drm_framebuffer *old_fb);
771fe6b9
JG		 486
487extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
488 struct drm_file *file_priv,
489 uint32_t handle,
490 uint32_t width,
491 uint32_t height);
492extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
493 int x, int y);
494
3c537889
AD		 495extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
496extern struct edid *
497radeon_combios_get_hardcoded_edid(struct radeon_device *rdev);
771fe6b9
JG		 498extern bool radeon_atom_get_clock_info(struct drm_device *dev);
499extern bool radeon_combios_get_clock_info(struct drm_device *dev);
500extern struct radeon_encoder_atom_dig *
501radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
fcec570b
AD		 502extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
503 struct radeon_encoder_int_tmds *tmds);
504extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
505 struct radeon_encoder_int_tmds *tmds);
506extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
507 struct radeon_encoder_int_tmds *tmds);
508extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
509 struct radeon_encoder_ext_tmds *tmds);
510extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
511 struct radeon_encoder_ext_tmds *tmds);
6fe7ac3f
AD		 512extern struct radeon_encoder_primary_dac *
513radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
514extern struct radeon_encoder_tv_dac *
515radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
771fe6b9
JG		 516extern struct radeon_encoder_lvds *
517radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
771fe6b9
JG		 518extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
519extern struct radeon_encoder_tv_dac *
520radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
521extern struct radeon_encoder_primary_dac *
522radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
fcec570b
AD		 523extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
524extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
771fe6b9
JG		 525extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
526extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
527extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
528extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
f657c2a7
YZ		 529extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
530extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
771fe6b9
JG		 531extern void
532radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
533extern void
534radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
535extern void
536radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
537extern void
538radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
539extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
540 u16 blue, int regno);
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DA		 541extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
542 u16 *blue, int regno);
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DA		 543void radeon_framebuffer_init(struct drm_device *dev,
544 struct radeon_framebuffer *rfb,
545 struct drm_mode_fb_cmd *mode_cmd,
546 struct drm_gem_object *obj);
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JG		 547
548int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
549bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
550bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
551void radeon_atombios_init_crtc(struct drm_device *dev,
552 struct radeon_crtc *radeon_crtc);
553void radeon_legacy_init_crtc(struct drm_device *dev,
554 struct radeon_crtc *radeon_crtc);
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JG		 555
556void radeon_get_clock_info(struct drm_device *dev);
557
558extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
559extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
560
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JG		 561void radeon_enc_destroy(struct drm_encoder *encoder);
562void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
563void radeon_combios_asic_init(struct drm_device *dev);
564extern int radeon_static_clocks_init(struct drm_device *dev);
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JG		 565bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
566 struct drm_display_mode *mode,
567 struct drm_display_mode *adjusted_mode);
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AD		 568void radeon_panel_mode_fixup(struct drm_encoder *encoder,
569 struct drm_display_mode *adjusted_mode);
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DA		 570void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
571
572/* legacy tv */
573void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
574 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
575 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
576void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
577 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
578 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
579void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
580 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
581 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
582void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
583 struct drm_display_mode *mode,
584 struct drm_display_mode *adjusted_mode);
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DA		 585
586/* fbdev layer */
587int radeon_fbdev_init(struct radeon_device *rdev);
588void radeon_fbdev_fini(struct radeon_device *rdev);
589void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
590int radeon_fbdev_total_size(struct radeon_device *rdev);
591bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
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DA		 592
593void radeon_fb_output_poll_changed(struct radeon_device *rdev);
771fe6b9 594#endif
Clone of davem's net-next-2.6 tree