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drm/radeon/kms: remove rv100 bios connector quirk
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06 52 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
771fe6b9
JG		 55
56/* from radeon_legacy_encoder.c */
57extern void
58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
60
61/* old legacy ATI BIOS routines */
62
63/* COMBIOS table offsets */
64enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
03047cdf
MD		 153 if (!rdev->bios)
154 return 0;
155
771fe6b9
JG		 156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325 if (check_offset)
326 offset = check_offset;
327 break;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
330 check_offset =
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332 if (check_offset) {
333 rev = RBIOS8(check_offset);
334 if (rev > 0) {
335 check_offset = RBIOS16(check_offset + 0x3);
336 if (check_offset)
337 offset = check_offset;
338 }
339 }
340 break;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344 if (check_offset) {
345 rev = RBIOS8(check_offset);
346 if (rev > 0) {
347 check_offset = RBIOS16(check_offset + 0x5);
348 if (check_offset)
349 offset = check_offset;
350 }
351 }
352 break;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356 if (check_offset) {
357 rev = RBIOS8(check_offset);
358 if (rev > 0) {
359 check_offset = RBIOS16(check_offset + 0x7);
360 if (check_offset)
361 offset = check_offset;
362 }
363 }
364 break;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
366 check_offset =
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368 if (check_offset) {
369 rev = RBIOS8(check_offset);
370 if (rev == 2) {
371 check_offset = RBIOS16(check_offset + 0x9);
372 if (check_offset)
373 offset = check_offset;
374 }
375 }
376 break;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
378 check_offset =
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380 if (check_offset) {
381 while (RBIOS8(check_offset++));
382 check_offset += 2;
383 if (check_offset)
384 offset = check_offset;
385 }
386 break;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
388 check_offset =
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390 if (check_offset) {
391 check_offset = RBIOS16(check_offset + 0x11);
392 if (check_offset)
393 offset = check_offset;
394 }
395 break;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
397 check_offset =
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399 if (check_offset) {
400 check_offset = RBIOS16(check_offset + 0x13);
401 if (check_offset)
402 offset = check_offset;
403 }
404 break;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
406 check_offset =
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408 if (check_offset) {
409 check_offset = RBIOS16(check_offset + 0x15);
410 if (check_offset)
411 offset = check_offset;
412 }
413 break;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
415 check_offset =
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417 if (check_offset) {
418 check_offset = RBIOS16(check_offset + 0x17);
419 if (check_offset)
420 offset = check_offset;
421 }
422 break;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
424 check_offset =
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426 if (check_offset) {
427 check_offset = RBIOS16(check_offset + 0x2);
428 if (check_offset)
429 offset = check_offset;
430 }
431 break;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
433 check_offset =
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435 if (check_offset) {
436 check_offset = RBIOS16(check_offset + 0x4);
437 if (check_offset)
438 offset = check_offset;
439 }
440 break;
441 default:
442 break;
443 }
444
445 return offset;
446
447}
448
3c537889
AD		 449bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450{
451 int edid_info;
452 struct edid *edid;
7466f4cc 453 unsigned char *raw;
3c537889
AD		 454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
455 if (!edid_info)
456 return false;
457
7466f4cc
AJ		 458 raw = rdev->bios + edid_info;
459 edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
3c537889
AD		 460 if (edid == NULL)
461 return false;
462
7466f4cc 463 memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
3c537889
AD		 464
465 if (!drm_edid_is_valid(edid)) {
466 kfree(edid);
467 return false;
468 }
469
470 rdev->mode_info.bios_hardcoded_edid = edid;
471 return true;
472}
473
474struct edid *
475radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
476{
477 if (rdev->mode_info.bios_hardcoded_edid)
478 return rdev->mode_info.bios_hardcoded_edid;
479 return NULL;
480}
481
6a93cb25
AD		 482static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
483 int ddc_line)
771fe6b9
JG		 484{
485 struct radeon_i2c_bus_rec i2c;
486
6a93cb25
AD		 487 if (ddc_line == RADEON_GPIOPAD_MASK) {
488 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
489 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
490 i2c.a_clk_reg = RADEON_GPIOPAD_A;
491 i2c.a_data_reg = RADEON_GPIOPAD_A;
492 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
493 i2c.en_data_reg = RADEON_GPIOPAD_EN;
494 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
495 i2c.y_data_reg = RADEON_GPIOPAD_Y;
496 } else if (ddc_line == RADEON_MDGPIO_MASK) {
497 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
498 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
499 i2c.a_clk_reg = RADEON_MDGPIO_A;
500 i2c.a_data_reg = RADEON_MDGPIO_A;
501 i2c.en_clk_reg = RADEON_MDGPIO_EN;
502 i2c.en_data_reg = RADEON_MDGPIO_EN;
503 i2c.y_clk_reg = RADEON_MDGPIO_Y;
504 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9 505 } else {
6a93cb25
AD		 506 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
507 i2c.mask_data_mask = RADEON_GPIO_EN_0;
508 i2c.a_clk_mask = RADEON_GPIO_A_1;
509 i2c.a_data_mask = RADEON_GPIO_A_0;
510 i2c.en_clk_mask = RADEON_GPIO_EN_1;
511 i2c.en_data_mask = RADEON_GPIO_EN_0;
512 i2c.y_clk_mask = RADEON_GPIO_Y_1;
513 i2c.y_data_mask = RADEON_GPIO_Y_0;
514
771fe6b9
JG		 515 i2c.mask_clk_reg = ddc_line;
516 i2c.mask_data_reg = ddc_line;
517 i2c.a_clk_reg = ddc_line;
518 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 519 i2c.en_clk_reg = ddc_line;
520 i2c.en_data_reg = ddc_line;
521 i2c.y_clk_reg = ddc_line;
522 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 523 }
524
40bacf16
AD		 525 switch (rdev->family) {
526 case CHIP_R100:
527 case CHIP_RV100:
528 case CHIP_RS100:
529 case CHIP_RV200:
530 case CHIP_RS200:
531 case CHIP_RS300:
532 switch (ddc_line) {
533 case RADEON_GPIO_DVI_DDC:
b28ea411 534 i2c.hw_capable = true;
40bacf16
AD		 535 break;
536 default:
537 i2c.hw_capable = false;
538 break;
539 }
540 break;
541 case CHIP_R200:
542 switch (ddc_line) {
543 case RADEON_GPIO_DVI_DDC:
544 case RADEON_GPIO_MONID:
545 i2c.hw_capable = true;
546 break;
547 default:
548 i2c.hw_capable = false;
549 break;
550 }
551 break;
552 case CHIP_RV250:
553 case CHIP_RV280:
554 switch (ddc_line) {
555 case RADEON_GPIO_VGA_DDC:
556 case RADEON_GPIO_DVI_DDC:
557 case RADEON_GPIO_CRT2_DDC:
558 i2c.hw_capable = true;
559 break;
560 default:
561 i2c.hw_capable = false;
562 break;
563 }
564 break;
565 case CHIP_R300:
566 case CHIP_R350:
567 switch (ddc_line) {
568 case RADEON_GPIO_VGA_DDC:
569 case RADEON_GPIO_DVI_DDC:
570 i2c.hw_capable = true;
571 break;
572 default:
573 i2c.hw_capable = false;
574 break;
575 }
576 break;
577 case CHIP_RV350:
578 case CHIP_RV380:
579 case CHIP_RS400:
580 case CHIP_RS480:
6a93cb25
AD		 581 switch (ddc_line) {
582 case RADEON_GPIO_VGA_DDC:
583 case RADEON_GPIO_DVI_DDC:
584 i2c.hw_capable = true;
585 break;
586 case RADEON_GPIO_MONID:
587 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
588 * reliably on some pre-r4xx hardware; not sure why.
589 */
590 i2c.hw_capable = false;
591 break;
592 default:
593 i2c.hw_capable = false;
594 break;
595 }
40bacf16
AD		 596 break;
597 default:
598 i2c.hw_capable = false;
599 break;
6a93cb25
AD		 600 }
601 i2c.mm_i2c = false;
602 i2c.i2c_id = 0;
8e36ed00 603 i2c.hpd = RADEON_HPD_NONE;
6a93cb25 604
771fe6b9
JG		 605 if (ddc_line)
606 i2c.valid = true;
607 else
608 i2c.valid = false;
609
610 return i2c;
611}
612
613bool radeon_combios_get_clock_info(struct drm_device *dev)
614{
615 struct radeon_device *rdev = dev->dev_private;
616 uint16_t pll_info;
617 struct radeon_pll *p1pll = &rdev->clock.p1pll;
618 struct radeon_pll *p2pll = &rdev->clock.p2pll;
619 struct radeon_pll *spll = &rdev->clock.spll;
620 struct radeon_pll *mpll = &rdev->clock.mpll;
621 int8_t rev;
622 uint16_t sclk, mclk;
623
771fe6b9
JG		 624 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
625 if (pll_info) {
626 rev = RBIOS8(pll_info);
627
628 /* pixel clocks */
629 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
630 p1pll->reference_div = RBIOS16(pll_info + 0x10);
631 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
632 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
86cb2bbf
AD		 633 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
634 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
771fe6b9
JG		 635
636 if (rev > 9) {
637 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
638 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
639 } else {
640 p1pll->pll_in_min = 40;
641 p1pll->pll_in_max = 500;
642 }
643 *p2pll = *p1pll;
644
645 /* system clock */
646 spll->reference_freq = RBIOS16(pll_info + 0x1a);
647 spll->reference_div = RBIOS16(pll_info + 0x1c);
648 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
649 spll->pll_out_max = RBIOS32(pll_info + 0x22);
650
651 if (rev > 10) {
652 spll->pll_in_min = RBIOS32(pll_info + 0x48);
653 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
654 } else {
655 /* ??? */
656 spll->pll_in_min = 40;
657 spll->pll_in_max = 500;
658 }
659
660 /* memory clock */
661 mpll->reference_freq = RBIOS16(pll_info + 0x26);
662 mpll->reference_div = RBIOS16(pll_info + 0x28);
663 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
664 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
665
666 if (rev > 10) {
667 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
668 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
669 } else {
670 /* ??? */
671 mpll->pll_in_min = 40;
672 mpll->pll_in_max = 500;
673 }
674
675 /* default sclk/mclk */
676 sclk = RBIOS16(pll_info + 0xa);
677 mclk = RBIOS16(pll_info + 0x8);
678 if (sclk == 0)
679 sclk = 200 * 100;
680 if (mclk == 0)
681 mclk = 200 * 100;
682
683 rdev->clock.default_sclk = sclk;
684 rdev->clock.default_mclk = mclk;
685
686 return true;
687 }
688 return false;
689}
690
06b6476d
AD		 691bool radeon_combios_sideport_present(struct radeon_device *rdev)
692{
693 struct drm_device *dev = rdev->ddev;
694 u16 igp_info;
695
696 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
697
698 if (igp_info) {
699 if (RBIOS16(igp_info + 0x4))
700 return true;
701 }
702 return false;
703}
704
246263cc
AD		 705static const uint32_t default_primarydac_adj[CHIP_LAST] = {
706 0x00000808, /* r100 */
707 0x00000808, /* rv100 */
708 0x00000808, /* rs100 */
709 0x00000808, /* rv200 */
710 0x00000808, /* rs200 */
711 0x00000808, /* r200 */
712 0x00000808, /* rv250 */
713 0x00000000, /* rs300 */
714 0x00000808, /* rv280 */
715 0x00000808, /* r300 */
716 0x00000808, /* r350 */
717 0x00000808, /* rv350 */
718 0x00000808, /* rv380 */
719 0x00000808, /* r420 */
720 0x00000808, /* r423 */
721 0x00000808, /* rv410 */
722 0x00000000, /* rs400 */
723 0x00000000, /* rs480 */
724};
725
726static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
727 struct radeon_encoder_primary_dac *p_dac)
728{
729 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
730 return;
731}
732
771fe6b9
JG		 733struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
734 radeon_encoder
735 *encoder)
736{
737 struct drm_device *dev = encoder->base.dev;
738 struct radeon_device *rdev = dev->dev_private;
739 uint16_t dac_info;
740 uint8_t rev, bg, dac;
741 struct radeon_encoder_primary_dac *p_dac = NULL;
246263cc 742 int found = 0;
771fe6b9 743
246263cc
AD		 744 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
745 GFP_KERNEL);
746
747 if (!p_dac)
771fe6b9
JG		 748 return NULL;
749
750 /* check CRT table */
751 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
752 if (dac_info) {
771fe6b9
JG		 753 rev = RBIOS8(dac_info) & 0x3;
754 if (rev < 2) {
755 bg = RBIOS8(dac_info + 0x2) & 0xf;
756 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
757 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
758 } else {
759 bg = RBIOS8(dac_info + 0x2) & 0xf;
760 dac = RBIOS8(dac_info + 0x3) & 0xf;
761 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
762 }
3a89b4a9
AD		 763 /* if the values are all zeros, use the table */
764 if (p_dac->ps2_pdac_adj)
765 found = 1;
771fe6b9
JG		 766 }
767
246263cc
AD		 768 if (!found) /* fallback to defaults */
769 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
770
771fe6b9
JG		 771 return p_dac;
772}
773
d79766fa
AD		 774enum radeon_tv_std
775radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 776{
d79766fa 777 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 778 uint16_t tv_info;
779 enum radeon_tv_std tv_std = TV_STD_NTSC;
780
781 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
782 if (tv_info) {
783 if (RBIOS8(tv_info + 6) == 'T') {
784 switch (RBIOS8(tv_info + 7) & 0xf) {
785 case 1:
786 tv_std = TV_STD_NTSC;
787 DRM_INFO("Default TV standard: NTSC\n");
788 break;
789 case 2:
790 tv_std = TV_STD_PAL;
791 DRM_INFO("Default TV standard: PAL\n");
792 break;
793 case 3:
794 tv_std = TV_STD_PAL_M;
795 DRM_INFO("Default TV standard: PAL-M\n");
796 break;
797 case 4:
798 tv_std = TV_STD_PAL_60;
799 DRM_INFO("Default TV standard: PAL-60\n");
800 break;
801 case 5:
802 tv_std = TV_STD_NTSC_J;
803 DRM_INFO("Default TV standard: NTSC-J\n");
804 break;
805 case 6:
806 tv_std = TV_STD_SCART_PAL;
807 DRM_INFO("Default TV standard: SCART-PAL\n");
808 break;
809 default:
810 tv_std = TV_STD_NTSC;
811 DRM_INFO
812 ("Unknown TV standard; defaulting to NTSC\n");
813 break;
814 }
815
816 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
817 case 0:
818 DRM_INFO("29.498928713 MHz TV ref clk\n");
819 break;
820 case 1:
821 DRM_INFO("28.636360000 MHz TV ref clk\n");
822 break;
823 case 2:
824 DRM_INFO("14.318180000 MHz TV ref clk\n");
825 break;
826 case 3:
827 DRM_INFO("27.000000000 MHz TV ref clk\n");
828 break;
829 default:
830 break;
831 }
832 }
833 }
834 return tv_std;
835}
836
837static const uint32_t default_tvdac_adj[CHIP_LAST] = {
838 0x00000000, /* r100 */
839 0x00280000, /* rv100 */
840 0x00000000, /* rs100 */
841 0x00880000, /* rv200 */
842 0x00000000, /* rs200 */
843 0x00000000, /* r200 */
844 0x00770000, /* rv250 */
845 0x00290000, /* rs300 */
846 0x00560000, /* rv280 */
847 0x00780000, /* r300 */
848 0x00770000, /* r350 */
849 0x00780000, /* rv350 */
850 0x00780000, /* rv380 */
851 0x01080000, /* r420 */
852 0x01080000, /* r423 */
853 0x01080000, /* rv410 */
854 0x00780000, /* rs400 */
855 0x00780000, /* rs480 */
856};
857
6a719e05
DA		 858static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
859 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 860{
771fe6b9
JG		 861 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
862 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
863 tv_dac->ps2_tvdac_adj = 0x00880000;
864 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
865 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 866 return;
771fe6b9
JG		 867}
868
869struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
870 radeon_encoder
871 *encoder)
872{
873 struct drm_device *dev = encoder->base.dev;
874 struct radeon_device *rdev = dev->dev_private;
875 uint16_t dac_info;
876 uint8_t rev, bg, dac;
877 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 878 int found = 0;
879
880 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
881 if (!tv_dac)
882 return NULL;
771fe6b9 883
771fe6b9
JG		 884 /* first check TV table */
885 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
886 if (dac_info) {
771fe6b9
JG		 887 rev = RBIOS8(dac_info + 0x3);
888 if (rev > 4) {
889 bg = RBIOS8(dac_info + 0xc) & 0xf;
890 dac = RBIOS8(dac_info + 0xd) & 0xf;
891 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
892
893 bg = RBIOS8(dac_info + 0xe) & 0xf;
894 dac = RBIOS8(dac_info + 0xf) & 0xf;
895 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
896
897 bg = RBIOS8(dac_info + 0x10) & 0xf;
898 dac = RBIOS8(dac_info + 0x11) & 0xf;
899 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 900 /* if the values are all zeros, use the table */
901 if (tv_dac->ps2_tvdac_adj)
902 found = 1;
771fe6b9
JG		 903 } else if (rev > 1) {
904 bg = RBIOS8(dac_info + 0xc) & 0xf;
905 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
906 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
907
908 bg = RBIOS8(dac_info + 0xd) & 0xf;
909 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
910 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
911
912 bg = RBIOS8(dac_info + 0xe) & 0xf;
913 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
914 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 915 /* if the values are all zeros, use the table */
916 if (tv_dac->ps2_tvdac_adj)
917 found = 1;
771fe6b9 918 }
d79766fa 919 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 920 }
921 if (!found) {
771fe6b9
JG		 922 /* then check CRT table */
923 dac_info =
924 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
925 if (dac_info) {
771fe6b9
JG		 926 rev = RBIOS8(dac_info) & 0x3;
927 if (rev < 2) {
928 bg = RBIOS8(dac_info + 0x3) & 0xf;
929 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
930 tv_dac->ps2_tvdac_adj =
931 (bg << 16) | (dac << 20);
932 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
933 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 934 /* if the values are all zeros, use the table */
935 if (tv_dac->ps2_tvdac_adj)
936 found = 1;
771fe6b9
JG		 937 } else {
938 bg = RBIOS8(dac_info + 0x4) & 0xf;
939 dac = RBIOS8(dac_info + 0x5) & 0xf;
940 tv_dac->ps2_tvdac_adj =
941 (bg << 16) | (dac << 20);
942 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
943 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 944 /* if the values are all zeros, use the table */
945 if (tv_dac->ps2_tvdac_adj)
946 found = 1;
771fe6b9 947 }
6fe7ac3f
AD		 948 } else {
949 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 950 }
951 }
952
6a719e05
DA		 953 if (!found) /* fallback to defaults */
954 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
955
771fe6b9
JG		 956 return tv_dac;
957}
958
959static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
960 radeon_device
961 *rdev)
962{
963 struct radeon_encoder_lvds *lvds = NULL;
964 uint32_t fp_vert_stretch, fp_horz_stretch;
965 uint32_t ppll_div_sel, ppll_val;
8b5c7444 966 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 967
968 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
969
970 if (!lvds)
971 return NULL;
972
973 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
974 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
975
8b5c7444
MD		 976 /* These should be fail-safe defaults, fingers crossed */
977 lvds->panel_pwr_delay = 200;
978 lvds->panel_vcc_delay = 2000;
979
980 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
981 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
982 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
983
771fe6b9 984 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 985 lvds->native_mode.vdisplay =
771fe6b9
JG		 986 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
987 RADEON_VERT_PANEL_SHIFT) + 1;
988 else
de2103e4 989 lvds->native_mode.vdisplay =
771fe6b9
JG		 990 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
991
992 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 993 lvds->native_mode.hdisplay =
771fe6b9
JG		 994 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
995 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
996 else
de2103e4 997 lvds->native_mode.hdisplay =
771fe6b9
JG		 998 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
999
de2103e4
AD		 1000 if ((lvds->native_mode.hdisplay < 640) ||
1001 (lvds->native_mode.vdisplay < 480)) {
1002 lvds->native_mode.hdisplay = 640;
1003 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 1004 }
1005
1006 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1007 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1008 if ((ppll_val & 0x000707ff) == 0x1bb)
1009 lvds->use_bios_dividers = false;
1010 else {
1011 lvds->panel_ref_divider =
1012 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1013 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1014 lvds->panel_fb_divider = ppll_val & 0x7ff;
1015
1016 if ((lvds->panel_ref_divider != 0) &&
1017 (lvds->panel_fb_divider > 3))
1018 lvds->use_bios_dividers = true;
1019 }
1020 lvds->panel_vcc_delay = 200;
1021
1022 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 1023 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1024 lvds->native_mode.vdisplay);
771fe6b9
JG		 1025
1026 return lvds;
1027}
1028
1029struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1030 *encoder)
1031{
1032 struct drm_device *dev = encoder->base.dev;
1033 struct radeon_device *rdev = dev->dev_private;
1034 uint16_t lcd_info;
1035 uint32_t panel_setup;
1036 char stmp[30];
1037 int tmp, i;
1038 struct radeon_encoder_lvds *lvds = NULL;
1039
771fe6b9
JG		 1040 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1041
1042 if (lcd_info) {
1043 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1044
1045 if (!lvds)
1046 return NULL;
1047
1048 for (i = 0; i < 24; i++)
1049 stmp[i] = RBIOS8(lcd_info + i + 1);
1050 stmp[24] = 0;
1051
1052 DRM_INFO("Panel ID String: %s\n", stmp);
1053
de2103e4
AD		 1054 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1055 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 1056
de2103e4
AD		 1057 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1058 lvds->native_mode.vdisplay);
771fe6b9
JG		 1059
1060 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
94cf6434 1061 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
771fe6b9
JG		 1062
1063 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1064 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1065 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1066
1067 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1068 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1069 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1070 if ((lvds->panel_ref_divider != 0) &&
1071 (lvds->panel_fb_divider > 3))
1072 lvds->use_bios_dividers = true;
1073
1074 panel_setup = RBIOS32(lcd_info + 0x39);
1075 lvds->lvds_gen_cntl = 0xff00;
1076 if (panel_setup & 0x1)
1077 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1078
1079 if ((panel_setup >> 4) & 0x1)
1080 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1081
1082 switch ((panel_setup >> 8) & 0x7) {
1083 case 0:
1084 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1085 break;
1086 case 1:
1087 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1088 break;
1089 case 2:
1090 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1091 break;
1092 default:
1093 break;
1094 }
1095
1096 if ((panel_setup >> 16) & 0x1)
1097 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1098
1099 if ((panel_setup >> 17) & 0x1)
1100 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1101
1102 if ((panel_setup >> 18) & 0x1)
1103 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1104
1105 if ((panel_setup >> 23) & 0x1)
1106 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1107
1108 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1109
1110 for (i = 0; i < 32; i++) {
1111 tmp = RBIOS16(lcd_info + 64 + i * 2);
1112 if (tmp == 0)
1113 break;
1114
de2103e4 1115 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
68b61a7f
AD		 1116 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1117 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1118 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1119 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1120 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1121 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1122 (RBIOS8(tmp + 23) * 8);
1123
1124 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1125 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1126 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1127 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1128 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1129 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
de2103e4
AD		 1130
1131 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1132 lvds->native_mode.flags = 0;
de2103e4
AD		 1133 /* set crtc values */
1134 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1135
771fe6b9
JG		 1136 }
1137 }
6fe7ac3f 1138 } else {
771fe6b9 1139 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1140 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1141 }
03047cdf 1142
8dfaa8a7
MD		 1143 if (lvds)
1144 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1145 return lvds;
1146}
1147
1148static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1149 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1150 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1151 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1152 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1153 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1154 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1155 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1156 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1157 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1158 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1159 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1160 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1161 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1162 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1163 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1164 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1165 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1166 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1167};
1168
445282db
DA		 1169bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1170 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1171{
445282db
DA		 1172 struct drm_device *dev = encoder->base.dev;
1173 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1174 int i;
771fe6b9
JG		 1175
1176 for (i = 0; i < 4; i++) {
1177 tmds->tmds_pll[i].value =
445282db 1178 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1179 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1180 }
1181
445282db 1182 return true;
771fe6b9
JG		 1183}
1184
445282db
DA		 1185bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1186 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1187{
1188 struct drm_device *dev = encoder->base.dev;
1189 struct radeon_device *rdev = dev->dev_private;
1190 uint16_t tmds_info;
1191 int i, n;
1192 uint8_t ver;
771fe6b9 1193
771fe6b9
JG		 1194 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1195
1196 if (tmds_info) {
771fe6b9
JG		 1197 ver = RBIOS8(tmds_info);
1198 DRM_INFO("DFP table revision: %d\n", ver);
1199 if (ver == 3) {
1200 n = RBIOS8(tmds_info + 5) + 1;
1201 if (n > 4)
1202 n = 4;
1203 for (i = 0; i < n; i++) {
1204 tmds->tmds_pll[i].value =
1205 RBIOS32(tmds_info + i * 10 + 0x08);
1206 tmds->tmds_pll[i].freq =
1207 RBIOS16(tmds_info + i * 10 + 0x10);
1208 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1209 tmds->tmds_pll[i].freq,
1210 tmds->tmds_pll[i].value);
1211 }
1212 } else if (ver == 4) {
1213 int stride = 0;
1214 n = RBIOS8(tmds_info + 5) + 1;
1215 if (n > 4)
1216 n = 4;
1217 for (i = 0; i < n; i++) {
1218 tmds->tmds_pll[i].value =
1219 RBIOS32(tmds_info + stride + 0x08);
1220 tmds->tmds_pll[i].freq =
1221 RBIOS16(tmds_info + stride + 0x10);
1222 if (i == 0)
1223 stride += 10;
1224 else
1225 stride += 6;
1226 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1227 tmds->tmds_pll[i].freq,
1228 tmds->tmds_pll[i].value);
1229 }
1230 }
fcec570b 1231 } else {
771fe6b9 1232 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1233 return false;
1234 }
445282db
DA		 1235 return true;
1236}
1237
fcec570b
AD		 1238bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1239 struct radeon_encoder_ext_tmds *tmds)
445282db 1240{
fcec570b
AD		 1241 struct drm_device *dev = encoder->base.dev;
1242 struct radeon_device *rdev = dev->dev_private;
1243 struct radeon_i2c_bus_rec i2c_bus;
445282db 1244
fcec570b 1245 /* default for macs */
6a93cb25 1246 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1247 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
445282db 1248
fcec570b
AD		 1249 /* XXX some macs have duallink chips */
1250 switch (rdev->mode_info.connector_table) {
1251 case CT_POWERBOOK_EXTERNAL:
1252 case CT_MINI_EXTERNAL:
1253 default:
1254 tmds->dvo_chip = DVO_SIL164;
1255 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1256 break;
1257 }
445282db 1258
fcec570b 1259 return true;
771fe6b9
JG		 1260}
1261
fcec570b
AD		 1262bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1263 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1264{
1265 struct drm_device *dev = encoder->base.dev;
1266 struct radeon_device *rdev = dev->dev_private;
fcec570b
AD		 1267 uint16_t offset;
1268 uint8_t ver, id, blocks, clk, data;
1269 int i;
1270 enum radeon_combios_ddc gpio;
1271 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1272
fcec570b
AD		 1273 tmds->i2c_bus = NULL;
1274 if (rdev->flags & RADEON_IS_IGP) {
1275 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1276 if (offset) {
1277 ver = RBIOS8(offset);
1278 DRM_INFO("GPIO Table revision: %d\n", ver);
1279 blocks = RBIOS8(offset + 2);
1280 for (i = 0; i < blocks; i++) {
1281 id = RBIOS8(offset + 3 + (i * 5) + 0);
1282 if (id == 136) {
1283 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1284 data = RBIOS8(offset + 3 + (i * 5) + 4);
1285 i2c_bus.valid = true;
1286 i2c_bus.mask_clk_mask = (1 << clk);
1287 i2c_bus.mask_data_mask = (1 << data);
1288 i2c_bus.a_clk_mask = (1 << clk);
1289 i2c_bus.a_data_mask = (1 << data);
1290 i2c_bus.en_clk_mask = (1 << clk);
1291 i2c_bus.en_data_mask = (1 << data);
1292 i2c_bus.y_clk_mask = (1 << clk);
1293 i2c_bus.y_data_mask = (1 << data);
1294 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1295 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1296 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1297 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1298 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1299 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1300 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1301 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1302 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1303 tmds->dvo_chip = DVO_SIL164;
1304 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1305 break;
1306 }
1307 }
1308 }
1309 } else {
1310 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1311 if (offset) {
1312 ver = RBIOS8(offset);
1313 DRM_INFO("External TMDS Table revision: %d\n", ver);
1314 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1315 tmds->slave_addr >>= 1; /* 7 bit addressing */
1316 gpio = RBIOS8(offset + 4 + 3);
1317 switch (gpio) {
1318 case DDC_MONID:
6a93cb25 1319 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b
AD		 1320 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1321 break;
1322 case DDC_DVI:
6a93cb25 1323 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b
AD		 1324 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1325 break;
1326 case DDC_VGA:
6a93cb25 1327 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
fcec570b
AD		 1328 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1329 break;
1330 case DDC_CRT2:
1331 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1332 if (rdev->family >= CHIP_R300)
6a93cb25 1333 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1334 else
6a93cb25 1335 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
fcec570b
AD		 1336 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1337 break;
1338 case DDC_LCD: /* MM i2c */
40bacf16
AD		 1339 i2c_bus.valid = true;
1340 i2c_bus.hw_capable = true;
1341 i2c_bus.mm_i2c = true;
1342 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
fcec570b
AD		 1343 break;
1344 default:
1345 DRM_ERROR("Unsupported gpio %d\n", gpio);
1346 break;
1347 }
1348 }
771fe6b9 1349 }
fcec570b
AD		 1350
1351 if (!tmds->i2c_bus) {
1352 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1353 return false;
1354 }
1355
1356 return true;
771fe6b9
JG		 1357}
1358
1359bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1360{
1361 struct radeon_device *rdev = dev->dev_private;
1362 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1363 struct radeon_hpd hpd;
771fe6b9
JG		 1364
1365 rdev->mode_info.connector_table = radeon_connector_table;
1366 if (rdev->mode_info.connector_table == CT_NONE) {
1367#ifdef CONFIG_PPC_PMAC
71a157e8 1368 if (of_machine_is_compatible("PowerBook3,3")) {
771fe6b9
JG		 1369 /* powerbook with VGA */
1370 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
71a157e8
GL		 1371 } else if (of_machine_is_compatible("PowerBook3,4") ||
1372 of_machine_is_compatible("PowerBook3,5")) {
771fe6b9
JG		 1373 /* powerbook with internal tmds */
1374 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
71a157e8
GL		 1375 } else if (of_machine_is_compatible("PowerBook5,1") ||
1376 of_machine_is_compatible("PowerBook5,2") ||
1377 of_machine_is_compatible("PowerBook5,3") ||
1378 of_machine_is_compatible("PowerBook5,4") ||
1379 of_machine_is_compatible("PowerBook5,5")) {
771fe6b9
JG		 1380 /* powerbook with external single link tmds (sil164) */
1381 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8 1382 } else if (of_machine_is_compatible("PowerBook5,6")) {
771fe6b9
JG		 1383 /* powerbook with external dual or single link tmds */
1384 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1385 } else if (of_machine_is_compatible("PowerBook5,7") ||
1386 of_machine_is_compatible("PowerBook5,8") ||
1387 of_machine_is_compatible("PowerBook5,9")) {
771fe6b9
JG		 1388 /* PowerBook6,2 ? */
1389 /* powerbook with external dual link tmds (sil1178?) */
1390 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1391 } else if (of_machine_is_compatible("PowerBook4,1") ||
1392 of_machine_is_compatible("PowerBook4,2") ||
1393 of_machine_is_compatible("PowerBook4,3") ||
1394 of_machine_is_compatible("PowerBook6,3") ||
1395 of_machine_is_compatible("PowerBook6,5") ||
1396 of_machine_is_compatible("PowerBook6,7")) {
771fe6b9
JG		 1397 /* ibook */
1398 rdev->mode_info.connector_table = CT_IBOOK;
71a157e8 1399 } else if (of_machine_is_compatible("PowerMac4,4")) {
771fe6b9
JG		 1400 /* emac */
1401 rdev->mode_info.connector_table = CT_EMAC;
71a157e8 1402 } else if (of_machine_is_compatible("PowerMac10,1")) {
771fe6b9
JG		 1403 /* mini with internal tmds */
1404 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
71a157e8 1405 } else if (of_machine_is_compatible("PowerMac10,2")) {
771fe6b9
JG		 1406 /* mini with external tmds */
1407 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
71a157e8 1408 } else if (of_machine_is_compatible("PowerMac12,1")) {
771fe6b9
JG		 1409 /* PowerMac8,1 ? */
1410 /* imac g5 isight */
1411 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1412 } else
1413#endif /* CONFIG_PPC_PMAC */
76a7142a
DA		 1414#ifdef CONFIG_PPC64
1415 if (ASIC_IS_RN50(rdev))
1416 rdev->mode_info.connector_table = CT_RN50_POWER;
1417 else
1418#endif
771fe6b9
JG		 1419 rdev->mode_info.connector_table = CT_GENERIC;
1420 }
1421
1422 switch (rdev->mode_info.connector_table) {
1423 case CT_GENERIC:
1424 DRM_INFO("Connector Table: %d (generic)\n",
1425 rdev->mode_info.connector_table);
1426 /* these are the most common settings */
1427 if (rdev->flags & RADEON_SINGLE_CRTC) {
1428 /* VGA - primary dac */
6a93cb25 1429 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1430 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1431 radeon_add_legacy_encoder(dev,
1432 radeon_get_encoder_id(dev,
1433 ATOM_DEVICE_CRT1_SUPPORT,
1434 1),
1435 ATOM_DEVICE_CRT1_SUPPORT);
1436 radeon_add_legacy_connector(dev, 0,
1437 ATOM_DEVICE_CRT1_SUPPORT,
1438 DRM_MODE_CONNECTOR_VGA,
b75fad06 1439 &ddc_i2c,
eed45b30
AD		 1440 CONNECTOR_OBJECT_ID_VGA,
1441 &hpd);
771fe6b9
JG		 1442 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1443 /* LVDS */
6a93cb25 1444 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
eed45b30 1445 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1446 radeon_add_legacy_encoder(dev,
1447 radeon_get_encoder_id(dev,
1448 ATOM_DEVICE_LCD1_SUPPORT,
1449 0),
1450 ATOM_DEVICE_LCD1_SUPPORT);
1451 radeon_add_legacy_connector(dev, 0,
1452 ATOM_DEVICE_LCD1_SUPPORT,
1453 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1454 &ddc_i2c,
eed45b30
AD		 1455 CONNECTOR_OBJECT_ID_LVDS,
1456 &hpd);
771fe6b9
JG		 1457
1458 /* VGA - primary dac */
6a93cb25 1459 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1460 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1461 radeon_add_legacy_encoder(dev,
1462 radeon_get_encoder_id(dev,
1463 ATOM_DEVICE_CRT1_SUPPORT,
1464 1),
1465 ATOM_DEVICE_CRT1_SUPPORT);
1466 radeon_add_legacy_connector(dev, 1,
1467 ATOM_DEVICE_CRT1_SUPPORT,
1468 DRM_MODE_CONNECTOR_VGA,
b75fad06 1469 &ddc_i2c,
eed45b30
AD		 1470 CONNECTOR_OBJECT_ID_VGA,
1471 &hpd);
771fe6b9
JG		 1472 } else {
1473 /* DVI-I - tv dac, int tmds */
6a93cb25 1474 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1475 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 1476 radeon_add_legacy_encoder(dev,
1477 radeon_get_encoder_id(dev,
1478 ATOM_DEVICE_DFP1_SUPPORT,
1479 0),
1480 ATOM_DEVICE_DFP1_SUPPORT);
1481 radeon_add_legacy_encoder(dev,
1482 radeon_get_encoder_id(dev,
1483 ATOM_DEVICE_CRT2_SUPPORT,
1484 2),
1485 ATOM_DEVICE_CRT2_SUPPORT);
1486 radeon_add_legacy_connector(dev, 0,
1487 ATOM_DEVICE_DFP1_SUPPORT |
1488 ATOM_DEVICE_CRT2_SUPPORT,
1489 DRM_MODE_CONNECTOR_DVII,
b75fad06 1490 &ddc_i2c,
eed45b30
AD		 1491 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1492 &hpd);
771fe6b9
JG		 1493
1494 /* VGA - primary dac */
6a93cb25 1495 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1496 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1497 radeon_add_legacy_encoder(dev,
1498 radeon_get_encoder_id(dev,
1499 ATOM_DEVICE_CRT1_SUPPORT,
1500 1),
1501 ATOM_DEVICE_CRT1_SUPPORT);
1502 radeon_add_legacy_connector(dev, 1,
1503 ATOM_DEVICE_CRT1_SUPPORT,
1504 DRM_MODE_CONNECTOR_VGA,
b75fad06 1505 &ddc_i2c,
eed45b30
AD		 1506 CONNECTOR_OBJECT_ID_VGA,
1507 &hpd);
771fe6b9
JG		 1508 }
1509
1510 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1511 /* TV - tv dac */
eed45b30
AD		 1512 ddc_i2c.valid = false;
1513 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1514 radeon_add_legacy_encoder(dev,
1515 radeon_get_encoder_id(dev,
1516 ATOM_DEVICE_TV1_SUPPORT,
1517 2),
1518 ATOM_DEVICE_TV1_SUPPORT);
1519 radeon_add_legacy_connector(dev, 2,
1520 ATOM_DEVICE_TV1_SUPPORT,
1521 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1522 &ddc_i2c,
eed45b30
AD		 1523 CONNECTOR_OBJECT_ID_SVIDEO,
1524 &hpd);
771fe6b9
JG		 1525 }
1526 break;
1527 case CT_IBOOK:
1528 DRM_INFO("Connector Table: %d (ibook)\n",
1529 rdev->mode_info.connector_table);
1530 /* LVDS */
6a93cb25 1531 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1532 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1533 radeon_add_legacy_encoder(dev,
1534 radeon_get_encoder_id(dev,
1535 ATOM_DEVICE_LCD1_SUPPORT,
1536 0),
1537 ATOM_DEVICE_LCD1_SUPPORT);
1538 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1539 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1540 CONNECTOR_OBJECT_ID_LVDS,
1541 &hpd);
771fe6b9 1542 /* VGA - TV DAC */
6a93cb25 1543 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1544 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1545 radeon_add_legacy_encoder(dev,
1546 radeon_get_encoder_id(dev,
1547 ATOM_DEVICE_CRT2_SUPPORT,
1548 2),
1549 ATOM_DEVICE_CRT2_SUPPORT);
1550 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1551 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1552 CONNECTOR_OBJECT_ID_VGA,
1553 &hpd);
771fe6b9 1554 /* TV - TV DAC */
eed45b30
AD		 1555 ddc_i2c.valid = false;
1556 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1557 radeon_add_legacy_encoder(dev,
1558 radeon_get_encoder_id(dev,
1559 ATOM_DEVICE_TV1_SUPPORT,
1560 2),
1561 ATOM_DEVICE_TV1_SUPPORT);
1562 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1563 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1564 &ddc_i2c,
eed45b30
AD		 1565 CONNECTOR_OBJECT_ID_SVIDEO,
1566 &hpd);
771fe6b9
JG		 1567 break;
1568 case CT_POWERBOOK_EXTERNAL:
1569 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1570 rdev->mode_info.connector_table);
1571 /* LVDS */
6a93cb25 1572 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1573 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1574 radeon_add_legacy_encoder(dev,
1575 radeon_get_encoder_id(dev,
1576 ATOM_DEVICE_LCD1_SUPPORT,
1577 0),
1578 ATOM_DEVICE_LCD1_SUPPORT);
1579 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1580 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1581 CONNECTOR_OBJECT_ID_LVDS,
1582 &hpd);
771fe6b9 1583 /* DVI-I - primary dac, ext tmds */
6a93cb25 1584 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1585 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1586 radeon_add_legacy_encoder(dev,
1587 radeon_get_encoder_id(dev,
1588 ATOM_DEVICE_DFP2_SUPPORT,
1589 0),
1590 ATOM_DEVICE_DFP2_SUPPORT);
1591 radeon_add_legacy_encoder(dev,
1592 radeon_get_encoder_id(dev,
1593 ATOM_DEVICE_CRT1_SUPPORT,
1594 1),
1595 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1596 /* XXX some are SL */
771fe6b9
JG		 1597 radeon_add_legacy_connector(dev, 1,
1598 ATOM_DEVICE_DFP2_SUPPORT |
1599 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1600 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1601 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1602 &hpd);
771fe6b9 1603 /* TV - TV DAC */
eed45b30
AD		 1604 ddc_i2c.valid = false;
1605 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1606 radeon_add_legacy_encoder(dev,
1607 radeon_get_encoder_id(dev,
1608 ATOM_DEVICE_TV1_SUPPORT,
1609 2),
1610 ATOM_DEVICE_TV1_SUPPORT);
1611 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1612 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1613 &ddc_i2c,
eed45b30
AD		 1614 CONNECTOR_OBJECT_ID_SVIDEO,
1615 &hpd);
771fe6b9
JG		 1616 break;
1617 case CT_POWERBOOK_INTERNAL:
1618 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1619 rdev->mode_info.connector_table);
1620 /* LVDS */
6a93cb25 1621 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1622 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1623 radeon_add_legacy_encoder(dev,
1624 radeon_get_encoder_id(dev,
1625 ATOM_DEVICE_LCD1_SUPPORT,
1626 0),
1627 ATOM_DEVICE_LCD1_SUPPORT);
1628 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1629 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1630 CONNECTOR_OBJECT_ID_LVDS,
1631 &hpd);
771fe6b9 1632 /* DVI-I - primary dac, int tmds */
6a93cb25 1633 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1634 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1635 radeon_add_legacy_encoder(dev,
1636 radeon_get_encoder_id(dev,
1637 ATOM_DEVICE_DFP1_SUPPORT,
1638 0),
1639 ATOM_DEVICE_DFP1_SUPPORT);
1640 radeon_add_legacy_encoder(dev,
1641 radeon_get_encoder_id(dev,
1642 ATOM_DEVICE_CRT1_SUPPORT,
1643 1),
1644 ATOM_DEVICE_CRT1_SUPPORT);
1645 radeon_add_legacy_connector(dev, 1,
1646 ATOM_DEVICE_DFP1_SUPPORT |
1647 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1648 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1649 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1650 &hpd);
771fe6b9 1651 /* TV - TV DAC */
eed45b30
AD		 1652 ddc_i2c.valid = false;
1653 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1654 radeon_add_legacy_encoder(dev,
1655 radeon_get_encoder_id(dev,
1656 ATOM_DEVICE_TV1_SUPPORT,
1657 2),
1658 ATOM_DEVICE_TV1_SUPPORT);
1659 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1660 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1661 &ddc_i2c,
eed45b30
AD		 1662 CONNECTOR_OBJECT_ID_SVIDEO,
1663 &hpd);
771fe6b9
JG		 1664 break;
1665 case CT_POWERBOOK_VGA:
1666 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1667 rdev->mode_info.connector_table);
1668 /* LVDS */
6a93cb25 1669 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1670 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1671 radeon_add_legacy_encoder(dev,
1672 radeon_get_encoder_id(dev,
1673 ATOM_DEVICE_LCD1_SUPPORT,
1674 0),
1675 ATOM_DEVICE_LCD1_SUPPORT);
1676 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1677 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1678 CONNECTOR_OBJECT_ID_LVDS,
1679 &hpd);
771fe6b9 1680 /* VGA - primary dac */
6a93cb25 1681 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1682 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1683 radeon_add_legacy_encoder(dev,
1684 radeon_get_encoder_id(dev,
1685 ATOM_DEVICE_CRT1_SUPPORT,
1686 1),
1687 ATOM_DEVICE_CRT1_SUPPORT);
1688 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1689 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1690 CONNECTOR_OBJECT_ID_VGA,
1691 &hpd);
771fe6b9 1692 /* TV - TV DAC */
eed45b30
AD		 1693 ddc_i2c.valid = false;
1694 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1695 radeon_add_legacy_encoder(dev,
1696 radeon_get_encoder_id(dev,
1697 ATOM_DEVICE_TV1_SUPPORT,
1698 2),
1699 ATOM_DEVICE_TV1_SUPPORT);
1700 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1701 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1702 &ddc_i2c,
eed45b30
AD		 1703 CONNECTOR_OBJECT_ID_SVIDEO,
1704 &hpd);
771fe6b9
JG		 1705 break;
1706 case CT_MINI_EXTERNAL:
1707 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1708 rdev->mode_info.connector_table);
1709 /* DVI-I - tv dac, ext tmds */
6a93cb25 1710 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1711 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1712 radeon_add_legacy_encoder(dev,
1713 radeon_get_encoder_id(dev,
1714 ATOM_DEVICE_DFP2_SUPPORT,
1715 0),
1716 ATOM_DEVICE_DFP2_SUPPORT);
1717 radeon_add_legacy_encoder(dev,
1718 radeon_get_encoder_id(dev,
1719 ATOM_DEVICE_CRT2_SUPPORT,
1720 2),
1721 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1722 /* XXX are any DL? */
771fe6b9
JG		 1723 radeon_add_legacy_connector(dev, 0,
1724 ATOM_DEVICE_DFP2_SUPPORT |
1725 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1726 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1727 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1728 &hpd);
771fe6b9 1729 /* TV - TV DAC */
eed45b30
AD		 1730 ddc_i2c.valid = false;
1731 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1732 radeon_add_legacy_encoder(dev,
1733 radeon_get_encoder_id(dev,
1734 ATOM_DEVICE_TV1_SUPPORT,
1735 2),
1736 ATOM_DEVICE_TV1_SUPPORT);
1737 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1738 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1739 &ddc_i2c,
eed45b30
AD		 1740 CONNECTOR_OBJECT_ID_SVIDEO,
1741 &hpd);
771fe6b9
JG		 1742 break;
1743 case CT_MINI_INTERNAL:
1744 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1745 rdev->mode_info.connector_table);
1746 /* DVI-I - tv dac, int tmds */
6a93cb25 1747 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1748 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1749 radeon_add_legacy_encoder(dev,
1750 radeon_get_encoder_id(dev,
1751 ATOM_DEVICE_DFP1_SUPPORT,
1752 0),
1753 ATOM_DEVICE_DFP1_SUPPORT);
1754 radeon_add_legacy_encoder(dev,
1755 radeon_get_encoder_id(dev,
1756 ATOM_DEVICE_CRT2_SUPPORT,
1757 2),
1758 ATOM_DEVICE_CRT2_SUPPORT);
1759 radeon_add_legacy_connector(dev, 0,
1760 ATOM_DEVICE_DFP1_SUPPORT |
1761 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1762 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1763 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1764 &hpd);
771fe6b9 1765 /* TV - TV DAC */
eed45b30
AD		 1766 ddc_i2c.valid = false;
1767 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1768 radeon_add_legacy_encoder(dev,
1769 radeon_get_encoder_id(dev,
1770 ATOM_DEVICE_TV1_SUPPORT,
1771 2),
1772 ATOM_DEVICE_TV1_SUPPORT);
1773 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1774 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1775 &ddc_i2c,
eed45b30
AD		 1776 CONNECTOR_OBJECT_ID_SVIDEO,
1777 &hpd);
771fe6b9
JG		 1778 break;
1779 case CT_IMAC_G5_ISIGHT:
1780 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1781 rdev->mode_info.connector_table);
1782 /* DVI-D - int tmds */
6a93cb25 1783 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
eed45b30 1784 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1785 radeon_add_legacy_encoder(dev,
1786 radeon_get_encoder_id(dev,
1787 ATOM_DEVICE_DFP1_SUPPORT,
1788 0),
1789 ATOM_DEVICE_DFP1_SUPPORT);
1790 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1791 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1792 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1793 &hpd);
771fe6b9 1794 /* VGA - tv dac */
6a93cb25 1795 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1796 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1797 radeon_add_legacy_encoder(dev,
1798 radeon_get_encoder_id(dev,
1799 ATOM_DEVICE_CRT2_SUPPORT,
1800 2),
1801 ATOM_DEVICE_CRT2_SUPPORT);
1802 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1803 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1804 CONNECTOR_OBJECT_ID_VGA,
1805 &hpd);
771fe6b9 1806 /* TV - TV DAC */
eed45b30
AD		 1807 ddc_i2c.valid = false;
1808 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1809 radeon_add_legacy_encoder(dev,
1810 radeon_get_encoder_id(dev,
1811 ATOM_DEVICE_TV1_SUPPORT,
1812 2),
1813 ATOM_DEVICE_TV1_SUPPORT);
1814 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1815 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1816 &ddc_i2c,
eed45b30
AD		 1817 CONNECTOR_OBJECT_ID_SVIDEO,
1818 &hpd);
771fe6b9
JG		 1819 break;
1820 case CT_EMAC:
1821 DRM_INFO("Connector Table: %d (emac)\n",
1822 rdev->mode_info.connector_table);
1823 /* VGA - primary dac */
6a93cb25 1824 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1825 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1826 radeon_add_legacy_encoder(dev,
1827 radeon_get_encoder_id(dev,
1828 ATOM_DEVICE_CRT1_SUPPORT,
1829 1),
1830 ATOM_DEVICE_CRT1_SUPPORT);
1831 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1832 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1833 CONNECTOR_OBJECT_ID_VGA,
1834 &hpd);
771fe6b9 1835 /* VGA - tv dac */
6a93cb25 1836 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1837 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1838 radeon_add_legacy_encoder(dev,
1839 radeon_get_encoder_id(dev,
1840 ATOM_DEVICE_CRT2_SUPPORT,
1841 2),
1842 ATOM_DEVICE_CRT2_SUPPORT);
1843 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1844 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1845 CONNECTOR_OBJECT_ID_VGA,
1846 &hpd);
771fe6b9 1847 /* TV - TV DAC */
eed45b30
AD		 1848 ddc_i2c.valid = false;
1849 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1850 radeon_add_legacy_encoder(dev,
1851 radeon_get_encoder_id(dev,
1852 ATOM_DEVICE_TV1_SUPPORT,
1853 2),
1854 ATOM_DEVICE_TV1_SUPPORT);
1855 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1856 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1857 &ddc_i2c,
eed45b30
AD		 1858 CONNECTOR_OBJECT_ID_SVIDEO,
1859 &hpd);
771fe6b9 1860 break;
76a7142a
DA		 1861 case CT_RN50_POWER:
1862 DRM_INFO("Connector Table: %d (rn50-power)\n",
1863 rdev->mode_info.connector_table);
1864 /* VGA - primary dac */
1865 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1866 hpd.hpd = RADEON_HPD_NONE;
1867 radeon_add_legacy_encoder(dev,
1868 radeon_get_encoder_id(dev,
1869 ATOM_DEVICE_CRT1_SUPPORT,
1870 1),
1871 ATOM_DEVICE_CRT1_SUPPORT);
1872 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1873 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1874 CONNECTOR_OBJECT_ID_VGA,
1875 &hpd);
1876 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1877 hpd.hpd = RADEON_HPD_NONE;
1878 radeon_add_legacy_encoder(dev,
1879 radeon_get_encoder_id(dev,
1880 ATOM_DEVICE_CRT2_SUPPORT,
1881 2),
1882 ATOM_DEVICE_CRT2_SUPPORT);
1883 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1884 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1885 CONNECTOR_OBJECT_ID_VGA,
1886 &hpd);
1887 break;
771fe6b9
JG		 1888 default:
1889 DRM_INFO("Connector table: %d (invalid)\n",
1890 rdev->mode_info.connector_table);
1891 return false;
1892 }
1893
1894 radeon_link_encoder_connector(dev);
1895
1896 return true;
1897}
1898
1899static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1900 int bios_index,
1901 enum radeon_combios_connector
1902 *legacy_connector,
eed45b30
AD		 1903 struct radeon_i2c_bus_rec *ddc_i2c,
1904 struct radeon_hpd *hpd)
771fe6b9
JG		 1905{
1906 struct radeon_device *rdev = dev->dev_private;
1907
1908 /* XPRESS DDC quirks */
1909 if ((rdev->family == CHIP_RS400 ||
1910 rdev->family == CHIP_RS480) &&
1911 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1912 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 1913 else if ((rdev->family == CHIP_RS400 ||
1914 rdev->family == CHIP_RS480) &&
1915 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
6a93cb25 1916 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 1917 ddc_i2c->mask_clk_mask = (0x20 << 8);
1918 ddc_i2c->mask_data_mask = 0x80;
1919 ddc_i2c->a_clk_mask = (0x20 << 8);
1920 ddc_i2c->a_data_mask = 0x80;
9b9fe724
AD		 1921 ddc_i2c->en_clk_mask = (0x20 << 8);
1922 ddc_i2c->en_data_mask = 0x80;
1923 ddc_i2c->y_clk_mask = (0x20 << 8);
1924 ddc_i2c->y_data_mask = 0x80;
771fe6b9
JG		 1925 }
1926
fcec570b
AD		 1927 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1928 if ((rdev->family >= CHIP_R300) &&
1929 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1930 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b 1931
771fe6b9
JG		 1932 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1933 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1934 if (dev->pdev->device == 0x515e &&
1935 dev->pdev->subsystem_vendor == 0x1014) {
1936 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1937 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1938 return false;
1939 }
1940
771fe6b9
JG		 1941 /* X300 card with extra non-existent DVI port */
1942 if (dev->pdev->device == 0x5B60 &&
1943 dev->pdev->subsystem_vendor == 0x17af &&
1944 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1945 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1946 return false;
1947 }
1948
1949 return true;
1950}
1951
790cfb34
AD		 1952static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1953{
1954 /* Acer 5102 has non-existent TV port */
1955 if (dev->pdev->device == 0x5975 &&
1956 dev->pdev->subsystem_vendor == 0x1025 &&
1957 dev->pdev->subsystem_device == 0x009f)
1958 return false;
1959
fc7f7119
AD		 1960 /* HP dc5750 has non-existent TV port */
1961 if (dev->pdev->device == 0x5974 &&
1962 dev->pdev->subsystem_vendor == 0x103c &&
1963 dev->pdev->subsystem_device == 0x280a)
1964 return false;
1965
fd874ad0
AD		 1966 /* MSI S270 has non-existent TV port */
1967 if (dev->pdev->device == 0x5955 &&
1968 dev->pdev->subsystem_vendor == 0x1462 &&
1969 dev->pdev->subsystem_device == 0x0131)
1970 return false;
1971
790cfb34
AD		 1972 return true;
1973}
1974
b75fad06
AD		 1975static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1976{
1977 struct radeon_device *rdev = dev->dev_private;
1978 uint32_t ext_tmds_info;
1979
1980 if (rdev->flags & RADEON_IS_IGP) {
1981 if (is_dvi_d)
1982 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1983 else
1984 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1985 }
1986 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1987 if (ext_tmds_info) {
1988 uint8_t rev = RBIOS8(ext_tmds_info);
1989 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1990 if (rev >= 3) {
1991 if (is_dvi_d)
1992 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1993 else
1994 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1995 } else {
1996 if (flags & 1) {
1997 if (is_dvi_d)
1998 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1999 else
2000 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2001 }
2002 }
2003 }
2004 if (is_dvi_d)
2005 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2006 else
2007 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2008}
2009
771fe6b9
JG		 2010bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2011{
2012 struct radeon_device *rdev = dev->dev_private;
2013 uint32_t conn_info, entry, devices;
b75fad06 2014 uint16_t tmp, connector_object_id;
771fe6b9
JG		 2015 enum radeon_combios_ddc ddc_type;
2016 enum radeon_combios_connector connector;
2017 int i = 0;
2018 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 2019 struct radeon_hpd hpd;
771fe6b9 2020
771fe6b9
JG		 2021 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2022 if (conn_info) {
2023 for (i = 0; i < 4; i++) {
2024 entry = conn_info + 2 + i * 2;
2025
2026 if (!RBIOS16(entry))
2027 break;
2028
2029 tmp = RBIOS16(entry);
2030
2031 connector = (tmp >> 12) & 0xf;
2032
2033 ddc_type = (tmp >> 8) & 0xf;
2034 switch (ddc_type) {
2035 case DDC_MONID:
2036 ddc_i2c =
6a93cb25 2037 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 2038 break;
2039 case DDC_DVI:
2040 ddc_i2c =
6a93cb25 2041 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 2042 break;
2043 case DDC_VGA:
2044 ddc_i2c =
6a93cb25 2045 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2046 break;
2047 case DDC_CRT2:
2048 ddc_i2c =
6a93cb25 2049 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2050 break;
2051 default:
d294ed69 2052 ddc_i2c.valid = false;
771fe6b9
JG		 2053 break;
2054 }
2055
eed45b30
AD		 2056 switch (connector) {
2057 case CONNECTOR_PROPRIETARY_LEGACY:
2058 case CONNECTOR_DVI_I_LEGACY:
2059 case CONNECTOR_DVI_D_LEGACY:
2060 if ((tmp >> 4) & 0x1)
2061 hpd.hpd = RADEON_HPD_2;
2062 else
2063 hpd.hpd = RADEON_HPD_1;
2064 break;
2065 default:
2066 hpd.hpd = RADEON_HPD_NONE;
2067 break;
2068 }
2069
2d152c6b 2070 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 2071 &ddc_i2c, &hpd))
2d152c6b 2072 continue;
771fe6b9
JG		 2073
2074 switch (connector) {
2075 case CONNECTOR_PROPRIETARY_LEGACY:
2076 if ((tmp >> 4) & 0x1)
2077 devices = ATOM_DEVICE_DFP2_SUPPORT;
2078 else
2079 devices = ATOM_DEVICE_DFP1_SUPPORT;
2080 radeon_add_legacy_encoder(dev,
2081 radeon_get_encoder_id
2082 (dev, devices, 0),
2083 devices);
2084 radeon_add_legacy_connector(dev, i, devices,
2085 legacy_connector_convert
2086 [connector],
b75fad06 2087 &ddc_i2c,
eed45b30
AD		 2088 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2089 &hpd);
771fe6b9
JG		 2090 break;
2091 case CONNECTOR_CRT_LEGACY:
2092 if (tmp & 0x1) {
2093 devices = ATOM_DEVICE_CRT2_SUPPORT;
2094 radeon_add_legacy_encoder(dev,
2095 radeon_get_encoder_id
2096 (dev,
2097 ATOM_DEVICE_CRT2_SUPPORT,
2098 2),
2099 ATOM_DEVICE_CRT2_SUPPORT);
2100 } else {
2101 devices = ATOM_DEVICE_CRT1_SUPPORT;
2102 radeon_add_legacy_encoder(dev,
2103 radeon_get_encoder_id
2104 (dev,
2105 ATOM_DEVICE_CRT1_SUPPORT,
2106 1),
2107 ATOM_DEVICE_CRT1_SUPPORT);
2108 }
2109 radeon_add_legacy_connector(dev,
2110 i,
2111 devices,
2112 legacy_connector_convert
2113 [connector],
b75fad06 2114 &ddc_i2c,
eed45b30
AD		 2115 CONNECTOR_OBJECT_ID_VGA,
2116 &hpd);
771fe6b9
JG		 2117 break;
2118 case CONNECTOR_DVI_I_LEGACY:
2119 devices = 0;
2120 if (tmp & 0x1) {
2121 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2122 radeon_add_legacy_encoder(dev,
2123 radeon_get_encoder_id
2124 (dev,
2125 ATOM_DEVICE_CRT2_SUPPORT,
2126 2),
2127 ATOM_DEVICE_CRT2_SUPPORT);
2128 } else {
2129 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2130 radeon_add_legacy_encoder(dev,
2131 radeon_get_encoder_id
2132 (dev,
2133 ATOM_DEVICE_CRT1_SUPPORT,
2134 1),
2135 ATOM_DEVICE_CRT1_SUPPORT);
2136 }
2137 if ((tmp >> 4) & 0x1) {
2138 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2139 radeon_add_legacy_encoder(dev,
2140 radeon_get_encoder_id
2141 (dev,
2142 ATOM_DEVICE_DFP2_SUPPORT,
2143 0),
2144 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2145 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2146 } else {
2147 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2148 radeon_add_legacy_encoder(dev,
2149 radeon_get_encoder_id
2150 (dev,
2151 ATOM_DEVICE_DFP1_SUPPORT,
2152 0),
2153 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2154 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2155 }
2156 radeon_add_legacy_connector(dev,
2157 i,
2158 devices,
2159 legacy_connector_convert
2160 [connector],
b75fad06 2161 &ddc_i2c,
eed45b30
AD		 2162 connector_object_id,
2163 &hpd);
771fe6b9
JG		 2164 break;
2165 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2166 if ((tmp >> 4) & 0x1) {
771fe6b9 2167 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2168 connector_object_id = combios_check_dl_dvi(dev, 1);
2169 } else {
771fe6b9 2170 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2171 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2172 }
771fe6b9
JG		 2173 radeon_add_legacy_encoder(dev,
2174 radeon_get_encoder_id
2175 (dev, devices, 0),
2176 devices);
2177 radeon_add_legacy_connector(dev, i, devices,
2178 legacy_connector_convert
2179 [connector],
b75fad06 2180 &ddc_i2c,
eed45b30
AD		 2181 connector_object_id,
2182 &hpd);
771fe6b9
JG		 2183 break;
2184 case CONNECTOR_CTV_LEGACY:
2185 case CONNECTOR_STV_LEGACY:
2186 radeon_add_legacy_encoder(dev,
2187 radeon_get_encoder_id
2188 (dev,
2189 ATOM_DEVICE_TV1_SUPPORT,
2190 2),
2191 ATOM_DEVICE_TV1_SUPPORT);
2192 radeon_add_legacy_connector(dev, i,
2193 ATOM_DEVICE_TV1_SUPPORT,
2194 legacy_connector_convert
2195 [connector],
b75fad06 2196 &ddc_i2c,
eed45b30
AD		 2197 CONNECTOR_OBJECT_ID_SVIDEO,
2198 &hpd);
771fe6b9
JG		 2199 break;
2200 default:
2201 DRM_ERROR("Unknown connector type: %d\n",
2202 connector);
2203 continue;
2204 }
2205
2206 }
2207 } else {
2208 uint16_t tmds_info =
2209 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2210 if (tmds_info) {
2211 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2212
2213 radeon_add_legacy_encoder(dev,
2214 radeon_get_encoder_id(dev,
2215 ATOM_DEVICE_CRT1_SUPPORT,
2216 1),
2217 ATOM_DEVICE_CRT1_SUPPORT);
2218 radeon_add_legacy_encoder(dev,
2219 radeon_get_encoder_id(dev,
2220 ATOM_DEVICE_DFP1_SUPPORT,
2221 0),
2222 ATOM_DEVICE_DFP1_SUPPORT);
2223
6a93cb25 2224 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
8e36ed00 2225 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 2226 radeon_add_legacy_connector(dev,
2227 0,
2228 ATOM_DEVICE_CRT1_SUPPORT |
2229 ATOM_DEVICE_DFP1_SUPPORT,
2230 DRM_MODE_CONNECTOR_DVII,
b75fad06 2231 &ddc_i2c,
eed45b30
AD		 2232 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2233 &hpd);
771fe6b9 2234 } else {
d0c403e9
AD		 2235 uint16_t crt_info =
2236 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2237 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2238 if (crt_info) {
2239 radeon_add_legacy_encoder(dev,
2240 radeon_get_encoder_id(dev,
2241 ATOM_DEVICE_CRT1_SUPPORT,
2242 1),
2243 ATOM_DEVICE_CRT1_SUPPORT);
6a93cb25 2244 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 2245 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2246 radeon_add_legacy_connector(dev,
2247 0,
2248 ATOM_DEVICE_CRT1_SUPPORT,
2249 DRM_MODE_CONNECTOR_VGA,
b75fad06 2250 &ddc_i2c,
eed45b30
AD		 2251 CONNECTOR_OBJECT_ID_VGA,
2252 &hpd);
d0c403e9
AD		 2253 } else {
2254 DRM_DEBUG("No connector info found\n");
2255 return false;
2256 }
771fe6b9
JG		 2257 }
2258 }
2259
2260 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2261 uint16_t lcd_info =
2262 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2263 if (lcd_info) {
2264 uint16_t lcd_ddc_info =
2265 combios_get_table_offset(dev,
2266 COMBIOS_LCD_DDC_INFO_TABLE);
2267
2268 radeon_add_legacy_encoder(dev,
2269 radeon_get_encoder_id(dev,
2270 ATOM_DEVICE_LCD1_SUPPORT,
2271 0),
2272 ATOM_DEVICE_LCD1_SUPPORT);
2273
2274 if (lcd_ddc_info) {
2275 ddc_type = RBIOS8(lcd_ddc_info + 2);
2276 switch (ddc_type) {
2277 case DDC_MONID:
2278 ddc_i2c =
2279 combios_setup_i2c_bus
6a93cb25 2280 (rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 2281 break;
2282 case DDC_DVI:
2283 ddc_i2c =
2284 combios_setup_i2c_bus
6a93cb25 2285 (rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 2286 break;
2287 case DDC_VGA:
2288 ddc_i2c =
2289 combios_setup_i2c_bus
6a93cb25 2290 (rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2291 break;
2292 case DDC_CRT2:
2293 ddc_i2c =
2294 combios_setup_i2c_bus
6a93cb25 2295 (rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2296 break;
2297 case DDC_LCD:
2298 ddc_i2c =
2299 combios_setup_i2c_bus
6a93cb25 2300 (rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 2301 ddc_i2c.mask_clk_mask =
2302 RBIOS32(lcd_ddc_info + 3);
2303 ddc_i2c.mask_data_mask =
2304 RBIOS32(lcd_ddc_info + 7);
2305 ddc_i2c.a_clk_mask =
2306 RBIOS32(lcd_ddc_info + 3);
2307 ddc_i2c.a_data_mask =
2308 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2309 ddc_i2c.en_clk_mask =
771fe6b9 2310 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2311 ddc_i2c.en_data_mask =
771fe6b9 2312 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2313 ddc_i2c.y_clk_mask =
771fe6b9 2314 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2315 ddc_i2c.y_data_mask =
771fe6b9
JG		 2316 RBIOS32(lcd_ddc_info + 7);
2317 break;
2318 case DDC_GPIO:
2319 ddc_i2c =
2320 combios_setup_i2c_bus
6a93cb25 2321 (rdev, RADEON_MDGPIO_MASK);
771fe6b9
JG		 2322 ddc_i2c.mask_clk_mask =
2323 RBIOS32(lcd_ddc_info + 3);
2324 ddc_i2c.mask_data_mask =
2325 RBIOS32(lcd_ddc_info + 7);
2326 ddc_i2c.a_clk_mask =
2327 RBIOS32(lcd_ddc_info + 3);
2328 ddc_i2c.a_data_mask =
2329 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2330 ddc_i2c.en_clk_mask =
771fe6b9 2331 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2332 ddc_i2c.en_data_mask =
771fe6b9 2333 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2334 ddc_i2c.y_clk_mask =
771fe6b9 2335 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2336 ddc_i2c.y_data_mask =
771fe6b9
JG		 2337 RBIOS32(lcd_ddc_info + 7);
2338 break;
2339 default:
2340 ddc_i2c.valid = false;
2341 break;
2342 }
2343 DRM_DEBUG("LCD DDC Info Table found!\n");
2344 } else
2345 ddc_i2c.valid = false;
2346
eed45b30 2347 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2348 radeon_add_legacy_connector(dev,
2349 5,
2350 ATOM_DEVICE_LCD1_SUPPORT,
2351 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2352 &ddc_i2c,
eed45b30
AD		 2353 CONNECTOR_OBJECT_ID_LVDS,
2354 &hpd);
771fe6b9
JG		 2355 }
2356 }
2357
2358 /* check TV table */
2359 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2360 uint32_t tv_info =
2361 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2362 if (tv_info) {
2363 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2364 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2365 hpd.hpd = RADEON_HPD_NONE;
d294ed69 2366 ddc_i2c.valid = false;
790cfb34
AD		 2367 radeon_add_legacy_encoder(dev,
2368 radeon_get_encoder_id
2369 (dev,
2370 ATOM_DEVICE_TV1_SUPPORT,
2371 2),
2372 ATOM_DEVICE_TV1_SUPPORT);
2373 radeon_add_legacy_connector(dev, 6,
2374 ATOM_DEVICE_TV1_SUPPORT,
2375 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2376 &ddc_i2c,
eed45b30
AD		 2377 CONNECTOR_OBJECT_ID_SVIDEO,
2378 &hpd);
790cfb34 2379 }
771fe6b9
JG		 2380 }
2381 }
2382 }
2383
2384 radeon_link_encoder_connector(dev);
2385
2386 return true;
2387}
2388
56278a8e
AD		 2389void radeon_combios_get_power_modes(struct radeon_device *rdev)
2390{
2391 struct drm_device *dev = rdev->ddev;
2392 u16 offset, misc, misc2 = 0;
2393 u8 rev, blocks, tmp;
2394 int state_index = 0;
2395
a48b9b4e 2396 rdev->pm.default_power_state_index = -1;
56278a8e 2397
56278a8e
AD		 2398 if (rdev->flags & RADEON_IS_MOBILITY) {
2399 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2400 if (offset) {
2401 rev = RBIOS8(offset);
2402 blocks = RBIOS8(offset + 0x2);
2403 /* power mode 0 tends to be the only valid one */
2404 rdev->pm.power_state[state_index].num_clock_modes = 1;
2405 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2406 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2407 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2408 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2409 goto default_mode;
0ec0e74f
AD		 2410 rdev->pm.power_state[state_index].type =
2411 POWER_STATE_TYPE_BATTERY;
56278a8e
AD		 2412 misc = RBIOS16(offset + 0x5 + 0x0);
2413 if (rev > 4)
2414 misc2 = RBIOS16(offset + 0x5 + 0xe);
79daedc9
AD		 2415 rdev->pm.power_state[state_index].misc = misc;
2416 rdev->pm.power_state[state_index].misc2 = misc2;
56278a8e
AD		 2417 if (misc & 0x4) {
2418 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2419 if (misc & 0x8)
2420 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2421 true;
2422 else
2423 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2424 false;
2425 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2426 if (rev < 6) {
2427 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2428 RBIOS16(offset + 0x5 + 0xb) * 4;
2429 tmp = RBIOS8(offset + 0x5 + 0xd);
2430 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2431 } else {
2432 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2433 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2434 if (entries && voltage_table_offset) {
2435 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2436 RBIOS16(voltage_table_offset) * 4;
2437 tmp = RBIOS8(voltage_table_offset + 0x2);
2438 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2439 } else
2440 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2441 }
2442 switch ((misc2 & 0x700) >> 8) {
2443 case 0:
2444 default:
2445 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2446 break;
2447 case 1:
2448 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2449 break;
2450 case 2:
2451 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2452 break;
2453 case 3:
2454 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2455 break;
2456 case 4:
2457 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2458 break;
2459 }
2460 } else
2461 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2462 if (rev > 6)
79daedc9 2463 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e 2464 RBIOS8(offset + 0x5 + 0x10);
d7311171 2465 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e
AD		 2466 state_index++;
2467 } else {
2468 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2469 }
2470 } else {
2471 /* XXX figure out some good default low power mode for desktop cards */
2472 }
2473
2474default_mode:
2475 /* add the default mode */
0ec0e74f
AD		 2476 rdev->pm.power_state[state_index].type =
2477 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2478 rdev->pm.power_state[state_index].num_clock_modes = 1;
2479 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2480 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2481 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
84d88f4c 2482 if ((state_index > 0) &&
8de016e2 2483 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
84d88f4c
AD		 2484 rdev->pm.power_state[state_index].clock_info[0].voltage =
2485 rdev->pm.power_state[0].clock_info[0].voltage;
2486 else
2487 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2488 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2489 rdev->pm.power_state[state_index].flags = 0;
2490 rdev->pm.default_power_state_index = state_index;
56278a8e 2491 rdev->pm.num_power_states = state_index + 1;
9038dfdf 2492
a48b9b4e
AD		 2493 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2494 rdev->pm.current_clock_mode_index = 0;
56278a8e
AD		 2495}
2496
fcec570b
AD		 2497void radeon_external_tmds_setup(struct drm_encoder *encoder)
2498{
2499 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2500 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2501
2502 if (!tmds)
2503 return;
2504
2505 switch (tmds->dvo_chip) {
2506 case DVO_SIL164:
2507 /* sil 164 */
5a6f98f5
AD		 2508 radeon_i2c_put_byte(tmds->i2c_bus,
2509 tmds->slave_addr,
2510 0x08, 0x30);
2511 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2512 tmds->slave_addr,
2513 0x09, 0x00);
5a6f98f5
AD		 2514 radeon_i2c_put_byte(tmds->i2c_bus,
2515 tmds->slave_addr,
2516 0x0a, 0x90);
2517 radeon_i2c_put_byte(tmds->i2c_bus,
2518 tmds->slave_addr,
2519 0x0c, 0x89);
2520 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2521 tmds->slave_addr,
2522 0x08, 0x3b);
fcec570b
AD		 2523 break;
2524 case DVO_SIL1178:
2525 /* sil 1178 - untested */
2526 /*
2527 * 0x0f, 0x44
2528 * 0x0f, 0x4c
2529 * 0x0e, 0x01
2530 * 0x0a, 0x80
2531 * 0x09, 0x30
2532 * 0x0c, 0xc9
2533 * 0x0d, 0x70
2534 * 0x08, 0x32
2535 * 0x08, 0x33
2536 */
2537 break;
2538 default:
2539 break;
2540 }
2541
2542}
2543
2544bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2545{
2546 struct drm_device *dev = encoder->dev;
2547 struct radeon_device *rdev = dev->dev_private;
2548 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2549 uint16_t offset;
2550 uint8_t blocks, slave_addr, rev;
2551 uint32_t index, id;
2552 uint32_t reg, val, and_mask, or_mask;
2553 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2554
fcec570b
AD		 2555 if (!tmds)
2556 return false;
2557
2558 if (rdev->flags & RADEON_IS_IGP) {
2559 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2560 rev = RBIOS8(offset);
2561 if (offset) {
2562 rev = RBIOS8(offset);
2563 if (rev > 1) {
2564 blocks = RBIOS8(offset + 3);
2565 index = offset + 4;
2566 while (blocks > 0) {
2567 id = RBIOS16(index);
2568 index += 2;
2569 switch (id >> 13) {
2570 case 0:
2571 reg = (id & 0x1fff) * 4;
2572 val = RBIOS32(index);
2573 index += 4;
2574 WREG32(reg, val);
2575 break;
2576 case 2:
2577 reg = (id & 0x1fff) * 4;
2578 and_mask = RBIOS32(index);
2579 index += 4;
2580 or_mask = RBIOS32(index);
2581 index += 4;
2582 val = RREG32(reg);
2583 val = (val & and_mask) | or_mask;
2584 WREG32(reg, val);
2585 break;
2586 case 3:
2587 val = RBIOS16(index);
2588 index += 2;
2589 udelay(val);
2590 break;
2591 case 4:
2592 val = RBIOS16(index);
2593 index += 2;
2594 udelay(val * 1000);
2595 break;
2596 case 6:
2597 slave_addr = id & 0xff;
2598 slave_addr >>= 1; /* 7 bit addressing */
2599 index++;
2600 reg = RBIOS8(index);
2601 index++;
2602 val = RBIOS8(index);
2603 index++;
5a6f98f5
AD		 2604 radeon_i2c_put_byte(tmds->i2c_bus,
2605 slave_addr,
2606 reg, val);
fcec570b
AD		 2607 break;
2608 default:
2609 DRM_ERROR("Unknown id %d\n", id >> 13);
2610 break;
2611 }
2612 blocks--;
2613 }
2614 return true;
2615 }
2616 }
2617 } else {
2618 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2619 if (offset) {
2620 index = offset + 10;
2621 id = RBIOS16(index);
2622 while (id != 0xffff) {
2623 index += 2;
2624 switch (id >> 13) {
2625 case 0:
2626 reg = (id & 0x1fff) * 4;
2627 val = RBIOS32(index);
2628 WREG32(reg, val);
2629 break;
2630 case 2:
2631 reg = (id & 0x1fff) * 4;
2632 and_mask = RBIOS32(index);
2633 index += 4;
2634 or_mask = RBIOS32(index);
2635 index += 4;
2636 val = RREG32(reg);
2637 val = (val & and_mask) | or_mask;
2638 WREG32(reg, val);
2639 break;
2640 case 4:
2641 val = RBIOS16(index);
2642 index += 2;
2643 udelay(val);
2644 break;
2645 case 5:
2646 reg = id & 0x1fff;
2647 and_mask = RBIOS32(index);
2648 index += 4;
2649 or_mask = RBIOS32(index);
2650 index += 4;
2651 val = RREG32_PLL(reg);
2652 val = (val & and_mask) | or_mask;
2653 WREG32_PLL(reg, val);
2654 break;
2655 case 6:
2656 reg = id & 0x1fff;
2657 val = RBIOS8(index);
2658 index += 1;
5a6f98f5
AD		 2659 radeon_i2c_put_byte(tmds->i2c_bus,
2660 tmds->slave_addr,
2661 reg, val);
fcec570b
AD		 2662 break;
2663 default:
2664 DRM_ERROR("Unknown id %d\n", id >> 13);
2665 break;
2666 }
2667 id = RBIOS16(index);
2668 }
2669 return true;
2670 }
2671 }
2672 return false;
2673}
2674
771fe6b9
JG		 2675static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2676{
2677 struct radeon_device *rdev = dev->dev_private;
2678
2679 if (offset) {
2680 while (RBIOS16(offset)) {
2681 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2682 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2683 uint32_t val, and_mask, or_mask;
2684 uint32_t tmp;
2685
2686 offset += 2;
2687 switch (cmd) {
2688 case 0:
2689 val = RBIOS32(offset);
2690 offset += 4;
2691 WREG32(addr, val);
2692 break;
2693 case 1:
2694 val = RBIOS32(offset);
2695 offset += 4;
2696 WREG32(addr, val);
2697 break;
2698 case 2:
2699 and_mask = RBIOS32(offset);
2700 offset += 4;
2701 or_mask = RBIOS32(offset);
2702 offset += 4;
2703 tmp = RREG32(addr);
2704 tmp &= and_mask;
2705 tmp |= or_mask;
2706 WREG32(addr, tmp);
2707 break;
2708 case 3:
2709 and_mask = RBIOS32(offset);
2710 offset += 4;
2711 or_mask = RBIOS32(offset);
2712 offset += 4;
2713 tmp = RREG32(addr);
2714 tmp &= and_mask;
2715 tmp |= or_mask;
2716 WREG32(addr, tmp);
2717 break;
2718 case 4:
2719 val = RBIOS16(offset);
2720 offset += 2;
2721 udelay(val);
2722 break;
2723 case 5:
2724 val = RBIOS16(offset);
2725 offset += 2;
2726 switch (addr) {
2727 case 8:
2728 while (val--) {
2729 if (!
2730 (RREG32_PLL
2731 (RADEON_CLK_PWRMGT_CNTL) &
2732 RADEON_MC_BUSY))
2733 break;
2734 }
2735 break;
2736 case 9:
2737 while (val--) {
2738 if ((RREG32(RADEON_MC_STATUS) &
2739 RADEON_MC_IDLE))
2740 break;
2741 }
2742 break;
2743 default:
2744 break;
2745 }
2746 break;
2747 default:
2748 break;
2749 }
2750 }
2751 }
2752}
2753
2754static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2755{
2756 struct radeon_device *rdev = dev->dev_private;
2757
2758 if (offset) {
2759 while (RBIOS8(offset)) {
2760 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2761 uint8_t addr = (RBIOS8(offset) & 0x3f);
2762 uint32_t val, shift, tmp;
2763 uint32_t and_mask, or_mask;
2764
2765 offset++;
2766 switch (cmd) {
2767 case 0:
2768 val = RBIOS32(offset);
2769 offset += 4;
2770 WREG32_PLL(addr, val);
2771 break;
2772 case 1:
2773 shift = RBIOS8(offset) * 8;
2774 offset++;
2775 and_mask = RBIOS8(offset) << shift;
2776 and_mask |= ~(0xff << shift);
2777 offset++;
2778 or_mask = RBIOS8(offset) << shift;
2779 offset++;
2780 tmp = RREG32_PLL(addr);
2781 tmp &= and_mask;
2782 tmp |= or_mask;
2783 WREG32_PLL(addr, tmp);
2784 break;
2785 case 2:
2786 case 3:
2787 tmp = 1000;
2788 switch (addr) {
2789 case 1:
2790 udelay(150);
2791 break;
2792 case 2:
2793 udelay(1000);
2794 break;
2795 case 3:
2796 while (tmp--) {
2797 if (!
2798 (RREG32_PLL
2799 (RADEON_CLK_PWRMGT_CNTL) &
2800 RADEON_MC_BUSY))
2801 break;
2802 }
2803 break;
2804 case 4:
2805 while (tmp--) {
2806 if (RREG32_PLL
2807 (RADEON_CLK_PWRMGT_CNTL) &
2808 RADEON_DLL_READY)
2809 break;
2810 }
2811 break;
2812 case 5:
2813 tmp =
2814 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2815 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2816#if 0
2817 uint32_t mclk_cntl =
2818 RREG32_PLL
2819 (RADEON_MCLK_CNTL);
2820 mclk_cntl &= 0xffff0000;
2821 /*mclk_cntl |= 0x00001111;*//* ??? */
2822 WREG32_PLL(RADEON_MCLK_CNTL,
2823 mclk_cntl);
2824 udelay(10000);
2825#endif
2826 WREG32_PLL
2827 (RADEON_CLK_PWRMGT_CNTL,
2828 tmp &
2829 ~RADEON_CG_NO1_DEBUG_0);
2830 udelay(10000);
2831 }
2832 break;
2833 default:
2834 break;
2835 }
2836 break;
2837 default:
2838 break;
2839 }
2840 }
2841 }
2842}
2843
2844static void combios_parse_ram_reset_table(struct drm_device *dev,
2845 uint16_t offset)
2846{
2847 struct radeon_device *rdev = dev->dev_private;
2848 uint32_t tmp;
2849
2850 if (offset) {
2851 uint8_t val = RBIOS8(offset);
2852 while (val != 0xff) {
2853 offset++;
2854
2855 if (val == 0x0f) {
2856 uint32_t channel_complete_mask;
2857
2858 if (ASIC_IS_R300(rdev))
2859 channel_complete_mask =
2860 R300_MEM_PWRUP_COMPLETE;
2861 else
2862 channel_complete_mask =
2863 RADEON_MEM_PWRUP_COMPLETE;
2864 tmp = 20000;
2865 while (tmp--) {
2866 if ((RREG32(RADEON_MEM_STR_CNTL) &
2867 channel_complete_mask) ==
2868 channel_complete_mask)
2869 break;
2870 }
2871 } else {
2872 uint32_t or_mask = RBIOS16(offset);
2873 offset += 2;
2874
2875 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2876 tmp &= RADEON_SDRAM_MODE_MASK;
2877 tmp |= or_mask;
2878 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2879
2880 or_mask = val << 24;
2881 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2882 tmp &= RADEON_B3MEM_RESET_MASK;
2883 tmp |= or_mask;
2884 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2885 }
2886 val = RBIOS8(offset);
2887 }
2888 }
2889}
2890
2891static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2892 int mem_addr_mapping)
2893{
2894 struct radeon_device *rdev = dev->dev_private;
2895 uint32_t mem_cntl;
2896 uint32_t mem_size;
2897 uint32_t addr = 0;
2898
2899 mem_cntl = RREG32(RADEON_MEM_CNTL);
2900 if (mem_cntl & RV100_HALF_MODE)
2901 ram /= 2;
2902 mem_size = ram;
2903 mem_cntl &= ~(0xff << 8);
2904 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2905 WREG32(RADEON_MEM_CNTL, mem_cntl);
2906 RREG32(RADEON_MEM_CNTL);
2907
2908 /* sdram reset ? */
2909
2910 /* something like this???? */
2911 while (ram--) {
2912 addr = ram * 1024 * 1024;
2913 /* write to each page */
2914 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2915 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2916 /* read back and verify */
2917 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2918 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2919 return 0;
2920 }
2921
2922 return mem_size;
2923}
2924
2925static void combios_write_ram_size(struct drm_device *dev)
2926{
2927 struct radeon_device *rdev = dev->dev_private;
2928 uint8_t rev;
2929 uint16_t offset;
2930 uint32_t mem_size = 0;
2931 uint32_t mem_cntl = 0;
2932
2933 /* should do something smarter here I guess... */
2934 if (rdev->flags & RADEON_IS_IGP)
2935 return;
2936
2937 /* first check detected mem table */
2938 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2939 if (offset) {
2940 rev = RBIOS8(offset);
2941 if (rev < 3) {
2942 mem_cntl = RBIOS32(offset + 1);
2943 mem_size = RBIOS16(offset + 5);
2944 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2945 ((dev->pdev->device != 0x515e)
2946 && (dev->pdev->device != 0x5969)))
2947 WREG32(RADEON_MEM_CNTL, mem_cntl);
2948 }
2949 }
2950
2951 if (!mem_size) {
2952 offset =
2953 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2954 if (offset) {
2955 rev = RBIOS8(offset - 1);
2956 if (rev < 1) {
2957 if (((rdev->flags & RADEON_FAMILY_MASK) <
2958 CHIP_R200)
2959 && ((dev->pdev->device != 0x515e)
2960 && (dev->pdev->device != 0x5969))) {
2961 int ram = 0;
2962 int mem_addr_mapping = 0;
2963
2964 while (RBIOS8(offset)) {
2965 ram = RBIOS8(offset);
2966 mem_addr_mapping =
2967 RBIOS8(offset + 1);
2968 if (mem_addr_mapping != 0x25)
2969 ram *= 2;
2970 mem_size =
2971 combios_detect_ram(dev, ram,
2972 mem_addr_mapping);
2973 if (mem_size)
2974 break;
2975 offset += 2;
2976 }
2977 } else
2978 mem_size = RBIOS8(offset);
2979 } else {
2980 mem_size = RBIOS8(offset);
2981 mem_size *= 2; /* convert to MB */
2982 }
2983 }
2984 }
2985
2986 mem_size *= (1024 * 1024); /* convert to bytes */
2987 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2988}
2989
2990void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2991{
2992 uint16_t dyn_clk_info =
2993 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2994
2995 if (dyn_clk_info)
2996 combios_parse_pll_table(dev, dyn_clk_info);
2997}
2998
2999void radeon_combios_asic_init(struct drm_device *dev)
3000{
3001 struct radeon_device *rdev = dev->dev_private;
3002 uint16_t table;
3003
3004 /* port hardcoded mac stuff from radeonfb */
3005 if (rdev->bios == NULL)
3006 return;
3007
3008 /* ASIC INIT 1 */
3009 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3010 if (table)
3011 combios_parse_mmio_table(dev, table);
3012
3013 /* PLL INIT */
3014 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3015 if (table)
3016 combios_parse_pll_table(dev, table);
3017
3018 /* ASIC INIT 2 */
3019 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3020 if (table)
3021 combios_parse_mmio_table(dev, table);
3022
3023 if (!(rdev->flags & RADEON_IS_IGP)) {
3024 /* ASIC INIT 4 */
3025 table =
3026 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3027 if (table)
3028 combios_parse_mmio_table(dev, table);
3029
3030 /* RAM RESET */
3031 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3032 if (table)
3033 combios_parse_ram_reset_table(dev, table);
3034
3035 /* ASIC INIT 3 */
3036 table =
3037 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3038 if (table)
3039 combios_parse_mmio_table(dev, table);
3040
3041 /* write CONFIG_MEMSIZE */
3042 combios_write_ram_size(dev);
3043 }
3044
580b4fff
DA		 3045 /* quirk for rs4xx HP nx6125 laptop to make it resume
3046 * - it hangs on resume inside the dynclk 1 table.
3047 */
3048 if (rdev->family == CHIP_RS480 &&
3049 rdev->pdev->subsystem_vendor == 0x103c &&
3050 rdev->pdev->subsystem_device == 0x308b)
3051 return;
3052
771fe6b9
JG		 3053 /* DYN CLK 1 */
3054 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3055 if (table)
3056 combios_parse_pll_table(dev, table);
3057
3058}
3059
3060void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3061{
3062 struct radeon_device *rdev = dev->dev_private;
3063 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3064
3065 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3066 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3067 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3068
3069 /* let the bios control the backlight */
3070 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3071
3072 /* tell the bios not to handle mode switching */
3073 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3074 RADEON_ACC_MODE_CHANGE);
3075
3076 /* tell the bios a driver is loaded */
3077 bios_7_scratch |= RADEON_DRV_LOADED;
3078
3079 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3080 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3081 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3082}
3083
3084void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3085{
3086 struct drm_device *dev = encoder->dev;
3087 struct radeon_device *rdev = dev->dev_private;
3088 uint32_t bios_6_scratch;
3089
3090 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3091
3092 if (lock)
3093 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3094 else
3095 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3096
3097 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3098}
3099
3100void
3101radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3102 struct drm_encoder *encoder,
3103 bool connected)
3104{
3105 struct drm_device *dev = connector->dev;
3106 struct radeon_device *rdev = dev->dev_private;
3107 struct radeon_connector *radeon_connector =
3108 to_radeon_connector(connector);
3109 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3110 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3111 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3112
3113 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3114 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3115 if (connected) {
3116 DRM_DEBUG("TV1 connected\n");
3117 /* fix me */
3118 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3119 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3120 bios_5_scratch |= RADEON_TV1_ON;
3121 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3122 } else {
3123 DRM_DEBUG("TV1 disconnected\n");
3124 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3125 bios_5_scratch &= ~RADEON_TV1_ON;
3126 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3127 }
3128 }
3129 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3130 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3131 if (connected) {
3132 DRM_DEBUG("LCD1 connected\n");
3133 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3134 bios_5_scratch |= RADEON_LCD1_ON;
3135 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3136 } else {
3137 DRM_DEBUG("LCD1 disconnected\n");
3138 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3139 bios_5_scratch &= ~RADEON_LCD1_ON;
3140 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3141 }
3142 }
3143 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3144 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3145 if (connected) {
3146 DRM_DEBUG("CRT1 connected\n");
3147 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3148 bios_5_scratch |= RADEON_CRT1_ON;
3149 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3150 } else {
3151 DRM_DEBUG("CRT1 disconnected\n");
3152 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3153 bios_5_scratch &= ~RADEON_CRT1_ON;
3154 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3155 }
3156 }
3157 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3158 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3159 if (connected) {
3160 DRM_DEBUG("CRT2 connected\n");
3161 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3162 bios_5_scratch |= RADEON_CRT2_ON;
3163 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3164 } else {
3165 DRM_DEBUG("CRT2 disconnected\n");
3166 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3167 bios_5_scratch &= ~RADEON_CRT2_ON;
3168 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3169 }
3170 }
3171 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3172 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3173 if (connected) {
3174 DRM_DEBUG("DFP1 connected\n");
3175 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3176 bios_5_scratch |= RADEON_DFP1_ON;
3177 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3178 } else {
3179 DRM_DEBUG("DFP1 disconnected\n");
3180 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3181 bios_5_scratch &= ~RADEON_DFP1_ON;
3182 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3183 }
3184 }
3185 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3186 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3187 if (connected) {
3188 DRM_DEBUG("DFP2 connected\n");
3189 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3190 bios_5_scratch |= RADEON_DFP2_ON;
3191 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3192 } else {
3193 DRM_DEBUG("DFP2 disconnected\n");
3194 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3195 bios_5_scratch &= ~RADEON_DFP2_ON;
3196 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3197 }
3198 }
3199 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3200 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3201}
3202
3203void
3204radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3205{
3206 struct drm_device *dev = encoder->dev;
3207 struct radeon_device *rdev = dev->dev_private;
3208 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3209 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3210
3211 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3212 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3213 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3214 }
3215 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3216 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3217 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3218 }
3219 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3220 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3221 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3222 }
3223 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3224 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3225 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3226 }
3227 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3228 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3229 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3230 }
3231 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3232 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3233 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3234 }
3235 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3236}
3237
3238void
3239radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3240{
3241 struct drm_device *dev = encoder->dev;
3242 struct radeon_device *rdev = dev->dev_private;
3243 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3244 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3245
3246 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3247 if (on)
3248 bios_6_scratch |= RADEON_TV_DPMS_ON;
3249 else
3250 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3251 }
3252 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3253 if (on)
3254 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3255 else
3256 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3257 }
3258 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3259 if (on)
3260 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3261 else
3262 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3263 }
3264 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3265 if (on)
3266 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3267 else
3268 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3269 }
3270 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3271}
Clone of davem's net-next-2.6 tree