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drm/radeon/kms: Fix up vertical blank interrupt support.
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon.h
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771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
47#include <asm/atomic.h>
48#include <linux/wait.h>
49#include <linux/list.h>
50#include <linux/kref.h>
51
52#include "radeon_mode.h"
53#include "radeon_reg.h"
068a117c 54#include "r300.h"
771fe6b9
JG		 55
56/*
57 * Modules parameters.
58 */
59extern int radeon_no_wb;
60extern int radeon_modeset;
61extern int radeon_dynclks;
62extern int radeon_r4xx_atom;
63extern int radeon_agpmode;
64extern int radeon_vram_limit;
65extern int radeon_gart_size;
66extern int radeon_benchmarking;
ecc0b326 67extern int radeon_testing;
771fe6b9
JG		 68extern int radeon_connector_table;
69
70/*
71 * Copy from radeon_drv.h so we don't have to include both and have conflicting
72 * symbol;
73 */
74#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
75#define RADEON_IB_POOL_SIZE 16
76#define RADEON_DEBUGFS_MAX_NUM_FILES 32
77#define RADEONFB_CONN_LIMIT 4
78
79enum radeon_family {
80 CHIP_R100,
81 CHIP_RV100,
82 CHIP_RS100,
83 CHIP_RV200,
84 CHIP_RS200,
85 CHIP_R200,
86 CHIP_RV250,
87 CHIP_RS300,
88 CHIP_RV280,
89 CHIP_R300,
90 CHIP_R350,
91 CHIP_RV350,
92 CHIP_RV380,
93 CHIP_R420,
94 CHIP_R423,
95 CHIP_RV410,
96 CHIP_RS400,
97 CHIP_RS480,
98 CHIP_RS600,
99 CHIP_RS690,
100 CHIP_RS740,
101 CHIP_RV515,
102 CHIP_R520,
103 CHIP_RV530,
104 CHIP_RV560,
105 CHIP_RV570,
106 CHIP_R580,
107 CHIP_R600,
108 CHIP_RV610,
109 CHIP_RV630,
110 CHIP_RV620,
111 CHIP_RV635,
112 CHIP_RV670,
113 CHIP_RS780,
114 CHIP_RV770,
115 CHIP_RV730,
116 CHIP_RV710,
c93bb85b 117 CHIP_RS880,
771fe6b9
JG		 118 CHIP_LAST,
119};
120
121enum radeon_chip_flags {
122 RADEON_FAMILY_MASK = 0x0000ffffUL,
123 RADEON_FLAGS_MASK = 0xffff0000UL,
124 RADEON_IS_MOBILITY = 0x00010000UL,
125 RADEON_IS_IGP = 0x00020000UL,
126 RADEON_SINGLE_CRTC = 0x00040000UL,
127 RADEON_IS_AGP = 0x00080000UL,
128 RADEON_HAS_HIERZ = 0x00100000UL,
129 RADEON_IS_PCIE = 0x00200000UL,
130 RADEON_NEW_MEMMAP = 0x00400000UL,
131 RADEON_IS_PCI = 0x00800000UL,
132 RADEON_IS_IGPGART = 0x01000000UL,
133};
134
135
136/*
137 * Errata workarounds.
138 */
139enum radeon_pll_errata {
140 CHIP_ERRATA_R300_CG = 0x00000001,
141 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
142 CHIP_ERRATA_PLL_DELAY = 0x00000004
143};
144
145
146struct radeon_device;
147
148
149/*
150 * BIOS.
151 */
152bool radeon_get_bios(struct radeon_device *rdev);
153
154/*
155 * Clocks
156 */
157
158struct radeon_clock {
159 struct radeon_pll p1pll;
160 struct radeon_pll p2pll;
161 struct radeon_pll spll;
162 struct radeon_pll mpll;
163 /* 10 Khz units */
164 uint32_t default_mclk;
165 uint32_t default_sclk;
166};
167
168/*
169 * Fences.
170 */
171struct radeon_fence_driver {
172 uint32_t scratch_reg;
173 atomic_t seq;
174 uint32_t last_seq;
175 unsigned long count_timeout;
176 wait_queue_head_t queue;
177 rwlock_t lock;
178 struct list_head created;
179 struct list_head emited;
180 struct list_head signaled;
181};
182
183struct radeon_fence {
184 struct radeon_device *rdev;
185 struct kref kref;
186 struct list_head list;
187 /* protected by radeon_fence.lock */
188 uint32_t seq;
189 unsigned long timeout;
190 bool emited;
191 bool signaled;
192};
193
194int radeon_fence_driver_init(struct radeon_device *rdev);
195void radeon_fence_driver_fini(struct radeon_device *rdev);
196int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
197int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
198void radeon_fence_process(struct radeon_device *rdev);
199bool radeon_fence_signaled(struct radeon_fence *fence);
200int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
201int radeon_fence_wait_next(struct radeon_device *rdev);
202int radeon_fence_wait_last(struct radeon_device *rdev);
203struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
204void radeon_fence_unref(struct radeon_fence **fence);
205
e024e110
DA		 206/*
207 * Tiling registers
208 */
209struct radeon_surface_reg {
210 struct radeon_object *robj;
211};
212
213#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 214
215/*
216 * Radeon buffer.
217 */
218struct radeon_object;
219
220struct radeon_object_list {
221 struct list_head list;
222 struct radeon_object *robj;
223 uint64_t gpu_offset;
224 unsigned rdomain;
225 unsigned wdomain;
e024e110 226 uint32_t tiling_flags;
771fe6b9
JG		 227};
228
229int radeon_object_init(struct radeon_device *rdev);
230void radeon_object_fini(struct radeon_device *rdev);
231int radeon_object_create(struct radeon_device *rdev,
232 struct drm_gem_object *gobj,
233 unsigned long size,
234 bool kernel,
235 uint32_t domain,
236 bool interruptible,
237 struct radeon_object **robj_ptr);
238int radeon_object_kmap(struct radeon_object *robj, void **ptr);
239void radeon_object_kunmap(struct radeon_object *robj);
240void radeon_object_unref(struct radeon_object **robj);
241int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
242 uint64_t *gpu_addr);
243void radeon_object_unpin(struct radeon_object *robj);
244int radeon_object_wait(struct radeon_object *robj);
245int radeon_object_evict_vram(struct radeon_device *rdev);
246int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
247void radeon_object_force_delete(struct radeon_device *rdev);
248void radeon_object_list_add_object(struct radeon_object_list *lobj,
249 struct list_head *head);
250int radeon_object_list_validate(struct list_head *head, void *fence);
251void radeon_object_list_unvalidate(struct list_head *head);
252void radeon_object_list_clean(struct list_head *head);
253int radeon_object_fbdev_mmap(struct radeon_object *robj,
254 struct vm_area_struct *vma);
255unsigned long radeon_object_size(struct radeon_object *robj);
e024e110
DA		 256void radeon_object_clear_surface_reg(struct radeon_object *robj);
257int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
258 bool force_drop);
259void radeon_object_set_tiling_flags(struct radeon_object *robj,
260 uint32_t tiling_flags, uint32_t pitch);
261void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
262void radeon_bo_move_notify(struct ttm_buffer_object *bo,
263 struct ttm_mem_reg *mem);
264void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
771fe6b9
JG		 265/*
266 * GEM objects.
267 */
268struct radeon_gem {
269 struct list_head objects;
270};
271
272int radeon_gem_init(struct radeon_device *rdev);
273void radeon_gem_fini(struct radeon_device *rdev);
274int radeon_gem_object_create(struct radeon_device *rdev, int size,
275 int alignment, int initial_domain,
276 bool discardable, bool kernel,
277 bool interruptible,
278 struct drm_gem_object **obj);
279int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
280 uint64_t *gpu_addr);
281void radeon_gem_object_unpin(struct drm_gem_object *obj);
282
283
284/*
285 * GART structures, functions & helpers
286 */
287struct radeon_mc;
288
289struct radeon_gart_table_ram {
290 volatile uint32_t *ptr;
291};
292
293struct radeon_gart_table_vram {
294 struct radeon_object *robj;
295 volatile uint32_t *ptr;
296};
297
298union radeon_gart_table {
299 struct radeon_gart_table_ram ram;
300 struct radeon_gart_table_vram vram;
301};
302
303struct radeon_gart {
304 dma_addr_t table_addr;
305 unsigned num_gpu_pages;
306 unsigned num_cpu_pages;
307 unsigned table_size;
308 union radeon_gart_table table;
309 struct page **pages;
310 dma_addr_t *pages_addr;
311 bool ready;
312};
313
314int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
315void radeon_gart_table_ram_free(struct radeon_device *rdev);
316int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
317void radeon_gart_table_vram_free(struct radeon_device *rdev);
318int radeon_gart_init(struct radeon_device *rdev);
319void radeon_gart_fini(struct radeon_device *rdev);
320void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
321 int pages);
322int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
323 int pages, struct page **pagelist);
324
325
326/*
327 * GPU MC structures, functions & helpers
328 */
329struct radeon_mc {
330 resource_size_t aper_size;
331 resource_size_t aper_base;
332 resource_size_t agp_base;
333 unsigned gtt_location;
334 unsigned gtt_size;
335 unsigned vram_location;
7a50f01a
DA		 336 /* for some chips with <= 32MB we need to lie
337 * about vram size near mc fb location */
338 unsigned mc_vram_size;
771fe6b9 339 unsigned vram_width;
7a50f01a 340 unsigned real_vram_size;
771fe6b9
JG		 341 int vram_mtrr;
342 bool vram_is_ddr;
343};
344
345int radeon_mc_setup(struct radeon_device *rdev);
346
347
348/*
349 * GPU scratch registers structures, functions & helpers
350 */
351struct radeon_scratch {
352 unsigned num_reg;
353 bool free[32];
354 uint32_t reg[32];
355};
356
357int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
358void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
359
360
361/*
362 * IRQS.
363 */
364struct radeon_irq {
365 bool installed;
366 bool sw_int;
367 /* FIXME: use a define max crtc rather than hardcode it */
368 bool crtc_vblank_int[2];
369};
370
371int radeon_irq_kms_init(struct radeon_device *rdev);
372void radeon_irq_kms_fini(struct radeon_device *rdev);
373
374
375/*
376 * CP & ring.
377 */
378struct radeon_ib {
379 struct list_head list;
380 unsigned long idx;
381 uint64_t gpu_addr;
382 struct radeon_fence *fence;
383 volatile uint32_t *ptr;
384 uint32_t length_dw;
385};
386
387struct radeon_ib_pool {
388 struct mutex mutex;
389 struct radeon_object *robj;
390 struct list_head scheduled_ibs;
391 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
392 bool ready;
393 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
394};
395
396struct radeon_cp {
397 struct radeon_object *ring_obj;
398 volatile uint32_t *ring;
399 unsigned rptr;
400 unsigned wptr;
401 unsigned wptr_old;
402 unsigned ring_size;
403 unsigned ring_free_dw;
404 int count_dw;
405 uint64_t gpu_addr;
406 uint32_t align_mask;
407 uint32_t ptr_mask;
408 struct mutex mutex;
409 bool ready;
410};
411
412int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
413void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
414int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
415int radeon_ib_pool_init(struct radeon_device *rdev);
416void radeon_ib_pool_fini(struct radeon_device *rdev);
417int radeon_ib_test(struct radeon_device *rdev);
418/* Ring access between begin & end cannot sleep */
419void radeon_ring_free_size(struct radeon_device *rdev);
420int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
421void radeon_ring_unlock_commit(struct radeon_device *rdev);
422void radeon_ring_unlock_undo(struct radeon_device *rdev);
423int radeon_ring_test(struct radeon_device *rdev);
424int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
425void radeon_ring_fini(struct radeon_device *rdev);
426
427
428/*
429 * CS.
430 */
431struct radeon_cs_reloc {
432 struct drm_gem_object *gobj;
433 struct radeon_object *robj;
434 struct radeon_object_list lobj;
435 uint32_t handle;
436 uint32_t flags;
437};
438
439struct radeon_cs_chunk {
440 uint32_t chunk_id;
441 uint32_t length_dw;
442 uint32_t *kdata;
443};
444
445struct radeon_cs_parser {
446 struct radeon_device *rdev;
447 struct drm_file *filp;
448 /* chunks */
449 unsigned nchunks;
450 struct radeon_cs_chunk *chunks;
451 uint64_t *chunks_array;
452 /* IB */
453 unsigned idx;
454 /* relocations */
455 unsigned nrelocs;
456 struct radeon_cs_reloc *relocs;
457 struct radeon_cs_reloc **relocs_ptr;
458 struct list_head validated;
459 /* indices of various chunks */
460 int chunk_ib_idx;
461 int chunk_relocs_idx;
462 struct radeon_ib *ib;
463 void *track;
464};
465
466struct radeon_cs_packet {
467 unsigned idx;
468 unsigned type;
469 unsigned reg;
470 unsigned opcode;
471 int count;
472 unsigned one_reg_wr;
473};
474
475typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
476 struct radeon_cs_packet *pkt,
477 unsigned idx, unsigned reg);
478typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
479 struct radeon_cs_packet *pkt);
480
481
482/*
483 * AGP
484 */
485int radeon_agp_init(struct radeon_device *rdev);
486void radeon_agp_fini(struct radeon_device *rdev);
487
488
489/*
490 * Writeback
491 */
492struct radeon_wb {
493 struct radeon_object *wb_obj;
494 volatile uint32_t *wb;
495 uint64_t gpu_addr;
496};
497
c93bb85b
JG		 498/**
499 * struct radeon_pm - power management datas
500 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
501 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
502 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
503 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
504 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
505 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
506 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
507 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
508 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
509 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
510 * @needed_bandwidth: current bandwidth needs
511 *
512 * It keeps track of various data needed to take powermanagement decision.
513 * Bandwith need is used to determine minimun clock of the GPU and memory.
514 * Equation between gpu/memory clock and available bandwidth is hw dependent
515 * (type of memory, bus size, efficiency, ...)
516 */
517struct radeon_pm {
518 fixed20_12 max_bandwidth;
519 fixed20_12 igp_sideport_mclk;
520 fixed20_12 igp_system_mclk;
521 fixed20_12 igp_ht_link_clk;
522 fixed20_12 igp_ht_link_width;
523 fixed20_12 k8_bandwidth;
524 fixed20_12 sideport_bandwidth;
525 fixed20_12 ht_bandwidth;
526 fixed20_12 core_bandwidth;
527 fixed20_12 sclk;
528 fixed20_12 needed_bandwidth;
529};
530
771fe6b9
JG		 531
532/*
533 * Benchmarking
534 */
535void radeon_benchmark(struct radeon_device *rdev);
536
537
ecc0b326
MD		 538/*
539 * Testing
540 */
541void radeon_test_moves(struct radeon_device *rdev);
542
543
771fe6b9
JG		 544/*
545 * Debugfs
546 */
547int radeon_debugfs_add_files(struct radeon_device *rdev,
548 struct drm_info_list *files,
549 unsigned nfiles);
550int radeon_debugfs_fence_init(struct radeon_device *rdev);
551int r100_debugfs_rbbm_init(struct radeon_device *rdev);
552int r100_debugfs_cp_init(struct radeon_device *rdev);
553
554
555/*
556 * ASIC specific functions.
557 */
558struct radeon_asic {
068a117c 559 int (*init)(struct radeon_device *rdev);
771fe6b9
JG		 560 void (*errata)(struct radeon_device *rdev);
561 void (*vram_info)(struct radeon_device *rdev);
562 int (*gpu_reset)(struct radeon_device *rdev);
563 int (*mc_init)(struct radeon_device *rdev);
564 void (*mc_fini)(struct radeon_device *rdev);
565 int (*wb_init)(struct radeon_device *rdev);
566 void (*wb_fini)(struct radeon_device *rdev);
567 int (*gart_enable)(struct radeon_device *rdev);
568 void (*gart_disable)(struct radeon_device *rdev);
569 void (*gart_tlb_flush)(struct radeon_device *rdev);
570 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
571 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
572 void (*cp_fini)(struct radeon_device *rdev);
573 void (*cp_disable)(struct radeon_device *rdev);
574 void (*ring_start)(struct radeon_device *rdev);
575 int (*irq_set)(struct radeon_device *rdev);
576 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 577 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 578 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
579 int (*cs_parse)(struct radeon_cs_parser *p);
580 int (*copy_blit)(struct radeon_device *rdev,
581 uint64_t src_offset,
582 uint64_t dst_offset,
583 unsigned num_pages,
584 struct radeon_fence *fence);
585 int (*copy_dma)(struct radeon_device *rdev,
586 uint64_t src_offset,
587 uint64_t dst_offset,
588 unsigned num_pages,
589 struct radeon_fence *fence);
590 int (*copy)(struct radeon_device *rdev,
591 uint64_t src_offset,
592 uint64_t dst_offset,
593 unsigned num_pages,
594 struct radeon_fence *fence);
595 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
596 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
597 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
598 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 599 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
600 uint32_t tiling_flags, uint32_t pitch,
601 uint32_t offset, uint32_t obj_size);
602 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 603 void (*bandwidth_update)(struct radeon_device *rdev);
771fe6b9
JG		 604};
605
068a117c
JG		 606union radeon_asic_config {
607 struct r300_asic r300;
608};
609
771fe6b9
JG		 610
611/*
612 * IOCTL.
613 */
614int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
615 struct drm_file *filp);
616int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
617 struct drm_file *filp);
618int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
619 struct drm_file *file_priv);
620int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
621 struct drm_file *file_priv);
622int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
623 struct drm_file *file_priv);
624int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
625 struct drm_file *file_priv);
626int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
627 struct drm_file *filp);
628int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
629 struct drm_file *filp);
630int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
631 struct drm_file *filp);
632int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
633 struct drm_file *filp);
634int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 635int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
636 struct drm_file *filp);
637int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
638 struct drm_file *filp);
771fe6b9
JG		 639
640
641/*
642 * Core structure, functions and helpers.
643 */
644typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
645typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
646
647struct radeon_device {
648 struct drm_device *ddev;
649 struct pci_dev *pdev;
650 /* ASIC */
068a117c 651 union radeon_asic_config config;
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JG		 652 enum radeon_family family;
653 unsigned long flags;
654 int usec_timeout;
655 enum radeon_pll_errata pll_errata;
656 int num_gb_pipes;
657 int disp_priority;
658 /* BIOS */
659 uint8_t *bios;
660 bool is_atom_bios;
661 uint16_t bios_header_start;
662 struct radeon_object *stollen_vga_memory;
663 struct fb_info *fbdev_info;
664 struct radeon_object *fbdev_robj;
665 struct radeon_framebuffer *fbdev_rfb;
666 /* Register mmio */
4c9bc75c
DA		 667 resource_size_t rmmio_base;
668 resource_size_t rmmio_size;
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JG		 669 void *rmmio;
670 radeon_rreg_t mm_rreg;
671 radeon_wreg_t mm_wreg;
672 radeon_rreg_t mc_rreg;
673 radeon_wreg_t mc_wreg;
674 radeon_rreg_t pll_rreg;
675 radeon_wreg_t pll_wreg;
676 radeon_rreg_t pcie_rreg;
677 radeon_wreg_t pcie_wreg;
678 radeon_rreg_t pciep_rreg;
679 radeon_wreg_t pciep_wreg;
680 struct radeon_clock clock;
681 struct radeon_mc mc;
682 struct radeon_gart gart;
683 struct radeon_mode_info mode_info;
684 struct radeon_scratch scratch;
685 struct radeon_mman mman;
686 struct radeon_fence_driver fence_drv;
687 struct radeon_cp cp;
688 struct radeon_ib_pool ib_pool;
689 struct radeon_irq irq;
690 struct radeon_asic *asic;
691 struct radeon_gem gem;
c93bb85b 692 struct radeon_pm pm;
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JG		 693 struct mutex cs_mutex;
694 struct radeon_wb wb;
695 bool gpu_lockup;
696 bool shutdown;
697 bool suspend;
ad49f501 698 bool need_dma32;
e024e110 699 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
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JG		 700};
701
702int radeon_device_init(struct radeon_device *rdev,
703 struct drm_device *ddev,
704 struct pci_dev *pdev,
705 uint32_t flags);
706void radeon_device_fini(struct radeon_device *rdev);
707int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
708
709
710/*
711 * Registers read & write functions.
712 */
713#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
714#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
715#define RREG32(reg) rdev->mm_rreg(rdev, (reg))
716#define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v))
717#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
718#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
719#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
720#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
721#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
722#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
723#define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg))
724#define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v))
725#define WREG32_P(reg, val, mask) \
726 do { \
727 uint32_t tmp_ = RREG32(reg); \
728 tmp_ &= (mask); \
729 tmp_ |= ((val) & ~(mask)); \
730 WREG32(reg, tmp_); \
731 } while (0)
732#define WREG32_PLL_P(reg, val, mask) \
733 do { \
734 uint32_t tmp_ = RREG32_PLL(reg); \
735 tmp_ &= (mask); \
736 tmp_ |= ((val) & ~(mask)); \
737 WREG32_PLL(reg, tmp_); \
738 } while (0)
739
740void r100_pll_errata_after_index(struct radeon_device *rdev);
741
742
743/*
744 * ASICs helpers.
745 */
b995e433
DA		 746#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
747 (rdev->pdev->device == 0x5969))
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JG		 748#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
749 (rdev->family == CHIP_RV200) || \
750 (rdev->family == CHIP_RS100) || \
751 (rdev->family == CHIP_RS200) || \
752 (rdev->family == CHIP_RV250) || \
753 (rdev->family == CHIP_RV280) || \
754 (rdev->family == CHIP_RS300))
755#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
756 (rdev->family == CHIP_RV350) || \
757 (rdev->family == CHIP_R350) || \
758 (rdev->family == CHIP_RV380) || \
759 (rdev->family == CHIP_R420) || \
760 (rdev->family == CHIP_R423) || \
761 (rdev->family == CHIP_RV410) || \
762 (rdev->family == CHIP_RS400) || \
763 (rdev->family == CHIP_RS480))
764#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
765#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
766#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
767
768
769/*
770 * BIOS helpers.
771 */
772#define RBIOS8(i) (rdev->bios[i])
773#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
774#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
775
776int radeon_combios_init(struct radeon_device *rdev);
777void radeon_combios_fini(struct radeon_device *rdev);
778int radeon_atombios_init(struct radeon_device *rdev);
779void radeon_atombios_fini(struct radeon_device *rdev);
780
781
782/*
783 * RING helpers.
784 */
785#define CP_PACKET0 0x00000000
786#define PACKET0_BASE_INDEX_SHIFT 0
787#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
788#define PACKET0_COUNT_SHIFT 16
789#define PACKET0_COUNT_MASK (0x3fff << 16)
790#define CP_PACKET1 0x40000000
791#define CP_PACKET2 0x80000000
792#define PACKET2_PAD_SHIFT 0
793#define PACKET2_PAD_MASK (0x3fffffff << 0)
794#define CP_PACKET3 0xC0000000
795#define PACKET3_IT_OPCODE_SHIFT 8
796#define PACKET3_IT_OPCODE_MASK (0xff << 8)
797#define PACKET3_COUNT_SHIFT 16
798#define PACKET3_COUNT_MASK (0x3fff << 16)
799/* PACKET3 op code */
800#define PACKET3_NOP 0x10
801#define PACKET3_3D_DRAW_VBUF 0x28
802#define PACKET3_3D_DRAW_IMMD 0x29
803#define PACKET3_3D_DRAW_INDX 0x2A
804#define PACKET3_3D_LOAD_VBPNTR 0x2F
805#define PACKET3_INDX_BUFFER 0x33
806#define PACKET3_3D_DRAW_VBUF_2 0x34
807#define PACKET3_3D_DRAW_IMMD_2 0x35
808#define PACKET3_3D_DRAW_INDX_2 0x36
809#define PACKET3_BITBLT_MULTI 0x9B
810
811#define PACKET0(reg, n) (CP_PACKET0 | \
812 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
813 REG_SET(PACKET0_COUNT, (n)))
814#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
815#define PACKET3(op, n) (CP_PACKET3 | \
816 REG_SET(PACKET3_IT_OPCODE, (op)) | \
817 REG_SET(PACKET3_COUNT, (n)))
818
819#define PACKET_TYPE0 0
820#define PACKET_TYPE1 1
821#define PACKET_TYPE2 2
822#define PACKET_TYPE3 3
823
824#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
825#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
826#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
827#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
828#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
829
830static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
831{
832#if DRM_DEBUG_CODE
833 if (rdev->cp.count_dw <= 0) {
834 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
835 }
836#endif
837 rdev->cp.ring[rdev->cp.wptr++] = v;
838 rdev->cp.wptr &= rdev->cp.ptr_mask;
839 rdev->cp.count_dw--;
840 rdev->cp.ring_free_dw--;
841}
842
843
844/*
845 * ASICs macro.
846 */
068a117c 847#define radeon_init(rdev) (rdev)->asic->init((rdev))
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JG		 848#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
849#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
850#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
851#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
852#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
853#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
854#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
855#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
856#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
857#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
858#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
859#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
860#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
861#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
862#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
863#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
864#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
865#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 866#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
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JG		 867#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
868#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
869#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
870#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
871#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
872#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
873#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
874#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 875#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
876#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 877#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
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JG		 878
879#endif
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