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drm/radeon/kms/igp: fix possible divide by 0 in bandwidth code (v2)
[net-next-2.6.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
771fe6b9 32#include "drmP.h"
3ce0a23d 33#include "radeon_drm.h"
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
771fe6b9 40
3ce0a23d
JG		 41#define PFP_UCODE_SIZE 576
42#define PM4_UCODE_SIZE 1792
d8f60cfc 43#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 44#define R700_PFP_UCODE_SIZE 848
45#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 46#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 47#define EVERGREEN_PFP_UCODE_SIZE 1120
48#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 49#define EVERGREEN_RLC_UCODE_SIZE 768
3ce0a23d
JG		 50
51/* Firmware Names */
52MODULE_FIRMWARE("radeon/R600_pfp.bin");
53MODULE_FIRMWARE("radeon/R600_me.bin");
54MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55MODULE_FIRMWARE("radeon/RV610_me.bin");
56MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57MODULE_FIRMWARE("radeon/RV630_me.bin");
58MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59MODULE_FIRMWARE("radeon/RV620_me.bin");
60MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61MODULE_FIRMWARE("radeon/RV635_me.bin");
62MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63MODULE_FIRMWARE("radeon/RV670_me.bin");
64MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65MODULE_FIRMWARE("radeon/RS780_me.bin");
66MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67MODULE_FIRMWARE("radeon/RV770_me.bin");
68MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69MODULE_FIRMWARE("radeon/RV730_me.bin");
70MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 72MODULE_FIRMWARE("radeon/R600_rlc.bin");
73MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 74MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 76MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 80MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 82MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 83MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 84MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 85MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
3ce0a23d
JG		 86
87int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 88
1a029b76 89/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 90int r600_mc_wait_for_idle(struct radeon_device *rdev);
91void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 92void r600_fini(struct radeon_device *rdev);
45f9a39b 93void r600_irq_disable(struct radeon_device *rdev);
771fe6b9 94
ce8f5370 95void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 96{
97 int i;
98
ce8f5370
AD		 99 rdev->pm.dynpm_can_upclock = true;
100 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 101
102 /* power state array is low to high, default is first */
103 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
104 int min_power_state_index = 0;
105
106 if (rdev->pm.num_power_states > 2)
107 min_power_state_index = 1;
108
ce8f5370
AD		 109 switch (rdev->pm.dynpm_planned_action) {
110 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 111 rdev->pm.requested_power_state_index = min_power_state_index;
112 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 113 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 114 break;
ce8f5370 115 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 116 if (rdev->pm.current_power_state_index == min_power_state_index) {
117 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 118 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 119 } else {
120 if (rdev->pm.active_crtc_count > 1) {
121 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 122 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 123 continue;
124 else if (i >= rdev->pm.current_power_state_index) {
125 rdev->pm.requested_power_state_index =
126 rdev->pm.current_power_state_index;
127 break;
128 } else {
129 rdev->pm.requested_power_state_index = i;
130 break;
131 }
132 }
133 } else
134 rdev->pm.requested_power_state_index =
135 rdev->pm.current_power_state_index - 1;
136 }
137 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 138 /* don't use the power state if crtcs are active and no display flag is set */
139 if ((rdev->pm.active_crtc_count > 0) &&
140 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
141 clock_info[rdev->pm.requested_clock_mode_index].flags &
142 RADEON_PM_MODE_NO_DISPLAY)) {
143 rdev->pm.requested_power_state_index++;
144 }
a48b9b4e 145 break;
ce8f5370 146 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 147 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
148 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 149 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 150 } else {
151 if (rdev->pm.active_crtc_count > 1) {
152 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 153 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 154 continue;
155 else if (i <= rdev->pm.current_power_state_index) {
156 rdev->pm.requested_power_state_index =
157 rdev->pm.current_power_state_index;
158 break;
159 } else {
160 rdev->pm.requested_power_state_index = i;
161 break;
162 }
163 }
164 } else
165 rdev->pm.requested_power_state_index =
166 rdev->pm.current_power_state_index + 1;
167 }
168 rdev->pm.requested_clock_mode_index = 0;
169 break;
ce8f5370 170 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 171 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
172 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 173 rdev->pm.dynpm_can_upclock = false;
58e21dff 174 break;
ce8f5370 175 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 176 default:
177 DRM_ERROR("Requested mode for not defined action\n");
178 return;
179 }
180 } else {
181 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
182 /* for now just select the first power state and switch between clock modes */
183 /* power state array is low to high, default is first (0) */
184 if (rdev->pm.active_crtc_count > 1) {
185 rdev->pm.requested_power_state_index = -1;
186 /* start at 1 as we don't want the default mode */
187 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 188 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 189 continue;
190 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
191 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
192 rdev->pm.requested_power_state_index = i;
193 break;
194 }
195 }
196 /* if nothing selected, grab the default state. */
197 if (rdev->pm.requested_power_state_index == -1)
198 rdev->pm.requested_power_state_index = 0;
199 } else
200 rdev->pm.requested_power_state_index = 1;
201
ce8f5370
AD		 202 switch (rdev->pm.dynpm_planned_action) {
203 case DYNPM_ACTION_MINIMUM:
a48b9b4e 204 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 205 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 206 break;
ce8f5370 207 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 208 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
209 if (rdev->pm.current_clock_mode_index == 0) {
210 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 211 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 212 } else
213 rdev->pm.requested_clock_mode_index =
214 rdev->pm.current_clock_mode_index - 1;
215 } else {
216 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 217 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 218 }
d7311171
AD		 219 /* don't use the power state if crtcs are active and no display flag is set */
220 if ((rdev->pm.active_crtc_count > 0) &&
221 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
222 clock_info[rdev->pm.requested_clock_mode_index].flags &
223 RADEON_PM_MODE_NO_DISPLAY)) {
224 rdev->pm.requested_clock_mode_index++;
225 }
a48b9b4e 226 break;
ce8f5370 227 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 228 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
229 if (rdev->pm.current_clock_mode_index ==
230 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
231 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 232 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 233 } else
234 rdev->pm.requested_clock_mode_index =
235 rdev->pm.current_clock_mode_index + 1;
236 } else {
237 rdev->pm.requested_clock_mode_index =
238 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 239 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 240 }
241 break;
ce8f5370 242 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 243 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
244 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 245 rdev->pm.dynpm_can_upclock = false;
58e21dff 246 break;
ce8f5370 247 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 248 default:
249 DRM_ERROR("Requested mode for not defined action\n");
250 return;
251 }
252 }
253
ce8a3eb2
AD		 254 DRM_DEBUG("Requested: e: %d m: %d p: %d\n",
255 rdev->pm.power_state[rdev->pm.requested_power_state_index].
256 clock_info[rdev->pm.requested_clock_mode_index].sclk,
257 rdev->pm.power_state[rdev->pm.requested_power_state_index].
258 clock_info[rdev->pm.requested_clock_mode_index].mclk,
259 rdev->pm.power_state[rdev->pm.requested_power_state_index].
260 pcie_lanes);
a48b9b4e
AD		 261}
262
ce8f5370
AD		 263static int r600_pm_get_type_index(struct radeon_device *rdev,
264 enum radeon_pm_state_type ps_type,
265 int instance)
bae6b562 266{
ce8f5370
AD		 267 int i;
268 int found_instance = -1;
bae6b562 269
ce8f5370
AD		 270 for (i = 0; i < rdev->pm.num_power_states; i++) {
271 if (rdev->pm.power_state[i].type == ps_type) {
272 found_instance++;
273 if (found_instance == instance)
274 return i;
a424816f 275 }
ce8f5370
AD		 276 }
277 /* return default if no match */
278 return rdev->pm.default_power_state_index;
279}
280
281void rs780_pm_init_profile(struct radeon_device *rdev)
282{
283 if (rdev->pm.num_power_states == 2) {
284 /* default */
285 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
286 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
287 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
288 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
289 /* low sh */
290 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
291 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
292 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
293 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 294 /* mid sh */
295 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
296 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
297 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
298 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 299 /* high sh */
300 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
301 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
302 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
304 /* low mh */
305 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 309 /* mid mh */
310 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 314 /* high mh */
315 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
317 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
319 } else if (rdev->pm.num_power_states == 3) {
320 /* default */
321 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
322 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
323 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
325 /* low sh */
326 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
327 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
328 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 330 /* mid sh */
331 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
332 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
333 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 335 /* high sh */
336 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
337 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
338 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
340 /* low mh */
341 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
342 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 345 /* mid mh */
346 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 350 /* high mh */
351 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
352 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
353 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
355 } else {
356 /* default */
357 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
358 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
359 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
360 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
361 /* low sh */
362 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
363 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
364 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
365 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 366 /* mid sh */
367 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
368 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
369 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
370 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 371 /* high sh */
372 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
373 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
374 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
375 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
376 /* low mh */
377 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
378 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
379 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
380 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 381 /* mid mh */
382 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
384 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
385 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 386 /* high mh */
387 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
388 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
389 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
391 }
392}
bae6b562 393
ce8f5370
AD		 394void r600_pm_init_profile(struct radeon_device *rdev)
395{
396 if (rdev->family == CHIP_R600) {
397 /* XXX */
398 /* default */
399 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
400 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
401 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 402 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 403 /* low sh */
404 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
405 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
406 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 407 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 408 /* mid sh */
409 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
410 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
411 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
412 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 413 /* high sh */
414 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
415 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
416 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 417 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 418 /* low mh */
419 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
420 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
421 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 422 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 423 /* mid mh */
424 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
425 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
426 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
427 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 428 /* high mh */
429 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
430 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
431 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 432 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 433 } else {
434 if (rdev->pm.num_power_states < 4) {
435 /* default */
436 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
437 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
439 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
440 /* low sh */
4bff5171
AD		 441 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
442 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 443 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 444 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
445 /* mid sh */
446 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
447 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
448 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
449 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 450 /* high sh */
4bff5171
AD		 451 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
452 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 453 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
454 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
455 /* low mh */
4bff5171
AD		 456 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
457 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 458 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 459 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
460 /* low mh */
461 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
462 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
463 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
464 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 465 /* high mh */
4bff5171
AD		 466 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
467 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 468 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
469 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
470 } else {
471 /* default */
472 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
473 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
474 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
475 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
476 /* low sh */
4bff5171
AD		 477 if (rdev->flags & RADEON_IS_MOBILITY) {
478 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
479 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
480 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
481 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
482 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21 483 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 484 } else {
485 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
486 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
487 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
488 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
489 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 490 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
491 }
492 /* mid sh */
493 if (rdev->flags & RADEON_IS_MOBILITY) {
494 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
495 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
496 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
497 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
500 } else {
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
502 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
503 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
504 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
506 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
4bff5171 507 }
ce8f5370 508 /* high sh */
4bff5171
AD		 509 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
510 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
511 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
512 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
ce8f5370
AD		 513 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
514 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
515 /* low mh */
4bff5171
AD		 516 if (rdev->flags & RADEON_IS_MOBILITY) {
517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
518 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
519 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
520 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
521 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21 522 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 523 } else {
524 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
525 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
526 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
527 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
528 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 529 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
530 }
531 /* mid mh */
532 if (rdev->flags & RADEON_IS_MOBILITY) {
533 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
534 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
535 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
536 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
537 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
538 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
539 } else {
540 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
541 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
542 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
543 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
544 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
545 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
4bff5171 546 }
ce8f5370 547 /* high mh */
4bff5171
AD		 548 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
549 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
550 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
551 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
ce8f5370
AD		 552 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
553 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
554 }
555 }
bae6b562
AD		 556}
557
49e02b73
AD		 558void r600_pm_misc(struct radeon_device *rdev)
559{
a081a9d6
RM		 560 int req_ps_idx = rdev->pm.requested_power_state_index;
561 int req_cm_idx = rdev->pm.requested_clock_mode_index;
562 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
563 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 564
4d60173f
AD		 565 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
566 if (voltage->voltage != rdev->pm.current_vddc) {
567 radeon_atom_set_voltage(rdev, voltage->voltage);
568 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 569 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 570 }
571 }
49e02b73
AD		 572}
573
def9ba9c
AD		 574bool r600_gui_idle(struct radeon_device *rdev)
575{
576 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
577 return false;
578 else
579 return true;
580}
581
e0df1ac5
AD		 582/* hpd for digital panel detect/disconnect */
583bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
584{
585 bool connected = false;
586
587 if (ASIC_IS_DCE3(rdev)) {
588 switch (hpd) {
589 case RADEON_HPD_1:
590 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
591 connected = true;
592 break;
593 case RADEON_HPD_2:
594 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
595 connected = true;
596 break;
597 case RADEON_HPD_3:
598 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
599 connected = true;
600 break;
601 case RADEON_HPD_4:
602 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
603 connected = true;
604 break;
605 /* DCE 3.2 */
606 case RADEON_HPD_5:
607 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
608 connected = true;
609 break;
610 case RADEON_HPD_6:
611 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
612 connected = true;
613 break;
614 default:
615 break;
616 }
617 } else {
618 switch (hpd) {
619 case RADEON_HPD_1:
620 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
621 connected = true;
622 break;
623 case RADEON_HPD_2:
624 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
625 connected = true;
626 break;
627 case RADEON_HPD_3:
628 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
629 connected = true;
630 break;
631 default:
632 break;
633 }
634 }
635 return connected;
636}
637
638void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 639 enum radeon_hpd_id hpd)
e0df1ac5
AD		 640{
641 u32 tmp;
642 bool connected = r600_hpd_sense(rdev, hpd);
643
644 if (ASIC_IS_DCE3(rdev)) {
645 switch (hpd) {
646 case RADEON_HPD_1:
647 tmp = RREG32(DC_HPD1_INT_CONTROL);
648 if (connected)
649 tmp &= ~DC_HPDx_INT_POLARITY;
650 else
651 tmp |= DC_HPDx_INT_POLARITY;
652 WREG32(DC_HPD1_INT_CONTROL, tmp);
653 break;
654 case RADEON_HPD_2:
655 tmp = RREG32(DC_HPD2_INT_CONTROL);
656 if (connected)
657 tmp &= ~DC_HPDx_INT_POLARITY;
658 else
659 tmp |= DC_HPDx_INT_POLARITY;
660 WREG32(DC_HPD2_INT_CONTROL, tmp);
661 break;
662 case RADEON_HPD_3:
663 tmp = RREG32(DC_HPD3_INT_CONTROL);
664 if (connected)
665 tmp &= ~DC_HPDx_INT_POLARITY;
666 else
667 tmp |= DC_HPDx_INT_POLARITY;
668 WREG32(DC_HPD3_INT_CONTROL, tmp);
669 break;
670 case RADEON_HPD_4:
671 tmp = RREG32(DC_HPD4_INT_CONTROL);
672 if (connected)
673 tmp &= ~DC_HPDx_INT_POLARITY;
674 else
675 tmp |= DC_HPDx_INT_POLARITY;
676 WREG32(DC_HPD4_INT_CONTROL, tmp);
677 break;
678 case RADEON_HPD_5:
679 tmp = RREG32(DC_HPD5_INT_CONTROL);
680 if (connected)
681 tmp &= ~DC_HPDx_INT_POLARITY;
682 else
683 tmp |= DC_HPDx_INT_POLARITY;
684 WREG32(DC_HPD5_INT_CONTROL, tmp);
685 break;
686 /* DCE 3.2 */
687 case RADEON_HPD_6:
688 tmp = RREG32(DC_HPD6_INT_CONTROL);
689 if (connected)
690 tmp &= ~DC_HPDx_INT_POLARITY;
691 else
692 tmp |= DC_HPDx_INT_POLARITY;
693 WREG32(DC_HPD6_INT_CONTROL, tmp);
694 break;
695 default:
696 break;
697 }
698 } else {
699 switch (hpd) {
700 case RADEON_HPD_1:
701 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
702 if (connected)
703 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
704 else
705 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
706 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
707 break;
708 case RADEON_HPD_2:
709 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
710 if (connected)
711 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
712 else
713 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
714 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
715 break;
716 case RADEON_HPD_3:
717 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
718 if (connected)
719 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
720 else
721 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
722 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
723 break;
724 default:
725 break;
726 }
727 }
728}
729
730void r600_hpd_init(struct radeon_device *rdev)
731{
732 struct drm_device *dev = rdev->ddev;
733 struct drm_connector *connector;
734
735 if (ASIC_IS_DCE3(rdev)) {
736 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
737 if (ASIC_IS_DCE32(rdev))
738 tmp |= DC_HPDx_EN;
739
740 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
741 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
742 switch (radeon_connector->hpd.hpd) {
743 case RADEON_HPD_1:
744 WREG32(DC_HPD1_CONTROL, tmp);
745 rdev->irq.hpd[0] = true;
746 break;
747 case RADEON_HPD_2:
748 WREG32(DC_HPD2_CONTROL, tmp);
749 rdev->irq.hpd[1] = true;
750 break;
751 case RADEON_HPD_3:
752 WREG32(DC_HPD3_CONTROL, tmp);
753 rdev->irq.hpd[2] = true;
754 break;
755 case RADEON_HPD_4:
756 WREG32(DC_HPD4_CONTROL, tmp);
757 rdev->irq.hpd[3] = true;
758 break;
759 /* DCE 3.2 */
760 case RADEON_HPD_5:
761 WREG32(DC_HPD5_CONTROL, tmp);
762 rdev->irq.hpd[4] = true;
763 break;
764 case RADEON_HPD_6:
765 WREG32(DC_HPD6_CONTROL, tmp);
766 rdev->irq.hpd[5] = true;
767 break;
768 default:
769 break;
770 }
771 }
772 } else {
773 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
774 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
775 switch (radeon_connector->hpd.hpd) {
776 case RADEON_HPD_1:
777 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
778 rdev->irq.hpd[0] = true;
779 break;
780 case RADEON_HPD_2:
781 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
782 rdev->irq.hpd[1] = true;
783 break;
784 case RADEON_HPD_3:
785 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
786 rdev->irq.hpd[2] = true;
787 break;
788 default:
789 break;
790 }
791 }
792 }
003e69f9
JG		 793 if (rdev->irq.installed)
794 r600_irq_set(rdev);
e0df1ac5
AD		 795}
796
797void r600_hpd_fini(struct radeon_device *rdev)
798{
799 struct drm_device *dev = rdev->ddev;
800 struct drm_connector *connector;
801
802 if (ASIC_IS_DCE3(rdev)) {
803 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
804 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
805 switch (radeon_connector->hpd.hpd) {
806 case RADEON_HPD_1:
807 WREG32(DC_HPD1_CONTROL, 0);
808 rdev->irq.hpd[0] = false;
809 break;
810 case RADEON_HPD_2:
811 WREG32(DC_HPD2_CONTROL, 0);
812 rdev->irq.hpd[1] = false;
813 break;
814 case RADEON_HPD_3:
815 WREG32(DC_HPD3_CONTROL, 0);
816 rdev->irq.hpd[2] = false;
817 break;
818 case RADEON_HPD_4:
819 WREG32(DC_HPD4_CONTROL, 0);
820 rdev->irq.hpd[3] = false;
821 break;
822 /* DCE 3.2 */
823 case RADEON_HPD_5:
824 WREG32(DC_HPD5_CONTROL, 0);
825 rdev->irq.hpd[4] = false;
826 break;
827 case RADEON_HPD_6:
828 WREG32(DC_HPD6_CONTROL, 0);
829 rdev->irq.hpd[5] = false;
830 break;
831 default:
832 break;
833 }
834 }
835 } else {
836 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
837 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
838 switch (radeon_connector->hpd.hpd) {
839 case RADEON_HPD_1:
840 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
841 rdev->irq.hpd[0] = false;
842 break;
843 case RADEON_HPD_2:
844 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
845 rdev->irq.hpd[1] = false;
846 break;
847 case RADEON_HPD_3:
848 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
849 rdev->irq.hpd[2] = false;
850 break;
851 default:
852 break;
853 }
854 }
855 }
856}
857
771fe6b9 858/*
3ce0a23d 859 * R600 PCIE GART
771fe6b9 860 */
3ce0a23d
JG		 861void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
862{
863 unsigned i;
864 u32 tmp;
865
2e98f10a
DA		 866 /* flush hdp cache so updates hit vram */
867 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
868
3ce0a23d
JG		 869 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
870 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
871 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
872 for (i = 0; i < rdev->usec_timeout; i++) {
873 /* read MC_STATUS */
874 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
875 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
876 if (tmp == 2) {
877 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
878 return;
879 }
880 if (tmp) {
881 return;
882 }
883 udelay(1);
884 }
885}
886
4aac0473 887int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 888{
4aac0473 889 int r;
3ce0a23d 890
4aac0473
JG		 891 if (rdev->gart.table.vram.robj) {
892 WARN(1, "R600 PCIE GART already initialized.\n");
893 return 0;
894 }
3ce0a23d
JG		 895 /* Initialize common gart structure */
896 r = radeon_gart_init(rdev);
4aac0473 897 if (r)
3ce0a23d 898 return r;
3ce0a23d 899 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 900 return radeon_gart_table_vram_alloc(rdev);
901}
902
903int r600_pcie_gart_enable(struct radeon_device *rdev)
904{
905 u32 tmp;
906 int r, i;
907
908 if (rdev->gart.table.vram.robj == NULL) {
909 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
910 return -EINVAL;
771fe6b9 911 }
4aac0473
JG		 912 r = radeon_gart_table_vram_pin(rdev);
913 if (r)
914 return r;
82568565 915 radeon_gart_restore(rdev);
bc1a631e 916
3ce0a23d
JG		 917 /* Setup L2 cache */
918 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
919 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
920 EFFECTIVE_L2_QUEUE_SIZE(7));
921 WREG32(VM_L2_CNTL2, 0);
922 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
923 /* Setup TLB control */
924 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
925 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
926 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
927 ENABLE_WAIT_L2_QUERY;
928 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
929 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
930 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
931 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
932 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
933 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
934 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
935 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
936 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
937 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
938 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
939 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
940 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
941 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
942 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 943 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 944 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
945 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
946 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
947 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
948 (u32)(rdev->dummy_page.addr >> 12));
949 for (i = 1; i < 7; i++)
950 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 951
3ce0a23d
JG		 952 r600_pcie_gart_tlb_flush(rdev);
953 rdev->gart.ready = true;
771fe6b9
JG		 954 return 0;
955}
956
3ce0a23d 957void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 958{
3ce0a23d 959 u32 tmp;
4c788679 960 int i, r;
771fe6b9 961
3ce0a23d
JG		 962 /* Disable all tables */
963 for (i = 0; i < 7; i++)
964 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 965
3ce0a23d
JG		 966 /* Disable L2 cache */
967 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
968 EFFECTIVE_L2_QUEUE_SIZE(7));
969 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
970 /* Setup L1 TLB control */
971 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
972 ENABLE_WAIT_L2_QUERY;
973 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
974 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
980 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
981 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
982 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
983 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
984 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
985 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
986 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473 987 if (rdev->gart.table.vram.robj) {
4c788679
JG		 988 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
989 if (likely(r == 0)) {
990 radeon_bo_kunmap(rdev->gart.table.vram.robj);
991 radeon_bo_unpin(rdev->gart.table.vram.robj);
992 radeon_bo_unreserve(rdev->gart.table.vram.robj);
993 }
4aac0473
JG		 994 }
995}
996
997void r600_pcie_gart_fini(struct radeon_device *rdev)
998{
f9274562 999 radeon_gart_fini(rdev);
4aac0473
JG		 1000 r600_pcie_gart_disable(rdev);
1001 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1002}
1003
1a029b76
JG		 1004void r600_agp_enable(struct radeon_device *rdev)
1005{
1006 u32 tmp;
1007 int i;
1008
1009 /* Setup L2 cache */
1010 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1011 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1012 EFFECTIVE_L2_QUEUE_SIZE(7));
1013 WREG32(VM_L2_CNTL2, 0);
1014 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1015 /* Setup TLB control */
1016 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1017 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1018 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1019 ENABLE_WAIT_L2_QUERY;
1020 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1021 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1022 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1023 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1024 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1025 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1026 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1027 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1028 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1029 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1030 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1031 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1032 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1033 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1034 for (i = 0; i < 7; i++)
1035 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1036}
1037
771fe6b9
JG		 1038int r600_mc_wait_for_idle(struct radeon_device *rdev)
1039{
3ce0a23d
JG		 1040 unsigned i;
1041 u32 tmp;
1042
1043 for (i = 0; i < rdev->usec_timeout; i++) {
1044 /* read MC_STATUS */
1045 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1046 if (!tmp)
1047 return 0;
1048 udelay(1);
1049 }
1050 return -1;
771fe6b9
JG		 1051}
1052
a3c1945a 1053static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1054{
a3c1945a 1055 struct rv515_mc_save save;
3ce0a23d
JG		 1056 u32 tmp;
1057 int i, j;
771fe6b9 1058
3ce0a23d
JG		 1059 /* Initialize HDP */
1060 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1061 WREG32((0x2c14 + j), 0x00000000);
1062 WREG32((0x2c18 + j), 0x00000000);
1063 WREG32((0x2c1c + j), 0x00000000);
1064 WREG32((0x2c20 + j), 0x00000000);
1065 WREG32((0x2c24 + j), 0x00000000);
1066 }
1067 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1068
a3c1945a 1069 rv515_mc_stop(rdev, &save);
3ce0a23d 1070 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1071 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1072 }
a3c1945a 1073 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1074 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1075 /* Update configuration */
1a029b76
JG		 1076 if (rdev->flags & RADEON_IS_AGP) {
1077 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1078 /* VRAM before AGP */
1079 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1080 rdev->mc.vram_start >> 12);
1081 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1082 rdev->mc.gtt_end >> 12);
1083 } else {
1084 /* VRAM after AGP */
1085 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1086 rdev->mc.gtt_start >> 12);
1087 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1088 rdev->mc.vram_end >> 12);
1089 }
1090 } else {
1091 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1092 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1093 }
3ce0a23d 1094 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 1095 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1096 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1097 WREG32(MC_VM_FB_LOCATION, tmp);
1098 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1099 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1100 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1101 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1102 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1103 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1104 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1105 } else {
1106 WREG32(MC_VM_AGP_BASE, 0);
1107 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1108 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1109 }
3ce0a23d 1110 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1111 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1112 }
a3c1945a 1113 rv515_mc_resume(rdev, &save);
698443d9
DA		 1114 /* we need to own VRAM, so turn off the VGA renderer here
1115 * to stop it overwriting our objects */
d39c3b89 1116 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1117}
1118
d594e46a
JG		 1119/**
1120 * r600_vram_gtt_location - try to find VRAM & GTT location
1121 * @rdev: radeon device structure holding all necessary informations
1122 * @mc: memory controller structure holding memory informations
1123 *
1124 * Function will place try to place VRAM at same place as in CPU (PCI)
1125 * address space as some GPU seems to have issue when we reprogram at
1126 * different address space.
1127 *
1128 * If there is not enough space to fit the unvisible VRAM after the
1129 * aperture then we limit the VRAM size to the aperture.
1130 *
1131 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1132 * them to be in one from GPU point of view so that we can program GPU to
1133 * catch access outside them (weird GPU policy see ??).
1134 *
1135 * This function will never fails, worst case are limiting VRAM or GTT.
1136 *
1137 * Note: GTT start, end, size should be initialized before calling this
1138 * function on AGP platform.
1139 */
1140void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1141{
1142 u64 size_bf, size_af;
1143
1144 if (mc->mc_vram_size > 0xE0000000) {
1145 /* leave room for at least 512M GTT */
1146 dev_warn(rdev->dev, "limiting VRAM\n");
1147 mc->real_vram_size = 0xE0000000;
1148 mc->mc_vram_size = 0xE0000000;
1149 }
1150 if (rdev->flags & RADEON_IS_AGP) {
1151 size_bf = mc->gtt_start;
1152 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1153 if (size_bf > size_af) {
1154 if (mc->mc_vram_size > size_bf) {
1155 dev_warn(rdev->dev, "limiting VRAM\n");
1156 mc->real_vram_size = size_bf;
1157 mc->mc_vram_size = size_bf;
1158 }
1159 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1160 } else {
1161 if (mc->mc_vram_size > size_af) {
1162 dev_warn(rdev->dev, "limiting VRAM\n");
1163 mc->real_vram_size = size_af;
1164 mc->mc_vram_size = size_af;
1165 }
1166 mc->vram_start = mc->gtt_end;
1167 }
1168 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1169 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1170 mc->mc_vram_size >> 20, mc->vram_start,
1171 mc->vram_end, mc->real_vram_size >> 20);
1172 } else {
1173 u64 base = 0;
1174 if (rdev->flags & RADEON_IS_IGP)
1175 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1176 radeon_vram_location(rdev, &rdev->mc, base);
1177 radeon_gtt_location(rdev, mc);
1178 }
1179}
1180
3ce0a23d 1181int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1182{
3ce0a23d 1183 u32 tmp;
5885b7a9 1184 int chansize, numchan;
771fe6b9 1185
3ce0a23d 1186 /* Get VRAM informations */
771fe6b9 1187 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1188 tmp = RREG32(RAMCFG);
1189 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1190 chansize = 16;
3ce0a23d 1191 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1192 chansize = 64;
1193 } else {
1194 chansize = 32;
1195 }
5885b7a9
AD		 1196 tmp = RREG32(CHMAP);
1197 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1198 case 0:
1199 default:
1200 numchan = 1;
1201 break;
1202 case 1:
1203 numchan = 2;
1204 break;
1205 case 2:
1206 numchan = 4;
1207 break;
1208 case 3:
1209 numchan = 8;
1210 break;
771fe6b9 1211 }
5885b7a9 1212 rdev->mc.vram_width = numchan * chansize;
3ce0a23d
JG		 1213 /* Could aper size report 0 ? */
1214 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1215 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1216 /* Setup GPU memory space */
1217 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1218 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1219 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1220 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1221
f892034a
AD		 1222 if (rdev->flags & RADEON_IS_IGP) {
1223 rs690_pm_info(rdev);
06b6476d 1224 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f892034a 1225 }
f47299c5 1226 radeon_update_bandwidth_info(rdev);
3ce0a23d 1227 return 0;
771fe6b9
JG		 1228}
1229
3ce0a23d
JG		 1230/* We doesn't check that the GPU really needs a reset we simply do the
1231 * reset, it's up to the caller to determine if the GPU needs one. We
1232 * might add an helper function to check that.
1233 */
1234int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 1235{
a3c1945a 1236 struct rv515_mc_save save;
3ce0a23d
JG		 1237 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1238 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1239 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1240 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1241 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1242 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1243 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1244 S_008010_GUI_ACTIVE(1);
1245 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1246 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1247 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1248 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1249 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1250 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1251 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1252 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 1253 u32 tmp;
771fe6b9 1254
1a029b76
JG		 1255 dev_info(rdev->dev, "GPU softreset \n");
1256 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1257 RREG32(R_008010_GRBM_STATUS));
1258 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 1259 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 1260 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1261 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 1262 rv515_mc_stop(rdev, &save);
1263 if (r600_mc_wait_for_idle(rdev)) {
1264 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1265 }
3ce0a23d 1266 /* Disable CP parsing/prefetching */
90aca4d2 1267 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 1268 /* Check if any of the rendering block is busy and reset it */
1269 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1270 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 1271 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 1272 S_008020_SOFT_RESET_DB(1) |
1273 S_008020_SOFT_RESET_CB(1) |
1274 S_008020_SOFT_RESET_PA(1) |
1275 S_008020_SOFT_RESET_SC(1) |
1276 S_008020_SOFT_RESET_SMX(1) |
1277 S_008020_SOFT_RESET_SPI(1) |
1278 S_008020_SOFT_RESET_SX(1) |
1279 S_008020_SOFT_RESET_SH(1) |
1280 S_008020_SOFT_RESET_TC(1) |
1281 S_008020_SOFT_RESET_TA(1) |
1282 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1283 S_008020_SOFT_RESET_VGT(1);
1a029b76 1284 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1285 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1286 RREG32(R_008020_GRBM_SOFT_RESET);
1287 mdelay(15);
3ce0a23d 1288 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1289 }
1290 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1291 tmp = S_008020_SOFT_RESET_CP(1);
1292 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1293 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1294 RREG32(R_008020_GRBM_SOFT_RESET);
1295 mdelay(15);
3ce0a23d 1296 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 1297 /* Wait a little for things to settle down */
225758d8 1298 mdelay(1);
1a029b76
JG		 1299 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1300 RREG32(R_008010_GRBM_STATUS));
1301 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1302 RREG32(R_008014_GRBM_STATUS2));
1303 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1304 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 1305 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 1306 return 0;
1307}
1308
225758d8
JG		 1309bool r600_gpu_is_lockup(struct radeon_device *rdev)
1310{
1311 u32 srbm_status;
1312 u32 grbm_status;
1313 u32 grbm_status2;
1314 int r;
1315
1316 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1317 grbm_status = RREG32(R_008010_GRBM_STATUS);
1318 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1319 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1320 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1321 return false;
1322 }
1323 /* force CP activities */
1324 r = radeon_ring_lock(rdev, 2);
1325 if (!r) {
1326 /* PACKET2 NOP */
1327 radeon_ring_write(rdev, 0x80000000);
1328 radeon_ring_write(rdev, 0x80000000);
1329 radeon_ring_unlock_commit(rdev);
1330 }
1331 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1332 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1333}
1334
a2d07b74 1335int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 1336{
1337 return r600_gpu_soft_reset(rdev);
1338}
1339
1340static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1341 u32 num_backends,
1342 u32 backend_disable_mask)
1343{
1344 u32 backend_map = 0;
1345 u32 enabled_backends_mask;
1346 u32 enabled_backends_count;
1347 u32 cur_pipe;
1348 u32 swizzle_pipe[R6XX_MAX_PIPES];
1349 u32 cur_backend;
1350 u32 i;
1351
1352 if (num_tile_pipes > R6XX_MAX_PIPES)
1353 num_tile_pipes = R6XX_MAX_PIPES;
1354 if (num_tile_pipes < 1)
1355 num_tile_pipes = 1;
1356 if (num_backends > R6XX_MAX_BACKENDS)
1357 num_backends = R6XX_MAX_BACKENDS;
1358 if (num_backends < 1)
1359 num_backends = 1;
1360
1361 enabled_backends_mask = 0;
1362 enabled_backends_count = 0;
1363 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1364 if (((backend_disable_mask >> i) & 1) == 0) {
1365 enabled_backends_mask |= (1 << i);
1366 ++enabled_backends_count;
1367 }
1368 if (enabled_backends_count == num_backends)
1369 break;
1370 }
1371
1372 if (enabled_backends_count == 0) {
1373 enabled_backends_mask = 1;
1374 enabled_backends_count = 1;
1375 }
1376
1377 if (enabled_backends_count != num_backends)
1378 num_backends = enabled_backends_count;
1379
1380 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1381 switch (num_tile_pipes) {
1382 case 1:
1383 swizzle_pipe[0] = 0;
1384 break;
1385 case 2:
1386 swizzle_pipe[0] = 0;
1387 swizzle_pipe[1] = 1;
1388 break;
1389 case 3:
1390 swizzle_pipe[0] = 0;
1391 swizzle_pipe[1] = 1;
1392 swizzle_pipe[2] = 2;
1393 break;
1394 case 4:
1395 swizzle_pipe[0] = 0;
1396 swizzle_pipe[1] = 1;
1397 swizzle_pipe[2] = 2;
1398 swizzle_pipe[3] = 3;
1399 break;
1400 case 5:
1401 swizzle_pipe[0] = 0;
1402 swizzle_pipe[1] = 1;
1403 swizzle_pipe[2] = 2;
1404 swizzle_pipe[3] = 3;
1405 swizzle_pipe[4] = 4;
1406 break;
1407 case 6:
1408 swizzle_pipe[0] = 0;
1409 swizzle_pipe[1] = 2;
1410 swizzle_pipe[2] = 4;
1411 swizzle_pipe[3] = 5;
1412 swizzle_pipe[4] = 1;
1413 swizzle_pipe[5] = 3;
1414 break;
1415 case 7:
1416 swizzle_pipe[0] = 0;
1417 swizzle_pipe[1] = 2;
1418 swizzle_pipe[2] = 4;
1419 swizzle_pipe[3] = 6;
1420 swizzle_pipe[4] = 1;
1421 swizzle_pipe[5] = 3;
1422 swizzle_pipe[6] = 5;
1423 break;
1424 case 8:
1425 swizzle_pipe[0] = 0;
1426 swizzle_pipe[1] = 2;
1427 swizzle_pipe[2] = 4;
1428 swizzle_pipe[3] = 6;
1429 swizzle_pipe[4] = 1;
1430 swizzle_pipe[5] = 3;
1431 swizzle_pipe[6] = 5;
1432 swizzle_pipe[7] = 7;
1433 break;
1434 }
1435
1436 cur_backend = 0;
1437 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1438 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1439 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1440
1441 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1442
1443 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1444 }
1445
1446 return backend_map;
1447}
1448
1449int r600_count_pipe_bits(uint32_t val)
1450{
1451 int i, ret = 0;
1452
1453 for (i = 0; i < 32; i++) {
1454 ret += val & 1;
1455 val >>= 1;
1456 }
1457 return ret;
771fe6b9
JG		 1458}
1459
3ce0a23d
JG		 1460void r600_gpu_init(struct radeon_device *rdev)
1461{
1462 u32 tiling_config;
1463 u32 ramcfg;
d03f5d59
AD		 1464 u32 backend_map;
1465 u32 cc_rb_backend_disable;
1466 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1467 u32 tmp;
1468 int i, j;
1469 u32 sq_config;
1470 u32 sq_gpr_resource_mgmt_1 = 0;
1471 u32 sq_gpr_resource_mgmt_2 = 0;
1472 u32 sq_thread_resource_mgmt = 0;
1473 u32 sq_stack_resource_mgmt_1 = 0;
1474 u32 sq_stack_resource_mgmt_2 = 0;
1475
1476 /* FIXME: implement */
1477 switch (rdev->family) {
1478 case CHIP_R600:
1479 rdev->config.r600.max_pipes = 4;
1480 rdev->config.r600.max_tile_pipes = 8;
1481 rdev->config.r600.max_simds = 4;
1482 rdev->config.r600.max_backends = 4;
1483 rdev->config.r600.max_gprs = 256;
1484 rdev->config.r600.max_threads = 192;
1485 rdev->config.r600.max_stack_entries = 256;
1486 rdev->config.r600.max_hw_contexts = 8;
1487 rdev->config.r600.max_gs_threads = 16;
1488 rdev->config.r600.sx_max_export_size = 128;
1489 rdev->config.r600.sx_max_export_pos_size = 16;
1490 rdev->config.r600.sx_max_export_smx_size = 128;
1491 rdev->config.r600.sq_num_cf_insts = 2;
1492 break;
1493 case CHIP_RV630:
1494 case CHIP_RV635:
1495 rdev->config.r600.max_pipes = 2;
1496 rdev->config.r600.max_tile_pipes = 2;
1497 rdev->config.r600.max_simds = 3;
1498 rdev->config.r600.max_backends = 1;
1499 rdev->config.r600.max_gprs = 128;
1500 rdev->config.r600.max_threads = 192;
1501 rdev->config.r600.max_stack_entries = 128;
1502 rdev->config.r600.max_hw_contexts = 8;
1503 rdev->config.r600.max_gs_threads = 4;
1504 rdev->config.r600.sx_max_export_size = 128;
1505 rdev->config.r600.sx_max_export_pos_size = 16;
1506 rdev->config.r600.sx_max_export_smx_size = 128;
1507 rdev->config.r600.sq_num_cf_insts = 2;
1508 break;
1509 case CHIP_RV610:
1510 case CHIP_RV620:
1511 case CHIP_RS780:
1512 case CHIP_RS880:
1513 rdev->config.r600.max_pipes = 1;
1514 rdev->config.r600.max_tile_pipes = 1;
1515 rdev->config.r600.max_simds = 2;
1516 rdev->config.r600.max_backends = 1;
1517 rdev->config.r600.max_gprs = 128;
1518 rdev->config.r600.max_threads = 192;
1519 rdev->config.r600.max_stack_entries = 128;
1520 rdev->config.r600.max_hw_contexts = 4;
1521 rdev->config.r600.max_gs_threads = 4;
1522 rdev->config.r600.sx_max_export_size = 128;
1523 rdev->config.r600.sx_max_export_pos_size = 16;
1524 rdev->config.r600.sx_max_export_smx_size = 128;
1525 rdev->config.r600.sq_num_cf_insts = 1;
1526 break;
1527 case CHIP_RV670:
1528 rdev->config.r600.max_pipes = 4;
1529 rdev->config.r600.max_tile_pipes = 4;
1530 rdev->config.r600.max_simds = 4;
1531 rdev->config.r600.max_backends = 4;
1532 rdev->config.r600.max_gprs = 192;
1533 rdev->config.r600.max_threads = 192;
1534 rdev->config.r600.max_stack_entries = 256;
1535 rdev->config.r600.max_hw_contexts = 8;
1536 rdev->config.r600.max_gs_threads = 16;
1537 rdev->config.r600.sx_max_export_size = 128;
1538 rdev->config.r600.sx_max_export_pos_size = 16;
1539 rdev->config.r600.sx_max_export_smx_size = 128;
1540 rdev->config.r600.sq_num_cf_insts = 2;
1541 break;
1542 default:
1543 break;
1544 }
1545
1546 /* Initialize HDP */
1547 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1548 WREG32((0x2c14 + j), 0x00000000);
1549 WREG32((0x2c18 + j), 0x00000000);
1550 WREG32((0x2c1c + j), 0x00000000);
1551 WREG32((0x2c20 + j), 0x00000000);
1552 WREG32((0x2c24 + j), 0x00000000);
1553 }
1554
1555 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1556
1557 /* Setup tiling */
1558 tiling_config = 0;
1559 ramcfg = RREG32(RAMCFG);
1560 switch (rdev->config.r600.max_tile_pipes) {
1561 case 1:
1562 tiling_config |= PIPE_TILING(0);
1563 break;
1564 case 2:
1565 tiling_config |= PIPE_TILING(1);
1566 break;
1567 case 4:
1568 tiling_config |= PIPE_TILING(2);
1569 break;
1570 case 8:
1571 tiling_config |= PIPE_TILING(3);
1572 break;
1573 default:
1574 break;
1575 }
d03f5d59 1576 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1577 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d
JG		 1578 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1579 tiling_config |= GROUP_SIZE(0);
961fb597 1580 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1581 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1582 if (tmp > 3) {
1583 tiling_config |= ROW_TILING(3);
1584 tiling_config |= SAMPLE_SPLIT(3);
1585 } else {
1586 tiling_config |= ROW_TILING(tmp);
1587 tiling_config |= SAMPLE_SPLIT(tmp);
1588 }
1589 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1590
1591 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1592 cc_rb_backend_disable |=
1593 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1594
1595 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1596 cc_gc_shader_pipe_config |=
1597 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1598 cc_gc_shader_pipe_config |=
1599 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1600
1601 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1602 (R6XX_MAX_BACKENDS -
1603 r600_count_pipe_bits((cc_rb_backend_disable &
1604 R6XX_MAX_BACKENDS_MASK) >> 16)),
1605 (cc_rb_backend_disable >> 16));
1606
1607 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1608 WREG32(GB_TILING_CONFIG, tiling_config);
1609 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1610 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1611
3ce0a23d 1612 /* Setup pipes */
d03f5d59
AD		 1613 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1614 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1615 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1616
d03f5d59 1617 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1618 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1619 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1620
1621 /* Setup some CP states */
1622 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1623 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1624
1625 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1626 SYNC_WALKER | SYNC_ALIGNER));
1627 /* Setup various GPU states */
1628 if (rdev->family == CHIP_RV670)
1629 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1630
1631 tmp = RREG32(SX_DEBUG_1);
1632 tmp |= SMX_EVENT_RELEASE;
1633 if ((rdev->family > CHIP_R600))
1634 tmp |= ENABLE_NEW_SMX_ADDRESS;
1635 WREG32(SX_DEBUG_1, tmp);
1636
1637 if (((rdev->family) == CHIP_R600) ||
1638 ((rdev->family) == CHIP_RV630) ||
1639 ((rdev->family) == CHIP_RV610) ||
1640 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1641 ((rdev->family) == CHIP_RS780) ||
1642 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1643 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1644 } else {
1645 WREG32(DB_DEBUG, 0);
1646 }
1647 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1648 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1649
1650 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1651 WREG32(VGT_NUM_INSTANCES, 0);
1652
1653 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1654 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1655
1656 tmp = RREG32(SQ_MS_FIFO_SIZES);
1657 if (((rdev->family) == CHIP_RV610) ||
1658 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1659 ((rdev->family) == CHIP_RS780) ||
1660 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1661 tmp = (CACHE_FIFO_SIZE(0xa) |
1662 FETCH_FIFO_HIWATER(0xa) |
1663 DONE_FIFO_HIWATER(0xe0) |
1664 ALU_UPDATE_FIFO_HIWATER(0x8));
1665 } else if (((rdev->family) == CHIP_R600) ||
1666 ((rdev->family) == CHIP_RV630)) {
1667 tmp &= ~DONE_FIFO_HIWATER(0xff);
1668 tmp |= DONE_FIFO_HIWATER(0x4);
1669 }
1670 WREG32(SQ_MS_FIFO_SIZES, tmp);
1671
1672 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1673 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1674 */
1675 sq_config = RREG32(SQ_CONFIG);
1676 sq_config &= ~(PS_PRIO(3) |
1677 VS_PRIO(3) |
1678 GS_PRIO(3) |
1679 ES_PRIO(3));
1680 sq_config |= (DX9_CONSTS |
1681 VC_ENABLE |
1682 PS_PRIO(0) |
1683 VS_PRIO(1) |
1684 GS_PRIO(2) |
1685 ES_PRIO(3));
1686
1687 if ((rdev->family) == CHIP_R600) {
1688 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1689 NUM_VS_GPRS(124) |
1690 NUM_CLAUSE_TEMP_GPRS(4));
1691 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1692 NUM_ES_GPRS(0));
1693 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1694 NUM_VS_THREADS(48) |
1695 NUM_GS_THREADS(4) |
1696 NUM_ES_THREADS(4));
1697 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1698 NUM_VS_STACK_ENTRIES(128));
1699 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1700 NUM_ES_STACK_ENTRIES(0));
1701 } else if (((rdev->family) == CHIP_RV610) ||
1702 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1703 ((rdev->family) == CHIP_RS780) ||
1704 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1705 /* no vertex cache */
1706 sq_config &= ~VC_ENABLE;
1707
1708 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1709 NUM_VS_GPRS(44) |
1710 NUM_CLAUSE_TEMP_GPRS(2));
1711 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1712 NUM_ES_GPRS(17));
1713 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1714 NUM_VS_THREADS(78) |
1715 NUM_GS_THREADS(4) |
1716 NUM_ES_THREADS(31));
1717 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1718 NUM_VS_STACK_ENTRIES(40));
1719 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1720 NUM_ES_STACK_ENTRIES(16));
1721 } else if (((rdev->family) == CHIP_RV630) ||
1722 ((rdev->family) == CHIP_RV635)) {
1723 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1724 NUM_VS_GPRS(44) |
1725 NUM_CLAUSE_TEMP_GPRS(2));
1726 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1727 NUM_ES_GPRS(18));
1728 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1729 NUM_VS_THREADS(78) |
1730 NUM_GS_THREADS(4) |
1731 NUM_ES_THREADS(31));
1732 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1733 NUM_VS_STACK_ENTRIES(40));
1734 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1735 NUM_ES_STACK_ENTRIES(16));
1736 } else if ((rdev->family) == CHIP_RV670) {
1737 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1738 NUM_VS_GPRS(44) |
1739 NUM_CLAUSE_TEMP_GPRS(2));
1740 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1741 NUM_ES_GPRS(17));
1742 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1743 NUM_VS_THREADS(78) |
1744 NUM_GS_THREADS(4) |
1745 NUM_ES_THREADS(31));
1746 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1747 NUM_VS_STACK_ENTRIES(64));
1748 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1749 NUM_ES_STACK_ENTRIES(64));
1750 }
1751
1752 WREG32(SQ_CONFIG, sq_config);
1753 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1754 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1755 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1756 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1757 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1758
1759 if (((rdev->family) == CHIP_RV610) ||
1760 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1761 ((rdev->family) == CHIP_RS780) ||
1762 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1763 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1764 } else {
1765 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1766 }
1767
1768 /* More default values. 2D/3D driver should adjust as needed */
1769 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1770 S1_X(0x4) | S1_Y(0xc)));
1771 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1772 S1_X(0x2) | S1_Y(0x2) |
1773 S2_X(0xa) | S2_Y(0x6) |
1774 S3_X(0x6) | S3_Y(0xa)));
1775 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1776 S1_X(0x4) | S1_Y(0xc) |
1777 S2_X(0x1) | S2_Y(0x6) |
1778 S3_X(0xa) | S3_Y(0xe)));
1779 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1780 S5_X(0x0) | S5_Y(0x0) |
1781 S6_X(0xb) | S6_Y(0x4) |
1782 S7_X(0x7) | S7_Y(0x8)));
1783
1784 WREG32(VGT_STRMOUT_EN, 0);
1785 tmp = rdev->config.r600.max_pipes * 16;
1786 switch (rdev->family) {
1787 case CHIP_RV610:
3ce0a23d 1788 case CHIP_RV620:
ee59f2b4
AD		 1789 case CHIP_RS780:
1790 case CHIP_RS880:
3ce0a23d
JG		 1791 tmp += 32;
1792 break;
1793 case CHIP_RV670:
1794 tmp += 128;
1795 break;
1796 default:
1797 break;
1798 }
1799 if (tmp > 256) {
1800 tmp = 256;
1801 }
1802 WREG32(VGT_ES_PER_GS, 128);
1803 WREG32(VGT_GS_PER_ES, tmp);
1804 WREG32(VGT_GS_PER_VS, 2);
1805 WREG32(VGT_GS_VERTEX_REUSE, 16);
1806
1807 /* more default values. 2D/3D driver should adjust as needed */
1808 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1809 WREG32(VGT_STRMOUT_EN, 0);
1810 WREG32(SX_MISC, 0);
1811 WREG32(PA_SC_MODE_CNTL, 0);
1812 WREG32(PA_SC_AA_CONFIG, 0);
1813 WREG32(PA_SC_LINE_STIPPLE, 0);
1814 WREG32(SPI_INPUT_Z, 0);
1815 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1816 WREG32(CB_COLOR7_FRAG, 0);
1817
1818 /* Clear render buffer base addresses */
1819 WREG32(CB_COLOR0_BASE, 0);
1820 WREG32(CB_COLOR1_BASE, 0);
1821 WREG32(CB_COLOR2_BASE, 0);
1822 WREG32(CB_COLOR3_BASE, 0);
1823 WREG32(CB_COLOR4_BASE, 0);
1824 WREG32(CB_COLOR5_BASE, 0);
1825 WREG32(CB_COLOR6_BASE, 0);
1826 WREG32(CB_COLOR7_BASE, 0);
1827 WREG32(CB_COLOR7_FRAG, 0);
1828
1829 switch (rdev->family) {
1830 case CHIP_RV610:
3ce0a23d 1831 case CHIP_RV620:
ee59f2b4
AD		 1832 case CHIP_RS780:
1833 case CHIP_RS880:
3ce0a23d
JG		 1834 tmp = TC_L2_SIZE(8);
1835 break;
1836 case CHIP_RV630:
1837 case CHIP_RV635:
1838 tmp = TC_L2_SIZE(4);
1839 break;
1840 case CHIP_R600:
1841 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1842 break;
1843 default:
1844 tmp = TC_L2_SIZE(0);
1845 break;
1846 }
1847 WREG32(TC_CNTL, tmp);
1848
1849 tmp = RREG32(HDP_HOST_PATH_CNTL);
1850 WREG32(HDP_HOST_PATH_CNTL, tmp);
1851
1852 tmp = RREG32(ARB_POP);
1853 tmp |= ENABLE_TC128;
1854 WREG32(ARB_POP, tmp);
1855
1856 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1857 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1858 NUM_CLIP_SEQ(3)));
1859 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1860}
1861
1862
771fe6b9
JG		 1863/*
1864 * Indirect registers accessor
1865 */
3ce0a23d
JG		 1866u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1867{
1868 u32 r;
1869
1870 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1871 (void)RREG32(PCIE_PORT_INDEX);
1872 r = RREG32(PCIE_PORT_DATA);
1873 return r;
1874}
1875
1876void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1877{
1878 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1879 (void)RREG32(PCIE_PORT_INDEX);
1880 WREG32(PCIE_PORT_DATA, (v));
1881 (void)RREG32(PCIE_PORT_DATA);
1882}
1883
3ce0a23d
JG		 1884/*
1885 * CP & Ring
1886 */
1887void r600_cp_stop(struct radeon_device *rdev)
1888{
1889 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1890}
1891
d8f60cfc 1892int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1893{
1894 struct platform_device *pdev;
1895 const char *chip_name;
d8f60cfc
AD		 1896 const char *rlc_chip_name;
1897 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1898 char fw_name[30];
1899 int err;
1900
1901 DRM_DEBUG("\n");
1902
1903 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1904 err = IS_ERR(pdev);
1905 if (err) {
1906 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1907 return -EINVAL;
1908 }
1909
1910 switch (rdev->family) {
d8f60cfc
AD		 1911 case CHIP_R600:
1912 chip_name = "R600";
1913 rlc_chip_name = "R600";
1914 break;
1915 case CHIP_RV610:
1916 chip_name = "RV610";
1917 rlc_chip_name = "R600";
1918 break;
1919 case CHIP_RV630:
1920 chip_name = "RV630";
1921 rlc_chip_name = "R600";
1922 break;
1923 case CHIP_RV620:
1924 chip_name = "RV620";
1925 rlc_chip_name = "R600";
1926 break;
1927 case CHIP_RV635:
1928 chip_name = "RV635";
1929 rlc_chip_name = "R600";
1930 break;
1931 case CHIP_RV670:
1932 chip_name = "RV670";
1933 rlc_chip_name = "R600";
1934 break;
3ce0a23d 1935 case CHIP_RS780:
d8f60cfc
AD		 1936 case CHIP_RS880:
1937 chip_name = "RS780";
1938 rlc_chip_name = "R600";
1939 break;
1940 case CHIP_RV770:
1941 chip_name = "RV770";
1942 rlc_chip_name = "R700";
1943 break;
3ce0a23d 1944 case CHIP_RV730:
d8f60cfc
AD		 1945 case CHIP_RV740:
1946 chip_name = "RV730";
1947 rlc_chip_name = "R700";
1948 break;
1949 case CHIP_RV710:
1950 chip_name = "RV710";
1951 rlc_chip_name = "R700";
1952 break;
fe251e2f
AD		 1953 case CHIP_CEDAR:
1954 chip_name = "CEDAR";
45f9a39b 1955 rlc_chip_name = "CEDAR";
fe251e2f
AD		 1956 break;
1957 case CHIP_REDWOOD:
1958 chip_name = "REDWOOD";
45f9a39b 1959 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 1960 break;
1961 case CHIP_JUNIPER:
1962 chip_name = "JUNIPER";
45f9a39b 1963 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 1964 break;
1965 case CHIP_CYPRESS:
1966 case CHIP_HEMLOCK:
1967 chip_name = "CYPRESS";
45f9a39b 1968 rlc_chip_name = "CYPRESS";
fe251e2f 1969 break;
3ce0a23d
JG		 1970 default: BUG();
1971 }
1972
fe251e2f
AD		 1973 if (rdev->family >= CHIP_CEDAR) {
1974 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1975 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 1976 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 1977 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 1978 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1979 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 1980 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 1981 } else {
1982 pfp_req_size = PFP_UCODE_SIZE * 4;
1983 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 1984 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 1985 }
1986
d8f60cfc 1987 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 1988
1989 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1990 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1991 if (err)
1992 goto out;
1993 if (rdev->pfp_fw->size != pfp_req_size) {
1994 printk(KERN_ERR
1995 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1996 rdev->pfp_fw->size, fw_name);
1997 err = -EINVAL;
1998 goto out;
1999 }
2000
2001 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2002 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2003 if (err)
2004 goto out;
2005 if (rdev->me_fw->size != me_req_size) {
2006 printk(KERN_ERR
2007 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2008 rdev->me_fw->size, fw_name);
2009 err = -EINVAL;
2010 }
d8f60cfc
AD		 2011
2012 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2013 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2014 if (err)
2015 goto out;
2016 if (rdev->rlc_fw->size != rlc_req_size) {
2017 printk(KERN_ERR
2018 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2019 rdev->rlc_fw->size, fw_name);
2020 err = -EINVAL;
2021 }
2022
3ce0a23d
JG		 2023out:
2024 platform_device_unregister(pdev);
2025
2026 if (err) {
2027 if (err != -EINVAL)
2028 printk(KERN_ERR
2029 "r600_cp: Failed to load firmware \"%s\"\n",
2030 fw_name);
2031 release_firmware(rdev->pfp_fw);
2032 rdev->pfp_fw = NULL;
2033 release_firmware(rdev->me_fw);
2034 rdev->me_fw = NULL;
d8f60cfc
AD		 2035 release_firmware(rdev->rlc_fw);
2036 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2037 }
2038 return err;
2039}
2040
2041static int r600_cp_load_microcode(struct radeon_device *rdev)
2042{
2043 const __be32 *fw_data;
2044 int i;
2045
2046 if (!rdev->me_fw || !rdev->pfp_fw)
2047 return -EINVAL;
2048
2049 r600_cp_stop(rdev);
2050
2051 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2052
2053 /* Reset cp */
2054 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2055 RREG32(GRBM_SOFT_RESET);
2056 mdelay(15);
2057 WREG32(GRBM_SOFT_RESET, 0);
2058
2059 WREG32(CP_ME_RAM_WADDR, 0);
2060
2061 fw_data = (const __be32 *)rdev->me_fw->data;
2062 WREG32(CP_ME_RAM_WADDR, 0);
2063 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2064 WREG32(CP_ME_RAM_DATA,
2065 be32_to_cpup(fw_data++));
2066
2067 fw_data = (const __be32 *)rdev->pfp_fw->data;
2068 WREG32(CP_PFP_UCODE_ADDR, 0);
2069 for (i = 0; i < PFP_UCODE_SIZE; i++)
2070 WREG32(CP_PFP_UCODE_DATA,
2071 be32_to_cpup(fw_data++));
2072
2073 WREG32(CP_PFP_UCODE_ADDR, 0);
2074 WREG32(CP_ME_RAM_WADDR, 0);
2075 WREG32(CP_ME_RAM_RADDR, 0);
2076 return 0;
2077}
2078
2079int r600_cp_start(struct radeon_device *rdev)
2080{
2081 int r;
2082 uint32_t cp_me;
2083
2084 r = radeon_ring_lock(rdev, 7);
2085 if (r) {
2086 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2087 return r;
2088 }
2089 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2090 radeon_ring_write(rdev, 0x1);
fe251e2f
AD		 2091 if (rdev->family >= CHIP_CEDAR) {
2092 radeon_ring_write(rdev, 0x0);
2093 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
2094 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2095 radeon_ring_write(rdev, 0x0);
2096 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f
AD		 2097 } else {
2098 radeon_ring_write(rdev, 0x3);
2099 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d
JG		 2100 }
2101 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2102 radeon_ring_write(rdev, 0);
2103 radeon_ring_write(rdev, 0);
2104 radeon_ring_unlock_commit(rdev);
2105
2106 cp_me = 0xff;
2107 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2108 return 0;
2109}
2110
2111int r600_cp_resume(struct radeon_device *rdev)
2112{
2113 u32 tmp;
2114 u32 rb_bufsz;
2115 int r;
2116
2117 /* Reset cp */
2118 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2119 RREG32(GRBM_SOFT_RESET);
2120 mdelay(15);
2121 WREG32(GRBM_SOFT_RESET, 0);
2122
2123 /* Set ring buffer size */
2124 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
d6f28938 2125 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2126#ifdef __BIG_ENDIAN
d6f28938 2127 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2128#endif
d6f28938 2129 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 2130 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2131
2132 /* Set the write pointer delay */
2133 WREG32(CP_RB_WPTR_DELAY, 0);
2134
2135 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2136 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2137 WREG32(CP_RB_RPTR_WR, 0);
2138 WREG32(CP_RB_WPTR, 0);
2139 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
2140 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
2141 mdelay(1);
2142 WREG32(CP_RB_CNTL, tmp);
2143
2144 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2145 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2146
2147 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2148 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2149
2150 r600_cp_start(rdev);
2151 rdev->cp.ready = true;
2152 r = radeon_ring_test(rdev);
2153 if (r) {
2154 rdev->cp.ready = false;
2155 return r;
2156 }
2157 return 0;
2158}
2159
2160void r600_cp_commit(struct radeon_device *rdev)
2161{
2162 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2163 (void)RREG32(CP_RB_WPTR);
2164}
2165
2166void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2167{
2168 u32 rb_bufsz;
2169
2170 /* Align ring size */
2171 rb_bufsz = drm_order(ring_size / 8);
2172 ring_size = (1 << (rb_bufsz + 1)) * 4;
2173 rdev->cp.ring_size = ring_size;
2174 rdev->cp.align_mask = 16 - 1;
2175}
2176
655efd3d
JG		 2177void r600_cp_fini(struct radeon_device *rdev)
2178{
2179 r600_cp_stop(rdev);
2180 radeon_ring_fini(rdev);
2181}
2182
3ce0a23d
JG		 2183
2184/*
2185 * GPU scratch registers helpers function.
2186 */
2187void r600_scratch_init(struct radeon_device *rdev)
2188{
2189 int i;
2190
2191 rdev->scratch.num_reg = 7;
2192 for (i = 0; i < rdev->scratch.num_reg; i++) {
2193 rdev->scratch.free[i] = true;
2194 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
2195 }
2196}
2197
2198int r600_ring_test(struct radeon_device *rdev)
2199{
2200 uint32_t scratch;
2201 uint32_t tmp = 0;
2202 unsigned i;
2203 int r;
2204
2205 r = radeon_scratch_get(rdev, &scratch);
2206 if (r) {
2207 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2208 return r;
2209 }
2210 WREG32(scratch, 0xCAFEDEAD);
2211 r = radeon_ring_lock(rdev, 3);
2212 if (r) {
2213 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2214 radeon_scratch_free(rdev, scratch);
2215 return r;
2216 }
2217 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2218 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2219 radeon_ring_write(rdev, 0xDEADBEEF);
2220 radeon_ring_unlock_commit(rdev);
2221 for (i = 0; i < rdev->usec_timeout; i++) {
2222 tmp = RREG32(scratch);
2223 if (tmp == 0xDEADBEEF)
2224 break;
2225 DRM_UDELAY(1);
2226 }
2227 if (i < rdev->usec_timeout) {
2228 DRM_INFO("ring test succeeded in %d usecs\n", i);
2229 } else {
2230 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2231 scratch, tmp);
2232 r = -EINVAL;
2233 }
2234 radeon_scratch_free(rdev, scratch);
2235 return r;
2236}
2237
81cc35bf
JG		 2238void r600_wb_disable(struct radeon_device *rdev)
2239{
4c788679
JG		 2240 int r;
2241
81cc35bf
JG		 2242 WREG32(SCRATCH_UMSK, 0);
2243 if (rdev->wb.wb_obj) {
4c788679
JG		 2244 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2245 if (unlikely(r != 0))
2246 return;
2247 radeon_bo_kunmap(rdev->wb.wb_obj);
2248 radeon_bo_unpin(rdev->wb.wb_obj);
2249 radeon_bo_unreserve(rdev->wb.wb_obj);
81cc35bf
JG		 2250 }
2251}
2252
2253void r600_wb_fini(struct radeon_device *rdev)
2254{
2255 r600_wb_disable(rdev);
2256 if (rdev->wb.wb_obj) {
4c788679 2257 radeon_bo_unref(&rdev->wb.wb_obj);
81cc35bf
JG		 2258 rdev->wb.wb = NULL;
2259 rdev->wb.wb_obj = NULL;
2260 }
2261}
2262
2263int r600_wb_enable(struct radeon_device *rdev)
3ce0a23d
JG		 2264{
2265 int r;
2266
2267 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 2268 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2269 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
3ce0a23d 2270 if (r) {
4c788679 2271 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
3ce0a23d
JG		 2272 return r;
2273 }
4c788679
JG		 2274 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2275 if (unlikely(r != 0)) {
2276 r600_wb_fini(rdev);
3ce0a23d
JG		 2277 return r;
2278 }
4c788679 2279 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
81cc35bf 2280 &rdev->wb.gpu_addr);
3ce0a23d 2281 if (r) {
4c788679
JG		 2282 radeon_bo_unreserve(rdev->wb.wb_obj);
2283 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
81cc35bf 2284 r600_wb_fini(rdev);
3ce0a23d
JG		 2285 return r;
2286 }
4c788679
JG		 2287 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2288 radeon_bo_unreserve(rdev->wb.wb_obj);
3ce0a23d 2289 if (r) {
4c788679 2290 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
81cc35bf 2291 r600_wb_fini(rdev);
3ce0a23d
JG		 2292 return r;
2293 }
2294 }
2295 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2296 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2297 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2298 WREG32(SCRATCH_UMSK, 0xff);
2299 return 0;
2300}
2301
3ce0a23d
JG		 2302void r600_fence_ring_emit(struct radeon_device *rdev,
2303 struct radeon_fence *fence)
2304{
d8f60cfc 2305 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
44224c3f
AD		 2306
2307 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2308 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2309 /* wait for 3D idle clean */
2310 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2311 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2312 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
3ce0a23d
JG		 2313 /* Emit fence sequence & fire IRQ */
2314 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2315 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2316 radeon_ring_write(rdev, fence->seq);
d8f60cfc
AD		 2317 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2318 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2319 radeon_ring_write(rdev, RB_INT_STAT);
3ce0a23d
JG		 2320}
2321
3ce0a23d
JG		 2322int r600_copy_blit(struct radeon_device *rdev,
2323 uint64_t src_offset, uint64_t dst_offset,
2324 unsigned num_pages, struct radeon_fence *fence)
2325{
ff82f052
JG		 2326 int r;
2327
2328 mutex_lock(&rdev->r600_blit.mutex);
2329 rdev->r600_blit.vb_ib = NULL;
2330 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2331 if (r) {
2332 if (rdev->r600_blit.vb_ib)
2333 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2334 mutex_unlock(&rdev->r600_blit.mutex);
2335 return r;
2336 }
a77f1718 2337 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d 2338 r600_blit_done_copy(rdev, fence);
ff82f052 2339 mutex_unlock(&rdev->r600_blit.mutex);
3ce0a23d
JG		 2340 return 0;
2341}
2342
3ce0a23d
JG		 2343int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2344 uint32_t tiling_flags, uint32_t pitch,
2345 uint32_t offset, uint32_t obj_size)
2346{
2347 /* FIXME: implement */
2348 return 0;
2349}
2350
2351void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2352{
2353 /* FIXME: implement */
2354}
2355
2356
2357bool r600_card_posted(struct radeon_device *rdev)
2358{
2359 uint32_t reg;
2360
2361 /* first check CRTCs */
2362 reg = RREG32(D1CRTC_CONTROL) |
2363 RREG32(D2CRTC_CONTROL);
2364 if (reg & CRTC_EN)
2365 return true;
2366
2367 /* then check MEM_SIZE, in case the crtcs are off */
2368 if (RREG32(CONFIG_MEMSIZE))
2369 return true;
2370
2371 return false;
2372}
2373
fc30b8ef 2374int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 2375{
2376 int r;
2377
779720a3
AD		 2378 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2379 r = r600_init_microcode(rdev);
2380 if (r) {
2381 DRM_ERROR("Failed to load firmware!\n");
2382 return r;
2383 }
2384 }
2385
a3c1945a 2386 r600_mc_program(rdev);
1a029b76
JG		 2387 if (rdev->flags & RADEON_IS_AGP) {
2388 r600_agp_enable(rdev);
2389 } else {
2390 r = r600_pcie_gart_enable(rdev);
2391 if (r)
2392 return r;
2393 }
3ce0a23d 2394 r600_gpu_init(rdev);
c38c7b64
JG		 2395 r = r600_blit_init(rdev);
2396 if (r) {
2397 r600_blit_fini(rdev);
2398 rdev->asic->copy = NULL;
2399 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2400 }
ff82f052
JG		 2401 /* pin copy shader into vram */
2402 if (rdev->r600_blit.shader_obj) {
2403 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2404 if (unlikely(r != 0))
2405 return r;
2406 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2407 &rdev->r600_blit.shader_gpu_addr);
2408 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
7923c615 2409 if (r) {
ff82f052 2410 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
7923c615
AD		 2411 return r;
2412 }
2413 }
d8f60cfc 2414 /* Enable IRQ */
d8f60cfc
AD		 2415 r = r600_irq_init(rdev);
2416 if (r) {
2417 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2418 radeon_irq_kms_fini(rdev);
2419 return r;
2420 }
2421 r600_irq_set(rdev);
2422
3ce0a23d
JG		 2423 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2424 if (r)
2425 return r;
2426 r = r600_cp_load_microcode(rdev);
2427 if (r)
2428 return r;
2429 r = r600_cp_resume(rdev);
2430 if (r)
2431 return r;
81cc35bf
JG		 2432 /* write back buffer are not vital so don't worry about failure */
2433 r600_wb_enable(rdev);
3ce0a23d
JG		 2434 return 0;
2435}
2436
28d52043
DA		 2437void r600_vga_set_state(struct radeon_device *rdev, bool state)
2438{
2439 uint32_t temp;
2440
2441 temp = RREG32(CONFIG_CNTL);
2442 if (state == false) {
2443 temp &= ~(1<<0);
2444 temp |= (1<<1);
2445 } else {
2446 temp &= ~(1<<1);
2447 }
2448 WREG32(CONFIG_CNTL, temp);
2449}
2450
fc30b8ef
DA		 2451int r600_resume(struct radeon_device *rdev)
2452{
2453 int r;
2454
1a029b76
JG		 2455 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2456 * posting will perform necessary task to bring back GPU into good
2457 * shape.
2458 */
fc30b8ef 2459 /* post card */
e7d40b9a 2460 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 2461 /* Initialize clocks */
2462 r = radeon_clocks_init(rdev);
2463 if (r) {
2464 return r;
2465 }
2466
2467 r = r600_startup(rdev);
2468 if (r) {
2469 DRM_ERROR("r600 startup failed on resume\n");
2470 return r;
2471 }
2472
62a8ea3f 2473 r = r600_ib_test(rdev);
fc30b8ef
DA		 2474 if (r) {
2475 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2476 return r;
2477 }
38fd2c6f
RM		 2478
2479 r = r600_audio_init(rdev);
2480 if (r) {
2481 DRM_ERROR("radeon: audio resume failed\n");
2482 return r;
2483 }
2484
fc30b8ef
DA		 2485 return r;
2486}
2487
3ce0a23d
JG		 2488int r600_suspend(struct radeon_device *rdev)
2489{
4c788679
JG		 2490 int r;
2491
38fd2c6f 2492 r600_audio_fini(rdev);
3ce0a23d
JG		 2493 /* FIXME: we should wait for ring to be empty */
2494 r600_cp_stop(rdev);
bc1a631e 2495 rdev->cp.ready = false;
0c45249f 2496 r600_irq_suspend(rdev);
81cc35bf 2497 r600_wb_disable(rdev);
4aac0473 2498 r600_pcie_gart_disable(rdev);
bc1a631e 2499 /* unpin shaders bo */
30d2d9a5
JG		 2500 if (rdev->r600_blit.shader_obj) {
2501 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2502 if (!r) {
2503 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2504 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2505 }
2506 }
3ce0a23d
JG		 2507 return 0;
2508}
2509
2510/* Plan is to move initialization in that function and use
2511 * helper function so that radeon_device_init pretty much
2512 * do nothing more than calling asic specific function. This
2513 * should also allow to remove a bunch of callback function
2514 * like vram_info.
2515 */
2516int r600_init(struct radeon_device *rdev)
771fe6b9 2517{
3ce0a23d 2518 int r;
771fe6b9 2519
3ce0a23d
JG		 2520 r = radeon_dummy_page_init(rdev);
2521 if (r)
2522 return r;
2523 if (r600_debugfs_mc_info_init(rdev)) {
2524 DRM_ERROR("Failed to register debugfs file for mc !\n");
2525 }
2526 /* This don't do much */
2527 r = radeon_gem_init(rdev);
2528 if (r)
2529 return r;
2530 /* Read BIOS */
2531 if (!radeon_get_bios(rdev)) {
2532 if (ASIC_IS_AVIVO(rdev))
2533 return -EINVAL;
2534 }
2535 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2536 if (!rdev->is_atom_bios) {
2537 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2538 return -EINVAL;
e7d40b9a 2539 }
3ce0a23d
JG		 2540 r = radeon_atombios_init(rdev);
2541 if (r)
2542 return r;
2543 /* Post card if necessary */
72542d77
DA		 2544 if (!r600_card_posted(rdev)) {
2545 if (!rdev->bios) {
2546 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2547 return -EINVAL;
2548 }
3ce0a23d
JG		 2549 DRM_INFO("GPU not posted. posting now...\n");
2550 atom_asic_init(rdev->mode_info.atom_context);
2551 }
2552 /* Initialize scratch registers */
2553 r600_scratch_init(rdev);
2554 /* Initialize surface registers */
2555 radeon_surface_init(rdev);
7433874e 2556 /* Initialize clocks */
5e6dde7e 2557 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 2558 r = radeon_clocks_init(rdev);
2559 if (r)
2560 return r;
2561 /* Fence driver */
2562 r = radeon_fence_driver_init(rdev);
2563 if (r)
2564 return r;
700a0cc0
JG		 2565 if (rdev->flags & RADEON_IS_AGP) {
2566 r = radeon_agp_init(rdev);
2567 if (r)
2568 radeon_agp_disable(rdev);
2569 }
3ce0a23d 2570 r = r600_mc_init(rdev);
b574f251 2571 if (r)
3ce0a23d 2572 return r;
3ce0a23d 2573 /* Memory manager */
4c788679 2574 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2575 if (r)
2576 return r;
d8f60cfc
AD		 2577
2578 r = radeon_irq_kms_init(rdev);
2579 if (r)
2580 return r;
2581
3ce0a23d
JG		 2582 rdev->cp.ring_obj = NULL;
2583 r600_ring_init(rdev, 1024 * 1024);
2584
d8f60cfc
AD		 2585 rdev->ih.ring_obj = NULL;
2586 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2587
4aac0473
JG		 2588 r = r600_pcie_gart_init(rdev);
2589 if (r)
2590 return r;
2591
779720a3 2592 rdev->accel_working = true;
fc30b8ef 2593 r = r600_startup(rdev);
3ce0a23d 2594 if (r) {
655efd3d
JG		 2595 dev_err(rdev->dev, "disabling GPU acceleration\n");
2596 r600_cp_fini(rdev);
75c81298 2597 r600_wb_fini(rdev);
655efd3d
JG		 2598 r600_irq_fini(rdev);
2599 radeon_irq_kms_fini(rdev);
75c81298 2600 r600_pcie_gart_fini(rdev);
733289c2 2601 rdev->accel_working = false;
3ce0a23d 2602 }
733289c2
JG		 2603 if (rdev->accel_working) {
2604 r = radeon_ib_pool_init(rdev);
2605 if (r) {
db96380e 2606 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 2607 rdev->accel_working = false;
db96380e
JG		 2608 } else {
2609 r = r600_ib_test(rdev);
2610 if (r) {
2611 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2612 rdev->accel_working = false;
2613 }
733289c2 2614 }
3ce0a23d 2615 }
dafc3bd5
CK		 2616
2617 r = r600_audio_init(rdev);
2618 if (r)
2619 return r; /* TODO error handling */
3ce0a23d
JG		 2620 return 0;
2621}
2622
2623void r600_fini(struct radeon_device *rdev)
2624{
dafc3bd5 2625 r600_audio_fini(rdev);
3ce0a23d 2626 r600_blit_fini(rdev);
655efd3d
JG		 2627 r600_cp_fini(rdev);
2628 r600_wb_fini(rdev);
d8f60cfc
AD		 2629 r600_irq_fini(rdev);
2630 radeon_irq_kms_fini(rdev);
4aac0473 2631 r600_pcie_gart_fini(rdev);
655efd3d 2632 radeon_agp_fini(rdev);
3ce0a23d
JG		 2633 radeon_gem_fini(rdev);
2634 radeon_fence_driver_fini(rdev);
2635 radeon_clocks_fini(rdev);
4c788679 2636 radeon_bo_fini(rdev);
e7d40b9a 2637 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2638 kfree(rdev->bios);
2639 rdev->bios = NULL;
2640 radeon_dummy_page_fini(rdev);
2641}
2642
2643
2644/*
2645 * CS stuff
2646 */
2647void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2648{
2649 /* FIXME: implement */
2650 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2651 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2652 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2653 radeon_ring_write(rdev, ib->length_dw);
2654}
2655
2656int r600_ib_test(struct radeon_device *rdev)
2657{
2658 struct radeon_ib *ib;
2659 uint32_t scratch;
2660 uint32_t tmp = 0;
2661 unsigned i;
2662 int r;
2663
2664 r = radeon_scratch_get(rdev, &scratch);
2665 if (r) {
2666 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2667 return r;
2668 }
2669 WREG32(scratch, 0xCAFEDEAD);
2670 r = radeon_ib_get(rdev, &ib);
2671 if (r) {
2672 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2673 return r;
2674 }
2675 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2676 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2677 ib->ptr[2] = 0xDEADBEEF;
2678 ib->ptr[3] = PACKET2(0);
2679 ib->ptr[4] = PACKET2(0);
2680 ib->ptr[5] = PACKET2(0);
2681 ib->ptr[6] = PACKET2(0);
2682 ib->ptr[7] = PACKET2(0);
2683 ib->ptr[8] = PACKET2(0);
2684 ib->ptr[9] = PACKET2(0);
2685 ib->ptr[10] = PACKET2(0);
2686 ib->ptr[11] = PACKET2(0);
2687 ib->ptr[12] = PACKET2(0);
2688 ib->ptr[13] = PACKET2(0);
2689 ib->ptr[14] = PACKET2(0);
2690 ib->ptr[15] = PACKET2(0);
2691 ib->length_dw = 16;
2692 r = radeon_ib_schedule(rdev, ib);
2693 if (r) {
2694 radeon_scratch_free(rdev, scratch);
2695 radeon_ib_free(rdev, &ib);
2696 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2697 return r;
2698 }
2699 r = radeon_fence_wait(ib->fence, false);
2700 if (r) {
2701 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2702 return r;
2703 }
2704 for (i = 0; i < rdev->usec_timeout; i++) {
2705 tmp = RREG32(scratch);
2706 if (tmp == 0xDEADBEEF)
2707 break;
2708 DRM_UDELAY(1);
2709 }
2710 if (i < rdev->usec_timeout) {
2711 DRM_INFO("ib test succeeded in %u usecs\n", i);
2712 } else {
2713 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2714 scratch, tmp);
2715 r = -EINVAL;
2716 }
2717 radeon_scratch_free(rdev, scratch);
2718 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2719 return r;
2720}
2721
d8f60cfc
AD		 2722/*
2723 * Interrupts
2724 *
2725 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2726 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2727 * writing to the ring and the GPU consuming, the GPU writes to the ring
2728 * and host consumes. As the host irq handler processes interrupts, it
2729 * increments the rptr. When the rptr catches up with the wptr, all the
2730 * current interrupts have been processed.
2731 */
2732
2733void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2734{
2735 u32 rb_bufsz;
2736
2737 /* Align ring size */
2738 rb_bufsz = drm_order(ring_size / 4);
2739 ring_size = (1 << rb_bufsz) * 4;
2740 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2741 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2742 rdev->ih.rptr = 0;
d8f60cfc
AD		 2743}
2744
0c45249f 2745static int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2746{
2747 int r;
2748
d8f60cfc
AD		 2749 /* Allocate ring buffer */
2750 if (rdev->ih.ring_obj == NULL) {
4c788679
JG		 2751 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2752 true,
2753 RADEON_GEM_DOMAIN_GTT,
2754 &rdev->ih.ring_obj);
d8f60cfc
AD		 2755 if (r) {
2756 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2757 return r;
2758 }
4c788679
JG		 2759 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2760 if (unlikely(r != 0))
2761 return r;
2762 r = radeon_bo_pin(rdev->ih.ring_obj,
2763 RADEON_GEM_DOMAIN_GTT,
2764 &rdev->ih.gpu_addr);
d8f60cfc 2765 if (r) {
4c788679 2766 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2767 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2768 return r;
2769 }
4c788679
JG		 2770 r = radeon_bo_kmap(rdev->ih.ring_obj,
2771 (void **)&rdev->ih.ring);
2772 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2773 if (r) {
2774 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2775 return r;
2776 }
2777 }
d8f60cfc
AD		 2778 return 0;
2779}
2780
2781static void r600_ih_ring_fini(struct radeon_device *rdev)
2782{
4c788679 2783 int r;
d8f60cfc 2784 if (rdev->ih.ring_obj) {
4c788679
JG		 2785 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2786 if (likely(r == 0)) {
2787 radeon_bo_kunmap(rdev->ih.ring_obj);
2788 radeon_bo_unpin(rdev->ih.ring_obj);
2789 radeon_bo_unreserve(rdev->ih.ring_obj);
2790 }
2791 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2792 rdev->ih.ring = NULL;
2793 rdev->ih.ring_obj = NULL;
2794 }
2795}
2796
45f9a39b 2797void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2798{
2799
45f9a39b
AD		 2800 if ((rdev->family >= CHIP_RV770) &&
2801 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2802 /* r7xx asics need to soft reset RLC before halting */
2803 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2804 RREG32(SRBM_SOFT_RESET);
2805 udelay(15000);
2806 WREG32(SRBM_SOFT_RESET, 0);
2807 RREG32(SRBM_SOFT_RESET);
2808 }
2809
2810 WREG32(RLC_CNTL, 0);
2811}
2812
2813static void r600_rlc_start(struct radeon_device *rdev)
2814{
2815 WREG32(RLC_CNTL, RLC_ENABLE);
2816}
2817
2818static int r600_rlc_init(struct radeon_device *rdev)
2819{
2820 u32 i;
2821 const __be32 *fw_data;
2822
2823 if (!rdev->rlc_fw)
2824 return -EINVAL;
2825
2826 r600_rlc_stop(rdev);
2827
2828 WREG32(RLC_HB_BASE, 0);
2829 WREG32(RLC_HB_CNTL, 0);
2830 WREG32(RLC_HB_RPTR, 0);
2831 WREG32(RLC_HB_WPTR, 0);
2832 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2833 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2834 WREG32(RLC_MC_CNTL, 0);
2835 WREG32(RLC_UCODE_CNTL, 0);
2836
2837 fw_data = (const __be32 *)rdev->rlc_fw->data;
45f9a39b
AD		 2838 if (rdev->family >= CHIP_CEDAR) {
2839 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2840 WREG32(RLC_UCODE_ADDR, i);
2841 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2842 }
2843 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2844 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2845 WREG32(RLC_UCODE_ADDR, i);
2846 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2847 }
2848 } else {
2849 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2850 WREG32(RLC_UCODE_ADDR, i);
2851 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2852 }
2853 }
2854 WREG32(RLC_UCODE_ADDR, 0);
2855
2856 r600_rlc_start(rdev);
2857
2858 return 0;
2859}
2860
2861static void r600_enable_interrupts(struct radeon_device *rdev)
2862{
2863 u32 ih_cntl = RREG32(IH_CNTL);
2864 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2865
2866 ih_cntl |= ENABLE_INTR;
2867 ih_rb_cntl |= IH_RB_ENABLE;
2868 WREG32(IH_CNTL, ih_cntl);
2869 WREG32(IH_RB_CNTL, ih_rb_cntl);
2870 rdev->ih.enabled = true;
2871}
2872
45f9a39b 2873void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2874{
2875 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2876 u32 ih_cntl = RREG32(IH_CNTL);
2877
2878 ih_rb_cntl &= ~IH_RB_ENABLE;
2879 ih_cntl &= ~ENABLE_INTR;
2880 WREG32(IH_RB_CNTL, ih_rb_cntl);
2881 WREG32(IH_CNTL, ih_cntl);
2882 /* set rptr, wptr to 0 */
2883 WREG32(IH_RB_RPTR, 0);
2884 WREG32(IH_RB_WPTR, 0);
2885 rdev->ih.enabled = false;
2886 rdev->ih.wptr = 0;
2887 rdev->ih.rptr = 0;
2888}
2889
e0df1ac5
AD		 2890static void r600_disable_interrupt_state(struct radeon_device *rdev)
2891{
2892 u32 tmp;
2893
2894 WREG32(CP_INT_CNTL, 0);
2895 WREG32(GRBM_INT_CNTL, 0);
2896 WREG32(DxMODE_INT_MASK, 0);
2897 if (ASIC_IS_DCE3(rdev)) {
2898 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2899 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2900 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2901 WREG32(DC_HPD1_INT_CONTROL, tmp);
2902 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2903 WREG32(DC_HPD2_INT_CONTROL, tmp);
2904 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2905 WREG32(DC_HPD3_INT_CONTROL, tmp);
2906 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2907 WREG32(DC_HPD4_INT_CONTROL, tmp);
2908 if (ASIC_IS_DCE32(rdev)) {
2909 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2910 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2911 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2912 WREG32(DC_HPD6_INT_CONTROL, tmp);
e0df1ac5
AD		 2913 }
2914 } else {
2915 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2916 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2917 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2918 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2919 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2920 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2921 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2922 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
e0df1ac5
AD		 2923 }
2924}
2925
d8f60cfc
AD		 2926int r600_irq_init(struct radeon_device *rdev)
2927{
2928 int ret = 0;
2929 int rb_bufsz;
2930 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2931
2932 /* allocate ring */
0c45249f 2933 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2934 if (ret)
2935 return ret;
2936
2937 /* disable irqs */
2938 r600_disable_interrupts(rdev);
2939
2940 /* init rlc */
2941 ret = r600_rlc_init(rdev);
2942 if (ret) {
2943 r600_ih_ring_fini(rdev);
2944 return ret;
2945 }
2946
2947 /* setup interrupt control */
2948 /* set dummy read address to ring address */
2949 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2950 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2951 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2952 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2953 */
2954 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2955 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2956 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2957 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2958
2959 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2960 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2961
2962 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2963 IH_WPTR_OVERFLOW_CLEAR |
2964 (rb_bufsz << 1));
2965 /* WPTR writeback, not yet */
2966 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2967 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2968 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2969
2970 WREG32(IH_RB_CNTL, ih_rb_cntl);
2971
2972 /* set rptr, wptr to 0 */
2973 WREG32(IH_RB_RPTR, 0);
2974 WREG32(IH_RB_WPTR, 0);
2975
2976 /* Default settings for IH_CNTL (disabled at first) */
2977 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2978 /* RPTR_REARM only works if msi's are enabled */
2979 if (rdev->msi_enabled)
2980 ih_cntl |= RPTR_REARM;
2981
2982#ifdef __BIG_ENDIAN
2983 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2984#endif
2985 WREG32(IH_CNTL, ih_cntl);
2986
2987 /* force the active interrupt state to all disabled */
45f9a39b
AD		 2988 if (rdev->family >= CHIP_CEDAR)
2989 evergreen_disable_interrupt_state(rdev);
2990 else
2991 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 2992
2993 /* enable irqs */
2994 r600_enable_interrupts(rdev);
2995
2996 return ret;
2997}
2998
0c45249f 2999void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 3000{
45f9a39b 3001 r600_irq_disable(rdev);
d8f60cfc 3002 r600_rlc_stop(rdev);
0c45249f
JG		 3003}
3004
3005void r600_irq_fini(struct radeon_device *rdev)
3006{
3007 r600_irq_suspend(rdev);
d8f60cfc
AD		 3008 r600_ih_ring_fini(rdev);
3009}
3010
3011int r600_irq_set(struct radeon_device *rdev)
3012{
e0df1ac5
AD		 3013 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3014 u32 mode_int = 0;
3015 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3016 u32 grbm_int_cntl = 0;
f2594933 3017 u32 hdmi1, hdmi2;
d8f60cfc 3018
003e69f9
JG		 3019 if (!rdev->irq.installed) {
3020 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
3021 return -EINVAL;
3022 }
d8f60cfc 3023 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3024 if (!rdev->ih.enabled) {
3025 r600_disable_interrupts(rdev);
3026 /* force the active interrupt state to all disabled */
3027 r600_disable_interrupt_state(rdev);
d8f60cfc 3028 return 0;
79c2bbc5 3029 }
d8f60cfc 3030
f2594933 3031 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5 3032 if (ASIC_IS_DCE3(rdev)) {
f2594933 3033 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3034 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3035 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3036 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3037 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3038 if (ASIC_IS_DCE32(rdev)) {
3039 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3040 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3041 }
3042 } else {
f2594933 3043 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3044 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3045 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3046 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3047 }
3048
d8f60cfc
AD		 3049 if (rdev->irq.sw_int) {
3050 DRM_DEBUG("r600_irq_set: sw int\n");
3051 cp_int_cntl |= RB_INT_ENABLE;
3052 }
3053 if (rdev->irq.crtc_vblank_int[0]) {
3054 DRM_DEBUG("r600_irq_set: vblank 0\n");
3055 mode_int |= D1MODE_VBLANK_INT_MASK;
3056 }
3057 if (rdev->irq.crtc_vblank_int[1]) {
3058 DRM_DEBUG("r600_irq_set: vblank 1\n");
3059 mode_int |= D2MODE_VBLANK_INT_MASK;
3060 }
e0df1ac5
AD		 3061 if (rdev->irq.hpd[0]) {
3062 DRM_DEBUG("r600_irq_set: hpd 1\n");
3063 hpd1 |= DC_HPDx_INT_EN;
3064 }
3065 if (rdev->irq.hpd[1]) {
3066 DRM_DEBUG("r600_irq_set: hpd 2\n");
3067 hpd2 |= DC_HPDx_INT_EN;
3068 }
3069 if (rdev->irq.hpd[2]) {
3070 DRM_DEBUG("r600_irq_set: hpd 3\n");
3071 hpd3 |= DC_HPDx_INT_EN;
3072 }
3073 if (rdev->irq.hpd[3]) {
3074 DRM_DEBUG("r600_irq_set: hpd 4\n");
3075 hpd4 |= DC_HPDx_INT_EN;
3076 }
3077 if (rdev->irq.hpd[4]) {
3078 DRM_DEBUG("r600_irq_set: hpd 5\n");
3079 hpd5 |= DC_HPDx_INT_EN;
3080 }
3081 if (rdev->irq.hpd[5]) {
3082 DRM_DEBUG("r600_irq_set: hpd 6\n");
3083 hpd6 |= DC_HPDx_INT_EN;
3084 }
f2594933
CK		 3085 if (rdev->irq.hdmi[0]) {
3086 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3087 hdmi1 |= R600_HDMI_INT_EN;
3088 }
3089 if (rdev->irq.hdmi[1]) {
3090 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3091 hdmi2 |= R600_HDMI_INT_EN;
3092 }
2031f77c
AD		 3093 if (rdev->irq.gui_idle) {
3094 DRM_DEBUG("gui idle\n");
3095 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3096 }
d8f60cfc
AD		 3097
3098 WREG32(CP_INT_CNTL, cp_int_cntl);
3099 WREG32(DxMODE_INT_MASK, mode_int);
2031f77c 3100 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
f2594933 3101 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
e0df1ac5 3102 if (ASIC_IS_DCE3(rdev)) {
f2594933 3103 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3104 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3105 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3106 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3107 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3108 if (ASIC_IS_DCE32(rdev)) {
3109 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3110 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3111 }
3112 } else {
f2594933 3113 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3114 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3115 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3116 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3117 }
d8f60cfc
AD		 3118
3119 return 0;
3120}
3121
e0df1ac5
AD		 3122static inline void r600_irq_ack(struct radeon_device *rdev,
3123 u32 *disp_int,
3124 u32 *disp_int_cont,
3125 u32 *disp_int_cont2)
d8f60cfc 3126{
e0df1ac5
AD		 3127 u32 tmp;
3128
3129 if (ASIC_IS_DCE3(rdev)) {
3130 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3131 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3132 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3133 } else {
3134 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3135 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3136 *disp_int_cont2 = 0;
3137 }
d8f60cfc 3138
e0df1ac5 3139 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3140 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 3141 if (*disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3142 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5 3143 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3144 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 3145 if (*disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3146 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5
AD		 3147 if (*disp_int & DC_HPD1_INTERRUPT) {
3148 if (ASIC_IS_DCE3(rdev)) {
3149 tmp = RREG32(DC_HPD1_INT_CONTROL);
3150 tmp |= DC_HPDx_INT_ACK;
3151 WREG32(DC_HPD1_INT_CONTROL, tmp);
3152 } else {
3153 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3154 tmp |= DC_HPDx_INT_ACK;
3155 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3156 }
3157 }
3158 if (*disp_int & DC_HPD2_INTERRUPT) {
3159 if (ASIC_IS_DCE3(rdev)) {
3160 tmp = RREG32(DC_HPD2_INT_CONTROL);
3161 tmp |= DC_HPDx_INT_ACK;
3162 WREG32(DC_HPD2_INT_CONTROL, tmp);
3163 } else {
3164 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3165 tmp |= DC_HPDx_INT_ACK;
3166 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3167 }
3168 }
3169 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3170 if (ASIC_IS_DCE3(rdev)) {
3171 tmp = RREG32(DC_HPD3_INT_CONTROL);
3172 tmp |= DC_HPDx_INT_ACK;
3173 WREG32(DC_HPD3_INT_CONTROL, tmp);
3174 } else {
3175 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3176 tmp |= DC_HPDx_INT_ACK;
3177 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3178 }
3179 }
3180 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3181 tmp = RREG32(DC_HPD4_INT_CONTROL);
3182 tmp |= DC_HPDx_INT_ACK;
3183 WREG32(DC_HPD4_INT_CONTROL, tmp);
3184 }
3185 if (ASIC_IS_DCE32(rdev)) {
3186 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3187 tmp = RREG32(DC_HPD5_INT_CONTROL);
3188 tmp |= DC_HPDx_INT_ACK;
3189 WREG32(DC_HPD5_INT_CONTROL, tmp);
3190 }
3191 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3192 tmp = RREG32(DC_HPD5_INT_CONTROL);
3193 tmp |= DC_HPDx_INT_ACK;
3194 WREG32(DC_HPD6_INT_CONTROL, tmp);
3195 }
3196 }
f2594933
CK		 3197 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3198 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3199 }
3200 if (ASIC_IS_DCE3(rdev)) {
3201 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3202 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3203 }
3204 } else {
3205 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3206 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3207 }
3208 }
d8f60cfc
AD		 3209}
3210
3211void r600_irq_disable(struct radeon_device *rdev)
3212{
e0df1ac5 3213 u32 disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc
AD		 3214
3215 r600_disable_interrupts(rdev);
3216 /* Wait and acknowledge irq */
3217 mdelay(1);
e0df1ac5
AD		 3218 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3219 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3220}
3221
3222static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3223{
3224 u32 wptr, tmp;
3ce0a23d 3225
d8f60cfc
AD		 3226 /* XXX use writeback */
3227 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3228
d8f60cfc 3229 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3230 /* When a ring buffer overflow happen start parsing interrupt
3231 * from the last not overwritten vector (wptr + 16). Hopefully
3232 * this should allow us to catchup.
3233 */
3234 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3235 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3236 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3237 tmp = RREG32(IH_RB_CNTL);
3238 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3239 WREG32(IH_RB_CNTL, tmp);
3240 }
0c45249f 3241 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3242}
3ce0a23d 3243
d8f60cfc
AD		 3244/* r600 IV Ring
3245 * Each IV ring entry is 128 bits:
3246 * [7:0] - interrupt source id
3247 * [31:8] - reserved
3248 * [59:32] - interrupt source data
3249 * [127:60] - reserved
3250 *
3251 * The basic interrupt vector entries
3252 * are decoded as follows:
3253 * src_id src_data description
3254 * 1 0 D1 Vblank
3255 * 1 1 D1 Vline
3256 * 5 0 D2 Vblank
3257 * 5 1 D2 Vline
3258 * 19 0 FP Hot plug detection A
3259 * 19 1 FP Hot plug detection B
3260 * 19 2 DAC A auto-detection
3261 * 19 3 DAC B auto-detection
f2594933
CK		 3262 * 21 4 HDMI block A
3263 * 21 5 HDMI block B
d8f60cfc
AD		 3264 * 176 - CP_INT RB
3265 * 177 - CP_INT IB1
3266 * 178 - CP_INT IB2
3267 * 181 - EOP Interrupt
3268 * 233 - GUI Idle
3269 *
3270 * Note, these are based on r600 and may need to be
3271 * adjusted or added to on newer asics
3272 */
3273
3274int r600_irq_process(struct radeon_device *rdev)
3275{
3276 u32 wptr = r600_get_ih_wptr(rdev);
3277 u32 rptr = rdev->ih.rptr;
3278 u32 src_id, src_data;
e0df1ac5 3279 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc 3280 unsigned long flags;
d4877cf2 3281 bool queue_hotplug = false;
d8f60cfc
AD		 3282
3283 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
79c2bbc5
JG		 3284 if (!rdev->ih.enabled)
3285 return IRQ_NONE;
d8f60cfc
AD		 3286
3287 spin_lock_irqsave(&rdev->ih.lock, flags);
3288
3289 if (rptr == wptr) {
3290 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3291 return IRQ_NONE;
3292 }
3293 if (rdev->shutdown) {
3294 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3295 return IRQ_NONE;
3296 }
3297
3298restart_ih:
3299 /* display interrupts */
e0df1ac5 3300 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
d8f60cfc
AD		 3301
3302 rdev->ih.wptr = wptr;
3303 while (rptr != wptr) {
3304 /* wptr/rptr are in bytes! */
3305 ring_index = rptr / 4;
3306 src_id = rdev->ih.ring[ring_index] & 0xff;
3307 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3308
3309 switch (src_id) {
3310 case 1: /* D1 vblank/vline */
3311 switch (src_data) {
3312 case 0: /* D1 vblank */
3313 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3314 drm_handle_vblank(rdev->ddev, 0);
839461d3 3315 rdev->pm.vblank_sync = true;
73a6d3fc 3316 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3317 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3318 DRM_DEBUG("IH: D1 vblank\n");
3319 }
3320 break;
3321 case 1: /* D1 vline */
3322 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3323 disp_int &= ~LB_D1_VLINE_INTERRUPT;
3324 DRM_DEBUG("IH: D1 vline\n");
3325 }
3326 break;
3327 default:
b042589c 3328 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3329 break;
3330 }
3331 break;
3332 case 5: /* D2 vblank/vline */
3333 switch (src_data) {
3334 case 0: /* D2 vblank */
3335 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3336 drm_handle_vblank(rdev->ddev, 1);
839461d3 3337 rdev->pm.vblank_sync = true;
73a6d3fc 3338 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3339 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3340 DRM_DEBUG("IH: D2 vblank\n");
3341 }
3342 break;
3343 case 1: /* D1 vline */
3344 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3345 disp_int &= ~LB_D2_VLINE_INTERRUPT;
3346 DRM_DEBUG("IH: D2 vline\n");
3347 }
3348 break;
3349 default:
b042589c 3350 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3351 break;
3352 }
3353 break;
e0df1ac5
AD		 3354 case 19: /* HPD/DAC hotplug */
3355 switch (src_data) {
3356 case 0:
3357 if (disp_int & DC_HPD1_INTERRUPT) {
3358 disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3359 queue_hotplug = true;
3360 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3361 }
3362 break;
3363 case 1:
3364 if (disp_int & DC_HPD2_INTERRUPT) {
3365 disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3366 queue_hotplug = true;
3367 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3368 }
3369 break;
3370 case 4:
3371 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3372 disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3373 queue_hotplug = true;
3374 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3375 }
3376 break;
3377 case 5:
3378 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3379 disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3380 queue_hotplug = true;
3381 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3382 }
3383 break;
3384 case 10:
3385 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
5898b1f3 3386 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3387 queue_hotplug = true;
3388 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3389 }
3390 break;
3391 case 12:
3392 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
5898b1f3 3393 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3394 queue_hotplug = true;
3395 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3396 }
3397 break;
3398 default:
b042589c 3399 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3400 break;
3401 }
3402 break;
f2594933
CK		 3403 case 21: /* HDMI */
3404 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3405 r600_audio_schedule_polling(rdev);
3406 break;
d8f60cfc
AD		 3407 case 176: /* CP_INT in ring buffer */
3408 case 177: /* CP_INT in IB1 */
3409 case 178: /* CP_INT in IB2 */
3410 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3411 radeon_fence_process(rdev);
3412 break;
3413 case 181: /* CP EOP event */
3414 DRM_DEBUG("IH: CP EOP\n");
3415 break;
2031f77c
AD		 3416 case 233: /* GUI IDLE */
3417 DRM_DEBUG("IH: CP EOP\n");
3418 rdev->pm.gui_idle = true;
3419 wake_up(&rdev->irq.idle_queue);
3420 break;
d8f60cfc 3421 default:
b042589c 3422 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3423 break;
3424 }
3425
3426 /* wptr/rptr are in bytes! */
0c45249f
JG		 3427 rptr += 16;
3428 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 3429 }
3430 /* make sure wptr hasn't changed while processing */
3431 wptr = r600_get_ih_wptr(rdev);
3432 if (wptr != rdev->ih.wptr)
3433 goto restart_ih;
d4877cf2
AD		 3434 if (queue_hotplug)
3435 queue_work(rdev->wq, &rdev->hotplug_work);
d8f60cfc
AD		 3436 rdev->ih.rptr = rptr;
3437 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3438 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3439 return IRQ_HANDLED;
3440}
3ce0a23d
JG		 3441
3442/*
3443 * Debugfs info
3444 */
3445#if defined(CONFIG_DEBUG_FS)
3446
3447static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 3448{
3ce0a23d
JG		 3449 struct drm_info_node *node = (struct drm_info_node *) m->private;
3450 struct drm_device *dev = node->minor->dev;
3451 struct radeon_device *rdev = dev->dev_private;
3ce0a23d
JG		 3452 unsigned count, i, j;
3453
3454 radeon_ring_free_size(rdev);
d6840766 3455 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3ce0a23d 3456 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
d6840766
RM		 3457 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3458 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3459 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3460 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3ce0a23d
JG		 3461 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3462 seq_printf(m, "%u dwords in ring\n", count);
d6840766 3463 i = rdev->cp.rptr;
3ce0a23d 3464 for (j = 0; j <= count; j++) {
3ce0a23d 3465 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
d6840766 3466 i = (i + 1) & rdev->cp.ptr_mask;
3ce0a23d
JG		 3467 }
3468 return 0;
3469}
3470
3471static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3472{
3473 struct drm_info_node *node = (struct drm_info_node *) m->private;
3474 struct drm_device *dev = node->minor->dev;
3475 struct radeon_device *rdev = dev->dev_private;
3476
3477 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3478 DREG32_SYS(m, rdev, VM_L2_STATUS);
3479 return 0;
3480}
3481
3482static struct drm_info_list r600_mc_info_list[] = {
3483 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3484 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3485};
3486#endif
3487
3488int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3489{
3490#if defined(CONFIG_DEBUG_FS)
3491 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3492#else
3493 return 0;
3494#endif
771fe6b9 3495}
062b389c
JG		 3496
3497/**
3498 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3499 * rdev: radeon device structure
3500 * bo: buffer object struct which userspace is waiting for idle
3501 *
3502 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3503 * through ring buffer, this leads to corruption in rendering, see
3504 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3505 * directly perform HDP flush by writing register through MMIO.
3506 */
3507void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3508{
3509 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3510}
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