]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/radeon/r100.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drivers/gpu/drm: Update WARN uses
[net-next-2.6.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9
JG		 30#include "drmP.h"
31#include "drm.h"
32#include "radeon_drm.h"
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "r100d.h"
d4550907
JG		 37#include "rs100d.h"
38#include "rv200d.h"
39#include "rv250d.h"
49e02b73 40#include "atom.h"
3ce0a23d 41
70967ab9
BH		 42#include <linux/firmware.h>
43#include <linux/platform_device.h>
44
551ebd83
DA		 45#include "r100_reg_safe.h"
46#include "rn50_reg_safe.h"
47
70967ab9
BH		 48/* Firmware Names */
49#define FIRMWARE_R100 "radeon/R100_cp.bin"
50#define FIRMWARE_R200 "radeon/R200_cp.bin"
51#define FIRMWARE_R300 "radeon/R300_cp.bin"
52#define FIRMWARE_R420 "radeon/R420_cp.bin"
53#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55#define FIRMWARE_R520 "radeon/R520_cp.bin"
56
57MODULE_FIRMWARE(FIRMWARE_R100);
58MODULE_FIRMWARE(FIRMWARE_R200);
59MODULE_FIRMWARE(FIRMWARE_R300);
60MODULE_FIRMWARE(FIRMWARE_R420);
61MODULE_FIRMWARE(FIRMWARE_RS690);
62MODULE_FIRMWARE(FIRMWARE_RS600);
63MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 64
551ebd83
DA		 65#include "r100_track.h"
66
771fe6b9
JG		 67/* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 69 */
771fe6b9 70
ce8f5370 71void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 72{
73 int i;
ce8f5370
AD		 74 rdev->pm.dynpm_can_upclock = true;
75 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 76
ce8f5370
AD		 77 switch (rdev->pm.dynpm_planned_action) {
78 case DYNPM_ACTION_MINIMUM:
a48b9b4e 79 rdev->pm.requested_power_state_index = 0;
ce8f5370 80 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 81 break;
ce8f5370 82 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 83 if (rdev->pm.current_power_state_index == 0) {
84 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 85 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 86 } else {
87 if (rdev->pm.active_crtc_count > 1) {
88 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 89 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 90 continue;
91 else if (i >= rdev->pm.current_power_state_index) {
92 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
93 break;
94 } else {
95 rdev->pm.requested_power_state_index = i;
96 break;
97 }
98 }
99 } else
100 rdev->pm.requested_power_state_index =
101 rdev->pm.current_power_state_index - 1;
102 }
d7311171
AD		 103 /* don't use the power state if crtcs are active and no display flag is set */
104 if ((rdev->pm.active_crtc_count > 0) &&
105 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
106 RADEON_PM_MODE_NO_DISPLAY)) {
107 rdev->pm.requested_power_state_index++;
108 }
a48b9b4e 109 break;
ce8f5370 110 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 111 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
112 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 113 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 114 } else {
115 if (rdev->pm.active_crtc_count > 1) {
116 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 117 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 118 continue;
119 else if (i <= rdev->pm.current_power_state_index) {
120 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
121 break;
122 } else {
123 rdev->pm.requested_power_state_index = i;
124 break;
125 }
126 }
127 } else
128 rdev->pm.requested_power_state_index =
129 rdev->pm.current_power_state_index + 1;
130 }
131 break;
ce8f5370 132 case DYNPM_ACTION_DEFAULT:
58e21dff 133 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 134 rdev->pm.dynpm_can_upclock = false;
58e21dff 135 break;
ce8f5370 136 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 137 default:
138 DRM_ERROR("Requested mode for not defined action\n");
139 return;
140 }
141 /* only one clock mode per power state */
142 rdev->pm.requested_clock_mode_index = 0;
143
d9fdaafb 144 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 145 rdev->pm.power_state[rdev->pm.requested_power_state_index].
146 clock_info[rdev->pm.requested_clock_mode_index].sclk,
147 rdev->pm.power_state[rdev->pm.requested_power_state_index].
148 clock_info[rdev->pm.requested_clock_mode_index].mclk,
149 rdev->pm.power_state[rdev->pm.requested_power_state_index].
150 pcie_lanes);
a48b9b4e
AD		 151}
152
ce8f5370
AD		 153void r100_pm_init_profile(struct radeon_device *rdev)
154{
155 /* default */
156 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
157 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
158 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
159 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
160 /* low sh */
161 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
162 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
163 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
164 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 165 /* mid sh */
166 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
167 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
168 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
169 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 170 /* high sh */
171 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
172 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
173 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
174 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
175 /* low mh */
176 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
177 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
178 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
179 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 180 /* mid mh */
181 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
182 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
183 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
184 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 185 /* high mh */
186 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
187 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
188 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
189 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 190}
191
49e02b73
AD		 192void r100_pm_misc(struct radeon_device *rdev)
193{
49e02b73
AD		 194 int requested_index = rdev->pm.requested_power_state_index;
195 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
196 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
197 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
198
199 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
200 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
201 tmp = RREG32(voltage->gpio.reg);
202 if (voltage->active_high)
203 tmp |= voltage->gpio.mask;
204 else
205 tmp &= ~(voltage->gpio.mask);
206 WREG32(voltage->gpio.reg, tmp);
207 if (voltage->delay)
208 udelay(voltage->delay);
209 } else {
210 tmp = RREG32(voltage->gpio.reg);
211 if (voltage->active_high)
212 tmp &= ~voltage->gpio.mask;
213 else
214 tmp |= voltage->gpio.mask;
215 WREG32(voltage->gpio.reg, tmp);
216 if (voltage->delay)
217 udelay(voltage->delay);
218 }
219 }
220
221 sclk_cntl = RREG32_PLL(SCLK_CNTL);
222 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
223 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
224 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
225 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
226 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
227 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
228 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
229 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
230 else
231 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
232 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
233 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
234 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
235 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
236 } else
237 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
238
239 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
240 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
241 if (voltage->delay) {
242 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
243 switch (voltage->delay) {
244 case 33:
245 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
246 break;
247 case 66:
248 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
249 break;
250 case 99:
251 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
252 break;
253 case 132:
254 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
255 break;
256 }
257 } else
258 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
259 } else
260 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
261
262 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
263 sclk_cntl &= ~FORCE_HDP;
264 else
265 sclk_cntl |= FORCE_HDP;
266
267 WREG32_PLL(SCLK_CNTL, sclk_cntl);
268 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
269 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
270
271 /* set pcie lanes */
272 if ((rdev->flags & RADEON_IS_PCIE) &&
273 !(rdev->flags & RADEON_IS_IGP) &&
274 rdev->asic->set_pcie_lanes &&
275 (ps->pcie_lanes !=
276 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
277 radeon_set_pcie_lanes(rdev,
278 ps->pcie_lanes);
d9fdaafb 279 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 280 }
49e02b73
AD		 281}
282
283void r100_pm_prepare(struct radeon_device *rdev)
284{
285 struct drm_device *ddev = rdev->ddev;
286 struct drm_crtc *crtc;
287 struct radeon_crtc *radeon_crtc;
288 u32 tmp;
289
290 /* disable any active CRTCs */
291 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
292 radeon_crtc = to_radeon_crtc(crtc);
293 if (radeon_crtc->enabled) {
294 if (radeon_crtc->crtc_id) {
295 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
296 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
297 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
298 } else {
299 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
300 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
301 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
302 }
303 }
304 }
305}
306
307void r100_pm_finish(struct radeon_device *rdev)
308{
309 struct drm_device *ddev = rdev->ddev;
310 struct drm_crtc *crtc;
311 struct radeon_crtc *radeon_crtc;
312 u32 tmp;
313
314 /* enable any active CRTCs */
315 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
316 radeon_crtc = to_radeon_crtc(crtc);
317 if (radeon_crtc->enabled) {
318 if (radeon_crtc->crtc_id) {
319 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
320 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
321 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
322 } else {
323 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
324 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
325 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
326 }
327 }
328 }
329}
330
def9ba9c
AD		 331bool r100_gui_idle(struct radeon_device *rdev)
332{
333 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
334 return false;
335 else
336 return true;
337}
338
05a05c50
AD		 339/* hpd for digital panel detect/disconnect */
340bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
341{
342 bool connected = false;
343
344 switch (hpd) {
345 case RADEON_HPD_1:
346 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
347 connected = true;
348 break;
349 case RADEON_HPD_2:
350 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
351 connected = true;
352 break;
353 default:
354 break;
355 }
356 return connected;
357}
358
359void r100_hpd_set_polarity(struct radeon_device *rdev,
360 enum radeon_hpd_id hpd)
361{
362 u32 tmp;
363 bool connected = r100_hpd_sense(rdev, hpd);
364
365 switch (hpd) {
366 case RADEON_HPD_1:
367 tmp = RREG32(RADEON_FP_GEN_CNTL);
368 if (connected)
369 tmp &= ~RADEON_FP_DETECT_INT_POL;
370 else
371 tmp |= RADEON_FP_DETECT_INT_POL;
372 WREG32(RADEON_FP_GEN_CNTL, tmp);
373 break;
374 case RADEON_HPD_2:
375 tmp = RREG32(RADEON_FP2_GEN_CNTL);
376 if (connected)
377 tmp &= ~RADEON_FP2_DETECT_INT_POL;
378 else
379 tmp |= RADEON_FP2_DETECT_INT_POL;
380 WREG32(RADEON_FP2_GEN_CNTL, tmp);
381 break;
382 default:
383 break;
384 }
385}
386
387void r100_hpd_init(struct radeon_device *rdev)
388{
389 struct drm_device *dev = rdev->ddev;
390 struct drm_connector *connector;
391
392 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
393 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
394 switch (radeon_connector->hpd.hpd) {
395 case RADEON_HPD_1:
396 rdev->irq.hpd[0] = true;
397 break;
398 case RADEON_HPD_2:
399 rdev->irq.hpd[1] = true;
400 break;
401 default:
402 break;
403 }
404 }
003e69f9
JG		 405 if (rdev->irq.installed)
406 r100_irq_set(rdev);
05a05c50
AD		 407}
408
409void r100_hpd_fini(struct radeon_device *rdev)
410{
411 struct drm_device *dev = rdev->ddev;
412 struct drm_connector *connector;
413
414 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
415 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
416 switch (radeon_connector->hpd.hpd) {
417 case RADEON_HPD_1:
418 rdev->irq.hpd[0] = false;
419 break;
420 case RADEON_HPD_2:
421 rdev->irq.hpd[1] = false;
422 break;
423 default:
424 break;
425 }
426 }
427}
428
771fe6b9
JG		 429/*
430 * PCI GART
431 */
432void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
433{
434 /* TODO: can we do somethings here ? */
435 /* It seems hw only cache one entry so we should discard this
436 * entry otherwise if first GPU GART read hit this entry it
437 * could end up in wrong address. */
438}
439
4aac0473 440int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 441{
771fe6b9
JG		 442 int r;
443
4aac0473 444 if (rdev->gart.table.ram.ptr) {
fce7d61b 445 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 446 return 0;
447 }
771fe6b9
JG		 448 /* Initialize common gart structure */
449 r = radeon_gart_init(rdev);
4aac0473 450 if (r)
771fe6b9 451 return r;
4aac0473
JG		 452 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
453 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
454 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
455 return radeon_gart_table_ram_alloc(rdev);
456}
457
17e15b0c
DA		 458/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
459void r100_enable_bm(struct radeon_device *rdev)
460{
461 uint32_t tmp;
462 /* Enable bus mastering */
463 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
464 WREG32(RADEON_BUS_CNTL, tmp);
465}
466
4aac0473
JG		 467int r100_pci_gart_enable(struct radeon_device *rdev)
468{
469 uint32_t tmp;
470
82568565 471 radeon_gart_restore(rdev);
771fe6b9
JG		 472 /* discard memory request outside of configured range */
473 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
474 WREG32(RADEON_AIC_CNTL, tmp);
475 /* set address range for PCI address translate */
d594e46a
JG		 476 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
477 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 478 /* set PCI GART page-table base address */
479 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
480 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
481 WREG32(RADEON_AIC_CNTL, tmp);
482 r100_pci_gart_tlb_flush(rdev);
483 rdev->gart.ready = true;
484 return 0;
485}
486
487void r100_pci_gart_disable(struct radeon_device *rdev)
488{
489 uint32_t tmp;
490
491 /* discard memory request outside of configured range */
492 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
493 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
494 WREG32(RADEON_AIC_LO_ADDR, 0);
495 WREG32(RADEON_AIC_HI_ADDR, 0);
496}
497
498int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
499{
500 if (i < 0 || i > rdev->gart.num_gpu_pages) {
501 return -EINVAL;
502 }
ed10f95d 503 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 504 return 0;
505}
506
4aac0473 507void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 508{
f9274562 509 radeon_gart_fini(rdev);
4aac0473
JG		 510 r100_pci_gart_disable(rdev);
511 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 512}
513
7ed220d7
MD		 514int r100_irq_set(struct radeon_device *rdev)
515{
516 uint32_t tmp = 0;
517
003e69f9 518 if (!rdev->irq.installed) {
fce7d61b 519 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 520 WREG32(R_000040_GEN_INT_CNTL, 0);
521 return -EINVAL;
522 }
7ed220d7
MD		 523 if (rdev->irq.sw_int) {
524 tmp |= RADEON_SW_INT_ENABLE;
525 }
2031f77c
AD		 526 if (rdev->irq.gui_idle) {
527 tmp |= RADEON_GUI_IDLE_MASK;
528 }
7ed220d7
MD		 529 if (rdev->irq.crtc_vblank_int[0]) {
530 tmp |= RADEON_CRTC_VBLANK_MASK;
531 }
532 if (rdev->irq.crtc_vblank_int[1]) {
533 tmp |= RADEON_CRTC2_VBLANK_MASK;
534 }
05a05c50
AD		 535 if (rdev->irq.hpd[0]) {
536 tmp |= RADEON_FP_DETECT_MASK;
537 }
538 if (rdev->irq.hpd[1]) {
539 tmp |= RADEON_FP2_DETECT_MASK;
540 }
7ed220d7
MD		 541 WREG32(RADEON_GEN_INT_CNTL, tmp);
542 return 0;
543}
544
9f022ddf
JG		 545void r100_irq_disable(struct radeon_device *rdev)
546{
547 u32 tmp;
548
549 WREG32(R_000040_GEN_INT_CNTL, 0);
550 /* Wait and acknowledge irq */
551 mdelay(1);
552 tmp = RREG32(R_000044_GEN_INT_STATUS);
553 WREG32(R_000044_GEN_INT_STATUS, tmp);
554}
555
7ed220d7
MD		 556static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
557{
558 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 559 uint32_t irq_mask = RADEON_SW_INT_TEST |
560 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
561 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7 562
2031f77c
AD		 563 /* the interrupt works, but the status bit is permanently asserted */
564 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
565 if (!rdev->irq.gui_idle_acked)
566 irq_mask |= RADEON_GUI_IDLE_STAT;
567 }
568
7ed220d7
MD		 569 if (irqs) {
570 WREG32(RADEON_GEN_INT_STATUS, irqs);
571 }
572 return irqs & irq_mask;
573}
574
575int r100_irq_process(struct radeon_device *rdev)
576{
3e5cb98d 577 uint32_t status, msi_rearm;
d4877cf2 578 bool queue_hotplug = false;
7ed220d7 579
2031f77c
AD		 580 /* reset gui idle ack. the status bit is broken */
581 rdev->irq.gui_idle_acked = false;
582
7ed220d7
MD		 583 status = r100_irq_ack(rdev);
584 if (!status) {
585 return IRQ_NONE;
586 }
a513c184
JG		 587 if (rdev->shutdown) {
588 return IRQ_NONE;
589 }
7ed220d7
MD		 590 while (status) {
591 /* SW interrupt */
592 if (status & RADEON_SW_INT_TEST) {
593 radeon_fence_process(rdev);
594 }
2031f77c
AD		 595 /* gui idle interrupt */
596 if (status & RADEON_GUI_IDLE_STAT) {
597 rdev->irq.gui_idle_acked = true;
598 rdev->pm.gui_idle = true;
599 wake_up(&rdev->irq.idle_queue);
600 }
7ed220d7
MD		 601 /* Vertical blank interrupts */
602 if (status & RADEON_CRTC_VBLANK_STAT) {
603 drm_handle_vblank(rdev->ddev, 0);
839461d3 604 rdev->pm.vblank_sync = true;
73a6d3fc 605 wake_up(&rdev->irq.vblank_queue);
7ed220d7
MD		 606 }
607 if (status & RADEON_CRTC2_VBLANK_STAT) {
608 drm_handle_vblank(rdev->ddev, 1);
839461d3 609 rdev->pm.vblank_sync = true;
73a6d3fc 610 wake_up(&rdev->irq.vblank_queue);
7ed220d7 611 }
05a05c50 612 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 613 queue_hotplug = true;
614 DRM_DEBUG("HPD1\n");
05a05c50
AD		 615 }
616 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 617 queue_hotplug = true;
618 DRM_DEBUG("HPD2\n");
05a05c50 619 }
7ed220d7
MD		 620 status = r100_irq_ack(rdev);
621 }
2031f77c
AD		 622 /* reset gui idle ack. the status bit is broken */
623 rdev->irq.gui_idle_acked = false;
d4877cf2
AD		 624 if (queue_hotplug)
625 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 626 if (rdev->msi_enabled) {
627 switch (rdev->family) {
628 case CHIP_RS400:
629 case CHIP_RS480:
630 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
631 WREG32(RADEON_AIC_CNTL, msi_rearm);
632 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
633 break;
634 default:
635 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
636 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
637 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
638 break;
639 }
640 }
7ed220d7
MD		 641 return IRQ_HANDLED;
642}
643
644u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
645{
646 if (crtc == 0)
647 return RREG32(RADEON_CRTC_CRNT_FRAME);
648 else
649 return RREG32(RADEON_CRTC2_CRNT_FRAME);
650}
651
9e5b2af7
PN		 652/* Who ever call radeon_fence_emit should call ring_lock and ask
653 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 654void r100_fence_ring_emit(struct radeon_device *rdev,
655 struct radeon_fence *fence)
656{
9e5b2af7
PN		 657 /* We have to make sure that caches are flushed before
658 * CPU might read something from VRAM. */
659 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
660 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
661 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
662 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 663 /* Wait until IDLE & CLEAN */
4612dc97
AD		 664 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
665 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
cafe6609
JG		 666 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
667 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
668 RADEON_HDP_READ_BUFFER_INVALIDATE);
669 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
670 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
771fe6b9
JG		 671 /* Emit fence sequence & fire IRQ */
672 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
673 radeon_ring_write(rdev, fence->seq);
674 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
675 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
676}
677
771fe6b9
JG		 678int r100_copy_blit(struct radeon_device *rdev,
679 uint64_t src_offset,
680 uint64_t dst_offset,
681 unsigned num_pages,
682 struct radeon_fence *fence)
683{
684 uint32_t cur_pages;
685 uint32_t stride_bytes = PAGE_SIZE;
686 uint32_t pitch;
687 uint32_t stride_pixels;
688 unsigned ndw;
689 int num_loops;
690 int r = 0;
691
692 /* radeon limited to 16k stride */
693 stride_bytes &= 0x3fff;
694 /* radeon pitch is /64 */
695 pitch = stride_bytes / 64;
696 stride_pixels = stride_bytes / 4;
697 num_loops = DIV_ROUND_UP(num_pages, 8191);
698
699 /* Ask for enough room for blit + flush + fence */
700 ndw = 64 + (10 * num_loops);
701 r = radeon_ring_lock(rdev, ndw);
702 if (r) {
703 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
704 return -EINVAL;
705 }
706 while (num_pages > 0) {
707 cur_pages = num_pages;
708 if (cur_pages > 8191) {
709 cur_pages = 8191;
710 }
711 num_pages -= cur_pages;
712
713 /* pages are in Y direction - height
714 page width in X direction - width */
715 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
716 radeon_ring_write(rdev,
717 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
718 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
719 RADEON_GMC_SRC_CLIPPING |
720 RADEON_GMC_DST_CLIPPING |
721 RADEON_GMC_BRUSH_NONE |
722 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
723 RADEON_GMC_SRC_DATATYPE_COLOR |
724 RADEON_ROP3_S |
725 RADEON_DP_SRC_SOURCE_MEMORY |
726 RADEON_GMC_CLR_CMP_CNTL_DIS |
727 RADEON_GMC_WR_MSK_DIS);
728 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
729 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
730 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
731 radeon_ring_write(rdev, 0);
732 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
733 radeon_ring_write(rdev, num_pages);
734 radeon_ring_write(rdev, num_pages);
735 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
736 }
737 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
738 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
739 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
740 radeon_ring_write(rdev,
741 RADEON_WAIT_2D_IDLECLEAN |
742 RADEON_WAIT_HOST_IDLECLEAN |
743 RADEON_WAIT_DMA_GUI_IDLE);
744 if (fence) {
745 r = radeon_fence_emit(rdev, fence);
746 }
747 radeon_ring_unlock_commit(rdev);
748 return r;
749}
750
45600232
JG		 751static int r100_cp_wait_for_idle(struct radeon_device *rdev)
752{
753 unsigned i;
754 u32 tmp;
755
756 for (i = 0; i < rdev->usec_timeout; i++) {
757 tmp = RREG32(R_000E40_RBBM_STATUS);
758 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
759 return 0;
760 }
761 udelay(1);
762 }
763 return -1;
764}
765
771fe6b9
JG		 766void r100_ring_start(struct radeon_device *rdev)
767{
768 int r;
769
770 r = radeon_ring_lock(rdev, 2);
771 if (r) {
772 return;
773 }
774 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
775 radeon_ring_write(rdev,
776 RADEON_ISYNC_ANY2D_IDLE3D |
777 RADEON_ISYNC_ANY3D_IDLE2D |
778 RADEON_ISYNC_WAIT_IDLEGUI |
779 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
780 radeon_ring_unlock_commit(rdev);
781}
782
70967ab9
BH		 783
784/* Load the microcode for the CP */
785static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 786{
70967ab9
BH		 787 struct platform_device *pdev;
788 const char *fw_name = NULL;
789 int err;
771fe6b9 790
d9fdaafb 791 DRM_DEBUG_KMS("\n");
771fe6b9 792
70967ab9
BH		 793 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
794 err = IS_ERR(pdev);
795 if (err) {
796 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
797 return -EINVAL;
798 }
771fe6b9
JG		 799 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
800 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
801 (rdev->family == CHIP_RS200)) {
802 DRM_INFO("Loading R100 Microcode\n");
70967ab9 803 fw_name = FIRMWARE_R100;
771fe6b9
JG		 804 } else if ((rdev->family == CHIP_R200) ||
805 (rdev->family == CHIP_RV250) ||
806 (rdev->family == CHIP_RV280) ||
807 (rdev->family == CHIP_RS300)) {
808 DRM_INFO("Loading R200 Microcode\n");
70967ab9 809 fw_name = FIRMWARE_R200;
771fe6b9
JG		 810 } else if ((rdev->family == CHIP_R300) ||
811 (rdev->family == CHIP_R350) ||
812 (rdev->family == CHIP_RV350) ||
813 (rdev->family == CHIP_RV380) ||
814 (rdev->family == CHIP_RS400) ||
815 (rdev->family == CHIP_RS480)) {
816 DRM_INFO("Loading R300 Microcode\n");
70967ab9 817 fw_name = FIRMWARE_R300;
771fe6b9
JG		 818 } else if ((rdev->family == CHIP_R420) ||
819 (rdev->family == CHIP_R423) ||
820 (rdev->family == CHIP_RV410)) {
821 DRM_INFO("Loading R400 Microcode\n");
70967ab9 822 fw_name = FIRMWARE_R420;
771fe6b9
JG		 823 } else if ((rdev->family == CHIP_RS690) ||
824 (rdev->family == CHIP_RS740)) {
825 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 826 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 827 } else if (rdev->family == CHIP_RS600) {
828 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 829 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 830 } else if ((rdev->family == CHIP_RV515) ||
831 (rdev->family == CHIP_R520) ||
832 (rdev->family == CHIP_RV530) ||
833 (rdev->family == CHIP_R580) ||
834 (rdev->family == CHIP_RV560) ||
835 (rdev->family == CHIP_RV570)) {
836 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 837 fw_name = FIRMWARE_R520;
838 }
839
3ce0a23d 840 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 841 platform_device_unregister(pdev);
842 if (err) {
843 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
844 fw_name);
3ce0a23d 845 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 846 printk(KERN_ERR
847 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 848 rdev->me_fw->size, fw_name);
70967ab9 849 err = -EINVAL;
3ce0a23d
JG		 850 release_firmware(rdev->me_fw);
851 rdev->me_fw = NULL;
70967ab9
BH		 852 }
853 return err;
854}
d4550907 855
70967ab9
BH		 856static void r100_cp_load_microcode(struct radeon_device *rdev)
857{
858 const __be32 *fw_data;
859 int i, size;
860
861 if (r100_gui_wait_for_idle(rdev)) {
862 printk(KERN_WARNING "Failed to wait GUI idle while "
863 "programming pipes. Bad things might happen.\n");
864 }
865
3ce0a23d
JG		 866 if (rdev->me_fw) {
867 size = rdev->me_fw->size / 4;
868 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 869 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
870 for (i = 0; i < size; i += 2) {
871 WREG32(RADEON_CP_ME_RAM_DATAH,
872 be32_to_cpup(&fw_data[i]));
873 WREG32(RADEON_CP_ME_RAM_DATAL,
874 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 875 }
876 }
877}
878
879int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
880{
881 unsigned rb_bufsz;
882 unsigned rb_blksz;
883 unsigned max_fetch;
884 unsigned pre_write_timer;
885 unsigned pre_write_limit;
886 unsigned indirect2_start;
887 unsigned indirect1_start;
888 uint32_t tmp;
889 int r;
890
891 if (r100_debugfs_cp_init(rdev)) {
892 DRM_ERROR("Failed to register debugfs file for CP !\n");
893 }
3ce0a23d 894 if (!rdev->me_fw) {
70967ab9
BH		 895 r = r100_cp_init_microcode(rdev);
896 if (r) {
897 DRM_ERROR("Failed to load firmware!\n");
898 return r;
899 }
900 }
901
771fe6b9
JG		 902 /* Align ring size */
903 rb_bufsz = drm_order(ring_size / 8);
904 ring_size = (1 << (rb_bufsz + 1)) * 4;
905 r100_cp_load_microcode(rdev);
906 r = radeon_ring_init(rdev, ring_size);
907 if (r) {
908 return r;
909 }
910 /* Each time the cp read 1024 bytes (16 dword/quadword) update
911 * the rptr copy in system ram */
912 rb_blksz = 9;
913 /* cp will read 128bytes at a time (4 dwords) */
914 max_fetch = 1;
915 rdev->cp.align_mask = 16 - 1;
916 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
917 pre_write_timer = 64;
918 /* Force CP_RB_WPTR write if written more than one time before the
919 * delay expire
920 */
921 pre_write_limit = 0;
922 /* Setup the cp cache like this (cache size is 96 dwords) :
923 * RING 0 to 15
924 * INDIRECT1 16 to 79
925 * INDIRECT2 80 to 95
926 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
927 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
928 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
929 * Idea being that most of the gpu cmd will be through indirect1 buffer
930 * so it gets the bigger cache.
931 */
932 indirect2_start = 80;
933 indirect1_start = 16;
934 /* cp setup */
935 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 936 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 937 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 938 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 939#ifdef __BIG_ENDIAN
940 tmp |= RADEON_BUF_SWAP_32BIT;
941#endif
724c80e1 942 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 943
771fe6b9
JG		 944 /* Set ring address */
945 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
946 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
947 /* Force read & write ptr to 0 */
724c80e1 948 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9
JG		 949 WREG32(RADEON_CP_RB_RPTR_WR, 0);
950 WREG32(RADEON_CP_RB_WPTR, 0);
724c80e1
AD		 951
952 /* set the wb address whether it's enabled or not */
953 WREG32(R_00070C_CP_RB_RPTR_ADDR,
954 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
955 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
956
957 if (rdev->wb.enabled)
958 WREG32(R_000770_SCRATCH_UMSK, 0xff);
959 else {
960 tmp |= RADEON_RB_NO_UPDATE;
961 WREG32(R_000770_SCRATCH_UMSK, 0);
962 }
963
771fe6b9
JG		 964 WREG32(RADEON_CP_RB_CNTL, tmp);
965 udelay(10);
966 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
967 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
9e5786bd
DA		 968 /* protect against crazy HW on resume */
969 rdev->cp.wptr &= rdev->cp.ptr_mask;
771fe6b9
JG		 970 /* Set cp mode to bus mastering & enable cp*/
971 WREG32(RADEON_CP_CSQ_MODE,
972 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
973 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
974 WREG32(0x718, 0);
975 WREG32(0x744, 0x00004D4D);
976 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
977 radeon_ring_start(rdev);
978 r = radeon_ring_test(rdev);
979 if (r) {
980 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
981 return r;
982 }
983 rdev->cp.ready = true;
c919b371 984 rdev->mc.active_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 985 return 0;
986}
987
988void r100_cp_fini(struct radeon_device *rdev)
989{
45600232
JG		 990 if (r100_cp_wait_for_idle(rdev)) {
991 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
992 }
771fe6b9 993 /* Disable ring */
a18d7ea1 994 r100_cp_disable(rdev);
771fe6b9
JG		 995 radeon_ring_fini(rdev);
996 DRM_INFO("radeon: cp finalized\n");
997}
998
999void r100_cp_disable(struct radeon_device *rdev)
1000{
1001 /* Disable ring */
c919b371 1002 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
771fe6b9
JG		 1003 rdev->cp.ready = false;
1004 WREG32(RADEON_CP_CSQ_MODE, 0);
1005 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1006 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1007 if (r100_gui_wait_for_idle(rdev)) {
1008 printk(KERN_WARNING "Failed to wait GUI idle while "
1009 "programming pipes. Bad things might happen.\n");
1010 }
1011}
1012
3ce0a23d
JG		 1013void r100_cp_commit(struct radeon_device *rdev)
1014{
1015 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1016 (void)RREG32(RADEON_CP_RB_WPTR);
1017}
1018
771fe6b9
JG		 1019
1020/*
1021 * CS functions
1022 */
1023int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1024 struct radeon_cs_packet *pkt,
068a117c 1025 const unsigned *auth, unsigned n,
771fe6b9
JG		 1026 radeon_packet0_check_t check)
1027{
1028 unsigned reg;
1029 unsigned i, j, m;
1030 unsigned idx;
1031 int r;
1032
1033 idx = pkt->idx + 1;
1034 reg = pkt->reg;
068a117c
JG		 1035 /* Check that register fall into register range
1036 * determined by the number of entry (n) in the
1037 * safe register bitmap.
1038 */
771fe6b9
JG		 1039 if (pkt->one_reg_wr) {
1040 if ((reg >> 7) > n) {
1041 return -EINVAL;
1042 }
1043 } else {
1044 if (((reg + (pkt->count << 2)) >> 7) > n) {
1045 return -EINVAL;
1046 }
1047 }
1048 for (i = 0; i <= pkt->count; i++, idx++) {
1049 j = (reg >> 7);
1050 m = 1 << ((reg >> 2) & 31);
1051 if (auth[j] & m) {
1052 r = check(p, pkt, idx, reg);
1053 if (r) {
1054 return r;
1055 }
1056 }
1057 if (pkt->one_reg_wr) {
1058 if (!(auth[j] & m)) {
1059 break;
1060 }
1061 } else {
1062 reg += 4;
1063 }
1064 }
1065 return 0;
1066}
1067
771fe6b9
JG		 1068void r100_cs_dump_packet(struct radeon_cs_parser *p,
1069 struct radeon_cs_packet *pkt)
1070{
771fe6b9
JG		 1071 volatile uint32_t *ib;
1072 unsigned i;
1073 unsigned idx;
1074
1075 ib = p->ib->ptr;
771fe6b9
JG		 1076 idx = pkt->idx;
1077 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1078 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1079 }
1080}
1081
1082/**
1083 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1084 * @parser: parser structure holding parsing context.
1085 * @pkt: where to store packet informations
1086 *
1087 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1088 * if packet is bigger than remaining ib size. or if packets is unknown.
1089 **/
1090int r100_cs_packet_parse(struct radeon_cs_parser *p,
1091 struct radeon_cs_packet *pkt,
1092 unsigned idx)
1093{
1094 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 1095 uint32_t header;
771fe6b9
JG		 1096
1097 if (idx >= ib_chunk->length_dw) {
1098 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1099 idx, ib_chunk->length_dw);
1100 return -EINVAL;
1101 }
513bcb46 1102 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 1103 pkt->idx = idx;
1104 pkt->type = CP_PACKET_GET_TYPE(header);
1105 pkt->count = CP_PACKET_GET_COUNT(header);
1106 switch (pkt->type) {
1107 case PACKET_TYPE0:
1108 pkt->reg = CP_PACKET0_GET_REG(header);
1109 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1110 break;
1111 case PACKET_TYPE3:
1112 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1113 break;
1114 case PACKET_TYPE2:
1115 pkt->count = -1;
1116 break;
1117 default:
1118 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1119 return -EINVAL;
1120 }
1121 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1122 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1123 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1124 return -EINVAL;
1125 }
1126 return 0;
1127}
1128
531369e6
DA		 1129/**
1130 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1131 * @parser: parser structure holding parsing context.
1132 *
1133 * Userspace sends a special sequence for VLINE waits.
1134 * PACKET0 - VLINE_START_END + value
1135 * PACKET0 - WAIT_UNTIL +_value
1136 * RELOC (P3) - crtc_id in reloc.
1137 *
1138 * This function parses this and relocates the VLINE START END
1139 * and WAIT UNTIL packets to the correct crtc.
1140 * It also detects a switched off crtc and nulls out the
1141 * wait in that case.
1142 */
1143int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1144{
531369e6
DA		 1145 struct drm_mode_object *obj;
1146 struct drm_crtc *crtc;
1147 struct radeon_crtc *radeon_crtc;
1148 struct radeon_cs_packet p3reloc, waitreloc;
1149 int crtc_id;
1150 int r;
1151 uint32_t header, h_idx, reg;
513bcb46 1152 volatile uint32_t *ib;
531369e6 1153
513bcb46 1154 ib = p->ib->ptr;
531369e6
DA		 1155
1156 /* parse the wait until */
1157 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1158 if (r)
1159 return r;
1160
1161 /* check its a wait until and only 1 count */
1162 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1163 waitreloc.count != 0) {
1164 DRM_ERROR("vline wait had illegal wait until segment\n");
1165 r = -EINVAL;
1166 return r;
1167 }
1168
513bcb46 1169 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6
DA		 1170 DRM_ERROR("vline wait had illegal wait until\n");
1171 r = -EINVAL;
1172 return r;
1173 }
1174
1175 /* jump over the NOP */
90ebd065 1176 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1177 if (r)
1178 return r;
1179
1180 h_idx = p->idx - 2;
90ebd065
AD		 1181 p->idx += waitreloc.count + 2;
1182 p->idx += p3reloc.count + 2;
531369e6 1183
513bcb46
DA		 1184 header = radeon_get_ib_value(p, h_idx);
1185 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 1186 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 1187 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1188 if (!obj) {
1189 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1190 r = -EINVAL;
1191 goto out;
1192 }
1193 crtc = obj_to_crtc(obj);
1194 radeon_crtc = to_radeon_crtc(crtc);
1195 crtc_id = radeon_crtc->crtc_id;
1196
1197 if (!crtc->enabled) {
1198 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1199 ib[h_idx + 2] = PACKET2(0);
1200 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1201 } else if (crtc_id == 1) {
1202 switch (reg) {
1203 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1204 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1205 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1206 break;
1207 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1208 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1209 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1210 break;
1211 default:
1212 DRM_ERROR("unknown crtc reloc\n");
1213 r = -EINVAL;
1214 goto out;
1215 }
513bcb46
DA		 1216 ib[h_idx] = header;
1217 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6
DA		 1218 }
1219out:
531369e6
DA		 1220 return r;
1221}
1222
771fe6b9
JG		 1223/**
1224 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1225 * @parser: parser structure holding parsing context.
1226 * @data: pointer to relocation data
1227 * @offset_start: starting offset
1228 * @offset_mask: offset mask (to align start offset on)
1229 * @reloc: reloc informations
1230 *
1231 * Check next packet is relocation packet3, do bo validation and compute
1232 * GPU offset using the provided start.
1233 **/
1234int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1235 struct radeon_cs_reloc **cs_reloc)
1236{
771fe6b9
JG		 1237 struct radeon_cs_chunk *relocs_chunk;
1238 struct radeon_cs_packet p3reloc;
1239 unsigned idx;
1240 int r;
1241
1242 if (p->chunk_relocs_idx == -1) {
1243 DRM_ERROR("No relocation chunk !\n");
1244 return -EINVAL;
1245 }
1246 *cs_reloc = NULL;
771fe6b9
JG		 1247 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1248 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1249 if (r) {
1250 return r;
1251 }
1252 p->idx += p3reloc.count + 2;
1253 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1254 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1255 p3reloc.idx);
1256 r100_cs_dump_packet(p, &p3reloc);
1257 return -EINVAL;
1258 }
513bcb46 1259 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1260 if (idx >= relocs_chunk->length_dw) {
1261 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1262 idx, relocs_chunk->length_dw);
1263 r100_cs_dump_packet(p, &p3reloc);
1264 return -EINVAL;
1265 }
1266 /* FIXME: we assume reloc size is 4 dwords */
1267 *cs_reloc = p->relocs_ptr[(idx / 4)];
1268 return 0;
1269}
1270
551ebd83
DA		 1271static int r100_get_vtx_size(uint32_t vtx_fmt)
1272{
1273 int vtx_size;
1274 vtx_size = 2;
1275 /* ordered according to bits in spec */
1276 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1277 vtx_size++;
1278 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1279 vtx_size += 3;
1280 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1281 vtx_size++;
1282 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1283 vtx_size++;
1284 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1285 vtx_size += 3;
1286 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1287 vtx_size++;
1288 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1289 vtx_size++;
1290 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1291 vtx_size += 2;
1292 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1293 vtx_size += 2;
1294 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1295 vtx_size++;
1296 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1297 vtx_size += 2;
1298 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1299 vtx_size++;
1300 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1301 vtx_size += 2;
1302 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1303 vtx_size++;
1304 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1305 vtx_size++;
1306 /* blend weight */
1307 if (vtx_fmt & (0x7 << 15))
1308 vtx_size += (vtx_fmt >> 15) & 0x7;
1309 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1310 vtx_size += 3;
1311 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1312 vtx_size += 2;
1313 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1314 vtx_size++;
1315 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1316 vtx_size++;
1317 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1318 vtx_size++;
1319 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1320 vtx_size++;
1321 return vtx_size;
1322}
1323
771fe6b9 1324static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1325 struct radeon_cs_packet *pkt,
1326 unsigned idx, unsigned reg)
771fe6b9 1327{
771fe6b9 1328 struct radeon_cs_reloc *reloc;
551ebd83 1329 struct r100_cs_track *track;
771fe6b9
JG		 1330 volatile uint32_t *ib;
1331 uint32_t tmp;
771fe6b9 1332 int r;
551ebd83 1333 int i, face;
e024e110 1334 u32 tile_flags = 0;
513bcb46 1335 u32 idx_value;
771fe6b9
JG		 1336
1337 ib = p->ib->ptr;
551ebd83
DA		 1338 track = (struct r100_cs_track *)p->track;
1339
513bcb46
DA		 1340 idx_value = radeon_get_ib_value(p, idx);
1341
551ebd83
DA		 1342 switch (reg) {
1343 case RADEON_CRTC_GUI_TRIG_VLINE:
1344 r = r100_cs_packet_parse_vline(p);
1345 if (r) {
1346 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1347 idx, reg);
1348 r100_cs_dump_packet(p, pkt);
1349 return r;
1350 }
1351 break;
771fe6b9
JG		 1352 /* FIXME: only allow PACKET3 blit? easier to check for out of
1353 * range access */
551ebd83
DA		 1354 case RADEON_DST_PITCH_OFFSET:
1355 case RADEON_SRC_PITCH_OFFSET:
1356 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1357 if (r)
1358 return r;
1359 break;
1360 case RADEON_RB3D_DEPTHOFFSET:
1361 r = r100_cs_packet_next_reloc(p, &reloc);
1362 if (r) {
1363 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1364 idx, reg);
1365 r100_cs_dump_packet(p, pkt);
1366 return r;
1367 }
1368 track->zb.robj = reloc->robj;
513bcb46
DA		 1369 track->zb.offset = idx_value;
1370 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1371 break;
1372 case RADEON_RB3D_COLOROFFSET:
1373 r = r100_cs_packet_next_reloc(p, &reloc);
1374 if (r) {
1375 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1376 idx, reg);
1377 r100_cs_dump_packet(p, pkt);
1378 return r;
1379 }
1380 track->cb[0].robj = reloc->robj;
513bcb46
DA		 1381 track->cb[0].offset = idx_value;
1382 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1383 break;
1384 case RADEON_PP_TXOFFSET_0:
1385 case RADEON_PP_TXOFFSET_1:
1386 case RADEON_PP_TXOFFSET_2:
1387 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1388 r = r100_cs_packet_next_reloc(p, &reloc);
1389 if (r) {
1390 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1391 idx, reg);
1392 r100_cs_dump_packet(p, pkt);
1393 return r;
1394 }
513bcb46 1395 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1396 track->textures[i].robj = reloc->robj;
1397 break;
1398 case RADEON_PP_CUBIC_OFFSET_T0_0:
1399 case RADEON_PP_CUBIC_OFFSET_T0_1:
1400 case RADEON_PP_CUBIC_OFFSET_T0_2:
1401 case RADEON_PP_CUBIC_OFFSET_T0_3:
1402 case RADEON_PP_CUBIC_OFFSET_T0_4:
1403 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1404 r = r100_cs_packet_next_reloc(p, &reloc);
1405 if (r) {
1406 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1407 idx, reg);
1408 r100_cs_dump_packet(p, pkt);
1409 return r;
1410 }
513bcb46
DA		 1411 track->textures[0].cube_info[i].offset = idx_value;
1412 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1413 track->textures[0].cube_info[i].robj = reloc->robj;
1414 break;
1415 case RADEON_PP_CUBIC_OFFSET_T1_0:
1416 case RADEON_PP_CUBIC_OFFSET_T1_1:
1417 case RADEON_PP_CUBIC_OFFSET_T1_2:
1418 case RADEON_PP_CUBIC_OFFSET_T1_3:
1419 case RADEON_PP_CUBIC_OFFSET_T1_4:
1420 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1421 r = r100_cs_packet_next_reloc(p, &reloc);
1422 if (r) {
1423 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1424 idx, reg);
1425 r100_cs_dump_packet(p, pkt);
1426 return r;
1427 }
513bcb46
DA		 1428 track->textures[1].cube_info[i].offset = idx_value;
1429 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1430 track->textures[1].cube_info[i].robj = reloc->robj;
1431 break;
1432 case RADEON_PP_CUBIC_OFFSET_T2_0:
1433 case RADEON_PP_CUBIC_OFFSET_T2_1:
1434 case RADEON_PP_CUBIC_OFFSET_T2_2:
1435 case RADEON_PP_CUBIC_OFFSET_T2_3:
1436 case RADEON_PP_CUBIC_OFFSET_T2_4:
1437 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1438 r = r100_cs_packet_next_reloc(p, &reloc);
1439 if (r) {
1440 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1441 idx, reg);
1442 r100_cs_dump_packet(p, pkt);
1443 return r;
1444 }
513bcb46
DA		 1445 track->textures[2].cube_info[i].offset = idx_value;
1446 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1447 track->textures[2].cube_info[i].robj = reloc->robj;
1448 break;
1449 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1450 track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83
DA		 1451 break;
1452 case RADEON_RB3D_COLORPITCH:
1453 r = r100_cs_packet_next_reloc(p, &reloc);
1454 if (r) {
1455 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1456 idx, reg);
1457 r100_cs_dump_packet(p, pkt);
1458 return r;
1459 }
e024e110 1460
551ebd83
DA		 1461 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1462 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1463 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1464 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1465
513bcb46 1466 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1467 tmp |= tile_flags;
1468 ib[idx] = tmp;
e024e110 1469
513bcb46 1470 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83
DA		 1471 break;
1472 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1473 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83
DA		 1474 break;
1475 case RADEON_RB3D_CNTL:
513bcb46 1476 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1477 case 7:
1478 case 8:
1479 case 9:
1480 case 11:
1481 case 12:
1482 track->cb[0].cpp = 1;
e024e110 1483 break;
551ebd83
DA		 1484 case 3:
1485 case 4:
1486 case 15:
1487 track->cb[0].cpp = 2;
1488 break;
1489 case 6:
1490 track->cb[0].cpp = 4;
1491 break;
1492 default:
1493 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1494 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1495 return -EINVAL;
1496 }
513bcb46 1497 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83
DA		 1498 break;
1499 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1500 switch (idx_value & 0xf) {
551ebd83
DA		 1501 case 0:
1502 track->zb.cpp = 2;
1503 break;
1504 case 2:
1505 case 3:
1506 case 4:
1507 case 5:
1508 case 9:
1509 case 11:
1510 track->zb.cpp = 4;
17782d99 1511 break;
771fe6b9 1512 default:
771fe6b9
JG		 1513 break;
1514 }
551ebd83
DA		 1515 break;
1516 case RADEON_RB3D_ZPASS_ADDR:
1517 r = r100_cs_packet_next_reloc(p, &reloc);
1518 if (r) {
1519 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1520 idx, reg);
1521 r100_cs_dump_packet(p, pkt);
1522 return r;
1523 }
513bcb46 1524 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1525 break;
1526 case RADEON_PP_CNTL:
1527 {
513bcb46 1528 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1529 for (i = 0; i < track->num_texture; i++)
1530 track->textures[i].enabled = !!(temp & (1 << i));
1531 }
1532 break;
1533 case RADEON_SE_VF_CNTL:
513bcb46 1534 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1535 break;
1536 case RADEON_SE_VTX_FMT:
513bcb46 1537 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1538 break;
1539 case RADEON_PP_TEX_SIZE_0:
1540 case RADEON_PP_TEX_SIZE_1:
1541 case RADEON_PP_TEX_SIZE_2:
1542 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1543 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1544 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83
DA		 1545 break;
1546 case RADEON_PP_TEX_PITCH_0:
1547 case RADEON_PP_TEX_PITCH_1:
1548 case RADEON_PP_TEX_PITCH_2:
1549 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1550 track->textures[i].pitch = idx_value + 32;
551ebd83
DA		 1551 break;
1552 case RADEON_PP_TXFILTER_0:
1553 case RADEON_PP_TXFILTER_1:
1554 case RADEON_PP_TXFILTER_2:
1555 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1556 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1557 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1558 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1559 if (tmp == 2 || tmp == 6)
1560 track->textures[i].roundup_w = false;
513bcb46 1561 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1562 if (tmp == 2 || tmp == 6)
1563 track->textures[i].roundup_h = false;
1564 break;
1565 case RADEON_PP_TXFORMAT_0:
1566 case RADEON_PP_TXFORMAT_1:
1567 case RADEON_PP_TXFORMAT_2:
1568 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1569 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1570 track->textures[i].use_pitch = 1;
1571 } else {
1572 track->textures[i].use_pitch = 0;
513bcb46
DA		 1573 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1574 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1575 }
513bcb46 1576 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1577 track->textures[i].tex_coord_type = 2;
513bcb46 1578 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1579 case RADEON_TXFORMAT_I8:
1580 case RADEON_TXFORMAT_RGB332:
1581 case RADEON_TXFORMAT_Y8:
1582 track->textures[i].cpp = 1;
f9da52d5 1583 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1584 break;
1585 case RADEON_TXFORMAT_AI88:
1586 case RADEON_TXFORMAT_ARGB1555:
1587 case RADEON_TXFORMAT_RGB565:
1588 case RADEON_TXFORMAT_ARGB4444:
1589 case RADEON_TXFORMAT_VYUY422:
1590 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1591 case RADEON_TXFORMAT_SHADOW16:
1592 case RADEON_TXFORMAT_LDUDV655:
1593 case RADEON_TXFORMAT_DUDV88:
1594 track->textures[i].cpp = 2;
f9da52d5 1595 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1596 break;
551ebd83
DA		 1597 case RADEON_TXFORMAT_ARGB8888:
1598 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1599 case RADEON_TXFORMAT_SHADOW32:
1600 case RADEON_TXFORMAT_LDUDUV8888:
1601 track->textures[i].cpp = 4;
f9da52d5 1602 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1603 break;
d785d78b
DA		 1604 case RADEON_TXFORMAT_DXT1:
1605 track->textures[i].cpp = 1;
1606 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1607 break;
1608 case RADEON_TXFORMAT_DXT23:
1609 case RADEON_TXFORMAT_DXT45:
1610 track->textures[i].cpp = 1;
1611 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1612 break;
551ebd83 1613 }
513bcb46
DA		 1614 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1615 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83
DA		 1616 break;
1617 case RADEON_PP_CUBIC_FACES_0:
1618 case RADEON_PP_CUBIC_FACES_1:
1619 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1620 tmp = idx_value;
551ebd83
DA		 1621 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1622 for (face = 0; face < 4; face++) {
1623 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1624 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1625 }
551ebd83
DA		 1626 break;
1627 default:
1628 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1629 reg, idx);
1630 return -EINVAL;
771fe6b9
JG		 1631 }
1632 return 0;
1633}
1634
068a117c
JG		 1635int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1636 struct radeon_cs_packet *pkt,
4c788679 1637 struct radeon_bo *robj)
068a117c 1638{
068a117c 1639 unsigned idx;
513bcb46 1640 u32 value;
068a117c 1641 idx = pkt->idx + 1;
513bcb46 1642 value = radeon_get_ib_value(p, idx + 2);
4c788679 1643 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1644 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1645 "(need %u have %lu) !\n",
513bcb46 1646 value + 1,
4c788679 1647 radeon_bo_size(robj));
068a117c
JG		 1648 return -EINVAL;
1649 }
1650 return 0;
1651}
1652
771fe6b9
JG		 1653static int r100_packet3_check(struct radeon_cs_parser *p,
1654 struct radeon_cs_packet *pkt)
1655{
771fe6b9 1656 struct radeon_cs_reloc *reloc;
551ebd83 1657 struct r100_cs_track *track;
771fe6b9 1658 unsigned idx;
771fe6b9
JG		 1659 volatile uint32_t *ib;
1660 int r;
1661
1662 ib = p->ib->ptr;
771fe6b9 1663 idx = pkt->idx + 1;
551ebd83 1664 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1665 switch (pkt->opcode) {
1666 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1667 r = r100_packet3_load_vbpntr(p, pkt, idx);
1668 if (r)
1669 return r;
771fe6b9
JG		 1670 break;
1671 case PACKET3_INDX_BUFFER:
1672 r = r100_cs_packet_next_reloc(p, &reloc);
1673 if (r) {
1674 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1675 r100_cs_dump_packet(p, pkt);
1676 return r;
1677 }
513bcb46 1678 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1679 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1680 if (r) {
1681 return r;
1682 }
771fe6b9
JG		 1683 break;
1684 case 0x23:
771fe6b9
JG		 1685 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1686 r = r100_cs_packet_next_reloc(p, &reloc);
1687 if (r) {
1688 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1689 r100_cs_dump_packet(p, pkt);
1690 return r;
1691 }
513bcb46 1692 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1693 track->num_arrays = 1;
513bcb46 1694 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1695
1696 track->arrays[0].robj = reloc->robj;
1697 track->arrays[0].esize = track->vtx_size;
1698
513bcb46 1699 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1700
513bcb46 1701 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1702 track->immd_dwords = pkt->count - 1;
1703 r = r100_cs_track_check(p->rdev, track);
1704 if (r)
1705 return r;
771fe6b9
JG		 1706 break;
1707 case PACKET3_3D_DRAW_IMMD:
513bcb46 1708 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1709 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1710 return -EINVAL;
1711 }
cf57fc7a 1712 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1713 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1714 track->immd_dwords = pkt->count - 1;
1715 r = r100_cs_track_check(p->rdev, track);
1716 if (r)
1717 return r;
1718 break;
771fe6b9
JG		 1719 /* triggers drawing using in-packet vertex data */
1720 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1721 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1722 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1723 return -EINVAL;
1724 }
513bcb46 1725 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1726 track->immd_dwords = pkt->count;
1727 r = r100_cs_track_check(p->rdev, track);
1728 if (r)
1729 return r;
1730 break;
771fe6b9
JG		 1731 /* triggers drawing using in-packet vertex data */
1732 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1733 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1734 r = r100_cs_track_check(p->rdev, track);
1735 if (r)
1736 return r;
1737 break;
771fe6b9
JG		 1738 /* triggers drawing of vertex buffers setup elsewhere */
1739 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1740 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1741 r = r100_cs_track_check(p->rdev, track);
1742 if (r)
1743 return r;
1744 break;
771fe6b9
JG		 1745 /* triggers drawing using indices to vertex buffer */
1746 case PACKET3_3D_DRAW_VBUF:
513bcb46 1747 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1748 r = r100_cs_track_check(p->rdev, track);
1749 if (r)
1750 return r;
1751 break;
771fe6b9
JG		 1752 /* triggers drawing of vertex buffers setup elsewhere */
1753 case PACKET3_3D_DRAW_INDX:
513bcb46 1754 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1755 r = r100_cs_track_check(p->rdev, track);
1756 if (r)
1757 return r;
1758 break;
771fe6b9 1759 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 1760 case PACKET3_3D_CLEAR_HIZ:
1761 case PACKET3_3D_CLEAR_ZMASK:
1762 if (p->rdev->hyperz_filp != p->filp)
1763 return -EINVAL;
1764 break;
771fe6b9
JG		 1765 case PACKET3_NOP:
1766 break;
1767 default:
1768 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1769 return -EINVAL;
1770 }
1771 return 0;
1772}
1773
1774int r100_cs_parse(struct radeon_cs_parser *p)
1775{
1776 struct radeon_cs_packet pkt;
9f022ddf 1777 struct r100_cs_track *track;
771fe6b9
JG		 1778 int r;
1779
9f022ddf
JG		 1780 track = kzalloc(sizeof(*track), GFP_KERNEL);
1781 r100_cs_track_clear(p->rdev, track);
1782 p->track = track;
771fe6b9
JG		 1783 do {
1784 r = r100_cs_packet_parse(p, &pkt, p->idx);
1785 if (r) {
1786 return r;
1787 }
1788 p->idx += pkt.count + 2;
1789 switch (pkt.type) {
068a117c 1790 case PACKET_TYPE0:
551ebd83
DA		 1791 if (p->rdev->family >= CHIP_R200)
1792 r = r100_cs_parse_packet0(p, &pkt,
1793 p->rdev->config.r100.reg_safe_bm,
1794 p->rdev->config.r100.reg_safe_bm_size,
1795 &r200_packet0_check);
1796 else
1797 r = r100_cs_parse_packet0(p, &pkt,
1798 p->rdev->config.r100.reg_safe_bm,
1799 p->rdev->config.r100.reg_safe_bm_size,
1800 &r100_packet0_check);
068a117c
JG		 1801 break;
1802 case PACKET_TYPE2:
1803 break;
1804 case PACKET_TYPE3:
1805 r = r100_packet3_check(p, &pkt);
1806 break;
1807 default:
1808 DRM_ERROR("Unknown packet type %d !\n",
1809 pkt.type);
1810 return -EINVAL;
771fe6b9
JG		 1811 }
1812 if (r) {
1813 return r;
1814 }
1815 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1816 return 0;
1817}
1818
1819
1820/*
1821 * Global GPU functions
1822 */
1823void r100_errata(struct radeon_device *rdev)
1824{
1825 rdev->pll_errata = 0;
1826
1827 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1828 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1829 }
1830
1831 if (rdev->family == CHIP_RV100 ||
1832 rdev->family == CHIP_RS100 ||
1833 rdev->family == CHIP_RS200) {
1834 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1835 }
1836}
1837
1838/* Wait for vertical sync on primary CRTC */
1839void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1840{
1841 uint32_t crtc_gen_cntl, tmp;
1842 int i;
1843
1844 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1845 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1846 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1847 return;
1848 }
1849 /* Clear the CRTC_VBLANK_SAVE bit */
1850 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1851 for (i = 0; i < rdev->usec_timeout; i++) {
1852 tmp = RREG32(RADEON_CRTC_STATUS);
1853 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1854 return;
1855 }
1856 DRM_UDELAY(1);
1857 }
1858}
1859
1860/* Wait for vertical sync on secondary CRTC */
1861void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1862{
1863 uint32_t crtc2_gen_cntl, tmp;
1864 int i;
1865
1866 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1867 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1868 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1869 return;
1870
1871 /* Clear the CRTC_VBLANK_SAVE bit */
1872 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1873 for (i = 0; i < rdev->usec_timeout; i++) {
1874 tmp = RREG32(RADEON_CRTC2_STATUS);
1875 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1876 return;
1877 }
1878 DRM_UDELAY(1);
1879 }
1880}
1881
1882int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1883{
1884 unsigned i;
1885 uint32_t tmp;
1886
1887 for (i = 0; i < rdev->usec_timeout; i++) {
1888 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1889 if (tmp >= n) {
1890 return 0;
1891 }
1892 DRM_UDELAY(1);
1893 }
1894 return -1;
1895}
1896
1897int r100_gui_wait_for_idle(struct radeon_device *rdev)
1898{
1899 unsigned i;
1900 uint32_t tmp;
1901
1902 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1903 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1904 " Bad things might happen.\n");
1905 }
1906 for (i = 0; i < rdev->usec_timeout; i++) {
1907 tmp = RREG32(RADEON_RBBM_STATUS);
4612dc97 1908 if (!(tmp & RADEON_RBBM_ACTIVE)) {
771fe6b9
JG		 1909 return 0;
1910 }
1911 DRM_UDELAY(1);
1912 }
1913 return -1;
1914}
1915
1916int r100_mc_wait_for_idle(struct radeon_device *rdev)
1917{
1918 unsigned i;
1919 uint32_t tmp;
1920
1921 for (i = 0; i < rdev->usec_timeout; i++) {
1922 /* read MC_STATUS */
4612dc97
AD		 1923 tmp = RREG32(RADEON_MC_STATUS);
1924 if (tmp & RADEON_MC_IDLE) {
771fe6b9
JG		 1925 return 0;
1926 }
1927 DRM_UDELAY(1);
1928 }
1929 return -1;
1930}
1931
225758d8 1932void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
771fe6b9 1933{
225758d8
JG		 1934 lockup->last_cp_rptr = cp->rptr;
1935 lockup->last_jiffies = jiffies;
1936}
1937
1938/**
1939 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1940 * @rdev: radeon device structure
1941 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
1942 * @cp: radeon_cp structure holding CP information
1943 *
1944 * We don't need to initialize the lockup tracking information as we will either
1945 * have CP rptr to a different value of jiffies wrap around which will force
1946 * initialization of the lockup tracking informations.
1947 *
1948 * A possible false positivie is if we get call after while and last_cp_rptr ==
1949 * the current CP rptr, even if it's unlikely it might happen. To avoid this
1950 * if the elapsed time since last call is bigger than 2 second than we return
1951 * false and update the tracking information. Due to this the caller must call
1952 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
1953 * the fencing code should be cautious about that.
1954 *
1955 * Caller should write to the ring to force CP to do something so we don't get
1956 * false positive when CP is just gived nothing to do.
1957 *
1958 **/
1959bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1960{
1961 unsigned long cjiffies, elapsed;
1962
1963 cjiffies = jiffies;
1964 if (!time_after(cjiffies, lockup->last_jiffies)) {
1965 /* likely a wrap around */
1966 lockup->last_cp_rptr = cp->rptr;
1967 lockup->last_jiffies = jiffies;
1968 return false;
1969 }
1970 if (cp->rptr != lockup->last_cp_rptr) {
1971 /* CP is still working no lockup */
1972 lockup->last_cp_rptr = cp->rptr;
1973 lockup->last_jiffies = jiffies;
1974 return false;
1975 }
1976 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
ec00efb7 1977 if (elapsed >= 10000) {
225758d8
JG		 1978 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
1979 return true;
1980 }
1981 /* give a chance to the GPU ... */
1982 return false;
771fe6b9
JG		 1983}
1984
225758d8 1985bool r100_gpu_is_lockup(struct radeon_device *rdev)
771fe6b9 1986{
225758d8
JG		 1987 u32 rbbm_status;
1988 int r;
771fe6b9 1989
225758d8
JG		 1990 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
1991 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
1992 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
1993 return false;
1994 }
1995 /* force CP activities */
1996 r = radeon_ring_lock(rdev, 2);
1997 if (!r) {
1998 /* PACKET2 NOP */
1999 radeon_ring_write(rdev, 0x80000000);
2000 radeon_ring_write(rdev, 0x80000000);
2001 radeon_ring_unlock_commit(rdev);
2002 }
2003 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2004 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
771fe6b9
JG		 2005}
2006
90aca4d2 2007void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2008{
90aca4d2 2009 u32 tmp;
771fe6b9 2010
90aca4d2
JG		 2011 /* disable bus mastering */
2012 tmp = RREG32(R_000030_BUS_CNTL);
2013 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2014 mdelay(1);
2015 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2016 mdelay(1);
2017 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2018 tmp = RREG32(RADEON_BUS_CNTL);
2019 mdelay(1);
2020 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2021 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
771fe6b9 2022 mdelay(1);
771fe6b9
JG		 2023}
2024
a2d07b74 2025int r100_asic_reset(struct radeon_device *rdev)
771fe6b9 2026{
90aca4d2
JG		 2027 struct r100_mc_save save;
2028 u32 status, tmp;
771fe6b9 2029
90aca4d2
JG		 2030 r100_mc_stop(rdev, &save);
2031 status = RREG32(R_000E40_RBBM_STATUS);
2032 if (!G_000E40_GUI_ACTIVE(status)) {
2033 return 0;
771fe6b9 2034 }
90aca4d2
JG		 2035 status = RREG32(R_000E40_RBBM_STATUS);
2036 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2037 /* stop CP */
2038 WREG32(RADEON_CP_CSQ_CNTL, 0);
2039 tmp = RREG32(RADEON_CP_RB_CNTL);
2040 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2041 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2042 WREG32(RADEON_CP_RB_WPTR, 0);
2043 WREG32(RADEON_CP_RB_CNTL, tmp);
2044 /* save PCI state */
2045 pci_save_state(rdev->pdev);
2046 /* disable bus mastering */
2047 r100_bm_disable(rdev);
2048 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2049 S_0000F0_SOFT_RESET_RE(1) |
2050 S_0000F0_SOFT_RESET_PP(1) |
2051 S_0000F0_SOFT_RESET_RB(1));
2052 RREG32(R_0000F0_RBBM_SOFT_RESET);
2053 mdelay(500);
2054 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2055 mdelay(1);
2056 status = RREG32(R_000E40_RBBM_STATUS);
2057 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
771fe6b9 2058 /* reset CP */
90aca4d2
JG		 2059 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2060 RREG32(R_0000F0_RBBM_SOFT_RESET);
2061 mdelay(500);
2062 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2063 mdelay(1);
2064 status = RREG32(R_000E40_RBBM_STATUS);
2065 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2066 /* restore PCI & busmastering */
2067 pci_restore_state(rdev->pdev);
2068 r100_enable_bm(rdev);
771fe6b9 2069 /* Check if GPU is idle */
90aca4d2
JG		 2070 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2071 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2072 dev_err(rdev->dev, "failed to reset GPU\n");
2073 rdev->gpu_lockup = true;
771fe6b9
JG		 2074 return -1;
2075 }
90aca4d2
JG		 2076 r100_mc_resume(rdev, &save);
2077 dev_info(rdev->dev, "GPU reset succeed\n");
771fe6b9
JG		 2078 return 0;
2079}
2080
92cde00c
AD		 2081void r100_set_common_regs(struct radeon_device *rdev)
2082{
2739d49c
AD		 2083 struct drm_device *dev = rdev->ddev;
2084 bool force_dac2 = false;
d668046c 2085 u32 tmp;
2739d49c 2086
92cde00c
AD		 2087 /* set these so they don't interfere with anything */
2088 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2089 WREG32(RADEON_SUBPIC_CNTL, 0);
2090 WREG32(RADEON_VIPH_CONTROL, 0);
2091 WREG32(RADEON_I2C_CNTL_1, 0);
2092 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2093 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2094 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2739d49c
AD		 2095
2096 /* always set up dac2 on rn50 and some rv100 as lots
2097 * of servers seem to wire it up to a VGA port but
2098 * don't report it in the bios connector
2099 * table.
2100 */
2101 switch (dev->pdev->device) {
2102 /* RN50 */
2103 case 0x515e:
2104 case 0x5969:
2105 force_dac2 = true;
2106 break;
2107 /* RV100*/
2108 case 0x5159:
2109 case 0x515a:
2110 /* DELL triple head servers */
2111 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2112 ((dev->pdev->subsystem_device == 0x016c) ||
2113 (dev->pdev->subsystem_device == 0x016d) ||
2114 (dev->pdev->subsystem_device == 0x016e) ||
2115 (dev->pdev->subsystem_device == 0x016f) ||
2116 (dev->pdev->subsystem_device == 0x0170) ||
2117 (dev->pdev->subsystem_device == 0x017d) ||
2118 (dev->pdev->subsystem_device == 0x017e) ||
2119 (dev->pdev->subsystem_device == 0x0183) ||
2120 (dev->pdev->subsystem_device == 0x018a) ||
2121 (dev->pdev->subsystem_device == 0x019a)))
2122 force_dac2 = true;
2123 break;
2124 }
2125
2126 if (force_dac2) {
2127 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2128 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2129 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2130
2131 /* For CRT on DAC2, don't turn it on if BIOS didn't
2132 enable it, even it's detected.
2133 */
2134
2135 /* force it to crtc0 */
2136 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2137 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2138 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2139
2140 /* set up the TV DAC */
2141 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2142 RADEON_TV_DAC_STD_MASK |
2143 RADEON_TV_DAC_RDACPD |
2144 RADEON_TV_DAC_GDACPD |
2145 RADEON_TV_DAC_BDACPD |
2146 RADEON_TV_DAC_BGADJ_MASK |
2147 RADEON_TV_DAC_DACADJ_MASK);
2148 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2149 RADEON_TV_DAC_NHOLD |
2150 RADEON_TV_DAC_STD_PS2 |
2151 (0x58 << 16));
2152
2153 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2154 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2155 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2156 }
d668046c
DA		 2157
2158 /* switch PM block to ACPI mode */
2159 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2160 tmp &= ~RADEON_PM_MODE_SEL;
2161 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2162
92cde00c 2163}
771fe6b9
JG		 2164
2165/*
2166 * VRAM info
2167 */
2168static void r100_vram_get_type(struct radeon_device *rdev)
2169{
2170 uint32_t tmp;
2171
2172 rdev->mc.vram_is_ddr = false;
2173 if (rdev->flags & RADEON_IS_IGP)
2174 rdev->mc.vram_is_ddr = true;
2175 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2176 rdev->mc.vram_is_ddr = true;
2177 if ((rdev->family == CHIP_RV100) ||
2178 (rdev->family == CHIP_RS100) ||
2179 (rdev->family == CHIP_RS200)) {
2180 tmp = RREG32(RADEON_MEM_CNTL);
2181 if (tmp & RV100_HALF_MODE) {
2182 rdev->mc.vram_width = 32;
2183 } else {
2184 rdev->mc.vram_width = 64;
2185 }
2186 if (rdev->flags & RADEON_SINGLE_CRTC) {
2187 rdev->mc.vram_width /= 4;
2188 rdev->mc.vram_is_ddr = true;
2189 }
2190 } else if (rdev->family <= CHIP_RV280) {
2191 tmp = RREG32(RADEON_MEM_CNTL);
2192 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2193 rdev->mc.vram_width = 128;
2194 } else {
2195 rdev->mc.vram_width = 64;
2196 }
2197 } else {
2198 /* newer IGPs */
2199 rdev->mc.vram_width = 128;
2200 }
2201}
2202
2a0f8918 2203static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 2204{
2a0f8918
DA		 2205 u32 aper_size;
2206 u8 byte;
2207
2208 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2209
2210 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2211 * that is has the 2nd generation multifunction PCI interface
2212 */
2213 if (rdev->family == CHIP_RV280 ||
2214 rdev->family >= CHIP_RV350) {
2215 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2216 ~RADEON_HDP_APER_CNTL);
2217 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2218 return aper_size * 2;
2219 }
2220
2221 /* Older cards have all sorts of funny issues to deal with. First
2222 * check if it's a multifunction card by reading the PCI config
2223 * header type... Limit those to one aperture size
2224 */
2225 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2226 if (byte & 0x80) {
2227 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2228 DRM_INFO("Limiting VRAM to one aperture\n");
2229 return aper_size;
2230 }
2231
2232 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2233 * have set it up. We don't write this as it's broken on some ASICs but
2234 * we expect the BIOS to have done the right thing (might be too optimistic...)
2235 */
2236 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2237 return aper_size * 2;
2238 return aper_size;
2239}
2240
2241void r100_vram_init_sizes(struct radeon_device *rdev)
2242{
2243 u64 config_aper_size;
2a0f8918 2244
d594e46a 2245 /* work out accessible VRAM */
01d73a69
JC		 2246 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2247 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
51e5fcd3
JG		 2248 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2249 /* FIXME we don't use the second aperture yet when we could use it */
2250 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2251 rdev->mc.visible_vram_size = rdev->mc.aper_size;
c919b371 2252 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2a0f8918 2253 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 2254 if (rdev->flags & RADEON_IS_IGP) {
2255 uint32_t tom;
2256 /* read NB_TOM to get the amount of ram stolen for the GPU */
2257 tom = RREG32(RADEON_NB_TOM);
7a50f01a 2258 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
7a50f01a
DA		 2259 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2260 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2261 } else {
7a50f01a 2262 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 2263 /* Some production boards of m6 will report 0
2264 * if it's 8 MB
2265 */
7a50f01a
DA		 2266 if (rdev->mc.real_vram_size == 0) {
2267 rdev->mc.real_vram_size = 8192 * 1024;
2268 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 2269 }
d594e46a
JG		 2270 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2271 * Novell bug 204882 + along with lots of ubuntu ones
2272 */
b7d8cce5
AD		 2273 if (rdev->mc.aper_size > config_aper_size)
2274 config_aper_size = rdev->mc.aper_size;
2275
7a50f01a
DA		 2276 if (config_aper_size > rdev->mc.real_vram_size)
2277 rdev->mc.mc_vram_size = config_aper_size;
2278 else
2279 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2280 }
2a0f8918
DA		 2281}
2282
28d52043
DA		 2283void r100_vga_set_state(struct radeon_device *rdev, bool state)
2284{
2285 uint32_t temp;
2286
2287 temp = RREG32(RADEON_CONFIG_CNTL);
2288 if (state == false) {
2289 temp &= ~(1<<8);
2290 temp |= (1<<9);
2291 } else {
2292 temp &= ~(1<<9);
2293 }
2294 WREG32(RADEON_CONFIG_CNTL, temp);
2295}
2296
d594e46a 2297void r100_mc_init(struct radeon_device *rdev)
2a0f8918 2298{
d594e46a 2299 u64 base;
2a0f8918 2300
d594e46a 2301 r100_vram_get_type(rdev);
2a0f8918 2302 r100_vram_init_sizes(rdev);
d594e46a
JG		 2303 base = rdev->mc.aper_base;
2304 if (rdev->flags & RADEON_IS_IGP)
2305 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2306 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 2307 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 2308 if (!(rdev->flags & RADEON_IS_AGP))
2309 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 2310 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 2311}
2312
2313
2314/*
2315 * Indirect registers accessor
2316 */
2317void r100_pll_errata_after_index(struct radeon_device *rdev)
2318{
4ce9198e
AD		 2319 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2320 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2321 (void)RREG32(RADEON_CRTC_GEN_CNTL);
771fe6b9 2322 }
771fe6b9
JG		 2323}
2324
2325static void r100_pll_errata_after_data(struct radeon_device *rdev)
2326{
2327 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2328 * or the chip could hang on a subsequent access
2329 */
2330 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2331 udelay(5000);
2332 }
2333
2334 /* This function is required to workaround a hardware bug in some (all?)
2335 * revisions of the R300. This workaround should be called after every
2336 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2337 * may not be correct.
2338 */
2339 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2340 uint32_t save, tmp;
2341
2342 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2343 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2344 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2345 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2346 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2347 }
2348}
2349
2350uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2351{
2352 uint32_t data;
2353
2354 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2355 r100_pll_errata_after_index(rdev);
2356 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2357 r100_pll_errata_after_data(rdev);
2358 return data;
2359}
2360
2361void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2362{
2363 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2364 r100_pll_errata_after_index(rdev);
2365 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2366 r100_pll_errata_after_data(rdev);
2367}
2368
d4550907 2369void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2370{
551ebd83
DA		 2371 if (ASIC_IS_RN50(rdev)) {
2372 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2373 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2374 } else if (rdev->family < CHIP_R200) {
2375 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2376 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2377 } else {
d4550907 2378 r200_set_safe_registers(rdev);
551ebd83 2379 }
068a117c
JG		 2380}
2381
771fe6b9
JG		 2382/*
2383 * Debugfs info
2384 */
2385#if defined(CONFIG_DEBUG_FS)
2386static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2387{
2388 struct drm_info_node *node = (struct drm_info_node *) m->private;
2389 struct drm_device *dev = node->minor->dev;
2390 struct radeon_device *rdev = dev->dev_private;
2391 uint32_t reg, value;
2392 unsigned i;
2393
2394 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2395 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2396 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2397 for (i = 0; i < 64; i++) {
2398 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2399 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2400 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2401 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2402 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2403 }
2404 return 0;
2405}
2406
2407static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2408{
2409 struct drm_info_node *node = (struct drm_info_node *) m->private;
2410 struct drm_device *dev = node->minor->dev;
2411 struct radeon_device *rdev = dev->dev_private;
2412 uint32_t rdp, wdp;
2413 unsigned count, i, j;
2414
2415 radeon_ring_free_size(rdev);
2416 rdp = RREG32(RADEON_CP_RB_RPTR);
2417 wdp = RREG32(RADEON_CP_RB_WPTR);
2418 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2419 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2420 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2421 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2422 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2423 seq_printf(m, "%u dwords in ring\n", count);
2424 for (j = 0; j <= count; j++) {
2425 i = (rdp + j) & rdev->cp.ptr_mask;
2426 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2427 }
2428 return 0;
2429}
2430
2431
2432static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2433{
2434 struct drm_info_node *node = (struct drm_info_node *) m->private;
2435 struct drm_device *dev = node->minor->dev;
2436 struct radeon_device *rdev = dev->dev_private;
2437 uint32_t csq_stat, csq2_stat, tmp;
2438 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2439 unsigned i;
2440
2441 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2442 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2443 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2444 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2445 r_rptr = (csq_stat >> 0) & 0x3ff;
2446 r_wptr = (csq_stat >> 10) & 0x3ff;
2447 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2448 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2449 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2450 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2451 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2452 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2453 seq_printf(m, "Ring rptr %u\n", r_rptr);
2454 seq_printf(m, "Ring wptr %u\n", r_wptr);
2455 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2456 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2457 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2458 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2459 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2460 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2461 seq_printf(m, "Ring fifo:\n");
2462 for (i = 0; i < 256; i++) {
2463 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2464 tmp = RREG32(RADEON_CP_CSQ_DATA);
2465 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2466 }
2467 seq_printf(m, "Indirect1 fifo:\n");
2468 for (i = 256; i <= 512; i++) {
2469 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2470 tmp = RREG32(RADEON_CP_CSQ_DATA);
2471 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2472 }
2473 seq_printf(m, "Indirect2 fifo:\n");
2474 for (i = 640; i < ib1_wptr; i++) {
2475 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2476 tmp = RREG32(RADEON_CP_CSQ_DATA);
2477 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2478 }
2479 return 0;
2480}
2481
2482static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2483{
2484 struct drm_info_node *node = (struct drm_info_node *) m->private;
2485 struct drm_device *dev = node->minor->dev;
2486 struct radeon_device *rdev = dev->dev_private;
2487 uint32_t tmp;
2488
2489 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2490 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2491 tmp = RREG32(RADEON_MC_FB_LOCATION);
2492 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2493 tmp = RREG32(RADEON_BUS_CNTL);
2494 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2495 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2496 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2497 tmp = RREG32(RADEON_AGP_BASE);
2498 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2499 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2500 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2501 tmp = RREG32(0x01D0);
2502 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2503 tmp = RREG32(RADEON_AIC_LO_ADDR);
2504 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2505 tmp = RREG32(RADEON_AIC_HI_ADDR);
2506 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2507 tmp = RREG32(0x01E4);
2508 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2509 return 0;
2510}
2511
2512static struct drm_info_list r100_debugfs_rbbm_list[] = {
2513 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2514};
2515
2516static struct drm_info_list r100_debugfs_cp_list[] = {
2517 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2518 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2519};
2520
2521static struct drm_info_list r100_debugfs_mc_info_list[] = {
2522 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2523};
2524#endif
2525
2526int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2527{
2528#if defined(CONFIG_DEBUG_FS)
2529 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2530#else
2531 return 0;
2532#endif
2533}
2534
2535int r100_debugfs_cp_init(struct radeon_device *rdev)
2536{
2537#if defined(CONFIG_DEBUG_FS)
2538 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2539#else
2540 return 0;
2541#endif
2542}
2543
2544int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2545{
2546#if defined(CONFIG_DEBUG_FS)
2547 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2548#else
2549 return 0;
2550#endif
2551}
e024e110
DA		 2552
2553int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2554 uint32_t tiling_flags, uint32_t pitch,
2555 uint32_t offset, uint32_t obj_size)
2556{
2557 int surf_index = reg * 16;
2558 int flags = 0;
2559
e024e110
DA		 2560 if (rdev->family <= CHIP_RS200) {
2561 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2562 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2563 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2564 if (tiling_flags & RADEON_TILING_MACRO)
2565 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2566 } else if (rdev->family <= CHIP_RV280) {
2567 if (tiling_flags & (RADEON_TILING_MACRO))
2568 flags |= R200_SURF_TILE_COLOR_MACRO;
2569 if (tiling_flags & RADEON_TILING_MICRO)
2570 flags |= R200_SURF_TILE_COLOR_MICRO;
2571 } else {
2572 if (tiling_flags & RADEON_TILING_MACRO)
2573 flags |= R300_SURF_TILE_MACRO;
2574 if (tiling_flags & RADEON_TILING_MICRO)
2575 flags |= R300_SURF_TILE_MICRO;
2576 }
2577
c88f9f0c
MD		 2578 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2579 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2580 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2581 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2582
f5c5f040
DA		 2583 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2584 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2585 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2586 if (ASIC_IS_RN50(rdev))
2587 pitch /= 16;
2588 }
2589
2590 /* r100/r200 divide by 16 */
2591 if (rdev->family < CHIP_R300)
2592 flags |= pitch / 16;
2593 else
2594 flags |= pitch / 8;
2595
2596
d9fdaafb 2597 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
e024e110
DA		 2598 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2599 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2600 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2601 return 0;
2602}
2603
2604void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2605{
2606 int surf_index = reg * 16;
2607 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2608}
c93bb85b
JG		 2609
2610void r100_bandwidth_update(struct radeon_device *rdev)
2611{
2612 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2613 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2614 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2615 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2616 fixed20_12 memtcas_ff[8] = {
68adac5e
BS		 2617 dfixed_init(1),
2618 dfixed_init(2),
2619 dfixed_init(3),
2620 dfixed_init(0),
2621 dfixed_init_half(1),
2622 dfixed_init_half(2),
2623 dfixed_init(0),
c93bb85b
JG		 2624 };
2625 fixed20_12 memtcas_rs480_ff[8] = {
68adac5e
BS		 2626 dfixed_init(0),
2627 dfixed_init(1),
2628 dfixed_init(2),
2629 dfixed_init(3),
2630 dfixed_init(0),
2631 dfixed_init_half(1),
2632 dfixed_init_half(2),
2633 dfixed_init_half(3),
c93bb85b
JG		 2634 };
2635 fixed20_12 memtcas2_ff[8] = {
68adac5e
BS		 2636 dfixed_init(0),
2637 dfixed_init(1),
2638 dfixed_init(2),
2639 dfixed_init(3),
2640 dfixed_init(4),
2641 dfixed_init(5),
2642 dfixed_init(6),
2643 dfixed_init(7),
c93bb85b
JG		 2644 };
2645 fixed20_12 memtrbs[8] = {
68adac5e
BS		 2646 dfixed_init(1),
2647 dfixed_init_half(1),
2648 dfixed_init(2),
2649 dfixed_init_half(2),
2650 dfixed_init(3),
2651 dfixed_init_half(3),
2652 dfixed_init(4),
2653 dfixed_init_half(4)
c93bb85b
JG		 2654 };
2655 fixed20_12 memtrbs_r4xx[8] = {
68adac5e
BS		 2656 dfixed_init(4),
2657 dfixed_init(5),
2658 dfixed_init(6),
2659 dfixed_init(7),
2660 dfixed_init(8),
2661 dfixed_init(9),
2662 dfixed_init(10),
2663 dfixed_init(11)
c93bb85b
JG		 2664 };
2665 fixed20_12 min_mem_eff;
2666 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2667 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2668 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2669 disp_drain_rate2, read_return_rate;
2670 fixed20_12 time_disp1_drop_priority;
2671 int c;
2672 int cur_size = 16; /* in octawords */
2673 int critical_point = 0, critical_point2;
2674/* uint32_t read_return_rate, time_disp1_drop_priority; */
2675 int stop_req, max_stop_req;
2676 struct drm_display_mode *mode1 = NULL;
2677 struct drm_display_mode *mode2 = NULL;
2678 uint32_t pixel_bytes1 = 0;
2679 uint32_t pixel_bytes2 = 0;
2680
f46c0120
AD		 2681 radeon_update_display_priority(rdev);
2682
c93bb85b
JG		 2683 if (rdev->mode_info.crtcs[0]->base.enabled) {
2684 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2685 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2686 }
dfee5614
DA		 2687 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2688 if (rdev->mode_info.crtcs[1]->base.enabled) {
2689 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2690 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2691 }
c93bb85b
JG		 2692 }
2693
68adac5e 2694 min_mem_eff.full = dfixed_const_8(0);
c93bb85b
JG		 2695 /* get modes */
2696 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2697 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2698 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2699 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2700 /* check crtc enables */
2701 if (mode2)
2702 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2703 if (mode1)
2704 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2705 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2706 }
2707
2708 /*
2709 * determine is there is enough bw for current mode
2710 */
f47299c5
AD		 2711 sclk_ff = rdev->pm.sclk;
2712 mclk_ff = rdev->pm.mclk;
c93bb85b
JG		 2713
2714 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
68adac5e
BS		 2715 temp_ff.full = dfixed_const(temp);
2716 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 2717
2718 pix_clk.full = 0;
2719 pix_clk2.full = 0;
2720 peak_disp_bw.full = 0;
2721 if (mode1) {
68adac5e
BS		 2722 temp_ff.full = dfixed_const(1000);
2723 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2724 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2725 temp_ff.full = dfixed_const(pixel_bytes1);
2726 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
c93bb85b
JG		 2727 }
2728 if (mode2) {
68adac5e
BS		 2729 temp_ff.full = dfixed_const(1000);
2730 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2731 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2732 temp_ff.full = dfixed_const(pixel_bytes2);
2733 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
c93bb85b
JG		 2734 }
2735
68adac5e 2736 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
c93bb85b
JG		 2737 if (peak_disp_bw.full >= mem_bw.full) {
2738 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2739 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2740 }
2741
2742 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2743 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2744 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2745 mem_trcd = ((temp >> 2) & 0x3) + 1;
2746 mem_trp = ((temp & 0x3)) + 1;
2747 mem_tras = ((temp & 0x70) >> 4) + 1;
2748 } else if (rdev->family == CHIP_R300 ||
2749 rdev->family == CHIP_R350) { /* r300, r350 */
2750 mem_trcd = (temp & 0x7) + 1;
2751 mem_trp = ((temp >> 8) & 0x7) + 1;
2752 mem_tras = ((temp >> 11) & 0xf) + 4;
2753 } else if (rdev->family == CHIP_RV350 ||
2754 rdev->family <= CHIP_RV380) {
2755 /* rv3x0 */
2756 mem_trcd = (temp & 0x7) + 3;
2757 mem_trp = ((temp >> 8) & 0x7) + 3;
2758 mem_tras = ((temp >> 11) & 0xf) + 6;
2759 } else if (rdev->family == CHIP_R420 ||
2760 rdev->family == CHIP_R423 ||
2761 rdev->family == CHIP_RV410) {
2762 /* r4xx */
2763 mem_trcd = (temp & 0xf) + 3;
2764 if (mem_trcd > 15)
2765 mem_trcd = 15;
2766 mem_trp = ((temp >> 8) & 0xf) + 3;
2767 if (mem_trp > 15)
2768 mem_trp = 15;
2769 mem_tras = ((temp >> 12) & 0x1f) + 6;
2770 if (mem_tras > 31)
2771 mem_tras = 31;
2772 } else { /* RV200, R200 */
2773 mem_trcd = (temp & 0x7) + 1;
2774 mem_trp = ((temp >> 8) & 0x7) + 1;
2775 mem_tras = ((temp >> 12) & 0xf) + 4;
2776 }
2777 /* convert to FF */
68adac5e
BS		 2778 trcd_ff.full = dfixed_const(mem_trcd);
2779 trp_ff.full = dfixed_const(mem_trp);
2780 tras_ff.full = dfixed_const(mem_tras);
c93bb85b
JG		 2781
2782 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2783 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2784 data = (temp & (7 << 20)) >> 20;
2785 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2786 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2787 tcas_ff = memtcas_rs480_ff[data];
2788 else
2789 tcas_ff = memtcas_ff[data];
2790 } else
2791 tcas_ff = memtcas2_ff[data];
2792
2793 if (rdev->family == CHIP_RS400 ||
2794 rdev->family == CHIP_RS480) {
2795 /* extra cas latency stored in bits 23-25 0-4 clocks */
2796 data = (temp >> 23) & 0x7;
2797 if (data < 5)
68adac5e 2798 tcas_ff.full += dfixed_const(data);
c93bb85b
JG		 2799 }
2800
2801 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2802 /* on the R300, Tcas is included in Trbs.
2803 */
2804 temp = RREG32(RADEON_MEM_CNTL);
2805 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2806 if (data == 1) {
2807 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2808 temp = RREG32(R300_MC_IND_INDEX);
2809 temp &= ~R300_MC_IND_ADDR_MASK;
2810 temp |= R300_MC_READ_CNTL_CD_mcind;
2811 WREG32(R300_MC_IND_INDEX, temp);
2812 temp = RREG32(R300_MC_IND_DATA);
2813 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2814 } else {
2815 temp = RREG32(R300_MC_READ_CNTL_AB);
2816 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2817 }
2818 } else {
2819 temp = RREG32(R300_MC_READ_CNTL_AB);
2820 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2821 }
2822 if (rdev->family == CHIP_RV410 ||
2823 rdev->family == CHIP_R420 ||
2824 rdev->family == CHIP_R423)
2825 trbs_ff = memtrbs_r4xx[data];
2826 else
2827 trbs_ff = memtrbs[data];
2828 tcas_ff.full += trbs_ff.full;
2829 }
2830
2831 sclk_eff_ff.full = sclk_ff.full;
2832
2833 if (rdev->flags & RADEON_IS_AGP) {
2834 fixed20_12 agpmode_ff;
68adac5e
BS		 2835 agpmode_ff.full = dfixed_const(radeon_agpmode);
2836 temp_ff.full = dfixed_const_666(16);
2837 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
c93bb85b
JG		 2838 }
2839 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2840
2841 if (ASIC_IS_R300(rdev)) {
68adac5e 2842 sclk_delay_ff.full = dfixed_const(250);
c93bb85b
JG		 2843 } else {
2844 if ((rdev->family == CHIP_RV100) ||
2845 rdev->flags & RADEON_IS_IGP) {
2846 if (rdev->mc.vram_is_ddr)
68adac5e 2847 sclk_delay_ff.full = dfixed_const(41);
c93bb85b 2848 else
68adac5e 2849 sclk_delay_ff.full = dfixed_const(33);
c93bb85b
JG		 2850 } else {
2851 if (rdev->mc.vram_width == 128)
68adac5e 2852 sclk_delay_ff.full = dfixed_const(57);
c93bb85b 2853 else
68adac5e 2854 sclk_delay_ff.full = dfixed_const(41);
c93bb85b
JG		 2855 }
2856 }
2857
68adac5e 2858 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
c93bb85b
JG		 2859
2860 if (rdev->mc.vram_is_ddr) {
2861 if (rdev->mc.vram_width == 32) {
68adac5e 2862 k1.full = dfixed_const(40);
c93bb85b
JG		 2863 c = 3;
2864 } else {
68adac5e 2865 k1.full = dfixed_const(20);
c93bb85b
JG		 2866 c = 1;
2867 }
2868 } else {
68adac5e 2869 k1.full = dfixed_const(40);
c93bb85b
JG		 2870 c = 3;
2871 }
2872
68adac5e
BS		 2873 temp_ff.full = dfixed_const(2);
2874 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2875 temp_ff.full = dfixed_const(c);
2876 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2877 temp_ff.full = dfixed_const(4);
2878 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2879 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
c93bb85b
JG		 2880 mc_latency_mclk.full += k1.full;
2881
68adac5e
BS		 2882 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2883 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 2884
2885 /*
2886 HW cursor time assuming worst case of full size colour cursor.
2887 */
68adac5e 2888 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
c93bb85b
JG		 2889 temp_ff.full += trcd_ff.full;
2890 if (temp_ff.full < tras_ff.full)
2891 temp_ff.full = tras_ff.full;
68adac5e 2892 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
c93bb85b 2893
68adac5e
BS		 2894 temp_ff.full = dfixed_const(cur_size);
2895 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 2896 /*
2897 Find the total latency for the display data.
2898 */
68adac5e
BS		 2899 disp_latency_overhead.full = dfixed_const(8);
2900 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
c93bb85b
JG		 2901 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2902 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2903
2904 if (mc_latency_mclk.full > mc_latency_sclk.full)
2905 disp_latency.full = mc_latency_mclk.full;
2906 else
2907 disp_latency.full = mc_latency_sclk.full;
2908
2909 /* setup Max GRPH_STOP_REQ default value */
2910 if (ASIC_IS_RV100(rdev))
2911 max_stop_req = 0x5c;
2912 else
2913 max_stop_req = 0x7c;
2914
2915 if (mode1) {
2916 /* CRTC1
2917 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2918 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2919 */
2920 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2921
2922 if (stop_req > max_stop_req)
2923 stop_req = max_stop_req;
2924
2925 /*
2926 Find the drain rate of the display buffer.
2927 */
68adac5e
BS		 2928 temp_ff.full = dfixed_const((16/pixel_bytes1));
2929 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
c93bb85b
JG		 2930
2931 /*
2932 Find the critical point of the display buffer.
2933 */
68adac5e
BS		 2934 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2935 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 2936
68adac5e 2937 critical_point = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 2938
2939 if (rdev->disp_priority == 2) {
2940 critical_point = 0;
2941 }
2942
2943 /*
2944 The critical point should never be above max_stop_req-4. Setting
2945 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2946 */
2947 if (max_stop_req - critical_point < 4)
2948 critical_point = 0;
2949
2950 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2951 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2952 critical_point = 0x10;
2953 }
2954
2955 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2956 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2957 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2958 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2959 if ((rdev->family == CHIP_R350) &&
2960 (stop_req > 0x15)) {
2961 stop_req -= 0x10;
2962 }
2963 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2964 temp |= RADEON_GRPH_BUFFER_SIZE;
2965 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2966 RADEON_GRPH_CRITICAL_AT_SOF |
2967 RADEON_GRPH_STOP_CNTL);
2968 /*
2969 Write the result into the register.
2970 */
2971 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2972 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2973
2974#if 0
2975 if ((rdev->family == CHIP_RS400) ||
2976 (rdev->family == CHIP_RS480)) {
2977 /* attempt to program RS400 disp regs correctly ??? */
2978 temp = RREG32(RS400_DISP1_REG_CNTL);
2979 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2980 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2981 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2982 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2983 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2984 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2985 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2986 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2987 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2988 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2989 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2990 }
2991#endif
2992
d9fdaafb 2993 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 2994 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2995 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2996 }
2997
2998 if (mode2) {
2999 u32 grph2_cntl;
3000 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3001
3002 if (stop_req > max_stop_req)
3003 stop_req = max_stop_req;
3004
3005 /*
3006 Find the drain rate of the display buffer.
3007 */
68adac5e
BS		 3008 temp_ff.full = dfixed_const((16/pixel_bytes2));
3009 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
c93bb85b
JG		 3010
3011 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3012 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3013 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3014 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3015 if ((rdev->family == CHIP_R350) &&
3016 (stop_req > 0x15)) {
3017 stop_req -= 0x10;
3018 }
3019 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3020 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3021 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3022 RADEON_GRPH_CRITICAL_AT_SOF |
3023 RADEON_GRPH_STOP_CNTL);
3024
3025 if ((rdev->family == CHIP_RS100) ||
3026 (rdev->family == CHIP_RS200))
3027 critical_point2 = 0;
3028 else {
3029 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
68adac5e
BS		 3030 temp_ff.full = dfixed_const(temp);
3031 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 3032 if (sclk_ff.full < temp_ff.full)
3033 temp_ff.full = sclk_ff.full;
3034
3035 read_return_rate.full = temp_ff.full;
3036
3037 if (mode1) {
3038 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
68adac5e 3039 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
c93bb85b
JG		 3040 } else {
3041 time_disp1_drop_priority.full = 0;
3042 }
3043 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
68adac5e
BS		 3044 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3045 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 3046
68adac5e 3047 critical_point2 = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 3048
3049 if (rdev->disp_priority == 2) {
3050 critical_point2 = 0;
3051 }
3052
3053 if (max_stop_req - critical_point2 < 4)
3054 critical_point2 = 0;
3055
3056 }
3057
3058 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3059 /* some R300 cards have problem with this set to 0 */
3060 critical_point2 = 0x10;
3061 }
3062
3063 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3064 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3065
3066 if ((rdev->family == CHIP_RS400) ||
3067 (rdev->family == CHIP_RS480)) {
3068#if 0
3069 /* attempt to program RS400 disp2 regs correctly ??? */
3070 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3071 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3072 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3073 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3074 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3075 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3076 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3077 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3078 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3079 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3080 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3081 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3082#endif
3083 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3084 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3085 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3086 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3087 }
3088
d9fdaafb 3089 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 3090 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3091 }
3092}
551ebd83
DA		 3093
3094static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3095{
3096 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 3097 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 3098 DRM_ERROR("width %d\n", t->width);
ceb776bc 3099 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 3100 DRM_ERROR("height %d\n", t->height);
ceb776bc 3101 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 3102 DRM_ERROR("num levels %d\n", t->num_levels);
3103 DRM_ERROR("depth %d\n", t->txdepth);
3104 DRM_ERROR("bpp %d\n", t->cpp);
3105 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3106 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3107 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 3108 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 3109}
3110
d785d78b
DA		 3111static int r100_track_compress_size(int compress_format, int w, int h)
3112{
3113 int block_width, block_height, block_bytes;
3114 int wblocks, hblocks;
3115 int min_wblocks;
3116 int sz;
3117
3118 block_width = 4;
3119 block_height = 4;
3120
3121 switch (compress_format) {
3122 case R100_TRACK_COMP_DXT1:
3123 block_bytes = 8;
3124 min_wblocks = 4;
3125 break;
3126 default:
3127 case R100_TRACK_COMP_DXT35:
3128 block_bytes = 16;
3129 min_wblocks = 2;
3130 break;
3131 }
3132
3133 hblocks = (h + block_height - 1) / block_height;
3134 wblocks = (w + block_width - 1) / block_width;
3135 if (wblocks < min_wblocks)
3136 wblocks = min_wblocks;
3137 sz = wblocks * hblocks * block_bytes;
3138 return sz;
3139}
3140
37cf6b03
RS		 3141static int r100_cs_track_cube(struct radeon_device *rdev,
3142 struct r100_cs_track *track, unsigned idx)
3143{
3144 unsigned face, w, h;
3145 struct radeon_bo *cube_robj;
3146 unsigned long size;
3147 unsigned compress_format = track->textures[idx].compress_format;
3148
3149 for (face = 0; face < 5; face++) {
3150 cube_robj = track->textures[idx].cube_info[face].robj;
3151 w = track->textures[idx].cube_info[face].width;
3152 h = track->textures[idx].cube_info[face].height;
3153
3154 if (compress_format) {
3155 size = r100_track_compress_size(compress_format, w, h);
3156 } else
3157 size = w * h;
3158 size *= track->textures[idx].cpp;
3159
3160 size += track->textures[idx].cube_info[face].offset;
3161
3162 if (size > radeon_bo_size(cube_robj)) {
3163 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3164 size, radeon_bo_size(cube_robj));
3165 r100_cs_track_texture_print(&track->textures[idx]);
3166 return -1;
3167 }
3168 }
3169 return 0;
3170}
3171
551ebd83
DA		 3172static int r100_cs_track_texture_check(struct radeon_device *rdev,
3173 struct r100_cs_track *track)
3174{
4c788679 3175 struct radeon_bo *robj;
551ebd83 3176 unsigned long size;
b73c5f8b 3177 unsigned u, i, w, h, d;
551ebd83
DA		 3178 int ret;
3179
3180 for (u = 0; u < track->num_texture; u++) {
3181 if (!track->textures[u].enabled)
3182 continue;
43b93fbf
AD		 3183 if (track->textures[u].lookup_disable)
3184 continue;
551ebd83
DA		 3185 robj = track->textures[u].robj;
3186 if (robj == NULL) {
3187 DRM_ERROR("No texture bound to unit %u\n", u);
3188 return -EINVAL;
3189 }
3190 size = 0;
3191 for (i = 0; i <= track->textures[u].num_levels; i++) {
3192 if (track->textures[u].use_pitch) {
3193 if (rdev->family < CHIP_R300)
3194 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3195 else
3196 w = track->textures[u].pitch / (1 << i);
3197 } else {
ceb776bc 3198 w = track->textures[u].width;
551ebd83
DA		 3199 if (rdev->family >= CHIP_RV515)
3200 w |= track->textures[u].width_11;
ceb776bc 3201 w = w / (1 << i);
551ebd83
DA		 3202 if (track->textures[u].roundup_w)
3203 w = roundup_pow_of_two(w);
3204 }
ceb776bc 3205 h = track->textures[u].height;
551ebd83
DA		 3206 if (rdev->family >= CHIP_RV515)
3207 h |= track->textures[u].height_11;
ceb776bc 3208 h = h / (1 << i);
551ebd83
DA		 3209 if (track->textures[u].roundup_h)
3210 h = roundup_pow_of_two(h);
b73c5f8b
MO		 3211 if (track->textures[u].tex_coord_type == 1) {
3212 d = (1 << track->textures[u].txdepth) / (1 << i);
3213 if (!d)
3214 d = 1;
3215 } else {
3216 d = 1;
3217 }
d785d78b
DA		 3218 if (track->textures[u].compress_format) {
3219
b73c5f8b 3220 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
d785d78b
DA		 3221 /* compressed textures are block based */
3222 } else
b73c5f8b 3223 size += w * h * d;
551ebd83
DA		 3224 }
3225 size *= track->textures[u].cpp;
d785d78b 3226
551ebd83
DA		 3227 switch (track->textures[u].tex_coord_type) {
3228 case 0:
551ebd83 3229 case 1:
551ebd83
DA		 3230 break;
3231 case 2:
3232 if (track->separate_cube) {
3233 ret = r100_cs_track_cube(rdev, track, u);
3234 if (ret)
3235 return ret;
3236 } else
3237 size *= 6;
3238 break;
3239 default:
3240 DRM_ERROR("Invalid texture coordinate type %u for unit "
3241 "%u\n", track->textures[u].tex_coord_type, u);
3242 return -EINVAL;
3243 }
4c788679 3244 if (size > radeon_bo_size(robj)) {
551ebd83 3245 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 3246 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 3247 r100_cs_track_texture_print(&track->textures[u]);
3248 return -EINVAL;
3249 }
3250 }
3251 return 0;
3252}
3253
3254int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3255{
3256 unsigned i;
3257 unsigned long size;
3258 unsigned prim_walk;
3259 unsigned nverts;
a41ceb1c 3260 unsigned num_cb = track->num_cb;
551ebd83 3261
a41ceb1c
MO		 3262 if (!track->zb_cb_clear && !track->color_channel_mask &&
3263 !track->blend_read_enable)
3264 num_cb = 0;
3265
3266 for (i = 0; i < num_cb; i++) {
551ebd83
DA		 3267 if (track->cb[i].robj == NULL) {
3268 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3269 return -EINVAL;
3270 }
3271 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3272 size += track->cb[i].offset;
4c788679 3273 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 3274 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3275 "(need %lu have %lu) !\n", i, size,
4c788679 3276 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 3277 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3278 i, track->cb[i].pitch, track->cb[i].cpp,
3279 track->cb[i].offset, track->maxy);
3280 return -EINVAL;
3281 }
3282 }
3283 if (track->z_enabled) {
3284 if (track->zb.robj == NULL) {
3285 DRM_ERROR("[drm] No buffer for z buffer !\n");
3286 return -EINVAL;
3287 }
3288 size = track->zb.pitch * track->zb.cpp * track->maxy;
3289 size += track->zb.offset;
4c788679 3290 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 3291 DRM_ERROR("[drm] Buffer too small for z buffer "
3292 "(need %lu have %lu) !\n", size,
4c788679 3293 radeon_bo_size(track->zb.robj));
551ebd83
DA		 3294 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3295 track->zb.pitch, track->zb.cpp,
3296 track->zb.offset, track->maxy);
3297 return -EINVAL;
3298 }
3299 }
3300 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
cae94b0a
MO		 3301 if (track->vap_vf_cntl & (1 << 14)) {
3302 nverts = track->vap_alt_nverts;
3303 } else {
3304 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3305 }
551ebd83
DA		 3306 switch (prim_walk) {
3307 case 1:
3308 for (i = 0; i < track->num_arrays; i++) {
3309 size = track->arrays[i].esize * track->max_indx * 4;
3310 if (track->arrays[i].robj == NULL) {
3311 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3312 "bound\n", prim_walk, i);
3313 return -EINVAL;
3314 }
4c788679
JG		 3315 if (size > radeon_bo_size(track->arrays[i].robj)) {
3316 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3317 "need %lu dwords have %lu dwords\n",
3318 prim_walk, i, size >> 2,
3319 radeon_bo_size(track->arrays[i].robj)
3320 >> 2);
551ebd83
DA		 3321 DRM_ERROR("Max indices %u\n", track->max_indx);
3322 return -EINVAL;
3323 }
3324 }
3325 break;
3326 case 2:
3327 for (i = 0; i < track->num_arrays; i++) {
3328 size = track->arrays[i].esize * (nverts - 1) * 4;
3329 if (track->arrays[i].robj == NULL) {
3330 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3331 "bound\n", prim_walk, i);
3332 return -EINVAL;
3333 }
4c788679
JG		 3334 if (size > radeon_bo_size(track->arrays[i].robj)) {
3335 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3336 "need %lu dwords have %lu dwords\n",
3337 prim_walk, i, size >> 2,
3338 radeon_bo_size(track->arrays[i].robj)
3339 >> 2);
551ebd83
DA		 3340 return -EINVAL;
3341 }
3342 }
3343 break;
3344 case 3:
3345 size = track->vtx_size * nverts;
3346 if (size != track->immd_dwords) {
3347 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3348 track->immd_dwords, size);
3349 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3350 nverts, track->vtx_size);
3351 return -EINVAL;
3352 }
3353 break;
3354 default:
3355 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3356 prim_walk);
3357 return -EINVAL;
3358 }
3359 return r100_cs_track_texture_check(rdev, track);
3360}
3361
3362void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3363{
3364 unsigned i, face;
3365
3366 if (rdev->family < CHIP_R300) {
3367 track->num_cb = 1;
3368 if (rdev->family <= CHIP_RS200)
3369 track->num_texture = 3;
3370 else
3371 track->num_texture = 6;
3372 track->maxy = 2048;
3373 track->separate_cube = 1;
3374 } else {
3375 track->num_cb = 4;
3376 track->num_texture = 16;
3377 track->maxy = 4096;
3378 track->separate_cube = 0;
3379 }
3380
3381 for (i = 0; i < track->num_cb; i++) {
3382 track->cb[i].robj = NULL;
3383 track->cb[i].pitch = 8192;
3384 track->cb[i].cpp = 16;
3385 track->cb[i].offset = 0;
3386 }
3387 track->z_enabled = true;
3388 track->zb.robj = NULL;
3389 track->zb.pitch = 8192;
3390 track->zb.cpp = 4;
3391 track->zb.offset = 0;
3392 track->vtx_size = 0x7F;
3393 track->immd_dwords = 0xFFFFFFFFUL;
3394 track->num_arrays = 11;
3395 track->max_indx = 0x00FFFFFFUL;
3396 for (i = 0; i < track->num_arrays; i++) {
3397 track->arrays[i].robj = NULL;
3398 track->arrays[i].esize = 0x7F;
3399 }
3400 for (i = 0; i < track->num_texture; i++) {
d785d78b 3401 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3402 track->textures[i].pitch = 16536;
3403 track->textures[i].width = 16536;
3404 track->textures[i].height = 16536;
3405 track->textures[i].width_11 = 1 << 11;
3406 track->textures[i].height_11 = 1 << 11;
3407 track->textures[i].num_levels = 12;
3408 if (rdev->family <= CHIP_RS200) {
3409 track->textures[i].tex_coord_type = 0;
3410 track->textures[i].txdepth = 0;
3411 } else {
3412 track->textures[i].txdepth = 16;
3413 track->textures[i].tex_coord_type = 1;
3414 }
3415 track->textures[i].cpp = 64;
3416 track->textures[i].robj = NULL;
3417 /* CS IB emission code makes sure texture unit are disabled */
3418 track->textures[i].enabled = false;
43b93fbf 3419 track->textures[i].lookup_disable = false;
551ebd83
DA		 3420 track->textures[i].roundup_w = true;
3421 track->textures[i].roundup_h = true;
3422 if (track->separate_cube)
3423 for (face = 0; face < 5; face++) {
3424 track->textures[i].cube_info[face].robj = NULL;
3425 track->textures[i].cube_info[face].width = 16536;
3426 track->textures[i].cube_info[face].height = 16536;
3427 track->textures[i].cube_info[face].offset = 0;
3428 }
3429 }
3430}
3ce0a23d
JG		 3431
3432int r100_ring_test(struct radeon_device *rdev)
3433{
3434 uint32_t scratch;
3435 uint32_t tmp = 0;
3436 unsigned i;
3437 int r;
3438
3439 r = radeon_scratch_get(rdev, &scratch);
3440 if (r) {
3441 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3442 return r;
3443 }
3444 WREG32(scratch, 0xCAFEDEAD);
3445 r = radeon_ring_lock(rdev, 2);
3446 if (r) {
3447 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3448 radeon_scratch_free(rdev, scratch);
3449 return r;
3450 }
3451 radeon_ring_write(rdev, PACKET0(scratch, 0));
3452 radeon_ring_write(rdev, 0xDEADBEEF);
3453 radeon_ring_unlock_commit(rdev);
3454 for (i = 0; i < rdev->usec_timeout; i++) {
3455 tmp = RREG32(scratch);
3456 if (tmp == 0xDEADBEEF) {
3457 break;
3458 }
3459 DRM_UDELAY(1);
3460 }
3461 if (i < rdev->usec_timeout) {
3462 DRM_INFO("ring test succeeded in %d usecs\n", i);
3463 } else {
3464 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3465 scratch, tmp);
3466 r = -EINVAL;
3467 }
3468 radeon_scratch_free(rdev, scratch);
3469 return r;
3470}
3471
3472void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3473{
3474 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3475 radeon_ring_write(rdev, ib->gpu_addr);
3476 radeon_ring_write(rdev, ib->length_dw);
3477}
3478
3479int r100_ib_test(struct radeon_device *rdev)
3480{
3481 struct radeon_ib *ib;
3482 uint32_t scratch;
3483 uint32_t tmp = 0;
3484 unsigned i;
3485 int r;
3486
3487 r = radeon_scratch_get(rdev, &scratch);
3488 if (r) {
3489 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3490 return r;
3491 }
3492 WREG32(scratch, 0xCAFEDEAD);
3493 r = radeon_ib_get(rdev, &ib);
3494 if (r) {
3495 return r;
3496 }
3497 ib->ptr[0] = PACKET0(scratch, 0);
3498 ib->ptr[1] = 0xDEADBEEF;
3499 ib->ptr[2] = PACKET2(0);
3500 ib->ptr[3] = PACKET2(0);
3501 ib->ptr[4] = PACKET2(0);
3502 ib->ptr[5] = PACKET2(0);
3503 ib->ptr[6] = PACKET2(0);
3504 ib->ptr[7] = PACKET2(0);
3505 ib->length_dw = 8;
3506 r = radeon_ib_schedule(rdev, ib);
3507 if (r) {
3508 radeon_scratch_free(rdev, scratch);
3509 radeon_ib_free(rdev, &ib);
3510 return r;
3511 }
3512 r = radeon_fence_wait(ib->fence, false);
3513 if (r) {
3514 return r;
3515 }
3516 for (i = 0; i < rdev->usec_timeout; i++) {
3517 tmp = RREG32(scratch);
3518 if (tmp == 0xDEADBEEF) {
3519 break;
3520 }
3521 DRM_UDELAY(1);
3522 }
3523 if (i < rdev->usec_timeout) {
3524 DRM_INFO("ib test succeeded in %u usecs\n", i);
3525 } else {
3526 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3527 scratch, tmp);
3528 r = -EINVAL;
3529 }
3530 radeon_scratch_free(rdev, scratch);
3531 radeon_ib_free(rdev, &ib);
3532 return r;
3533}
9f022ddf
JG		 3534
3535void r100_ib_fini(struct radeon_device *rdev)
3536{
3537 radeon_ib_pool_fini(rdev);
3538}
3539
3540int r100_ib_init(struct radeon_device *rdev)
3541{
3542 int r;
3543
3544 r = radeon_ib_pool_init(rdev);
3545 if (r) {
3546 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3547 r100_ib_fini(rdev);
3548 return r;
3549 }
3550 r = r100_ib_test(rdev);
3551 if (r) {
3552 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3553 r100_ib_fini(rdev);
3554 return r;
3555 }
3556 return 0;
3557}
3558
3559void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3560{
3561 /* Shutdown CP we shouldn't need to do that but better be safe than
3562 * sorry
3563 */
3564 rdev->cp.ready = false;
3565 WREG32(R_000740_CP_CSQ_CNTL, 0);
3566
3567 /* Save few CRTC registers */
ca6ffc64 3568 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3569 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3570 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3571 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3572 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3573 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3574 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3575 }
3576
3577 /* Disable VGA aperture access */
ca6ffc64 3578 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3579 /* Disable cursor, overlay, crtc */
3580 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3581 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3582 S_000054_CRTC_DISPLAY_DIS(1));
3583 WREG32(R_000050_CRTC_GEN_CNTL,
3584 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3585 S_000050_CRTC_DISP_REQ_EN_B(1));
3586 WREG32(R_000420_OV0_SCALE_CNTL,
3587 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3588 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3589 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3590 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3591 S_000360_CUR2_LOCK(1));
3592 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3593 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3594 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3595 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3596 WREG32(R_000360_CUR2_OFFSET,
3597 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3598 }
3599}
3600
3601void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3602{
3603 /* Update base address for crtc */
d594e46a 3604 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3605 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3606 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3607 }
3608 /* Restore CRTC registers */
ca6ffc64 3609 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3610 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3611 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3612 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3613 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3614 }
3615}
ca6ffc64
JG		 3616
3617void r100_vga_render_disable(struct radeon_device *rdev)
3618{
d4550907 3619 u32 tmp;
ca6ffc64 3620
d4550907 3621 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3622 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3623}
d4550907
JG		 3624
3625static void r100_debugfs(struct radeon_device *rdev)
3626{
3627 int r;
3628
3629 r = r100_debugfs_mc_info_init(rdev);
3630 if (r)
3631 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3632}
3633
3634static void r100_mc_program(struct radeon_device *rdev)
3635{
3636 struct r100_mc_save save;
3637
3638 /* Stops all mc clients */
3639 r100_mc_stop(rdev, &save);
3640 if (rdev->flags & RADEON_IS_AGP) {
3641 WREG32(R_00014C_MC_AGP_LOCATION,
3642 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3643 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3644 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3645 if (rdev->family > CHIP_RV200)
3646 WREG32(R_00015C_AGP_BASE_2,
3647 upper_32_bits(rdev->mc.agp_base) & 0xff);
3648 } else {
3649 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3650 WREG32(R_000170_AGP_BASE, 0);
3651 if (rdev->family > CHIP_RV200)
3652 WREG32(R_00015C_AGP_BASE_2, 0);
3653 }
3654 /* Wait for mc idle */
3655 if (r100_mc_wait_for_idle(rdev))
3656 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3657 /* Program MC, should be a 32bits limited address space */
3658 WREG32(R_000148_MC_FB_LOCATION,
3659 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3660 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3661 r100_mc_resume(rdev, &save);
3662}
3663
3664void r100_clock_startup(struct radeon_device *rdev)
3665{
3666 u32 tmp;
3667
3668 if (radeon_dynclks != -1 && radeon_dynclks)
3669 radeon_legacy_set_clock_gating(rdev, 1);
3670 /* We need to force on some of the block */
3671 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3672 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3673 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3674 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3675 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3676}
3677
3678static int r100_startup(struct radeon_device *rdev)
3679{
3680 int r;
3681
92cde00c
AD		 3682 /* set common regs */
3683 r100_set_common_regs(rdev);
3684 /* program mc */
d4550907
JG		 3685 r100_mc_program(rdev);
3686 /* Resume clock */
3687 r100_clock_startup(rdev);
3688 /* Initialize GPU configuration (# pipes, ...) */
90aca4d2 3689// r100_gpu_init(rdev);
d4550907
JG		 3690 /* Initialize GART (initialize after TTM so we can allocate
3691 * memory through TTM but finalize after TTM) */
17e15b0c 3692 r100_enable_bm(rdev);
d4550907
JG		 3693 if (rdev->flags & RADEON_IS_PCI) {
3694 r = r100_pci_gart_enable(rdev);
3695 if (r)
3696 return r;
3697 }
724c80e1
AD		 3698
3699 /* allocate wb buffer */
3700 r = radeon_wb_init(rdev);
3701 if (r)
3702 return r;
3703
d4550907 3704 /* Enable IRQ */
d4550907 3705 r100_irq_set(rdev);
cafe6609 3706 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3707 /* 1M ring buffer */
3708 r = r100_cp_init(rdev, 1024 * 1024);
3709 if (r) {
3710 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3711 return r;
3712 }
d4550907
JG		 3713 r = r100_ib_init(rdev);
3714 if (r) {
3715 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3716 return r;
3717 }
3718 return 0;
3719}
3720
3721int r100_resume(struct radeon_device *rdev)
3722{
3723 /* Make sur GART are not working */
3724 if (rdev->flags & RADEON_IS_PCI)
3725 r100_pci_gart_disable(rdev);
3726 /* Resume clock before doing reset */
3727 r100_clock_startup(rdev);
3728 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3729 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3730 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3731 RREG32(R_000E40_RBBM_STATUS),
3732 RREG32(R_0007C0_CP_STAT));
3733 }
3734 /* post */
3735 radeon_combios_asic_init(rdev->ddev);
3736 /* Resume clock after posting */
3737 r100_clock_startup(rdev);
550e2d92
DA		 3738 /* Initialize surface registers */
3739 radeon_surface_init(rdev);
d4550907
JG		 3740 return r100_startup(rdev);
3741}
3742
3743int r100_suspend(struct radeon_device *rdev)
3744{
3745 r100_cp_disable(rdev);
724c80e1 3746 radeon_wb_disable(rdev);
d4550907
JG		 3747 r100_irq_disable(rdev);
3748 if (rdev->flags & RADEON_IS_PCI)
3749 r100_pci_gart_disable(rdev);
3750 return 0;
3751}
3752
3753void r100_fini(struct radeon_device *rdev)
3754{
d4550907 3755 r100_cp_fini(rdev);
724c80e1 3756 radeon_wb_fini(rdev);
d4550907
JG		 3757 r100_ib_fini(rdev);
3758 radeon_gem_fini(rdev);
3759 if (rdev->flags & RADEON_IS_PCI)
3760 r100_pci_gart_fini(rdev);
d0269ed8 3761 radeon_agp_fini(rdev);
d4550907
JG		 3762 radeon_irq_kms_fini(rdev);
3763 radeon_fence_driver_fini(rdev);
4c788679 3764 radeon_bo_fini(rdev);
d4550907
JG		 3765 radeon_atombios_fini(rdev);
3766 kfree(rdev->bios);
3767 rdev->bios = NULL;
3768}
3769
4c712e6c
DA		 3770/*
3771 * Due to how kexec works, it can leave the hw fully initialised when it
3772 * boots the new kernel. However doing our init sequence with the CP and
3773 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3774 * do some quick sanity checks and restore sane values to avoid this
3775 * problem.
3776 */
3777void r100_restore_sanity(struct radeon_device *rdev)
3778{
3779 u32 tmp;
3780
3781 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3782 if (tmp) {
3783 WREG32(RADEON_CP_CSQ_CNTL, 0);
3784 }
3785 tmp = RREG32(RADEON_CP_RB_CNTL);
3786 if (tmp) {
3787 WREG32(RADEON_CP_RB_CNTL, 0);
3788 }
3789 tmp = RREG32(RADEON_SCRATCH_UMSK);
3790 if (tmp) {
3791 WREG32(RADEON_SCRATCH_UMSK, 0);
3792 }
3793}
3794
d4550907
JG		 3795int r100_init(struct radeon_device *rdev)
3796{
3797 int r;
3798
d4550907
JG		 3799 /* Register debugfs file specific to this group of asics */
3800 r100_debugfs(rdev);
3801 /* Disable VGA */
3802 r100_vga_render_disable(rdev);
3803 /* Initialize scratch registers */
3804 radeon_scratch_init(rdev);
3805 /* Initialize surface registers */
3806 radeon_surface_init(rdev);
4c712e6c
DA		 3807 /* sanity check some register to avoid hangs like after kexec */
3808 r100_restore_sanity(rdev);
d4550907
JG		 3809 /* TODO: disable VGA need to use VGA request */
3810 /* BIOS*/
3811 if (!radeon_get_bios(rdev)) {
3812 if (ASIC_IS_AVIVO(rdev))
3813 return -EINVAL;
3814 }
3815 if (rdev->is_atom_bios) {
3816 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3817 return -EINVAL;
3818 } else {
3819 r = radeon_combios_init(rdev);
3820 if (r)
3821 return r;
3822 }
3823 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3824 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3825 dev_warn(rdev->dev,
3826 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3827 RREG32(R_000E40_RBBM_STATUS),
3828 RREG32(R_0007C0_CP_STAT));
3829 }
3830 /* check if cards are posted or not */
72542d77
DA		 3831 if (radeon_boot_test_post_card(rdev) == false)
3832 return -EINVAL;
d4550907
JG		 3833 /* Set asic errata */
3834 r100_errata(rdev);
3835 /* Initialize clocks */
3836 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 3837 /* initialize AGP */
3838 if (rdev->flags & RADEON_IS_AGP) {
3839 r = radeon_agp_init(rdev);
3840 if (r) {
3841 radeon_agp_disable(rdev);
3842 }
3843 }
3844 /* initialize VRAM */
3845 r100_mc_init(rdev);
d4550907
JG		 3846 /* Fence driver */
3847 r = radeon_fence_driver_init(rdev);
3848 if (r)
3849 return r;
3850 r = radeon_irq_kms_init(rdev);
3851 if (r)
3852 return r;
3853 /* Memory manager */
4c788679 3854 r = radeon_bo_init(rdev);
d4550907
JG		 3855 if (r)
3856 return r;
3857 if (rdev->flags & RADEON_IS_PCI) {
3858 r = r100_pci_gart_init(rdev);
3859 if (r)
3860 return r;
3861 }
3862 r100_set_safe_registers(rdev);
3863 rdev->accel_working = true;
3864 r = r100_startup(rdev);
3865 if (r) {
3866 /* Somethings want wront with the accel init stop accel */
3867 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 3868 r100_cp_fini(rdev);
724c80e1 3869 radeon_wb_fini(rdev);
d4550907 3870 r100_ib_fini(rdev);
655efd3d 3871 radeon_irq_kms_fini(rdev);
d4550907
JG		 3872 if (rdev->flags & RADEON_IS_PCI)
3873 r100_pci_gart_fini(rdev);
d4550907
JG		 3874 rdev->accel_working = false;
3875 }
3876 return 0;
3877}
Clone of davem's net-next-2.6 tree