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drm/radeon/r100/r200: fix calculation of compressed cube maps
[net-next-2.6.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9
JG		 30#include "drmP.h"
31#include "drm.h"
32#include "radeon_drm.h"
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "r100d.h"
d4550907
JG		 37#include "rs100d.h"
38#include "rv200d.h"
39#include "rv250d.h"
49e02b73 40#include "atom.h"
3ce0a23d 41
70967ab9
BH		 42#include <linux/firmware.h>
43#include <linux/platform_device.h>
44
551ebd83
DA		 45#include "r100_reg_safe.h"
46#include "rn50_reg_safe.h"
47
70967ab9
BH		 48/* Firmware Names */
49#define FIRMWARE_R100 "radeon/R100_cp.bin"
50#define FIRMWARE_R200 "radeon/R200_cp.bin"
51#define FIRMWARE_R300 "radeon/R300_cp.bin"
52#define FIRMWARE_R420 "radeon/R420_cp.bin"
53#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55#define FIRMWARE_R520 "radeon/R520_cp.bin"
56
57MODULE_FIRMWARE(FIRMWARE_R100);
58MODULE_FIRMWARE(FIRMWARE_R200);
59MODULE_FIRMWARE(FIRMWARE_R300);
60MODULE_FIRMWARE(FIRMWARE_R420);
61MODULE_FIRMWARE(FIRMWARE_RS690);
62MODULE_FIRMWARE(FIRMWARE_RS600);
63MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 64
551ebd83
DA		 65#include "r100_track.h"
66
771fe6b9
JG		 67/* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 69 */
771fe6b9 70
ce8f5370 71void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 72{
73 int i;
ce8f5370
AD		 74 rdev->pm.dynpm_can_upclock = true;
75 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 76
ce8f5370
AD		 77 switch (rdev->pm.dynpm_planned_action) {
78 case DYNPM_ACTION_MINIMUM:
a48b9b4e 79 rdev->pm.requested_power_state_index = 0;
ce8f5370 80 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 81 break;
ce8f5370 82 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 83 if (rdev->pm.current_power_state_index == 0) {
84 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 85 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 86 } else {
87 if (rdev->pm.active_crtc_count > 1) {
88 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 89 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 90 continue;
91 else if (i >= rdev->pm.current_power_state_index) {
92 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
93 break;
94 } else {
95 rdev->pm.requested_power_state_index = i;
96 break;
97 }
98 }
99 } else
100 rdev->pm.requested_power_state_index =
101 rdev->pm.current_power_state_index - 1;
102 }
d7311171
AD		 103 /* don't use the power state if crtcs are active and no display flag is set */
104 if ((rdev->pm.active_crtc_count > 0) &&
105 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
106 RADEON_PM_MODE_NO_DISPLAY)) {
107 rdev->pm.requested_power_state_index++;
108 }
a48b9b4e 109 break;
ce8f5370 110 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 111 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
112 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 113 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 114 } else {
115 if (rdev->pm.active_crtc_count > 1) {
116 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 117 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 118 continue;
119 else if (i <= rdev->pm.current_power_state_index) {
120 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
121 break;
122 } else {
123 rdev->pm.requested_power_state_index = i;
124 break;
125 }
126 }
127 } else
128 rdev->pm.requested_power_state_index =
129 rdev->pm.current_power_state_index + 1;
130 }
131 break;
ce8f5370 132 case DYNPM_ACTION_DEFAULT:
58e21dff 133 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 134 rdev->pm.dynpm_can_upclock = false;
58e21dff 135 break;
ce8f5370 136 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 137 default:
138 DRM_ERROR("Requested mode for not defined action\n");
139 return;
140 }
141 /* only one clock mode per power state */
142 rdev->pm.requested_clock_mode_index = 0;
143
ce8a3eb2
AD		 144 DRM_DEBUG("Requested: e: %d m: %d p: %d\n",
145 rdev->pm.power_state[rdev->pm.requested_power_state_index].
146 clock_info[rdev->pm.requested_clock_mode_index].sclk,
147 rdev->pm.power_state[rdev->pm.requested_power_state_index].
148 clock_info[rdev->pm.requested_clock_mode_index].mclk,
149 rdev->pm.power_state[rdev->pm.requested_power_state_index].
150 pcie_lanes);
a48b9b4e
AD		 151}
152
ce8f5370
AD		 153void r100_pm_init_profile(struct radeon_device *rdev)
154{
155 /* default */
156 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
157 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
158 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
159 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
160 /* low sh */
161 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
162 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
163 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
164 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 165 /* mid sh */
166 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
167 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
168 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
169 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 170 /* high sh */
171 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
172 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
173 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
174 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
175 /* low mh */
176 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
177 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
178 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
179 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 180 /* mid mh */
181 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
182 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
183 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
184 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 185 /* high mh */
186 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
187 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
188 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
189 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 190}
191
49e02b73
AD		 192void r100_pm_misc(struct radeon_device *rdev)
193{
49e02b73
AD		 194 int requested_index = rdev->pm.requested_power_state_index;
195 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
196 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
197 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
198
199 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
200 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
201 tmp = RREG32(voltage->gpio.reg);
202 if (voltage->active_high)
203 tmp |= voltage->gpio.mask;
204 else
205 tmp &= ~(voltage->gpio.mask);
206 WREG32(voltage->gpio.reg, tmp);
207 if (voltage->delay)
208 udelay(voltage->delay);
209 } else {
210 tmp = RREG32(voltage->gpio.reg);
211 if (voltage->active_high)
212 tmp &= ~voltage->gpio.mask;
213 else
214 tmp |= voltage->gpio.mask;
215 WREG32(voltage->gpio.reg, tmp);
216 if (voltage->delay)
217 udelay(voltage->delay);
218 }
219 }
220
221 sclk_cntl = RREG32_PLL(SCLK_CNTL);
222 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
223 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
224 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
225 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
226 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
227 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
228 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
229 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
230 else
231 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
232 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
233 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
234 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
235 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
236 } else
237 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
238
239 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
240 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
241 if (voltage->delay) {
242 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
243 switch (voltage->delay) {
244 case 33:
245 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
246 break;
247 case 66:
248 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
249 break;
250 case 99:
251 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
252 break;
253 case 132:
254 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
255 break;
256 }
257 } else
258 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
259 } else
260 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
261
262 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
263 sclk_cntl &= ~FORCE_HDP;
264 else
265 sclk_cntl |= FORCE_HDP;
266
267 WREG32_PLL(SCLK_CNTL, sclk_cntl);
268 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
269 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
270
271 /* set pcie lanes */
272 if ((rdev->flags & RADEON_IS_PCIE) &&
273 !(rdev->flags & RADEON_IS_IGP) &&
274 rdev->asic->set_pcie_lanes &&
275 (ps->pcie_lanes !=
276 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
277 radeon_set_pcie_lanes(rdev,
278 ps->pcie_lanes);
ce8a3eb2 279 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 280 }
49e02b73
AD		 281}
282
283void r100_pm_prepare(struct radeon_device *rdev)
284{
285 struct drm_device *ddev = rdev->ddev;
286 struct drm_crtc *crtc;
287 struct radeon_crtc *radeon_crtc;
288 u32 tmp;
289
290 /* disable any active CRTCs */
291 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
292 radeon_crtc = to_radeon_crtc(crtc);
293 if (radeon_crtc->enabled) {
294 if (radeon_crtc->crtc_id) {
295 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
296 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
297 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
298 } else {
299 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
300 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
301 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
302 }
303 }
304 }
305}
306
307void r100_pm_finish(struct radeon_device *rdev)
308{
309 struct drm_device *ddev = rdev->ddev;
310 struct drm_crtc *crtc;
311 struct radeon_crtc *radeon_crtc;
312 u32 tmp;
313
314 /* enable any active CRTCs */
315 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
316 radeon_crtc = to_radeon_crtc(crtc);
317 if (radeon_crtc->enabled) {
318 if (radeon_crtc->crtc_id) {
319 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
320 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
321 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
322 } else {
323 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
324 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
325 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
326 }
327 }
328 }
329}
330
def9ba9c
AD		 331bool r100_gui_idle(struct radeon_device *rdev)
332{
333 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
334 return false;
335 else
336 return true;
337}
338
05a05c50
AD		 339/* hpd for digital panel detect/disconnect */
340bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
341{
342 bool connected = false;
343
344 switch (hpd) {
345 case RADEON_HPD_1:
346 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
347 connected = true;
348 break;
349 case RADEON_HPD_2:
350 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
351 connected = true;
352 break;
353 default:
354 break;
355 }
356 return connected;
357}
358
359void r100_hpd_set_polarity(struct radeon_device *rdev,
360 enum radeon_hpd_id hpd)
361{
362 u32 tmp;
363 bool connected = r100_hpd_sense(rdev, hpd);
364
365 switch (hpd) {
366 case RADEON_HPD_1:
367 tmp = RREG32(RADEON_FP_GEN_CNTL);
368 if (connected)
369 tmp &= ~RADEON_FP_DETECT_INT_POL;
370 else
371 tmp |= RADEON_FP_DETECT_INT_POL;
372 WREG32(RADEON_FP_GEN_CNTL, tmp);
373 break;
374 case RADEON_HPD_2:
375 tmp = RREG32(RADEON_FP2_GEN_CNTL);
376 if (connected)
377 tmp &= ~RADEON_FP2_DETECT_INT_POL;
378 else
379 tmp |= RADEON_FP2_DETECT_INT_POL;
380 WREG32(RADEON_FP2_GEN_CNTL, tmp);
381 break;
382 default:
383 break;
384 }
385}
386
387void r100_hpd_init(struct radeon_device *rdev)
388{
389 struct drm_device *dev = rdev->ddev;
390 struct drm_connector *connector;
391
392 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
393 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
394 switch (radeon_connector->hpd.hpd) {
395 case RADEON_HPD_1:
396 rdev->irq.hpd[0] = true;
397 break;
398 case RADEON_HPD_2:
399 rdev->irq.hpd[1] = true;
400 break;
401 default:
402 break;
403 }
404 }
003e69f9
JG		 405 if (rdev->irq.installed)
406 r100_irq_set(rdev);
05a05c50
AD		 407}
408
409void r100_hpd_fini(struct radeon_device *rdev)
410{
411 struct drm_device *dev = rdev->ddev;
412 struct drm_connector *connector;
413
414 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
415 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
416 switch (radeon_connector->hpd.hpd) {
417 case RADEON_HPD_1:
418 rdev->irq.hpd[0] = false;
419 break;
420 case RADEON_HPD_2:
421 rdev->irq.hpd[1] = false;
422 break;
423 default:
424 break;
425 }
426 }
427}
428
771fe6b9
JG		 429/*
430 * PCI GART
431 */
432void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
433{
434 /* TODO: can we do somethings here ? */
435 /* It seems hw only cache one entry so we should discard this
436 * entry otherwise if first GPU GART read hit this entry it
437 * could end up in wrong address. */
438}
439
4aac0473 440int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 441{
771fe6b9
JG		 442 int r;
443
4aac0473
JG		 444 if (rdev->gart.table.ram.ptr) {
445 WARN(1, "R100 PCI GART already initialized.\n");
446 return 0;
447 }
771fe6b9
JG		 448 /* Initialize common gart structure */
449 r = radeon_gart_init(rdev);
4aac0473 450 if (r)
771fe6b9 451 return r;
4aac0473
JG		 452 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
453 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
454 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
455 return radeon_gart_table_ram_alloc(rdev);
456}
457
17e15b0c
DA		 458/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
459void r100_enable_bm(struct radeon_device *rdev)
460{
461 uint32_t tmp;
462 /* Enable bus mastering */
463 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
464 WREG32(RADEON_BUS_CNTL, tmp);
465}
466
4aac0473
JG		 467int r100_pci_gart_enable(struct radeon_device *rdev)
468{
469 uint32_t tmp;
470
82568565 471 radeon_gart_restore(rdev);
771fe6b9
JG		 472 /* discard memory request outside of configured range */
473 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
474 WREG32(RADEON_AIC_CNTL, tmp);
475 /* set address range for PCI address translate */
d594e46a
JG		 476 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
477 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 478 /* set PCI GART page-table base address */
479 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
480 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
481 WREG32(RADEON_AIC_CNTL, tmp);
482 r100_pci_gart_tlb_flush(rdev);
483 rdev->gart.ready = true;
484 return 0;
485}
486
487void r100_pci_gart_disable(struct radeon_device *rdev)
488{
489 uint32_t tmp;
490
491 /* discard memory request outside of configured range */
492 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
493 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
494 WREG32(RADEON_AIC_LO_ADDR, 0);
495 WREG32(RADEON_AIC_HI_ADDR, 0);
496}
497
498int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
499{
500 if (i < 0 || i > rdev->gart.num_gpu_pages) {
501 return -EINVAL;
502 }
ed10f95d 503 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 504 return 0;
505}
506
4aac0473 507void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 508{
f9274562 509 radeon_gart_fini(rdev);
4aac0473
JG		 510 r100_pci_gart_disable(rdev);
511 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 512}
513
7ed220d7
MD		 514int r100_irq_set(struct radeon_device *rdev)
515{
516 uint32_t tmp = 0;
517
003e69f9
JG		 518 if (!rdev->irq.installed) {
519 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
520 WREG32(R_000040_GEN_INT_CNTL, 0);
521 return -EINVAL;
522 }
7ed220d7
MD		 523 if (rdev->irq.sw_int) {
524 tmp |= RADEON_SW_INT_ENABLE;
525 }
2031f77c
AD		 526 if (rdev->irq.gui_idle) {
527 tmp |= RADEON_GUI_IDLE_MASK;
528 }
7ed220d7
MD		 529 if (rdev->irq.crtc_vblank_int[0]) {
530 tmp |= RADEON_CRTC_VBLANK_MASK;
531 }
532 if (rdev->irq.crtc_vblank_int[1]) {
533 tmp |= RADEON_CRTC2_VBLANK_MASK;
534 }
05a05c50
AD		 535 if (rdev->irq.hpd[0]) {
536 tmp |= RADEON_FP_DETECT_MASK;
537 }
538 if (rdev->irq.hpd[1]) {
539 tmp |= RADEON_FP2_DETECT_MASK;
540 }
7ed220d7
MD		 541 WREG32(RADEON_GEN_INT_CNTL, tmp);
542 return 0;
543}
544
9f022ddf
JG		 545void r100_irq_disable(struct radeon_device *rdev)
546{
547 u32 tmp;
548
549 WREG32(R_000040_GEN_INT_CNTL, 0);
550 /* Wait and acknowledge irq */
551 mdelay(1);
552 tmp = RREG32(R_000044_GEN_INT_STATUS);
553 WREG32(R_000044_GEN_INT_STATUS, tmp);
554}
555
7ed220d7
MD		 556static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
557{
558 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 559 uint32_t irq_mask = RADEON_SW_INT_TEST |
560 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
561 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7 562
2031f77c
AD		 563 /* the interrupt works, but the status bit is permanently asserted */
564 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
565 if (!rdev->irq.gui_idle_acked)
566 irq_mask |= RADEON_GUI_IDLE_STAT;
567 }
568
7ed220d7
MD		 569 if (irqs) {
570 WREG32(RADEON_GEN_INT_STATUS, irqs);
571 }
572 return irqs & irq_mask;
573}
574
575int r100_irq_process(struct radeon_device *rdev)
576{
3e5cb98d 577 uint32_t status, msi_rearm;
d4877cf2 578 bool queue_hotplug = false;
7ed220d7 579
2031f77c
AD		 580 /* reset gui idle ack. the status bit is broken */
581 rdev->irq.gui_idle_acked = false;
582
7ed220d7
MD		 583 status = r100_irq_ack(rdev);
584 if (!status) {
585 return IRQ_NONE;
586 }
a513c184
JG		 587 if (rdev->shutdown) {
588 return IRQ_NONE;
589 }
7ed220d7
MD		 590 while (status) {
591 /* SW interrupt */
592 if (status & RADEON_SW_INT_TEST) {
593 radeon_fence_process(rdev);
594 }
2031f77c
AD		 595 /* gui idle interrupt */
596 if (status & RADEON_GUI_IDLE_STAT) {
597 rdev->irq.gui_idle_acked = true;
598 rdev->pm.gui_idle = true;
599 wake_up(&rdev->irq.idle_queue);
600 }
7ed220d7
MD		 601 /* Vertical blank interrupts */
602 if (status & RADEON_CRTC_VBLANK_STAT) {
603 drm_handle_vblank(rdev->ddev, 0);
839461d3 604 rdev->pm.vblank_sync = true;
73a6d3fc 605 wake_up(&rdev->irq.vblank_queue);
7ed220d7
MD		 606 }
607 if (status & RADEON_CRTC2_VBLANK_STAT) {
608 drm_handle_vblank(rdev->ddev, 1);
839461d3 609 rdev->pm.vblank_sync = true;
73a6d3fc 610 wake_up(&rdev->irq.vblank_queue);
7ed220d7 611 }
05a05c50 612 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 613 queue_hotplug = true;
614 DRM_DEBUG("HPD1\n");
05a05c50
AD		 615 }
616 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 617 queue_hotplug = true;
618 DRM_DEBUG("HPD2\n");
05a05c50 619 }
7ed220d7
MD		 620 status = r100_irq_ack(rdev);
621 }
2031f77c
AD		 622 /* reset gui idle ack. the status bit is broken */
623 rdev->irq.gui_idle_acked = false;
d4877cf2
AD		 624 if (queue_hotplug)
625 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 626 if (rdev->msi_enabled) {
627 switch (rdev->family) {
628 case CHIP_RS400:
629 case CHIP_RS480:
630 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
631 WREG32(RADEON_AIC_CNTL, msi_rearm);
632 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
633 break;
634 default:
635 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
636 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
637 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
638 break;
639 }
640 }
7ed220d7
MD		 641 return IRQ_HANDLED;
642}
643
644u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
645{
646 if (crtc == 0)
647 return RREG32(RADEON_CRTC_CRNT_FRAME);
648 else
649 return RREG32(RADEON_CRTC2_CRNT_FRAME);
650}
651
9e5b2af7
PN		 652/* Who ever call radeon_fence_emit should call ring_lock and ask
653 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 654void r100_fence_ring_emit(struct radeon_device *rdev,
655 struct radeon_fence *fence)
656{
9e5b2af7
PN		 657 /* We have to make sure that caches are flushed before
658 * CPU might read something from VRAM. */
659 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
660 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
661 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
662 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 663 /* Wait until IDLE & CLEAN */
4612dc97
AD		 664 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
665 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
cafe6609
JG		 666 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
667 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
668 RADEON_HDP_READ_BUFFER_INVALIDATE);
669 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
670 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
771fe6b9
JG		 671 /* Emit fence sequence & fire IRQ */
672 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
673 radeon_ring_write(rdev, fence->seq);
674 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
675 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
676}
677
771fe6b9
JG		 678int r100_wb_init(struct radeon_device *rdev)
679{
680 int r;
681
682 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 683 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
684 RADEON_GEM_DOMAIN_GTT,
685 &rdev->wb.wb_obj);
771fe6b9 686 if (r) {
4c788679 687 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
771fe6b9
JG		 688 return r;
689 }
4c788679
JG		 690 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
691 if (unlikely(r != 0))
692 return r;
693 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
694 &rdev->wb.gpu_addr);
771fe6b9 695 if (r) {
4c788679
JG		 696 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
697 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9
JG		 698 return r;
699 }
4c788679
JG		 700 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
701 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9 702 if (r) {
4c788679 703 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
771fe6b9
JG		 704 return r;
705 }
706 }
9f022ddf
JG		 707 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
708 WREG32(R_00070C_CP_RB_RPTR_ADDR,
709 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
710 WREG32(R_000770_SCRATCH_UMSK, 0xff);
771fe6b9
JG		 711 return 0;
712}
713
9f022ddf
JG		 714void r100_wb_disable(struct radeon_device *rdev)
715{
716 WREG32(R_000770_SCRATCH_UMSK, 0);
717}
718
771fe6b9
JG		 719void r100_wb_fini(struct radeon_device *rdev)
720{
4c788679
JG		 721 int r;
722
9f022ddf 723 r100_wb_disable(rdev);
771fe6b9 724 if (rdev->wb.wb_obj) {
4c788679
JG		 725 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
726 if (unlikely(r != 0)) {
727 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
728 return;
729 }
730 radeon_bo_kunmap(rdev->wb.wb_obj);
731 radeon_bo_unpin(rdev->wb.wb_obj);
732 radeon_bo_unreserve(rdev->wb.wb_obj);
733 radeon_bo_unref(&rdev->wb.wb_obj);
771fe6b9
JG		 734 rdev->wb.wb = NULL;
735 rdev->wb.wb_obj = NULL;
736 }
737}
738
739int r100_copy_blit(struct radeon_device *rdev,
740 uint64_t src_offset,
741 uint64_t dst_offset,
742 unsigned num_pages,
743 struct radeon_fence *fence)
744{
745 uint32_t cur_pages;
746 uint32_t stride_bytes = PAGE_SIZE;
747 uint32_t pitch;
748 uint32_t stride_pixels;
749 unsigned ndw;
750 int num_loops;
751 int r = 0;
752
753 /* radeon limited to 16k stride */
754 stride_bytes &= 0x3fff;
755 /* radeon pitch is /64 */
756 pitch = stride_bytes / 64;
757 stride_pixels = stride_bytes / 4;
758 num_loops = DIV_ROUND_UP(num_pages, 8191);
759
760 /* Ask for enough room for blit + flush + fence */
761 ndw = 64 + (10 * num_loops);
762 r = radeon_ring_lock(rdev, ndw);
763 if (r) {
764 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
765 return -EINVAL;
766 }
767 while (num_pages > 0) {
768 cur_pages = num_pages;
769 if (cur_pages > 8191) {
770 cur_pages = 8191;
771 }
772 num_pages -= cur_pages;
773
774 /* pages are in Y direction - height
775 page width in X direction - width */
776 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
777 radeon_ring_write(rdev,
778 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
779 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
780 RADEON_GMC_SRC_CLIPPING |
781 RADEON_GMC_DST_CLIPPING |
782 RADEON_GMC_BRUSH_NONE |
783 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
784 RADEON_GMC_SRC_DATATYPE_COLOR |
785 RADEON_ROP3_S |
786 RADEON_DP_SRC_SOURCE_MEMORY |
787 RADEON_GMC_CLR_CMP_CNTL_DIS |
788 RADEON_GMC_WR_MSK_DIS);
789 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
790 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
791 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
792 radeon_ring_write(rdev, 0);
793 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
794 radeon_ring_write(rdev, num_pages);
795 radeon_ring_write(rdev, num_pages);
796 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
797 }
798 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
799 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
800 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
801 radeon_ring_write(rdev,
802 RADEON_WAIT_2D_IDLECLEAN |
803 RADEON_WAIT_HOST_IDLECLEAN |
804 RADEON_WAIT_DMA_GUI_IDLE);
805 if (fence) {
806 r = radeon_fence_emit(rdev, fence);
807 }
808 radeon_ring_unlock_commit(rdev);
809 return r;
810}
811
45600232
JG		 812static int r100_cp_wait_for_idle(struct radeon_device *rdev)
813{
814 unsigned i;
815 u32 tmp;
816
817 for (i = 0; i < rdev->usec_timeout; i++) {
818 tmp = RREG32(R_000E40_RBBM_STATUS);
819 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
820 return 0;
821 }
822 udelay(1);
823 }
824 return -1;
825}
826
771fe6b9
JG		 827void r100_ring_start(struct radeon_device *rdev)
828{
829 int r;
830
831 r = radeon_ring_lock(rdev, 2);
832 if (r) {
833 return;
834 }
835 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
836 radeon_ring_write(rdev,
837 RADEON_ISYNC_ANY2D_IDLE3D |
838 RADEON_ISYNC_ANY3D_IDLE2D |
839 RADEON_ISYNC_WAIT_IDLEGUI |
840 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
841 radeon_ring_unlock_commit(rdev);
842}
843
70967ab9
BH		 844
845/* Load the microcode for the CP */
846static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 847{
70967ab9
BH		 848 struct platform_device *pdev;
849 const char *fw_name = NULL;
850 int err;
771fe6b9 851
70967ab9 852 DRM_DEBUG("\n");
771fe6b9 853
70967ab9
BH		 854 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
855 err = IS_ERR(pdev);
856 if (err) {
857 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
858 return -EINVAL;
859 }
771fe6b9
JG		 860 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
861 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
862 (rdev->family == CHIP_RS200)) {
863 DRM_INFO("Loading R100 Microcode\n");
70967ab9 864 fw_name = FIRMWARE_R100;
771fe6b9
JG		 865 } else if ((rdev->family == CHIP_R200) ||
866 (rdev->family == CHIP_RV250) ||
867 (rdev->family == CHIP_RV280) ||
868 (rdev->family == CHIP_RS300)) {
869 DRM_INFO("Loading R200 Microcode\n");
70967ab9 870 fw_name = FIRMWARE_R200;
771fe6b9
JG		 871 } else if ((rdev->family == CHIP_R300) ||
872 (rdev->family == CHIP_R350) ||
873 (rdev->family == CHIP_RV350) ||
874 (rdev->family == CHIP_RV380) ||
875 (rdev->family == CHIP_RS400) ||
876 (rdev->family == CHIP_RS480)) {
877 DRM_INFO("Loading R300 Microcode\n");
70967ab9 878 fw_name = FIRMWARE_R300;
771fe6b9
JG		 879 } else if ((rdev->family == CHIP_R420) ||
880 (rdev->family == CHIP_R423) ||
881 (rdev->family == CHIP_RV410)) {
882 DRM_INFO("Loading R400 Microcode\n");
70967ab9 883 fw_name = FIRMWARE_R420;
771fe6b9
JG		 884 } else if ((rdev->family == CHIP_RS690) ||
885 (rdev->family == CHIP_RS740)) {
886 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 887 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 888 } else if (rdev->family == CHIP_RS600) {
889 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 890 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 891 } else if ((rdev->family == CHIP_RV515) ||
892 (rdev->family == CHIP_R520) ||
893 (rdev->family == CHIP_RV530) ||
894 (rdev->family == CHIP_R580) ||
895 (rdev->family == CHIP_RV560) ||
896 (rdev->family == CHIP_RV570)) {
897 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 898 fw_name = FIRMWARE_R520;
899 }
900
3ce0a23d 901 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 902 platform_device_unregister(pdev);
903 if (err) {
904 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
905 fw_name);
3ce0a23d 906 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 907 printk(KERN_ERR
908 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 909 rdev->me_fw->size, fw_name);
70967ab9 910 err = -EINVAL;
3ce0a23d
JG		 911 release_firmware(rdev->me_fw);
912 rdev->me_fw = NULL;
70967ab9
BH		 913 }
914 return err;
915}
d4550907 916
70967ab9
BH		 917static void r100_cp_load_microcode(struct radeon_device *rdev)
918{
919 const __be32 *fw_data;
920 int i, size;
921
922 if (r100_gui_wait_for_idle(rdev)) {
923 printk(KERN_WARNING "Failed to wait GUI idle while "
924 "programming pipes. Bad things might happen.\n");
925 }
926
3ce0a23d
JG		 927 if (rdev->me_fw) {
928 size = rdev->me_fw->size / 4;
929 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 930 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
931 for (i = 0; i < size; i += 2) {
932 WREG32(RADEON_CP_ME_RAM_DATAH,
933 be32_to_cpup(&fw_data[i]));
934 WREG32(RADEON_CP_ME_RAM_DATAL,
935 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 936 }
937 }
938}
939
940int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
941{
942 unsigned rb_bufsz;
943 unsigned rb_blksz;
944 unsigned max_fetch;
945 unsigned pre_write_timer;
946 unsigned pre_write_limit;
947 unsigned indirect2_start;
948 unsigned indirect1_start;
949 uint32_t tmp;
950 int r;
951
952 if (r100_debugfs_cp_init(rdev)) {
953 DRM_ERROR("Failed to register debugfs file for CP !\n");
954 }
3ce0a23d 955 if (!rdev->me_fw) {
70967ab9
BH		 956 r = r100_cp_init_microcode(rdev);
957 if (r) {
958 DRM_ERROR("Failed to load firmware!\n");
959 return r;
960 }
961 }
962
771fe6b9
JG		 963 /* Align ring size */
964 rb_bufsz = drm_order(ring_size / 8);
965 ring_size = (1 << (rb_bufsz + 1)) * 4;
966 r100_cp_load_microcode(rdev);
967 r = radeon_ring_init(rdev, ring_size);
968 if (r) {
969 return r;
970 }
971 /* Each time the cp read 1024 bytes (16 dword/quadword) update
972 * the rptr copy in system ram */
973 rb_blksz = 9;
974 /* cp will read 128bytes at a time (4 dwords) */
975 max_fetch = 1;
976 rdev->cp.align_mask = 16 - 1;
977 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
978 pre_write_timer = 64;
979 /* Force CP_RB_WPTR write if written more than one time before the
980 * delay expire
981 */
982 pre_write_limit = 0;
983 /* Setup the cp cache like this (cache size is 96 dwords) :
984 * RING 0 to 15
985 * INDIRECT1 16 to 79
986 * INDIRECT2 80 to 95
987 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
988 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
989 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
990 * Idea being that most of the gpu cmd will be through indirect1 buffer
991 * so it gets the bigger cache.
992 */
993 indirect2_start = 80;
994 indirect1_start = 16;
995 /* cp setup */
996 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 997 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9
JG		 998 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
999 REG_SET(RADEON_MAX_FETCH, max_fetch) |
1000 RADEON_RB_NO_UPDATE);
d6f28938
AD		 1001#ifdef __BIG_ENDIAN
1002 tmp |= RADEON_BUF_SWAP_32BIT;
1003#endif
1004 WREG32(RADEON_CP_RB_CNTL, tmp);
1005
771fe6b9
JG		 1006 /* Set ring address */
1007 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1008 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1009 /* Force read & write ptr to 0 */
771fe6b9
JG		 1010 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
1011 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1012 WREG32(RADEON_CP_RB_WPTR, 0);
1013 WREG32(RADEON_CP_RB_CNTL, tmp);
1014 udelay(10);
1015 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1016 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
9e5786bd
DA		 1017 /* protect against crazy HW on resume */
1018 rdev->cp.wptr &= rdev->cp.ptr_mask;
771fe6b9
JG		 1019 /* Set cp mode to bus mastering & enable cp*/
1020 WREG32(RADEON_CP_CSQ_MODE,
1021 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1022 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1023 WREG32(0x718, 0);
1024 WREG32(0x744, 0x00004D4D);
1025 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1026 radeon_ring_start(rdev);
1027 r = radeon_ring_test(rdev);
1028 if (r) {
1029 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1030 return r;
1031 }
1032 rdev->cp.ready = true;
1033 return 0;
1034}
1035
1036void r100_cp_fini(struct radeon_device *rdev)
1037{
45600232
JG		 1038 if (r100_cp_wait_for_idle(rdev)) {
1039 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1040 }
771fe6b9 1041 /* Disable ring */
a18d7ea1 1042 r100_cp_disable(rdev);
771fe6b9
JG		 1043 radeon_ring_fini(rdev);
1044 DRM_INFO("radeon: cp finalized\n");
1045}
1046
1047void r100_cp_disable(struct radeon_device *rdev)
1048{
1049 /* Disable ring */
1050 rdev->cp.ready = false;
1051 WREG32(RADEON_CP_CSQ_MODE, 0);
1052 WREG32(RADEON_CP_CSQ_CNTL, 0);
1053 if (r100_gui_wait_for_idle(rdev)) {
1054 printk(KERN_WARNING "Failed to wait GUI idle while "
1055 "programming pipes. Bad things might happen.\n");
1056 }
1057}
1058
3ce0a23d
JG		 1059void r100_cp_commit(struct radeon_device *rdev)
1060{
1061 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1062 (void)RREG32(RADEON_CP_RB_WPTR);
1063}
1064
771fe6b9
JG		 1065
1066/*
1067 * CS functions
1068 */
1069int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1070 struct radeon_cs_packet *pkt,
068a117c 1071 const unsigned *auth, unsigned n,
771fe6b9
JG		 1072 radeon_packet0_check_t check)
1073{
1074 unsigned reg;
1075 unsigned i, j, m;
1076 unsigned idx;
1077 int r;
1078
1079 idx = pkt->idx + 1;
1080 reg = pkt->reg;
068a117c
JG		 1081 /* Check that register fall into register range
1082 * determined by the number of entry (n) in the
1083 * safe register bitmap.
1084 */
771fe6b9
JG		 1085 if (pkt->one_reg_wr) {
1086 if ((reg >> 7) > n) {
1087 return -EINVAL;
1088 }
1089 } else {
1090 if (((reg + (pkt->count << 2)) >> 7) > n) {
1091 return -EINVAL;
1092 }
1093 }
1094 for (i = 0; i <= pkt->count; i++, idx++) {
1095 j = (reg >> 7);
1096 m = 1 << ((reg >> 2) & 31);
1097 if (auth[j] & m) {
1098 r = check(p, pkt, idx, reg);
1099 if (r) {
1100 return r;
1101 }
1102 }
1103 if (pkt->one_reg_wr) {
1104 if (!(auth[j] & m)) {
1105 break;
1106 }
1107 } else {
1108 reg += 4;
1109 }
1110 }
1111 return 0;
1112}
1113
771fe6b9
JG		 1114void r100_cs_dump_packet(struct radeon_cs_parser *p,
1115 struct radeon_cs_packet *pkt)
1116{
771fe6b9
JG		 1117 volatile uint32_t *ib;
1118 unsigned i;
1119 unsigned idx;
1120
1121 ib = p->ib->ptr;
771fe6b9
JG		 1122 idx = pkt->idx;
1123 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1124 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1125 }
1126}
1127
1128/**
1129 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1130 * @parser: parser structure holding parsing context.
1131 * @pkt: where to store packet informations
1132 *
1133 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1134 * if packet is bigger than remaining ib size. or if packets is unknown.
1135 **/
1136int r100_cs_packet_parse(struct radeon_cs_parser *p,
1137 struct radeon_cs_packet *pkt,
1138 unsigned idx)
1139{
1140 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 1141 uint32_t header;
771fe6b9
JG		 1142
1143 if (idx >= ib_chunk->length_dw) {
1144 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1145 idx, ib_chunk->length_dw);
1146 return -EINVAL;
1147 }
513bcb46 1148 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 1149 pkt->idx = idx;
1150 pkt->type = CP_PACKET_GET_TYPE(header);
1151 pkt->count = CP_PACKET_GET_COUNT(header);
1152 switch (pkt->type) {
1153 case PACKET_TYPE0:
1154 pkt->reg = CP_PACKET0_GET_REG(header);
1155 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1156 break;
1157 case PACKET_TYPE3:
1158 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1159 break;
1160 case PACKET_TYPE2:
1161 pkt->count = -1;
1162 break;
1163 default:
1164 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1165 return -EINVAL;
1166 }
1167 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1168 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1169 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1170 return -EINVAL;
1171 }
1172 return 0;
1173}
1174
531369e6
DA		 1175/**
1176 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1177 * @parser: parser structure holding parsing context.
1178 *
1179 * Userspace sends a special sequence for VLINE waits.
1180 * PACKET0 - VLINE_START_END + value
1181 * PACKET0 - WAIT_UNTIL +_value
1182 * RELOC (P3) - crtc_id in reloc.
1183 *
1184 * This function parses this and relocates the VLINE START END
1185 * and WAIT UNTIL packets to the correct crtc.
1186 * It also detects a switched off crtc and nulls out the
1187 * wait in that case.
1188 */
1189int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1190{
531369e6
DA		 1191 struct drm_mode_object *obj;
1192 struct drm_crtc *crtc;
1193 struct radeon_crtc *radeon_crtc;
1194 struct radeon_cs_packet p3reloc, waitreloc;
1195 int crtc_id;
1196 int r;
1197 uint32_t header, h_idx, reg;
513bcb46 1198 volatile uint32_t *ib;
531369e6 1199
513bcb46 1200 ib = p->ib->ptr;
531369e6
DA		 1201
1202 /* parse the wait until */
1203 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1204 if (r)
1205 return r;
1206
1207 /* check its a wait until and only 1 count */
1208 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1209 waitreloc.count != 0) {
1210 DRM_ERROR("vline wait had illegal wait until segment\n");
1211 r = -EINVAL;
1212 return r;
1213 }
1214
513bcb46 1215 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6
DA		 1216 DRM_ERROR("vline wait had illegal wait until\n");
1217 r = -EINVAL;
1218 return r;
1219 }
1220
1221 /* jump over the NOP */
90ebd065 1222 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1223 if (r)
1224 return r;
1225
1226 h_idx = p->idx - 2;
90ebd065
AD		 1227 p->idx += waitreloc.count + 2;
1228 p->idx += p3reloc.count + 2;
531369e6 1229
513bcb46
DA		 1230 header = radeon_get_ib_value(p, h_idx);
1231 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 1232 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 1233 mutex_lock(&p->rdev->ddev->mode_config.mutex);
1234 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1235 if (!obj) {
1236 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1237 r = -EINVAL;
1238 goto out;
1239 }
1240 crtc = obj_to_crtc(obj);
1241 radeon_crtc = to_radeon_crtc(crtc);
1242 crtc_id = radeon_crtc->crtc_id;
1243
1244 if (!crtc->enabled) {
1245 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1246 ib[h_idx + 2] = PACKET2(0);
1247 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1248 } else if (crtc_id == 1) {
1249 switch (reg) {
1250 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1251 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1252 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1253 break;
1254 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1255 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1256 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1257 break;
1258 default:
1259 DRM_ERROR("unknown crtc reloc\n");
1260 r = -EINVAL;
1261 goto out;
1262 }
513bcb46
DA		 1263 ib[h_idx] = header;
1264 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6
DA		 1265 }
1266out:
1267 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1268 return r;
1269}
1270
771fe6b9
JG		 1271/**
1272 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1273 * @parser: parser structure holding parsing context.
1274 * @data: pointer to relocation data
1275 * @offset_start: starting offset
1276 * @offset_mask: offset mask (to align start offset on)
1277 * @reloc: reloc informations
1278 *
1279 * Check next packet is relocation packet3, do bo validation and compute
1280 * GPU offset using the provided start.
1281 **/
1282int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1283 struct radeon_cs_reloc **cs_reloc)
1284{
771fe6b9
JG		 1285 struct radeon_cs_chunk *relocs_chunk;
1286 struct radeon_cs_packet p3reloc;
1287 unsigned idx;
1288 int r;
1289
1290 if (p->chunk_relocs_idx == -1) {
1291 DRM_ERROR("No relocation chunk !\n");
1292 return -EINVAL;
1293 }
1294 *cs_reloc = NULL;
771fe6b9
JG		 1295 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1296 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1297 if (r) {
1298 return r;
1299 }
1300 p->idx += p3reloc.count + 2;
1301 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1302 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1303 p3reloc.idx);
1304 r100_cs_dump_packet(p, &p3reloc);
1305 return -EINVAL;
1306 }
513bcb46 1307 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1308 if (idx >= relocs_chunk->length_dw) {
1309 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1310 idx, relocs_chunk->length_dw);
1311 r100_cs_dump_packet(p, &p3reloc);
1312 return -EINVAL;
1313 }
1314 /* FIXME: we assume reloc size is 4 dwords */
1315 *cs_reloc = p->relocs_ptr[(idx / 4)];
1316 return 0;
1317}
1318
551ebd83
DA		 1319static int r100_get_vtx_size(uint32_t vtx_fmt)
1320{
1321 int vtx_size;
1322 vtx_size = 2;
1323 /* ordered according to bits in spec */
1324 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1325 vtx_size++;
1326 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1327 vtx_size += 3;
1328 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1329 vtx_size++;
1330 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1331 vtx_size++;
1332 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1333 vtx_size += 3;
1334 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1335 vtx_size++;
1336 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1337 vtx_size++;
1338 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1339 vtx_size += 2;
1340 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1341 vtx_size += 2;
1342 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1343 vtx_size++;
1344 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1345 vtx_size += 2;
1346 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1347 vtx_size++;
1348 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1349 vtx_size += 2;
1350 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1351 vtx_size++;
1352 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1353 vtx_size++;
1354 /* blend weight */
1355 if (vtx_fmt & (0x7 << 15))
1356 vtx_size += (vtx_fmt >> 15) & 0x7;
1357 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1358 vtx_size += 3;
1359 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1360 vtx_size += 2;
1361 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1362 vtx_size++;
1363 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1364 vtx_size++;
1365 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1366 vtx_size++;
1367 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1368 vtx_size++;
1369 return vtx_size;
1370}
1371
771fe6b9 1372static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1373 struct radeon_cs_packet *pkt,
1374 unsigned idx, unsigned reg)
771fe6b9 1375{
771fe6b9 1376 struct radeon_cs_reloc *reloc;
551ebd83 1377 struct r100_cs_track *track;
771fe6b9
JG		 1378 volatile uint32_t *ib;
1379 uint32_t tmp;
771fe6b9 1380 int r;
551ebd83 1381 int i, face;
e024e110 1382 u32 tile_flags = 0;
513bcb46 1383 u32 idx_value;
771fe6b9
JG		 1384
1385 ib = p->ib->ptr;
551ebd83
DA		 1386 track = (struct r100_cs_track *)p->track;
1387
513bcb46
DA		 1388 idx_value = radeon_get_ib_value(p, idx);
1389
551ebd83
DA		 1390 switch (reg) {
1391 case RADEON_CRTC_GUI_TRIG_VLINE:
1392 r = r100_cs_packet_parse_vline(p);
1393 if (r) {
1394 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1395 idx, reg);
1396 r100_cs_dump_packet(p, pkt);
1397 return r;
1398 }
1399 break;
771fe6b9
JG		 1400 /* FIXME: only allow PACKET3 blit? easier to check for out of
1401 * range access */
551ebd83
DA		 1402 case RADEON_DST_PITCH_OFFSET:
1403 case RADEON_SRC_PITCH_OFFSET:
1404 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1405 if (r)
1406 return r;
1407 break;
1408 case RADEON_RB3D_DEPTHOFFSET:
1409 r = r100_cs_packet_next_reloc(p, &reloc);
1410 if (r) {
1411 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1412 idx, reg);
1413 r100_cs_dump_packet(p, pkt);
1414 return r;
1415 }
1416 track->zb.robj = reloc->robj;
513bcb46
DA		 1417 track->zb.offset = idx_value;
1418 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1419 break;
1420 case RADEON_RB3D_COLOROFFSET:
1421 r = r100_cs_packet_next_reloc(p, &reloc);
1422 if (r) {
1423 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1424 idx, reg);
1425 r100_cs_dump_packet(p, pkt);
1426 return r;
1427 }
1428 track->cb[0].robj = reloc->robj;
513bcb46
DA		 1429 track->cb[0].offset = idx_value;
1430 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1431 break;
1432 case RADEON_PP_TXOFFSET_0:
1433 case RADEON_PP_TXOFFSET_1:
1434 case RADEON_PP_TXOFFSET_2:
1435 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1436 r = r100_cs_packet_next_reloc(p, &reloc);
1437 if (r) {
1438 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1439 idx, reg);
1440 r100_cs_dump_packet(p, pkt);
1441 return r;
1442 }
513bcb46 1443 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1444 track->textures[i].robj = reloc->robj;
1445 break;
1446 case RADEON_PP_CUBIC_OFFSET_T0_0:
1447 case RADEON_PP_CUBIC_OFFSET_T0_1:
1448 case RADEON_PP_CUBIC_OFFSET_T0_2:
1449 case RADEON_PP_CUBIC_OFFSET_T0_3:
1450 case RADEON_PP_CUBIC_OFFSET_T0_4:
1451 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1452 r = r100_cs_packet_next_reloc(p, &reloc);
1453 if (r) {
1454 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1455 idx, reg);
1456 r100_cs_dump_packet(p, pkt);
1457 return r;
1458 }
513bcb46
DA		 1459 track->textures[0].cube_info[i].offset = idx_value;
1460 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1461 track->textures[0].cube_info[i].robj = reloc->robj;
1462 break;
1463 case RADEON_PP_CUBIC_OFFSET_T1_0:
1464 case RADEON_PP_CUBIC_OFFSET_T1_1:
1465 case RADEON_PP_CUBIC_OFFSET_T1_2:
1466 case RADEON_PP_CUBIC_OFFSET_T1_3:
1467 case RADEON_PP_CUBIC_OFFSET_T1_4:
1468 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1469 r = r100_cs_packet_next_reloc(p, &reloc);
1470 if (r) {
1471 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1472 idx, reg);
1473 r100_cs_dump_packet(p, pkt);
1474 return r;
1475 }
513bcb46
DA		 1476 track->textures[1].cube_info[i].offset = idx_value;
1477 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1478 track->textures[1].cube_info[i].robj = reloc->robj;
1479 break;
1480 case RADEON_PP_CUBIC_OFFSET_T2_0:
1481 case RADEON_PP_CUBIC_OFFSET_T2_1:
1482 case RADEON_PP_CUBIC_OFFSET_T2_2:
1483 case RADEON_PP_CUBIC_OFFSET_T2_3:
1484 case RADEON_PP_CUBIC_OFFSET_T2_4:
1485 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1486 r = r100_cs_packet_next_reloc(p, &reloc);
1487 if (r) {
1488 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1489 idx, reg);
1490 r100_cs_dump_packet(p, pkt);
1491 return r;
1492 }
513bcb46
DA		 1493 track->textures[2].cube_info[i].offset = idx_value;
1494 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1495 track->textures[2].cube_info[i].robj = reloc->robj;
1496 break;
1497 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1498 track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83
DA		 1499 break;
1500 case RADEON_RB3D_COLORPITCH:
1501 r = r100_cs_packet_next_reloc(p, &reloc);
1502 if (r) {
1503 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1504 idx, reg);
1505 r100_cs_dump_packet(p, pkt);
1506 return r;
1507 }
e024e110 1508
551ebd83
DA		 1509 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1510 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1511 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1512 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1513
513bcb46 1514 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1515 tmp |= tile_flags;
1516 ib[idx] = tmp;
e024e110 1517
513bcb46 1518 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83
DA		 1519 break;
1520 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1521 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83
DA		 1522 break;
1523 case RADEON_RB3D_CNTL:
513bcb46 1524 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1525 case 7:
1526 case 8:
1527 case 9:
1528 case 11:
1529 case 12:
1530 track->cb[0].cpp = 1;
e024e110 1531 break;
551ebd83
DA		 1532 case 3:
1533 case 4:
1534 case 15:
1535 track->cb[0].cpp = 2;
1536 break;
1537 case 6:
1538 track->cb[0].cpp = 4;
1539 break;
1540 default:
1541 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1542 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1543 return -EINVAL;
1544 }
513bcb46 1545 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83
DA		 1546 break;
1547 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1548 switch (idx_value & 0xf) {
551ebd83
DA		 1549 case 0:
1550 track->zb.cpp = 2;
1551 break;
1552 case 2:
1553 case 3:
1554 case 4:
1555 case 5:
1556 case 9:
1557 case 11:
1558 track->zb.cpp = 4;
17782d99 1559 break;
771fe6b9 1560 default:
771fe6b9
JG		 1561 break;
1562 }
551ebd83
DA		 1563 break;
1564 case RADEON_RB3D_ZPASS_ADDR:
1565 r = r100_cs_packet_next_reloc(p, &reloc);
1566 if (r) {
1567 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1568 idx, reg);
1569 r100_cs_dump_packet(p, pkt);
1570 return r;
1571 }
513bcb46 1572 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1573 break;
1574 case RADEON_PP_CNTL:
1575 {
513bcb46 1576 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1577 for (i = 0; i < track->num_texture; i++)
1578 track->textures[i].enabled = !!(temp & (1 << i));
1579 }
1580 break;
1581 case RADEON_SE_VF_CNTL:
513bcb46 1582 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1583 break;
1584 case RADEON_SE_VTX_FMT:
513bcb46 1585 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1586 break;
1587 case RADEON_PP_TEX_SIZE_0:
1588 case RADEON_PP_TEX_SIZE_1:
1589 case RADEON_PP_TEX_SIZE_2:
1590 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1591 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1592 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83
DA		 1593 break;
1594 case RADEON_PP_TEX_PITCH_0:
1595 case RADEON_PP_TEX_PITCH_1:
1596 case RADEON_PP_TEX_PITCH_2:
1597 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1598 track->textures[i].pitch = idx_value + 32;
551ebd83
DA		 1599 break;
1600 case RADEON_PP_TXFILTER_0:
1601 case RADEON_PP_TXFILTER_1:
1602 case RADEON_PP_TXFILTER_2:
1603 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1604 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1605 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1606 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1607 if (tmp == 2 || tmp == 6)
1608 track->textures[i].roundup_w = false;
513bcb46 1609 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1610 if (tmp == 2 || tmp == 6)
1611 track->textures[i].roundup_h = false;
1612 break;
1613 case RADEON_PP_TXFORMAT_0:
1614 case RADEON_PP_TXFORMAT_1:
1615 case RADEON_PP_TXFORMAT_2:
1616 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1617 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1618 track->textures[i].use_pitch = 1;
1619 } else {
1620 track->textures[i].use_pitch = 0;
513bcb46
DA		 1621 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1622 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1623 }
513bcb46 1624 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1625 track->textures[i].tex_coord_type = 2;
513bcb46 1626 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1627 case RADEON_TXFORMAT_I8:
1628 case RADEON_TXFORMAT_RGB332:
1629 case RADEON_TXFORMAT_Y8:
1630 track->textures[i].cpp = 1;
f9da52d5 1631 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1632 break;
1633 case RADEON_TXFORMAT_AI88:
1634 case RADEON_TXFORMAT_ARGB1555:
1635 case RADEON_TXFORMAT_RGB565:
1636 case RADEON_TXFORMAT_ARGB4444:
1637 case RADEON_TXFORMAT_VYUY422:
1638 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1639 case RADEON_TXFORMAT_SHADOW16:
1640 case RADEON_TXFORMAT_LDUDV655:
1641 case RADEON_TXFORMAT_DUDV88:
1642 track->textures[i].cpp = 2;
f9da52d5 1643 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1644 break;
551ebd83
DA		 1645 case RADEON_TXFORMAT_ARGB8888:
1646 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1647 case RADEON_TXFORMAT_SHADOW32:
1648 case RADEON_TXFORMAT_LDUDUV8888:
1649 track->textures[i].cpp = 4;
f9da52d5 1650 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1651 break;
d785d78b
DA		 1652 case RADEON_TXFORMAT_DXT1:
1653 track->textures[i].cpp = 1;
1654 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1655 break;
1656 case RADEON_TXFORMAT_DXT23:
1657 case RADEON_TXFORMAT_DXT45:
1658 track->textures[i].cpp = 1;
1659 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1660 break;
551ebd83 1661 }
513bcb46
DA		 1662 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1663 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83
DA		 1664 break;
1665 case RADEON_PP_CUBIC_FACES_0:
1666 case RADEON_PP_CUBIC_FACES_1:
1667 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1668 tmp = idx_value;
551ebd83
DA		 1669 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1670 for (face = 0; face < 4; face++) {
1671 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1672 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1673 }
551ebd83
DA		 1674 break;
1675 default:
1676 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1677 reg, idx);
1678 return -EINVAL;
771fe6b9
JG		 1679 }
1680 return 0;
1681}
1682
068a117c
JG		 1683int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1684 struct radeon_cs_packet *pkt,
4c788679 1685 struct radeon_bo *robj)
068a117c 1686{
068a117c 1687 unsigned idx;
513bcb46 1688 u32 value;
068a117c 1689 idx = pkt->idx + 1;
513bcb46 1690 value = radeon_get_ib_value(p, idx + 2);
4c788679 1691 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1692 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1693 "(need %u have %lu) !\n",
513bcb46 1694 value + 1,
4c788679 1695 radeon_bo_size(robj));
068a117c
JG		 1696 return -EINVAL;
1697 }
1698 return 0;
1699}
1700
771fe6b9
JG		 1701static int r100_packet3_check(struct radeon_cs_parser *p,
1702 struct radeon_cs_packet *pkt)
1703{
771fe6b9 1704 struct radeon_cs_reloc *reloc;
551ebd83 1705 struct r100_cs_track *track;
771fe6b9 1706 unsigned idx;
771fe6b9
JG		 1707 volatile uint32_t *ib;
1708 int r;
1709
1710 ib = p->ib->ptr;
771fe6b9 1711 idx = pkt->idx + 1;
551ebd83 1712 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1713 switch (pkt->opcode) {
1714 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1715 r = r100_packet3_load_vbpntr(p, pkt, idx);
1716 if (r)
1717 return r;
771fe6b9
JG		 1718 break;
1719 case PACKET3_INDX_BUFFER:
1720 r = r100_cs_packet_next_reloc(p, &reloc);
1721 if (r) {
1722 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1723 r100_cs_dump_packet(p, pkt);
1724 return r;
1725 }
513bcb46 1726 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1727 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1728 if (r) {
1729 return r;
1730 }
771fe6b9
JG		 1731 break;
1732 case 0x23:
771fe6b9
JG		 1733 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1734 r = r100_cs_packet_next_reloc(p, &reloc);
1735 if (r) {
1736 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1737 r100_cs_dump_packet(p, pkt);
1738 return r;
1739 }
513bcb46 1740 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1741 track->num_arrays = 1;
513bcb46 1742 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1743
1744 track->arrays[0].robj = reloc->robj;
1745 track->arrays[0].esize = track->vtx_size;
1746
513bcb46 1747 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1748
513bcb46 1749 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1750 track->immd_dwords = pkt->count - 1;
1751 r = r100_cs_track_check(p->rdev, track);
1752 if (r)
1753 return r;
771fe6b9
JG		 1754 break;
1755 case PACKET3_3D_DRAW_IMMD:
513bcb46 1756 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1757 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1758 return -EINVAL;
1759 }
cf57fc7a 1760 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1761 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1762 track->immd_dwords = pkt->count - 1;
1763 r = r100_cs_track_check(p->rdev, track);
1764 if (r)
1765 return r;
1766 break;
771fe6b9
JG		 1767 /* triggers drawing using in-packet vertex data */
1768 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1769 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1770 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1771 return -EINVAL;
1772 }
513bcb46 1773 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1774 track->immd_dwords = pkt->count;
1775 r = r100_cs_track_check(p->rdev, track);
1776 if (r)
1777 return r;
1778 break;
771fe6b9
JG		 1779 /* triggers drawing using in-packet vertex data */
1780 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1781 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1782 r = r100_cs_track_check(p->rdev, track);
1783 if (r)
1784 return r;
1785 break;
771fe6b9
JG		 1786 /* triggers drawing of vertex buffers setup elsewhere */
1787 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1788 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1789 r = r100_cs_track_check(p->rdev, track);
1790 if (r)
1791 return r;
1792 break;
771fe6b9
JG		 1793 /* triggers drawing using indices to vertex buffer */
1794 case PACKET3_3D_DRAW_VBUF:
513bcb46 1795 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1796 r = r100_cs_track_check(p->rdev, track);
1797 if (r)
1798 return r;
1799 break;
771fe6b9
JG		 1800 /* triggers drawing of vertex buffers setup elsewhere */
1801 case PACKET3_3D_DRAW_INDX:
513bcb46 1802 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1803 r = r100_cs_track_check(p->rdev, track);
1804 if (r)
1805 return r;
1806 break;
771fe6b9
JG		 1807 /* triggers drawing using indices to vertex buffer */
1808 case PACKET3_NOP:
1809 break;
1810 default:
1811 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1812 return -EINVAL;
1813 }
1814 return 0;
1815}
1816
1817int r100_cs_parse(struct radeon_cs_parser *p)
1818{
1819 struct radeon_cs_packet pkt;
9f022ddf 1820 struct r100_cs_track *track;
771fe6b9
JG		 1821 int r;
1822
9f022ddf
JG		 1823 track = kzalloc(sizeof(*track), GFP_KERNEL);
1824 r100_cs_track_clear(p->rdev, track);
1825 p->track = track;
771fe6b9
JG		 1826 do {
1827 r = r100_cs_packet_parse(p, &pkt, p->idx);
1828 if (r) {
1829 return r;
1830 }
1831 p->idx += pkt.count + 2;
1832 switch (pkt.type) {
068a117c 1833 case PACKET_TYPE0:
551ebd83
DA		 1834 if (p->rdev->family >= CHIP_R200)
1835 r = r100_cs_parse_packet0(p, &pkt,
1836 p->rdev->config.r100.reg_safe_bm,
1837 p->rdev->config.r100.reg_safe_bm_size,
1838 &r200_packet0_check);
1839 else
1840 r = r100_cs_parse_packet0(p, &pkt,
1841 p->rdev->config.r100.reg_safe_bm,
1842 p->rdev->config.r100.reg_safe_bm_size,
1843 &r100_packet0_check);
068a117c
JG		 1844 break;
1845 case PACKET_TYPE2:
1846 break;
1847 case PACKET_TYPE3:
1848 r = r100_packet3_check(p, &pkt);
1849 break;
1850 default:
1851 DRM_ERROR("Unknown packet type %d !\n",
1852 pkt.type);
1853 return -EINVAL;
771fe6b9
JG		 1854 }
1855 if (r) {
1856 return r;
1857 }
1858 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1859 return 0;
1860}
1861
1862
1863/*
1864 * Global GPU functions
1865 */
1866void r100_errata(struct radeon_device *rdev)
1867{
1868 rdev->pll_errata = 0;
1869
1870 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1871 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1872 }
1873
1874 if (rdev->family == CHIP_RV100 ||
1875 rdev->family == CHIP_RS100 ||
1876 rdev->family == CHIP_RS200) {
1877 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1878 }
1879}
1880
1881/* Wait for vertical sync on primary CRTC */
1882void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1883{
1884 uint32_t crtc_gen_cntl, tmp;
1885 int i;
1886
1887 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1888 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1889 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1890 return;
1891 }
1892 /* Clear the CRTC_VBLANK_SAVE bit */
1893 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1894 for (i = 0; i < rdev->usec_timeout; i++) {
1895 tmp = RREG32(RADEON_CRTC_STATUS);
1896 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1897 return;
1898 }
1899 DRM_UDELAY(1);
1900 }
1901}
1902
1903/* Wait for vertical sync on secondary CRTC */
1904void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1905{
1906 uint32_t crtc2_gen_cntl, tmp;
1907 int i;
1908
1909 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1910 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1911 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1912 return;
1913
1914 /* Clear the CRTC_VBLANK_SAVE bit */
1915 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1916 for (i = 0; i < rdev->usec_timeout; i++) {
1917 tmp = RREG32(RADEON_CRTC2_STATUS);
1918 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1919 return;
1920 }
1921 DRM_UDELAY(1);
1922 }
1923}
1924
1925int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1926{
1927 unsigned i;
1928 uint32_t tmp;
1929
1930 for (i = 0; i < rdev->usec_timeout; i++) {
1931 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1932 if (tmp >= n) {
1933 return 0;
1934 }
1935 DRM_UDELAY(1);
1936 }
1937 return -1;
1938}
1939
1940int r100_gui_wait_for_idle(struct radeon_device *rdev)
1941{
1942 unsigned i;
1943 uint32_t tmp;
1944
1945 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1946 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1947 " Bad things might happen.\n");
1948 }
1949 for (i = 0; i < rdev->usec_timeout; i++) {
1950 tmp = RREG32(RADEON_RBBM_STATUS);
4612dc97 1951 if (!(tmp & RADEON_RBBM_ACTIVE)) {
771fe6b9
JG		 1952 return 0;
1953 }
1954 DRM_UDELAY(1);
1955 }
1956 return -1;
1957}
1958
1959int r100_mc_wait_for_idle(struct radeon_device *rdev)
1960{
1961 unsigned i;
1962 uint32_t tmp;
1963
1964 for (i = 0; i < rdev->usec_timeout; i++) {
1965 /* read MC_STATUS */
4612dc97
AD		 1966 tmp = RREG32(RADEON_MC_STATUS);
1967 if (tmp & RADEON_MC_IDLE) {
771fe6b9
JG		 1968 return 0;
1969 }
1970 DRM_UDELAY(1);
1971 }
1972 return -1;
1973}
1974
225758d8 1975void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
771fe6b9 1976{
225758d8
JG		 1977 lockup->last_cp_rptr = cp->rptr;
1978 lockup->last_jiffies = jiffies;
1979}
1980
1981/**
1982 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1983 * @rdev: radeon device structure
1984 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
1985 * @cp: radeon_cp structure holding CP information
1986 *
1987 * We don't need to initialize the lockup tracking information as we will either
1988 * have CP rptr to a different value of jiffies wrap around which will force
1989 * initialization of the lockup tracking informations.
1990 *
1991 * A possible false positivie is if we get call after while and last_cp_rptr ==
1992 * the current CP rptr, even if it's unlikely it might happen. To avoid this
1993 * if the elapsed time since last call is bigger than 2 second than we return
1994 * false and update the tracking information. Due to this the caller must call
1995 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
1996 * the fencing code should be cautious about that.
1997 *
1998 * Caller should write to the ring to force CP to do something so we don't get
1999 * false positive when CP is just gived nothing to do.
2000 *
2001 **/
2002bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2003{
2004 unsigned long cjiffies, elapsed;
2005
2006 cjiffies = jiffies;
2007 if (!time_after(cjiffies, lockup->last_jiffies)) {
2008 /* likely a wrap around */
2009 lockup->last_cp_rptr = cp->rptr;
2010 lockup->last_jiffies = jiffies;
2011 return false;
2012 }
2013 if (cp->rptr != lockup->last_cp_rptr) {
2014 /* CP is still working no lockup */
2015 lockup->last_cp_rptr = cp->rptr;
2016 lockup->last_jiffies = jiffies;
2017 return false;
2018 }
2019 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2020 if (elapsed >= 3000) {
2021 /* very likely the improbable case where current
2022 * rptr is equal to last recorded, a while ago, rptr
2023 * this is more likely a false positive update tracking
2024 * information which should force us to be recall at
2025 * latter point
2026 */
2027 lockup->last_cp_rptr = cp->rptr;
2028 lockup->last_jiffies = jiffies;
2029 return false;
2030 }
2031 if (elapsed >= 1000) {
2032 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2033 return true;
2034 }
2035 /* give a chance to the GPU ... */
2036 return false;
771fe6b9
JG		 2037}
2038
225758d8 2039bool r100_gpu_is_lockup(struct radeon_device *rdev)
771fe6b9 2040{
225758d8
JG		 2041 u32 rbbm_status;
2042 int r;
771fe6b9 2043
225758d8
JG		 2044 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2045 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2046 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2047 return false;
2048 }
2049 /* force CP activities */
2050 r = radeon_ring_lock(rdev, 2);
2051 if (!r) {
2052 /* PACKET2 NOP */
2053 radeon_ring_write(rdev, 0x80000000);
2054 radeon_ring_write(rdev, 0x80000000);
2055 radeon_ring_unlock_commit(rdev);
2056 }
2057 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2058 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
771fe6b9
JG		 2059}
2060
90aca4d2 2061void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2062{
90aca4d2 2063 u32 tmp;
771fe6b9 2064
90aca4d2
JG		 2065 /* disable bus mastering */
2066 tmp = RREG32(R_000030_BUS_CNTL);
2067 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2068 mdelay(1);
2069 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2070 mdelay(1);
2071 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2072 tmp = RREG32(RADEON_BUS_CNTL);
2073 mdelay(1);
2074 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2075 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
771fe6b9 2076 mdelay(1);
771fe6b9
JG		 2077}
2078
a2d07b74 2079int r100_asic_reset(struct radeon_device *rdev)
771fe6b9 2080{
90aca4d2
JG		 2081 struct r100_mc_save save;
2082 u32 status, tmp;
771fe6b9 2083
90aca4d2
JG		 2084 r100_mc_stop(rdev, &save);
2085 status = RREG32(R_000E40_RBBM_STATUS);
2086 if (!G_000E40_GUI_ACTIVE(status)) {
2087 return 0;
771fe6b9 2088 }
90aca4d2
JG		 2089 status = RREG32(R_000E40_RBBM_STATUS);
2090 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2091 /* stop CP */
2092 WREG32(RADEON_CP_CSQ_CNTL, 0);
2093 tmp = RREG32(RADEON_CP_RB_CNTL);
2094 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2095 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2096 WREG32(RADEON_CP_RB_WPTR, 0);
2097 WREG32(RADEON_CP_RB_CNTL, tmp);
2098 /* save PCI state */
2099 pci_save_state(rdev->pdev);
2100 /* disable bus mastering */
2101 r100_bm_disable(rdev);
2102 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2103 S_0000F0_SOFT_RESET_RE(1) |
2104 S_0000F0_SOFT_RESET_PP(1) |
2105 S_0000F0_SOFT_RESET_RB(1));
2106 RREG32(R_0000F0_RBBM_SOFT_RESET);
2107 mdelay(500);
2108 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2109 mdelay(1);
2110 status = RREG32(R_000E40_RBBM_STATUS);
2111 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
771fe6b9 2112 /* reset CP */
90aca4d2
JG		 2113 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2114 RREG32(R_0000F0_RBBM_SOFT_RESET);
2115 mdelay(500);
2116 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2117 mdelay(1);
2118 status = RREG32(R_000E40_RBBM_STATUS);
2119 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2120 /* restore PCI & busmastering */
2121 pci_restore_state(rdev->pdev);
2122 r100_enable_bm(rdev);
771fe6b9 2123 /* Check if GPU is idle */
90aca4d2
JG		 2124 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2125 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2126 dev_err(rdev->dev, "failed to reset GPU\n");
2127 rdev->gpu_lockup = true;
771fe6b9
JG		 2128 return -1;
2129 }
90aca4d2
JG		 2130 r100_mc_resume(rdev, &save);
2131 dev_info(rdev->dev, "GPU reset succeed\n");
771fe6b9
JG		 2132 return 0;
2133}
2134
92cde00c
AD		 2135void r100_set_common_regs(struct radeon_device *rdev)
2136{
2739d49c
AD		 2137 struct drm_device *dev = rdev->ddev;
2138 bool force_dac2 = false;
d668046c 2139 u32 tmp;
2739d49c 2140
92cde00c
AD		 2141 /* set these so they don't interfere with anything */
2142 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2143 WREG32(RADEON_SUBPIC_CNTL, 0);
2144 WREG32(RADEON_VIPH_CONTROL, 0);
2145 WREG32(RADEON_I2C_CNTL_1, 0);
2146 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2147 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2148 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2739d49c
AD		 2149
2150 /* always set up dac2 on rn50 and some rv100 as lots
2151 * of servers seem to wire it up to a VGA port but
2152 * don't report it in the bios connector
2153 * table.
2154 */
2155 switch (dev->pdev->device) {
2156 /* RN50 */
2157 case 0x515e:
2158 case 0x5969:
2159 force_dac2 = true;
2160 break;
2161 /* RV100*/
2162 case 0x5159:
2163 case 0x515a:
2164 /* DELL triple head servers */
2165 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2166 ((dev->pdev->subsystem_device == 0x016c) ||
2167 (dev->pdev->subsystem_device == 0x016d) ||
2168 (dev->pdev->subsystem_device == 0x016e) ||
2169 (dev->pdev->subsystem_device == 0x016f) ||
2170 (dev->pdev->subsystem_device == 0x0170) ||
2171 (dev->pdev->subsystem_device == 0x017d) ||
2172 (dev->pdev->subsystem_device == 0x017e) ||
2173 (dev->pdev->subsystem_device == 0x0183) ||
2174 (dev->pdev->subsystem_device == 0x018a) ||
2175 (dev->pdev->subsystem_device == 0x019a)))
2176 force_dac2 = true;
2177 break;
2178 }
2179
2180 if (force_dac2) {
2181 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2182 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2183 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2184
2185 /* For CRT on DAC2, don't turn it on if BIOS didn't
2186 enable it, even it's detected.
2187 */
2188
2189 /* force it to crtc0 */
2190 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2191 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2192 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2193
2194 /* set up the TV DAC */
2195 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2196 RADEON_TV_DAC_STD_MASK |
2197 RADEON_TV_DAC_RDACPD |
2198 RADEON_TV_DAC_GDACPD |
2199 RADEON_TV_DAC_BDACPD |
2200 RADEON_TV_DAC_BGADJ_MASK |
2201 RADEON_TV_DAC_DACADJ_MASK);
2202 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2203 RADEON_TV_DAC_NHOLD |
2204 RADEON_TV_DAC_STD_PS2 |
2205 (0x58 << 16));
2206
2207 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2208 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2209 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2210 }
d668046c
DA		 2211
2212 /* switch PM block to ACPI mode */
2213 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2214 tmp &= ~RADEON_PM_MODE_SEL;
2215 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2216
92cde00c 2217}
771fe6b9
JG		 2218
2219/*
2220 * VRAM info
2221 */
2222static void r100_vram_get_type(struct radeon_device *rdev)
2223{
2224 uint32_t tmp;
2225
2226 rdev->mc.vram_is_ddr = false;
2227 if (rdev->flags & RADEON_IS_IGP)
2228 rdev->mc.vram_is_ddr = true;
2229 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2230 rdev->mc.vram_is_ddr = true;
2231 if ((rdev->family == CHIP_RV100) ||
2232 (rdev->family == CHIP_RS100) ||
2233 (rdev->family == CHIP_RS200)) {
2234 tmp = RREG32(RADEON_MEM_CNTL);
2235 if (tmp & RV100_HALF_MODE) {
2236 rdev->mc.vram_width = 32;
2237 } else {
2238 rdev->mc.vram_width = 64;
2239 }
2240 if (rdev->flags & RADEON_SINGLE_CRTC) {
2241 rdev->mc.vram_width /= 4;
2242 rdev->mc.vram_is_ddr = true;
2243 }
2244 } else if (rdev->family <= CHIP_RV280) {
2245 tmp = RREG32(RADEON_MEM_CNTL);
2246 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2247 rdev->mc.vram_width = 128;
2248 } else {
2249 rdev->mc.vram_width = 64;
2250 }
2251 } else {
2252 /* newer IGPs */
2253 rdev->mc.vram_width = 128;
2254 }
2255}
2256
2a0f8918 2257static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 2258{
2a0f8918
DA		 2259 u32 aper_size;
2260 u8 byte;
2261
2262 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2263
2264 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2265 * that is has the 2nd generation multifunction PCI interface
2266 */
2267 if (rdev->family == CHIP_RV280 ||
2268 rdev->family >= CHIP_RV350) {
2269 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2270 ~RADEON_HDP_APER_CNTL);
2271 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2272 return aper_size * 2;
2273 }
2274
2275 /* Older cards have all sorts of funny issues to deal with. First
2276 * check if it's a multifunction card by reading the PCI config
2277 * header type... Limit those to one aperture size
2278 */
2279 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2280 if (byte & 0x80) {
2281 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2282 DRM_INFO("Limiting VRAM to one aperture\n");
2283 return aper_size;
2284 }
2285
2286 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2287 * have set it up. We don't write this as it's broken on some ASICs but
2288 * we expect the BIOS to have done the right thing (might be too optimistic...)
2289 */
2290 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2291 return aper_size * 2;
2292 return aper_size;
2293}
2294
2295void r100_vram_init_sizes(struct radeon_device *rdev)
2296{
2297 u64 config_aper_size;
2a0f8918 2298
d594e46a 2299 /* work out accessible VRAM */
d594e46a
JG		 2300 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2301 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
51e5fcd3
JG		 2302 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2303 /* FIXME we don't use the second aperture yet when we could use it */
2304 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2305 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2a0f8918 2306 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 2307 if (rdev->flags & RADEON_IS_IGP) {
2308 uint32_t tom;
2309 /* read NB_TOM to get the amount of ram stolen for the GPU */
2310 tom = RREG32(RADEON_NB_TOM);
7a50f01a 2311 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
7a50f01a
DA		 2312 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2313 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2314 } else {
7a50f01a 2315 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 2316 /* Some production boards of m6 will report 0
2317 * if it's 8 MB
2318 */
7a50f01a
DA		 2319 if (rdev->mc.real_vram_size == 0) {
2320 rdev->mc.real_vram_size = 8192 * 1024;
2321 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 2322 }
d594e46a
JG		 2323 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2324 * Novell bug 204882 + along with lots of ubuntu ones
2325 */
7a50f01a
DA		 2326 if (config_aper_size > rdev->mc.real_vram_size)
2327 rdev->mc.mc_vram_size = config_aper_size;
2328 else
2329 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2330 }
2a0f8918
DA		 2331}
2332
28d52043
DA		 2333void r100_vga_set_state(struct radeon_device *rdev, bool state)
2334{
2335 uint32_t temp;
2336
2337 temp = RREG32(RADEON_CONFIG_CNTL);
2338 if (state == false) {
2339 temp &= ~(1<<8);
2340 temp |= (1<<9);
2341 } else {
2342 temp &= ~(1<<9);
2343 }
2344 WREG32(RADEON_CONFIG_CNTL, temp);
2345}
2346
d594e46a 2347void r100_mc_init(struct radeon_device *rdev)
2a0f8918 2348{
d594e46a 2349 u64 base;
2a0f8918 2350
d594e46a 2351 r100_vram_get_type(rdev);
2a0f8918 2352 r100_vram_init_sizes(rdev);
d594e46a
JG		 2353 base = rdev->mc.aper_base;
2354 if (rdev->flags & RADEON_IS_IGP)
2355 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2356 radeon_vram_location(rdev, &rdev->mc, base);
2357 if (!(rdev->flags & RADEON_IS_AGP))
2358 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 2359 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 2360}
2361
2362
2363/*
2364 * Indirect registers accessor
2365 */
2366void r100_pll_errata_after_index(struct radeon_device *rdev)
2367{
2368 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2369 return;
2370 }
2371 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2372 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2373}
2374
2375static void r100_pll_errata_after_data(struct radeon_device *rdev)
2376{
2377 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2378 * or the chip could hang on a subsequent access
2379 */
2380 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2381 udelay(5000);
2382 }
2383
2384 /* This function is required to workaround a hardware bug in some (all?)
2385 * revisions of the R300. This workaround should be called after every
2386 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2387 * may not be correct.
2388 */
2389 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2390 uint32_t save, tmp;
2391
2392 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2393 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2394 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2395 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2396 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2397 }
2398}
2399
2400uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2401{
2402 uint32_t data;
2403
2404 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2405 r100_pll_errata_after_index(rdev);
2406 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2407 r100_pll_errata_after_data(rdev);
2408 return data;
2409}
2410
2411void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2412{
2413 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2414 r100_pll_errata_after_index(rdev);
2415 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2416 r100_pll_errata_after_data(rdev);
2417}
2418
d4550907 2419void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2420{
551ebd83
DA		 2421 if (ASIC_IS_RN50(rdev)) {
2422 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2423 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2424 } else if (rdev->family < CHIP_R200) {
2425 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2426 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2427 } else {
d4550907 2428 r200_set_safe_registers(rdev);
551ebd83 2429 }
068a117c
JG		 2430}
2431
771fe6b9
JG		 2432/*
2433 * Debugfs info
2434 */
2435#if defined(CONFIG_DEBUG_FS)
2436static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2437{
2438 struct drm_info_node *node = (struct drm_info_node *) m->private;
2439 struct drm_device *dev = node->minor->dev;
2440 struct radeon_device *rdev = dev->dev_private;
2441 uint32_t reg, value;
2442 unsigned i;
2443
2444 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2445 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2446 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2447 for (i = 0; i < 64; i++) {
2448 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2449 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2450 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2451 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2452 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2453 }
2454 return 0;
2455}
2456
2457static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2458{
2459 struct drm_info_node *node = (struct drm_info_node *) m->private;
2460 struct drm_device *dev = node->minor->dev;
2461 struct radeon_device *rdev = dev->dev_private;
2462 uint32_t rdp, wdp;
2463 unsigned count, i, j;
2464
2465 radeon_ring_free_size(rdev);
2466 rdp = RREG32(RADEON_CP_RB_RPTR);
2467 wdp = RREG32(RADEON_CP_RB_WPTR);
2468 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2469 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2470 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2471 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2472 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2473 seq_printf(m, "%u dwords in ring\n", count);
2474 for (j = 0; j <= count; j++) {
2475 i = (rdp + j) & rdev->cp.ptr_mask;
2476 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2477 }
2478 return 0;
2479}
2480
2481
2482static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2483{
2484 struct drm_info_node *node = (struct drm_info_node *) m->private;
2485 struct drm_device *dev = node->minor->dev;
2486 struct radeon_device *rdev = dev->dev_private;
2487 uint32_t csq_stat, csq2_stat, tmp;
2488 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2489 unsigned i;
2490
2491 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2492 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2493 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2494 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2495 r_rptr = (csq_stat >> 0) & 0x3ff;
2496 r_wptr = (csq_stat >> 10) & 0x3ff;
2497 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2498 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2499 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2500 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2501 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2502 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2503 seq_printf(m, "Ring rptr %u\n", r_rptr);
2504 seq_printf(m, "Ring wptr %u\n", r_wptr);
2505 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2506 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2507 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2508 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2509 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2510 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2511 seq_printf(m, "Ring fifo:\n");
2512 for (i = 0; i < 256; i++) {
2513 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2514 tmp = RREG32(RADEON_CP_CSQ_DATA);
2515 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2516 }
2517 seq_printf(m, "Indirect1 fifo:\n");
2518 for (i = 256; i <= 512; i++) {
2519 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2520 tmp = RREG32(RADEON_CP_CSQ_DATA);
2521 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2522 }
2523 seq_printf(m, "Indirect2 fifo:\n");
2524 for (i = 640; i < ib1_wptr; i++) {
2525 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2526 tmp = RREG32(RADEON_CP_CSQ_DATA);
2527 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2528 }
2529 return 0;
2530}
2531
2532static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2533{
2534 struct drm_info_node *node = (struct drm_info_node *) m->private;
2535 struct drm_device *dev = node->minor->dev;
2536 struct radeon_device *rdev = dev->dev_private;
2537 uint32_t tmp;
2538
2539 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2540 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2541 tmp = RREG32(RADEON_MC_FB_LOCATION);
2542 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2543 tmp = RREG32(RADEON_BUS_CNTL);
2544 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2545 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2546 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2547 tmp = RREG32(RADEON_AGP_BASE);
2548 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2549 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2550 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2551 tmp = RREG32(0x01D0);
2552 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2553 tmp = RREG32(RADEON_AIC_LO_ADDR);
2554 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2555 tmp = RREG32(RADEON_AIC_HI_ADDR);
2556 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2557 tmp = RREG32(0x01E4);
2558 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2559 return 0;
2560}
2561
2562static struct drm_info_list r100_debugfs_rbbm_list[] = {
2563 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2564};
2565
2566static struct drm_info_list r100_debugfs_cp_list[] = {
2567 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2568 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2569};
2570
2571static struct drm_info_list r100_debugfs_mc_info_list[] = {
2572 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2573};
2574#endif
2575
2576int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2577{
2578#if defined(CONFIG_DEBUG_FS)
2579 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2580#else
2581 return 0;
2582#endif
2583}
2584
2585int r100_debugfs_cp_init(struct radeon_device *rdev)
2586{
2587#if defined(CONFIG_DEBUG_FS)
2588 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2589#else
2590 return 0;
2591#endif
2592}
2593
2594int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2595{
2596#if defined(CONFIG_DEBUG_FS)
2597 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2598#else
2599 return 0;
2600#endif
2601}
e024e110
DA		 2602
2603int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2604 uint32_t tiling_flags, uint32_t pitch,
2605 uint32_t offset, uint32_t obj_size)
2606{
2607 int surf_index = reg * 16;
2608 int flags = 0;
2609
e024e110
DA		 2610 if (rdev->family <= CHIP_RS200) {
2611 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2612 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2613 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2614 if (tiling_flags & RADEON_TILING_MACRO)
2615 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2616 } else if (rdev->family <= CHIP_RV280) {
2617 if (tiling_flags & (RADEON_TILING_MACRO))
2618 flags |= R200_SURF_TILE_COLOR_MACRO;
2619 if (tiling_flags & RADEON_TILING_MICRO)
2620 flags |= R200_SURF_TILE_COLOR_MICRO;
2621 } else {
2622 if (tiling_flags & RADEON_TILING_MACRO)
2623 flags |= R300_SURF_TILE_MACRO;
2624 if (tiling_flags & RADEON_TILING_MICRO)
2625 flags |= R300_SURF_TILE_MICRO;
2626 }
2627
c88f9f0c
MD		 2628 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2629 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2630 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2631 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2632
f5c5f040
DA		 2633 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2634 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2635 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2636 if (ASIC_IS_RN50(rdev))
2637 pitch /= 16;
2638 }
2639
2640 /* r100/r200 divide by 16 */
2641 if (rdev->family < CHIP_R300)
2642 flags |= pitch / 16;
2643 else
2644 flags |= pitch / 8;
2645
2646
e024e110
DA		 2647 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2648 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2649 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2650 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2651 return 0;
2652}
2653
2654void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2655{
2656 int surf_index = reg * 16;
2657 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2658}
c93bb85b
JG		 2659
2660void r100_bandwidth_update(struct radeon_device *rdev)
2661{
2662 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2663 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2664 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2665 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2666 fixed20_12 memtcas_ff[8] = {
68adac5e
BS		 2667 dfixed_init(1),
2668 dfixed_init(2),
2669 dfixed_init(3),
2670 dfixed_init(0),
2671 dfixed_init_half(1),
2672 dfixed_init_half(2),
2673 dfixed_init(0),
c93bb85b
JG		 2674 };
2675 fixed20_12 memtcas_rs480_ff[8] = {
68adac5e
BS		 2676 dfixed_init(0),
2677 dfixed_init(1),
2678 dfixed_init(2),
2679 dfixed_init(3),
2680 dfixed_init(0),
2681 dfixed_init_half(1),
2682 dfixed_init_half(2),
2683 dfixed_init_half(3),
c93bb85b
JG		 2684 };
2685 fixed20_12 memtcas2_ff[8] = {
68adac5e
BS		 2686 dfixed_init(0),
2687 dfixed_init(1),
2688 dfixed_init(2),
2689 dfixed_init(3),
2690 dfixed_init(4),
2691 dfixed_init(5),
2692 dfixed_init(6),
2693 dfixed_init(7),
c93bb85b
JG		 2694 };
2695 fixed20_12 memtrbs[8] = {
68adac5e
BS		 2696 dfixed_init(1),
2697 dfixed_init_half(1),
2698 dfixed_init(2),
2699 dfixed_init_half(2),
2700 dfixed_init(3),
2701 dfixed_init_half(3),
2702 dfixed_init(4),
2703 dfixed_init_half(4)
c93bb85b
JG		 2704 };
2705 fixed20_12 memtrbs_r4xx[8] = {
68adac5e
BS		 2706 dfixed_init(4),
2707 dfixed_init(5),
2708 dfixed_init(6),
2709 dfixed_init(7),
2710 dfixed_init(8),
2711 dfixed_init(9),
2712 dfixed_init(10),
2713 dfixed_init(11)
c93bb85b
JG		 2714 };
2715 fixed20_12 min_mem_eff;
2716 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2717 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2718 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2719 disp_drain_rate2, read_return_rate;
2720 fixed20_12 time_disp1_drop_priority;
2721 int c;
2722 int cur_size = 16; /* in octawords */
2723 int critical_point = 0, critical_point2;
2724/* uint32_t read_return_rate, time_disp1_drop_priority; */
2725 int stop_req, max_stop_req;
2726 struct drm_display_mode *mode1 = NULL;
2727 struct drm_display_mode *mode2 = NULL;
2728 uint32_t pixel_bytes1 = 0;
2729 uint32_t pixel_bytes2 = 0;
2730
f46c0120
AD		 2731 radeon_update_display_priority(rdev);
2732
c93bb85b
JG		 2733 if (rdev->mode_info.crtcs[0]->base.enabled) {
2734 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2735 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2736 }
dfee5614
DA		 2737 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2738 if (rdev->mode_info.crtcs[1]->base.enabled) {
2739 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2740 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2741 }
c93bb85b
JG		 2742 }
2743
68adac5e 2744 min_mem_eff.full = dfixed_const_8(0);
c93bb85b
JG		 2745 /* get modes */
2746 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2747 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2748 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2749 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2750 /* check crtc enables */
2751 if (mode2)
2752 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2753 if (mode1)
2754 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2755 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2756 }
2757
2758 /*
2759 * determine is there is enough bw for current mode
2760 */
f47299c5
AD		 2761 sclk_ff = rdev->pm.sclk;
2762 mclk_ff = rdev->pm.mclk;
c93bb85b
JG		 2763
2764 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
68adac5e
BS		 2765 temp_ff.full = dfixed_const(temp);
2766 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 2767
2768 pix_clk.full = 0;
2769 pix_clk2.full = 0;
2770 peak_disp_bw.full = 0;
2771 if (mode1) {
68adac5e
BS		 2772 temp_ff.full = dfixed_const(1000);
2773 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2774 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2775 temp_ff.full = dfixed_const(pixel_bytes1);
2776 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
c93bb85b
JG		 2777 }
2778 if (mode2) {
68adac5e
BS		 2779 temp_ff.full = dfixed_const(1000);
2780 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2781 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2782 temp_ff.full = dfixed_const(pixel_bytes2);
2783 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
c93bb85b
JG		 2784 }
2785
68adac5e 2786 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
c93bb85b
JG		 2787 if (peak_disp_bw.full >= mem_bw.full) {
2788 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2789 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2790 }
2791
2792 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2793 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2794 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2795 mem_trcd = ((temp >> 2) & 0x3) + 1;
2796 mem_trp = ((temp & 0x3)) + 1;
2797 mem_tras = ((temp & 0x70) >> 4) + 1;
2798 } else if (rdev->family == CHIP_R300 ||
2799 rdev->family == CHIP_R350) { /* r300, r350 */
2800 mem_trcd = (temp & 0x7) + 1;
2801 mem_trp = ((temp >> 8) & 0x7) + 1;
2802 mem_tras = ((temp >> 11) & 0xf) + 4;
2803 } else if (rdev->family == CHIP_RV350 ||
2804 rdev->family <= CHIP_RV380) {
2805 /* rv3x0 */
2806 mem_trcd = (temp & 0x7) + 3;
2807 mem_trp = ((temp >> 8) & 0x7) + 3;
2808 mem_tras = ((temp >> 11) & 0xf) + 6;
2809 } else if (rdev->family == CHIP_R420 ||
2810 rdev->family == CHIP_R423 ||
2811 rdev->family == CHIP_RV410) {
2812 /* r4xx */
2813 mem_trcd = (temp & 0xf) + 3;
2814 if (mem_trcd > 15)
2815 mem_trcd = 15;
2816 mem_trp = ((temp >> 8) & 0xf) + 3;
2817 if (mem_trp > 15)
2818 mem_trp = 15;
2819 mem_tras = ((temp >> 12) & 0x1f) + 6;
2820 if (mem_tras > 31)
2821 mem_tras = 31;
2822 } else { /* RV200, R200 */
2823 mem_trcd = (temp & 0x7) + 1;
2824 mem_trp = ((temp >> 8) & 0x7) + 1;
2825 mem_tras = ((temp >> 12) & 0xf) + 4;
2826 }
2827 /* convert to FF */
68adac5e
BS		 2828 trcd_ff.full = dfixed_const(mem_trcd);
2829 trp_ff.full = dfixed_const(mem_trp);
2830 tras_ff.full = dfixed_const(mem_tras);
c93bb85b
JG		 2831
2832 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2833 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2834 data = (temp & (7 << 20)) >> 20;
2835 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2836 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2837 tcas_ff = memtcas_rs480_ff[data];
2838 else
2839 tcas_ff = memtcas_ff[data];
2840 } else
2841 tcas_ff = memtcas2_ff[data];
2842
2843 if (rdev->family == CHIP_RS400 ||
2844 rdev->family == CHIP_RS480) {
2845 /* extra cas latency stored in bits 23-25 0-4 clocks */
2846 data = (temp >> 23) & 0x7;
2847 if (data < 5)
68adac5e 2848 tcas_ff.full += dfixed_const(data);
c93bb85b
JG		 2849 }
2850
2851 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2852 /* on the R300, Tcas is included in Trbs.
2853 */
2854 temp = RREG32(RADEON_MEM_CNTL);
2855 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2856 if (data == 1) {
2857 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2858 temp = RREG32(R300_MC_IND_INDEX);
2859 temp &= ~R300_MC_IND_ADDR_MASK;
2860 temp |= R300_MC_READ_CNTL_CD_mcind;
2861 WREG32(R300_MC_IND_INDEX, temp);
2862 temp = RREG32(R300_MC_IND_DATA);
2863 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2864 } else {
2865 temp = RREG32(R300_MC_READ_CNTL_AB);
2866 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2867 }
2868 } else {
2869 temp = RREG32(R300_MC_READ_CNTL_AB);
2870 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2871 }
2872 if (rdev->family == CHIP_RV410 ||
2873 rdev->family == CHIP_R420 ||
2874 rdev->family == CHIP_R423)
2875 trbs_ff = memtrbs_r4xx[data];
2876 else
2877 trbs_ff = memtrbs[data];
2878 tcas_ff.full += trbs_ff.full;
2879 }
2880
2881 sclk_eff_ff.full = sclk_ff.full;
2882
2883 if (rdev->flags & RADEON_IS_AGP) {
2884 fixed20_12 agpmode_ff;
68adac5e
BS		 2885 agpmode_ff.full = dfixed_const(radeon_agpmode);
2886 temp_ff.full = dfixed_const_666(16);
2887 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
c93bb85b
JG		 2888 }
2889 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2890
2891 if (ASIC_IS_R300(rdev)) {
68adac5e 2892 sclk_delay_ff.full = dfixed_const(250);
c93bb85b
JG		 2893 } else {
2894 if ((rdev->family == CHIP_RV100) ||
2895 rdev->flags & RADEON_IS_IGP) {
2896 if (rdev->mc.vram_is_ddr)
68adac5e 2897 sclk_delay_ff.full = dfixed_const(41);
c93bb85b 2898 else
68adac5e 2899 sclk_delay_ff.full = dfixed_const(33);
c93bb85b
JG		 2900 } else {
2901 if (rdev->mc.vram_width == 128)
68adac5e 2902 sclk_delay_ff.full = dfixed_const(57);
c93bb85b 2903 else
68adac5e 2904 sclk_delay_ff.full = dfixed_const(41);
c93bb85b
JG		 2905 }
2906 }
2907
68adac5e 2908 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
c93bb85b
JG		 2909
2910 if (rdev->mc.vram_is_ddr) {
2911 if (rdev->mc.vram_width == 32) {
68adac5e 2912 k1.full = dfixed_const(40);
c93bb85b
JG		 2913 c = 3;
2914 } else {
68adac5e 2915 k1.full = dfixed_const(20);
c93bb85b
JG		 2916 c = 1;
2917 }
2918 } else {
68adac5e 2919 k1.full = dfixed_const(40);
c93bb85b
JG		 2920 c = 3;
2921 }
2922
68adac5e
BS		 2923 temp_ff.full = dfixed_const(2);
2924 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2925 temp_ff.full = dfixed_const(c);
2926 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2927 temp_ff.full = dfixed_const(4);
2928 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2929 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
c93bb85b
JG		 2930 mc_latency_mclk.full += k1.full;
2931
68adac5e
BS		 2932 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2933 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 2934
2935 /*
2936 HW cursor time assuming worst case of full size colour cursor.
2937 */
68adac5e 2938 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
c93bb85b
JG		 2939 temp_ff.full += trcd_ff.full;
2940 if (temp_ff.full < tras_ff.full)
2941 temp_ff.full = tras_ff.full;
68adac5e 2942 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
c93bb85b 2943
68adac5e
BS		 2944 temp_ff.full = dfixed_const(cur_size);
2945 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 2946 /*
2947 Find the total latency for the display data.
2948 */
68adac5e
BS		 2949 disp_latency_overhead.full = dfixed_const(8);
2950 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
c93bb85b
JG		 2951 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2952 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2953
2954 if (mc_latency_mclk.full > mc_latency_sclk.full)
2955 disp_latency.full = mc_latency_mclk.full;
2956 else
2957 disp_latency.full = mc_latency_sclk.full;
2958
2959 /* setup Max GRPH_STOP_REQ default value */
2960 if (ASIC_IS_RV100(rdev))
2961 max_stop_req = 0x5c;
2962 else
2963 max_stop_req = 0x7c;
2964
2965 if (mode1) {
2966 /* CRTC1
2967 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2968 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2969 */
2970 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2971
2972 if (stop_req > max_stop_req)
2973 stop_req = max_stop_req;
2974
2975 /*
2976 Find the drain rate of the display buffer.
2977 */
68adac5e
BS		 2978 temp_ff.full = dfixed_const((16/pixel_bytes1));
2979 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
c93bb85b
JG		 2980
2981 /*
2982 Find the critical point of the display buffer.
2983 */
68adac5e
BS		 2984 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2985 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 2986
68adac5e 2987 critical_point = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 2988
2989 if (rdev->disp_priority == 2) {
2990 critical_point = 0;
2991 }
2992
2993 /*
2994 The critical point should never be above max_stop_req-4. Setting
2995 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2996 */
2997 if (max_stop_req - critical_point < 4)
2998 critical_point = 0;
2999
3000 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3001 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3002 critical_point = 0x10;
3003 }
3004
3005 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3006 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3007 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3008 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3009 if ((rdev->family == CHIP_R350) &&
3010 (stop_req > 0x15)) {
3011 stop_req -= 0x10;
3012 }
3013 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3014 temp |= RADEON_GRPH_BUFFER_SIZE;
3015 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3016 RADEON_GRPH_CRITICAL_AT_SOF |
3017 RADEON_GRPH_STOP_CNTL);
3018 /*
3019 Write the result into the register.
3020 */
3021 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3022 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3023
3024#if 0
3025 if ((rdev->family == CHIP_RS400) ||
3026 (rdev->family == CHIP_RS480)) {
3027 /* attempt to program RS400 disp regs correctly ??? */
3028 temp = RREG32(RS400_DISP1_REG_CNTL);
3029 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3030 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3031 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3032 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3033 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3034 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3035 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3036 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3037 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3038 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3039 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3040 }
3041#endif
3042
3043 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
3044 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3045 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3046 }
3047
3048 if (mode2) {
3049 u32 grph2_cntl;
3050 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3051
3052 if (stop_req > max_stop_req)
3053 stop_req = max_stop_req;
3054
3055 /*
3056 Find the drain rate of the display buffer.
3057 */
68adac5e
BS		 3058 temp_ff.full = dfixed_const((16/pixel_bytes2));
3059 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
c93bb85b
JG		 3060
3061 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3062 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3063 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3064 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3065 if ((rdev->family == CHIP_R350) &&
3066 (stop_req > 0x15)) {
3067 stop_req -= 0x10;
3068 }
3069 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3070 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3071 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3072 RADEON_GRPH_CRITICAL_AT_SOF |
3073 RADEON_GRPH_STOP_CNTL);
3074
3075 if ((rdev->family == CHIP_RS100) ||
3076 (rdev->family == CHIP_RS200))
3077 critical_point2 = 0;
3078 else {
3079 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
68adac5e
BS		 3080 temp_ff.full = dfixed_const(temp);
3081 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 3082 if (sclk_ff.full < temp_ff.full)
3083 temp_ff.full = sclk_ff.full;
3084
3085 read_return_rate.full = temp_ff.full;
3086
3087 if (mode1) {
3088 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
68adac5e 3089 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
c93bb85b
JG		 3090 } else {
3091 time_disp1_drop_priority.full = 0;
3092 }
3093 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
68adac5e
BS		 3094 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3095 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 3096
68adac5e 3097 critical_point2 = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 3098
3099 if (rdev->disp_priority == 2) {
3100 critical_point2 = 0;
3101 }
3102
3103 if (max_stop_req - critical_point2 < 4)
3104 critical_point2 = 0;
3105
3106 }
3107
3108 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3109 /* some R300 cards have problem with this set to 0 */
3110 critical_point2 = 0x10;
3111 }
3112
3113 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3114 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3115
3116 if ((rdev->family == CHIP_RS400) ||
3117 (rdev->family == CHIP_RS480)) {
3118#if 0
3119 /* attempt to program RS400 disp2 regs correctly ??? */
3120 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3121 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3122 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3123 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3124 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3125 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3126 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3127 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3128 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3129 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3130 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3131 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3132#endif
3133 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3134 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3135 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3136 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3137 }
3138
3139 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
3140 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3141 }
3142}
551ebd83
DA		 3143
3144static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3145{
3146 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 3147 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 3148 DRM_ERROR("width %d\n", t->width);
ceb776bc 3149 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 3150 DRM_ERROR("height %d\n", t->height);
ceb776bc 3151 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 3152 DRM_ERROR("num levels %d\n", t->num_levels);
3153 DRM_ERROR("depth %d\n", t->txdepth);
3154 DRM_ERROR("bpp %d\n", t->cpp);
3155 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3156 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3157 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 3158 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 3159}
3160
d785d78b
DA		 3161static int r100_track_compress_size(int compress_format, int w, int h)
3162{
3163 int block_width, block_height, block_bytes;
3164 int wblocks, hblocks;
3165 int min_wblocks;
3166 int sz;
3167
3168 block_width = 4;
3169 block_height = 4;
3170
3171 switch (compress_format) {
3172 case R100_TRACK_COMP_DXT1:
3173 block_bytes = 8;
3174 min_wblocks = 4;
3175 break;
3176 default:
3177 case R100_TRACK_COMP_DXT35:
3178 block_bytes = 16;
3179 min_wblocks = 2;
3180 break;
3181 }
3182
3183 hblocks = (h + block_height - 1) / block_height;
3184 wblocks = (w + block_width - 1) / block_width;
3185 if (wblocks < min_wblocks)
3186 wblocks = min_wblocks;
3187 sz = wblocks * hblocks * block_bytes;
3188 return sz;
3189}
3190
37cf6b03
RS		 3191static int r100_cs_track_cube(struct radeon_device *rdev,
3192 struct r100_cs_track *track, unsigned idx)
3193{
3194 unsigned face, w, h;
3195 struct radeon_bo *cube_robj;
3196 unsigned long size;
3197 unsigned compress_format = track->textures[idx].compress_format;
3198
3199 for (face = 0; face < 5; face++) {
3200 cube_robj = track->textures[idx].cube_info[face].robj;
3201 w = track->textures[idx].cube_info[face].width;
3202 h = track->textures[idx].cube_info[face].height;
3203
3204 if (compress_format) {
3205 size = r100_track_compress_size(compress_format, w, h);
3206 } else
3207 size = w * h;
3208 size *= track->textures[idx].cpp;
3209
3210 size += track->textures[idx].cube_info[face].offset;
3211
3212 if (size > radeon_bo_size(cube_robj)) {
3213 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3214 size, radeon_bo_size(cube_robj));
3215 r100_cs_track_texture_print(&track->textures[idx]);
3216 return -1;
3217 }
3218 }
3219 return 0;
3220}
3221
551ebd83
DA		 3222static int r100_cs_track_texture_check(struct radeon_device *rdev,
3223 struct r100_cs_track *track)
3224{
4c788679 3225 struct radeon_bo *robj;
551ebd83 3226 unsigned long size;
b73c5f8b 3227 unsigned u, i, w, h, d;
551ebd83
DA		 3228 int ret;
3229
3230 for (u = 0; u < track->num_texture; u++) {
3231 if (!track->textures[u].enabled)
3232 continue;
3233 robj = track->textures[u].robj;
3234 if (robj == NULL) {
3235 DRM_ERROR("No texture bound to unit %u\n", u);
3236 return -EINVAL;
3237 }
3238 size = 0;
3239 for (i = 0; i <= track->textures[u].num_levels; i++) {
3240 if (track->textures[u].use_pitch) {
3241 if (rdev->family < CHIP_R300)
3242 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3243 else
3244 w = track->textures[u].pitch / (1 << i);
3245 } else {
ceb776bc 3246 w = track->textures[u].width;
551ebd83
DA		 3247 if (rdev->family >= CHIP_RV515)
3248 w |= track->textures[u].width_11;
ceb776bc 3249 w = w / (1 << i);
551ebd83
DA		 3250 if (track->textures[u].roundup_w)
3251 w = roundup_pow_of_two(w);
3252 }
ceb776bc 3253 h = track->textures[u].height;
551ebd83
DA		 3254 if (rdev->family >= CHIP_RV515)
3255 h |= track->textures[u].height_11;
ceb776bc 3256 h = h / (1 << i);
551ebd83
DA		 3257 if (track->textures[u].roundup_h)
3258 h = roundup_pow_of_two(h);
b73c5f8b
MO		 3259 if (track->textures[u].tex_coord_type == 1) {
3260 d = (1 << track->textures[u].txdepth) / (1 << i);
3261 if (!d)
3262 d = 1;
3263 } else {
3264 d = 1;
3265 }
d785d78b
DA		 3266 if (track->textures[u].compress_format) {
3267
b73c5f8b 3268 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
d785d78b
DA		 3269 /* compressed textures are block based */
3270 } else
b73c5f8b 3271 size += w * h * d;
551ebd83
DA		 3272 }
3273 size *= track->textures[u].cpp;
d785d78b 3274
551ebd83
DA		 3275 switch (track->textures[u].tex_coord_type) {
3276 case 0:
551ebd83 3277 case 1:
551ebd83
DA		 3278 break;
3279 case 2:
3280 if (track->separate_cube) {
3281 ret = r100_cs_track_cube(rdev, track, u);
3282 if (ret)
3283 return ret;
3284 } else
3285 size *= 6;
3286 break;
3287 default:
3288 DRM_ERROR("Invalid texture coordinate type %u for unit "
3289 "%u\n", track->textures[u].tex_coord_type, u);
3290 return -EINVAL;
3291 }
4c788679 3292 if (size > radeon_bo_size(robj)) {
551ebd83 3293 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 3294 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 3295 r100_cs_track_texture_print(&track->textures[u]);
3296 return -EINVAL;
3297 }
3298 }
3299 return 0;
3300}
3301
3302int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3303{
3304 unsigned i;
3305 unsigned long size;
3306 unsigned prim_walk;
3307 unsigned nverts;
3308
3309 for (i = 0; i < track->num_cb; i++) {
3310 if (track->cb[i].robj == NULL) {
797fd5b9 3311 if (!(track->zb_cb_clear || track->color_channel_mask ||
46c64d4b
MO		 3312 track->blend_read_enable)) {
3313 continue;
3314 }
551ebd83
DA		 3315 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3316 return -EINVAL;
3317 }
3318 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3319 size += track->cb[i].offset;
4c788679 3320 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 3321 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3322 "(need %lu have %lu) !\n", i, size,
4c788679 3323 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 3324 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3325 i, track->cb[i].pitch, track->cb[i].cpp,
3326 track->cb[i].offset, track->maxy);
3327 return -EINVAL;
3328 }
3329 }
3330 if (track->z_enabled) {
3331 if (track->zb.robj == NULL) {
3332 DRM_ERROR("[drm] No buffer for z buffer !\n");
3333 return -EINVAL;
3334 }
3335 size = track->zb.pitch * track->zb.cpp * track->maxy;
3336 size += track->zb.offset;
4c788679 3337 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 3338 DRM_ERROR("[drm] Buffer too small for z buffer "
3339 "(need %lu have %lu) !\n", size,
4c788679 3340 radeon_bo_size(track->zb.robj));
551ebd83
DA		 3341 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3342 track->zb.pitch, track->zb.cpp,
3343 track->zb.offset, track->maxy);
3344 return -EINVAL;
3345 }
3346 }
3347 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
cae94b0a
MO		 3348 if (track->vap_vf_cntl & (1 << 14)) {
3349 nverts = track->vap_alt_nverts;
3350 } else {
3351 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3352 }
551ebd83
DA		 3353 switch (prim_walk) {
3354 case 1:
3355 for (i = 0; i < track->num_arrays; i++) {
3356 size = track->arrays[i].esize * track->max_indx * 4;
3357 if (track->arrays[i].robj == NULL) {
3358 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3359 "bound\n", prim_walk, i);
3360 return -EINVAL;
3361 }
4c788679
JG		 3362 if (size > radeon_bo_size(track->arrays[i].robj)) {
3363 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3364 "need %lu dwords have %lu dwords\n",
3365 prim_walk, i, size >> 2,
3366 radeon_bo_size(track->arrays[i].robj)
3367 >> 2);
551ebd83
DA		 3368 DRM_ERROR("Max indices %u\n", track->max_indx);
3369 return -EINVAL;
3370 }
3371 }
3372 break;
3373 case 2:
3374 for (i = 0; i < track->num_arrays; i++) {
3375 size = track->arrays[i].esize * (nverts - 1) * 4;
3376 if (track->arrays[i].robj == NULL) {
3377 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3378 "bound\n", prim_walk, i);
3379 return -EINVAL;
3380 }
4c788679
JG		 3381 if (size > radeon_bo_size(track->arrays[i].robj)) {
3382 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3383 "need %lu dwords have %lu dwords\n",
3384 prim_walk, i, size >> 2,
3385 radeon_bo_size(track->arrays[i].robj)
3386 >> 2);
551ebd83
DA		 3387 return -EINVAL;
3388 }
3389 }
3390 break;
3391 case 3:
3392 size = track->vtx_size * nverts;
3393 if (size != track->immd_dwords) {
3394 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3395 track->immd_dwords, size);
3396 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3397 nverts, track->vtx_size);
3398 return -EINVAL;
3399 }
3400 break;
3401 default:
3402 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3403 prim_walk);
3404 return -EINVAL;
3405 }
3406 return r100_cs_track_texture_check(rdev, track);
3407}
3408
3409void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3410{
3411 unsigned i, face;
3412
3413 if (rdev->family < CHIP_R300) {
3414 track->num_cb = 1;
3415 if (rdev->family <= CHIP_RS200)
3416 track->num_texture = 3;
3417 else
3418 track->num_texture = 6;
3419 track->maxy = 2048;
3420 track->separate_cube = 1;
3421 } else {
3422 track->num_cb = 4;
3423 track->num_texture = 16;
3424 track->maxy = 4096;
3425 track->separate_cube = 0;
3426 }
3427
3428 for (i = 0; i < track->num_cb; i++) {
3429 track->cb[i].robj = NULL;
3430 track->cb[i].pitch = 8192;
3431 track->cb[i].cpp = 16;
3432 track->cb[i].offset = 0;
3433 }
3434 track->z_enabled = true;
3435 track->zb.robj = NULL;
3436 track->zb.pitch = 8192;
3437 track->zb.cpp = 4;
3438 track->zb.offset = 0;
3439 track->vtx_size = 0x7F;
3440 track->immd_dwords = 0xFFFFFFFFUL;
3441 track->num_arrays = 11;
3442 track->max_indx = 0x00FFFFFFUL;
3443 for (i = 0; i < track->num_arrays; i++) {
3444 track->arrays[i].robj = NULL;
3445 track->arrays[i].esize = 0x7F;
3446 }
3447 for (i = 0; i < track->num_texture; i++) {
d785d78b 3448 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3449 track->textures[i].pitch = 16536;
3450 track->textures[i].width = 16536;
3451 track->textures[i].height = 16536;
3452 track->textures[i].width_11 = 1 << 11;
3453 track->textures[i].height_11 = 1 << 11;
3454 track->textures[i].num_levels = 12;
3455 if (rdev->family <= CHIP_RS200) {
3456 track->textures[i].tex_coord_type = 0;
3457 track->textures[i].txdepth = 0;
3458 } else {
3459 track->textures[i].txdepth = 16;
3460 track->textures[i].tex_coord_type = 1;
3461 }
3462 track->textures[i].cpp = 64;
3463 track->textures[i].robj = NULL;
3464 /* CS IB emission code makes sure texture unit are disabled */
3465 track->textures[i].enabled = false;
3466 track->textures[i].roundup_w = true;
3467 track->textures[i].roundup_h = true;
3468 if (track->separate_cube)
3469 for (face = 0; face < 5; face++) {
3470 track->textures[i].cube_info[face].robj = NULL;
3471 track->textures[i].cube_info[face].width = 16536;
3472 track->textures[i].cube_info[face].height = 16536;
3473 track->textures[i].cube_info[face].offset = 0;
3474 }
3475 }
3476}
3ce0a23d
JG		 3477
3478int r100_ring_test(struct radeon_device *rdev)
3479{
3480 uint32_t scratch;
3481 uint32_t tmp = 0;
3482 unsigned i;
3483 int r;
3484
3485 r = radeon_scratch_get(rdev, &scratch);
3486 if (r) {
3487 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3488 return r;
3489 }
3490 WREG32(scratch, 0xCAFEDEAD);
3491 r = radeon_ring_lock(rdev, 2);
3492 if (r) {
3493 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3494 radeon_scratch_free(rdev, scratch);
3495 return r;
3496 }
3497 radeon_ring_write(rdev, PACKET0(scratch, 0));
3498 radeon_ring_write(rdev, 0xDEADBEEF);
3499 radeon_ring_unlock_commit(rdev);
3500 for (i = 0; i < rdev->usec_timeout; i++) {
3501 tmp = RREG32(scratch);
3502 if (tmp == 0xDEADBEEF) {
3503 break;
3504 }
3505 DRM_UDELAY(1);
3506 }
3507 if (i < rdev->usec_timeout) {
3508 DRM_INFO("ring test succeeded in %d usecs\n", i);
3509 } else {
3510 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3511 scratch, tmp);
3512 r = -EINVAL;
3513 }
3514 radeon_scratch_free(rdev, scratch);
3515 return r;
3516}
3517
3518void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3519{
3520 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3521 radeon_ring_write(rdev, ib->gpu_addr);
3522 radeon_ring_write(rdev, ib->length_dw);
3523}
3524
3525int r100_ib_test(struct radeon_device *rdev)
3526{
3527 struct radeon_ib *ib;
3528 uint32_t scratch;
3529 uint32_t tmp = 0;
3530 unsigned i;
3531 int r;
3532
3533 r = radeon_scratch_get(rdev, &scratch);
3534 if (r) {
3535 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3536 return r;
3537 }
3538 WREG32(scratch, 0xCAFEDEAD);
3539 r = radeon_ib_get(rdev, &ib);
3540 if (r) {
3541 return r;
3542 }
3543 ib->ptr[0] = PACKET0(scratch, 0);
3544 ib->ptr[1] = 0xDEADBEEF;
3545 ib->ptr[2] = PACKET2(0);
3546 ib->ptr[3] = PACKET2(0);
3547 ib->ptr[4] = PACKET2(0);
3548 ib->ptr[5] = PACKET2(0);
3549 ib->ptr[6] = PACKET2(0);
3550 ib->ptr[7] = PACKET2(0);
3551 ib->length_dw = 8;
3552 r = radeon_ib_schedule(rdev, ib);
3553 if (r) {
3554 radeon_scratch_free(rdev, scratch);
3555 radeon_ib_free(rdev, &ib);
3556 return r;
3557 }
3558 r = radeon_fence_wait(ib->fence, false);
3559 if (r) {
3560 return r;
3561 }
3562 for (i = 0; i < rdev->usec_timeout; i++) {
3563 tmp = RREG32(scratch);
3564 if (tmp == 0xDEADBEEF) {
3565 break;
3566 }
3567 DRM_UDELAY(1);
3568 }
3569 if (i < rdev->usec_timeout) {
3570 DRM_INFO("ib test succeeded in %u usecs\n", i);
3571 } else {
3572 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3573 scratch, tmp);
3574 r = -EINVAL;
3575 }
3576 radeon_scratch_free(rdev, scratch);
3577 radeon_ib_free(rdev, &ib);
3578 return r;
3579}
9f022ddf
JG		 3580
3581void r100_ib_fini(struct radeon_device *rdev)
3582{
3583 radeon_ib_pool_fini(rdev);
3584}
3585
3586int r100_ib_init(struct radeon_device *rdev)
3587{
3588 int r;
3589
3590 r = radeon_ib_pool_init(rdev);
3591 if (r) {
3592 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3593 r100_ib_fini(rdev);
3594 return r;
3595 }
3596 r = r100_ib_test(rdev);
3597 if (r) {
3598 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3599 r100_ib_fini(rdev);
3600 return r;
3601 }
3602 return 0;
3603}
3604
3605void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3606{
3607 /* Shutdown CP we shouldn't need to do that but better be safe than
3608 * sorry
3609 */
3610 rdev->cp.ready = false;
3611 WREG32(R_000740_CP_CSQ_CNTL, 0);
3612
3613 /* Save few CRTC registers */
ca6ffc64 3614 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3615 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3616 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3617 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3618 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3619 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3620 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3621 }
3622
3623 /* Disable VGA aperture access */
ca6ffc64 3624 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3625 /* Disable cursor, overlay, crtc */
3626 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3627 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3628 S_000054_CRTC_DISPLAY_DIS(1));
3629 WREG32(R_000050_CRTC_GEN_CNTL,
3630 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3631 S_000050_CRTC_DISP_REQ_EN_B(1));
3632 WREG32(R_000420_OV0_SCALE_CNTL,
3633 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3634 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3635 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3636 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3637 S_000360_CUR2_LOCK(1));
3638 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3639 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3640 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3641 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3642 WREG32(R_000360_CUR2_OFFSET,
3643 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3644 }
3645}
3646
3647void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3648{
3649 /* Update base address for crtc */
d594e46a 3650 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3651 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3652 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3653 }
3654 /* Restore CRTC registers */
ca6ffc64 3655 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3656 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3657 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3658 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3659 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3660 }
3661}
ca6ffc64
JG		 3662
3663void r100_vga_render_disable(struct radeon_device *rdev)
3664{
d4550907 3665 u32 tmp;
ca6ffc64 3666
d4550907 3667 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3668 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3669}
d4550907
JG		 3670
3671static void r100_debugfs(struct radeon_device *rdev)
3672{
3673 int r;
3674
3675 r = r100_debugfs_mc_info_init(rdev);
3676 if (r)
3677 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3678}
3679
3680static void r100_mc_program(struct radeon_device *rdev)
3681{
3682 struct r100_mc_save save;
3683
3684 /* Stops all mc clients */
3685 r100_mc_stop(rdev, &save);
3686 if (rdev->flags & RADEON_IS_AGP) {
3687 WREG32(R_00014C_MC_AGP_LOCATION,
3688 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3689 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3690 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3691 if (rdev->family > CHIP_RV200)
3692 WREG32(R_00015C_AGP_BASE_2,
3693 upper_32_bits(rdev->mc.agp_base) & 0xff);
3694 } else {
3695 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3696 WREG32(R_000170_AGP_BASE, 0);
3697 if (rdev->family > CHIP_RV200)
3698 WREG32(R_00015C_AGP_BASE_2, 0);
3699 }
3700 /* Wait for mc idle */
3701 if (r100_mc_wait_for_idle(rdev))
3702 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3703 /* Program MC, should be a 32bits limited address space */
3704 WREG32(R_000148_MC_FB_LOCATION,
3705 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3706 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3707 r100_mc_resume(rdev, &save);
3708}
3709
3710void r100_clock_startup(struct radeon_device *rdev)
3711{
3712 u32 tmp;
3713
3714 if (radeon_dynclks != -1 && radeon_dynclks)
3715 radeon_legacy_set_clock_gating(rdev, 1);
3716 /* We need to force on some of the block */
3717 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3718 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3719 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3720 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3721 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3722}
3723
3724static int r100_startup(struct radeon_device *rdev)
3725{
3726 int r;
3727
92cde00c
AD		 3728 /* set common regs */
3729 r100_set_common_regs(rdev);
3730 /* program mc */
d4550907
JG		 3731 r100_mc_program(rdev);
3732 /* Resume clock */
3733 r100_clock_startup(rdev);
3734 /* Initialize GPU configuration (# pipes, ...) */
90aca4d2 3735// r100_gpu_init(rdev);
d4550907
JG		 3736 /* Initialize GART (initialize after TTM so we can allocate
3737 * memory through TTM but finalize after TTM) */
17e15b0c 3738 r100_enable_bm(rdev);
d4550907
JG		 3739 if (rdev->flags & RADEON_IS_PCI) {
3740 r = r100_pci_gart_enable(rdev);
3741 if (r)
3742 return r;
3743 }
3744 /* Enable IRQ */
d4550907 3745 r100_irq_set(rdev);
cafe6609 3746 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3747 /* 1M ring buffer */
3748 r = r100_cp_init(rdev, 1024 * 1024);
3749 if (r) {
3750 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3751 return r;
3752 }
3753 r = r100_wb_init(rdev);
3754 if (r)
3755 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3756 r = r100_ib_init(rdev);
3757 if (r) {
3758 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3759 return r;
3760 }
3761 return 0;
3762}
3763
3764int r100_resume(struct radeon_device *rdev)
3765{
3766 /* Make sur GART are not working */
3767 if (rdev->flags & RADEON_IS_PCI)
3768 r100_pci_gart_disable(rdev);
3769 /* Resume clock before doing reset */
3770 r100_clock_startup(rdev);
3771 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3772 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3773 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3774 RREG32(R_000E40_RBBM_STATUS),
3775 RREG32(R_0007C0_CP_STAT));
3776 }
3777 /* post */
3778 radeon_combios_asic_init(rdev->ddev);
3779 /* Resume clock after posting */
3780 r100_clock_startup(rdev);
550e2d92
DA		 3781 /* Initialize surface registers */
3782 radeon_surface_init(rdev);
d4550907
JG		 3783 return r100_startup(rdev);
3784}
3785
3786int r100_suspend(struct radeon_device *rdev)
3787{
3788 r100_cp_disable(rdev);
3789 r100_wb_disable(rdev);
3790 r100_irq_disable(rdev);
3791 if (rdev->flags & RADEON_IS_PCI)
3792 r100_pci_gart_disable(rdev);
3793 return 0;
3794}
3795
3796void r100_fini(struct radeon_device *rdev)
3797{
d4550907
JG		 3798 r100_cp_fini(rdev);
3799 r100_wb_fini(rdev);
3800 r100_ib_fini(rdev);
3801 radeon_gem_fini(rdev);
3802 if (rdev->flags & RADEON_IS_PCI)
3803 r100_pci_gart_fini(rdev);
d0269ed8 3804 radeon_agp_fini(rdev);
d4550907
JG		 3805 radeon_irq_kms_fini(rdev);
3806 radeon_fence_driver_fini(rdev);
4c788679 3807 radeon_bo_fini(rdev);
d4550907
JG		 3808 radeon_atombios_fini(rdev);
3809 kfree(rdev->bios);
3810 rdev->bios = NULL;
3811}
3812
d4550907
JG		 3813int r100_init(struct radeon_device *rdev)
3814{
3815 int r;
3816
d4550907
JG		 3817 /* Register debugfs file specific to this group of asics */
3818 r100_debugfs(rdev);
3819 /* Disable VGA */
3820 r100_vga_render_disable(rdev);
3821 /* Initialize scratch registers */
3822 radeon_scratch_init(rdev);
3823 /* Initialize surface registers */
3824 radeon_surface_init(rdev);
3825 /* TODO: disable VGA need to use VGA request */
3826 /* BIOS*/
3827 if (!radeon_get_bios(rdev)) {
3828 if (ASIC_IS_AVIVO(rdev))
3829 return -EINVAL;
3830 }
3831 if (rdev->is_atom_bios) {
3832 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3833 return -EINVAL;
3834 } else {
3835 r = radeon_combios_init(rdev);
3836 if (r)
3837 return r;
3838 }
3839 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3840 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3841 dev_warn(rdev->dev,
3842 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3843 RREG32(R_000E40_RBBM_STATUS),
3844 RREG32(R_0007C0_CP_STAT));
3845 }
3846 /* check if cards are posted or not */
72542d77
DA		 3847 if (radeon_boot_test_post_card(rdev) == false)
3848 return -EINVAL;
d4550907
JG		 3849 /* Set asic errata */
3850 r100_errata(rdev);
3851 /* Initialize clocks */
3852 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 3853 /* initialize AGP */
3854 if (rdev->flags & RADEON_IS_AGP) {
3855 r = radeon_agp_init(rdev);
3856 if (r) {
3857 radeon_agp_disable(rdev);
3858 }
3859 }
3860 /* initialize VRAM */
3861 r100_mc_init(rdev);
d4550907
JG		 3862 /* Fence driver */
3863 r = radeon_fence_driver_init(rdev);
3864 if (r)
3865 return r;
3866 r = radeon_irq_kms_init(rdev);
3867 if (r)
3868 return r;
3869 /* Memory manager */
4c788679 3870 r = radeon_bo_init(rdev);
d4550907
JG		 3871 if (r)
3872 return r;
3873 if (rdev->flags & RADEON_IS_PCI) {
3874 r = r100_pci_gart_init(rdev);
3875 if (r)
3876 return r;
3877 }
3878 r100_set_safe_registers(rdev);
3879 rdev->accel_working = true;
3880 r = r100_startup(rdev);
3881 if (r) {
3882 /* Somethings want wront with the accel init stop accel */
3883 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907
JG		 3884 r100_cp_fini(rdev);
3885 r100_wb_fini(rdev);
3886 r100_ib_fini(rdev);
655efd3d 3887 radeon_irq_kms_fini(rdev);
d4550907
JG		 3888 if (rdev->flags & RADEON_IS_PCI)
3889 r100_pci_gart_fini(rdev);
d4550907
JG		 3890 rdev->accel_working = false;
3891 }
3892 return 0;
3893}
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