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drm/i915: introduce intel_ring_buffer structure (V2)
[net-next-2.6.git] / drivers / gpu / drm / i915 / intel_overlay.c
CommitLineData
02e792fb
DV		 1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
32#include "i915_reg.h"
33#include "intel_drv.h"
34
35/* Limits for overlay size. According to intel doc, the real limits are:
36 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
37 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
38 * the mininum of both. */
39#define IMAGE_MAX_WIDTH 2048
40#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
41/* on 830 and 845 these large limits result in the card hanging */
42#define IMAGE_MAX_WIDTH_LEGACY 1024
43#define IMAGE_MAX_HEIGHT_LEGACY 1088
44
45/* overlay register definitions */
46/* OCMD register */
47#define OCMD_TILED_SURFACE (0x1<<19)
48#define OCMD_MIRROR_MASK (0x3<<17)
49#define OCMD_MIRROR_MODE (0x3<<17)
50#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
51#define OCMD_MIRROR_VERTICAL (0x2<<17)
52#define OCMD_MIRROR_BOTH (0x3<<17)
53#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
54#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
55#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
56#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
57#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
58#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
59#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
60#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
61#define OCMD_YUV_422_PACKED (0x8<<10)
62#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
63#define OCMD_YUV_420_PLANAR (0xc<<10)
64#define OCMD_YUV_422_PLANAR (0xd<<10)
65#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
66#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
67#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
68#define OCMD_BUF_TYPE_MASK (Ox1<<5)
69#define OCMD_BUF_TYPE_FRAME (0x0<<5)
70#define OCMD_BUF_TYPE_FIELD (0x1<<5)
71#define OCMD_TEST_MODE (0x1<<4)
72#define OCMD_BUFFER_SELECT (0x3<<2)
73#define OCMD_BUFFER0 (0x0<<2)
74#define OCMD_BUFFER1 (0x1<<2)
75#define OCMD_FIELD_SELECT (0x1<<2)
76#define OCMD_FIELD0 (0x0<<1)
77#define OCMD_FIELD1 (0x1<<1)
78#define OCMD_ENABLE (0x1<<0)
79
80/* OCONFIG register */
81#define OCONF_PIPE_MASK (0x1<<18)
82#define OCONF_PIPE_A (0x0<<18)
83#define OCONF_PIPE_B (0x1<<18)
84#define OCONF_GAMMA2_ENABLE (0x1<<16)
85#define OCONF_CSC_MODE_BT601 (0x0<<5)
86#define OCONF_CSC_MODE_BT709 (0x1<<5)
87#define OCONF_CSC_BYPASS (0x1<<4)
88#define OCONF_CC_OUT_8BIT (0x1<<3)
89#define OCONF_TEST_MODE (0x1<<2)
90#define OCONF_THREE_LINE_BUFFER (0x1<<0)
91#define OCONF_TWO_LINE_BUFFER (0x0<<0)
92
93/* DCLRKM (dst-key) register */
94#define DST_KEY_ENABLE (0x1<<31)
95#define CLK_RGB24_MASK 0x0
96#define CLK_RGB16_MASK 0x070307
97#define CLK_RGB15_MASK 0x070707
98#define CLK_RGB8I_MASK 0xffffff
99
100#define RGB16_TO_COLORKEY(c) \
101 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
102#define RGB15_TO_COLORKEY(c) \
103 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104
105/* overlay flip addr flag */
106#define OFC_UPDATE 0x1
107
108/* polyphase filter coefficients */
109#define N_HORIZ_Y_TAPS 5
110#define N_VERT_Y_TAPS 3
111#define N_HORIZ_UV_TAPS 3
112#define N_VERT_UV_TAPS 3
113#define N_PHASES 17
114#define MAX_TAPS 5
115
116/* memory bufferd overlay registers */
117struct overlay_registers {
118 u32 OBUF_0Y;
119 u32 OBUF_1Y;
120 u32 OBUF_0U;
121 u32 OBUF_0V;
122 u32 OBUF_1U;
123 u32 OBUF_1V;
124 u32 OSTRIDE;
125 u32 YRGB_VPH;
126 u32 UV_VPH;
127 u32 HORZ_PH;
128 u32 INIT_PHS;
129 u32 DWINPOS;
130 u32 DWINSZ;
131 u32 SWIDTH;
132 u32 SWIDTHSW;
133 u32 SHEIGHT;
134 u32 YRGBSCALE;
135 u32 UVSCALE;
136 u32 OCLRC0;
137 u32 OCLRC1;
138 u32 DCLRKV;
139 u32 DCLRKM;
140 u32 SCLRKVH;
141 u32 SCLRKVL;
142 u32 SCLRKEN;
143 u32 OCONFIG;
144 u32 OCMD;
145 u32 RESERVED1; /* 0x6C */
146 u32 OSTART_0Y;
147 u32 OSTART_1Y;
148 u32 OSTART_0U;
149 u32 OSTART_0V;
150 u32 OSTART_1U;
151 u32 OSTART_1V;
152 u32 OTILEOFF_0Y;
153 u32 OTILEOFF_1Y;
154 u32 OTILEOFF_0U;
155 u32 OTILEOFF_0V;
156 u32 OTILEOFF_1U;
157 u32 OTILEOFF_1V;
158 u32 FASTHSCALE; /* 0xA0 */
159 u32 UVSCALEV; /* 0xA4 */
160 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
161 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
162 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
163 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
164 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
165 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
166 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
167 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
168 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
169};
170
171/* overlay flip addr flag */
172#define OFC_UPDATE 0x1
173
174#define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
bad720ff 175#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev) && !IS_GEN6(dev))
02e792fb
DV		 176
177
178static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
179{
180 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
181 struct overlay_registers *regs;
182
183 /* no recursive mappings */
184 BUG_ON(overlay->virt_addr);
185
186 if (OVERLAY_NONPHYSICAL(overlay->dev)) {
187 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
188 overlay->reg_bo->gtt_offset);
189
190 if (!regs) {
191 DRM_ERROR("failed to map overlay regs in GTT\n");
192 return NULL;
193 }
194 } else
195 regs = overlay->reg_bo->phys_obj->handle->vaddr;
196
197 return overlay->virt_addr = regs;
198}
199
200static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
201{
02e792fb
DV		 202 if (OVERLAY_NONPHYSICAL(overlay->dev))
203 io_mapping_unmap_atomic(overlay->virt_addr);
204
205 overlay->virt_addr = NULL;
206
02e792fb
DV		 207 return;
208}
209
210/* overlay needs to be disable in OCMD reg */
211static int intel_overlay_on(struct intel_overlay *overlay)
212{
213 struct drm_device *dev = overlay->dev;
02e792fb 214 int ret;
02e792fb
DV		 215
216 BUG_ON(overlay->active);
217
03f77ea5
DV		 218 overlay->active = 1;
219 overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP;
220
4f8a567c 221 BEGIN_LP_RING(4);
02e792fb
DV		 222 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
223 OUT_RING(overlay->flip_addr | OFC_UPDATE);
224 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
225 OUT_RING(MI_NOOP);
226 ADVANCE_LP_RING();
227
03f77ea5
DV		 228 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
229 if (overlay->last_flip_req == 0)
230 return -ENOMEM;
02e792fb 231
03f77ea5
DV		 232 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
233 if (ret != 0)
234 return ret;
02e792fb 235
03f77ea5
DV		 236 overlay->hw_wedged = 0;
237 overlay->last_flip_req = 0;
02e792fb
DV		 238 return 0;
239}
240
241/* overlay needs to be enabled in OCMD reg */
242static void intel_overlay_continue(struct intel_overlay *overlay,
243 bool load_polyphase_filter)
244{
245 struct drm_device *dev = overlay->dev;
246 drm_i915_private_t *dev_priv = dev->dev_private;
247 u32 flip_addr = overlay->flip_addr;
248 u32 tmp;
02e792fb
DV		 249
250 BUG_ON(!overlay->active);
251
252 if (load_polyphase_filter)
253 flip_addr |= OFC_UPDATE;
254
255 /* check for underruns */
256 tmp = I915_READ(DOVSTA);
257 if (tmp & (1 << 17))
258 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
259
4f8a567c 260 BEGIN_LP_RING(2);
02e792fb
DV		 261 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
262 OUT_RING(flip_addr);
5a5a0c64
DV		 263 ADVANCE_LP_RING();
264
265 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
266}
267
268static int intel_overlay_wait_flip(struct intel_overlay *overlay)
269{
270 struct drm_device *dev = overlay->dev;
271 drm_i915_private_t *dev_priv = dev->dev_private;
272 int ret;
273 u32 tmp;
5a5a0c64
DV		 274
275 if (overlay->last_flip_req != 0) {
5c5a4359
DV		 276 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
277 if (ret == 0) {
278 overlay->last_flip_req = 0;
5a5a0c64 279
5c5a4359 280 tmp = I915_READ(ISR);
5a5a0c64 281
5c5a4359
DV		 282 if (!(tmp & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT))
283 return 0;
284 }
5a5a0c64
DV		 285 }
286
287 /* synchronous slowpath */
03f77ea5
DV		 288 overlay->hw_wedged = RELEASE_OLD_VID;
289
5a5a0c64 290 BEGIN_LP_RING(2);
02e792fb
DV		 291 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
292 OUT_RING(MI_NOOP);
293 ADVANCE_LP_RING();
294
03f77ea5
DV		 295 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
296 if (overlay->last_flip_req == 0)
297 return -ENOMEM;
02e792fb 298
03f77ea5
DV		 299 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
300 if (ret != 0)
301 return ret;
302
303 overlay->hw_wedged = 0;
304 overlay->last_flip_req = 0;
305 return 0;
02e792fb
DV		 306}
307
308/* overlay needs to be disabled in OCMD reg */
309static int intel_overlay_off(struct intel_overlay *overlay)
310{
311 u32 flip_addr = overlay->flip_addr;
312 struct drm_device *dev = overlay->dev;
02e792fb 313 int ret;
02e792fb
DV		 314
315 BUG_ON(!overlay->active);
316
317 /* According to intel docs the overlay hw may hang (when switching
318 * off) without loading the filter coeffs. It is however unclear whether
319 * this applies to the disabling of the overlay or to the switching off
320 * of the hw. Do it in both cases */
321 flip_addr |= OFC_UPDATE;
322
323 /* wait for overlay to go idle */
03f77ea5
DV		 324 overlay->hw_wedged = SWITCH_OFF_STAGE_1;
325
4f8a567c 326 BEGIN_LP_RING(4);
02e792fb
DV		 327 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
328 OUT_RING(flip_addr);
329 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
330 OUT_RING(MI_NOOP);
331 ADVANCE_LP_RING();
332
03f77ea5
DV		 333 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
334 if (overlay->last_flip_req == 0)
335 return -ENOMEM;
336
337 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
338 if (ret != 0)
02e792fb 339 return ret;
02e792fb
DV		 340
341 /* turn overlay off */
03f77ea5
DV		 342 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
343
4f8a567c 344 BEGIN_LP_RING(4);
02e792fb
DV		 345 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
346 OUT_RING(flip_addr);
347 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
348 OUT_RING(MI_NOOP);
349 ADVANCE_LP_RING();
350
03f77ea5
DV		 351 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
352 if (overlay->last_flip_req == 0)
353 return -ENOMEM;
354
355 ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
356 if (ret != 0)
02e792fb 357 return ret;
02e792fb 358
03f77ea5
DV		 359 overlay->hw_wedged = 0;
360 overlay->last_flip_req = 0;
02e792fb
DV		 361 return ret;
362}
363
12ca45fe
DV		 364static void intel_overlay_off_tail(struct intel_overlay *overlay)
365{
366 struct drm_gem_object *obj;
367
368 /* never have the overlay hw on without showing a frame */
369 BUG_ON(!overlay->vid_bo);
a8089e84 370 obj = &overlay->vid_bo->base;
12ca45fe
DV		 371
372 i915_gem_object_unpin(obj);
373 drm_gem_object_unreference(obj);
374 overlay->vid_bo = NULL;
375
376 overlay->crtc->overlay = NULL;
377 overlay->crtc = NULL;
378 overlay->active = 0;
379}
380
03f77ea5
DV		 381/* recover from an interruption due to a signal
382 * We have to be careful not to repeat work forever an make forward progess. */
383int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
384 int interruptible)
385{
386 struct drm_device *dev = overlay->dev;
03f77ea5
DV		 387 struct drm_gem_object *obj;
388 u32 flip_addr;
389 int ret;
03f77ea5
DV		 390
391 if (overlay->hw_wedged == HW_WEDGED)
392 return -EIO;
393
394 if (overlay->last_flip_req == 0) {
395 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
396 if (overlay->last_flip_req == 0)
397 return -ENOMEM;
398 }
399
400 ret = i915_do_wait_request(dev, overlay->last_flip_req, interruptible);
401 if (ret != 0)
402 return ret;
403
404 switch (overlay->hw_wedged) {
405 case RELEASE_OLD_VID:
a8089e84 406 obj = &overlay->old_vid_bo->base;
03f77ea5
DV		 407 i915_gem_object_unpin(obj);
408 drm_gem_object_unreference(obj);
409 overlay->old_vid_bo = NULL;
410 break;
411 case SWITCH_OFF_STAGE_1:
412 flip_addr = overlay->flip_addr;
413 flip_addr |= OFC_UPDATE;
414
415 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
416
4f8a567c 417 BEGIN_LP_RING(4);
03f77ea5
DV		 418 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
419 OUT_RING(flip_addr);
420 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
421 OUT_RING(MI_NOOP);
422 ADVANCE_LP_RING();
423
424 overlay->last_flip_req = i915_add_request(dev, NULL, 0);
425 if (overlay->last_flip_req == 0)
426 return -ENOMEM;
427
428 ret = i915_do_wait_request(dev, overlay->last_flip_req,
429 interruptible);
430 if (ret != 0)
431 return ret;
432
433 case SWITCH_OFF_STAGE_2:
12ca45fe 434 intel_overlay_off_tail(overlay);
03f77ea5
DV		 435 break;
436 default:
437 BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
438 }
439
440 overlay->hw_wedged = 0;
441 overlay->last_flip_req = 0;
442 return 0;
443}
444
5a5a0c64
DV		 445/* Wait for pending overlay flip and release old frame.
446 * Needs to be called before the overlay register are changed
447 * via intel_overlay_(un)map_regs_atomic */
02e792fb
DV		 448static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
449{
450 int ret;
451 struct drm_gem_object *obj;
452
03f77ea5
DV		 453 /* only wait if there is actually an old frame to release to
454 * guarantee forward progress */
455 if (!overlay->old_vid_bo)
456 return 0;
457
02e792fb
DV		 458 ret = intel_overlay_wait_flip(overlay);
459 if (ret != 0)
460 return ret;
461
a8089e84 462 obj = &overlay->old_vid_bo->base;
02e792fb
DV		 463 i915_gem_object_unpin(obj);
464 drm_gem_object_unreference(obj);
465 overlay->old_vid_bo = NULL;
466
467 return 0;
468}
469
470struct put_image_params {
471 int format;
472 short dst_x;
473 short dst_y;
474 short dst_w;
475 short dst_h;
476 short src_w;
477 short src_scan_h;
478 short src_scan_w;
479 short src_h;
480 short stride_Y;
481 short stride_UV;
482 int offset_Y;
483 int offset_U;
484 int offset_V;
485};
486
487static int packed_depth_bytes(u32 format)
488{
489 switch (format & I915_OVERLAY_DEPTH_MASK) {
490 case I915_OVERLAY_YUV422:
491 return 4;
492 case I915_OVERLAY_YUV411:
493 /* return 6; not implemented */
494 default:
495 return -EINVAL;
496 }
497}
498
499static int packed_width_bytes(u32 format, short width)
500{
501 switch (format & I915_OVERLAY_DEPTH_MASK) {
502 case I915_OVERLAY_YUV422:
503 return width << 1;
504 default:
505 return -EINVAL;
506 }
507}
508
509static int uv_hsubsampling(u32 format)
510{
511 switch (format & I915_OVERLAY_DEPTH_MASK) {
512 case I915_OVERLAY_YUV422:
513 case I915_OVERLAY_YUV420:
514 return 2;
515 case I915_OVERLAY_YUV411:
516 case I915_OVERLAY_YUV410:
517 return 4;
518 default:
519 return -EINVAL;
520 }
521}
522
523static int uv_vsubsampling(u32 format)
524{
525 switch (format & I915_OVERLAY_DEPTH_MASK) {
526 case I915_OVERLAY_YUV420:
527 case I915_OVERLAY_YUV410:
528 return 2;
529 case I915_OVERLAY_YUV422:
530 case I915_OVERLAY_YUV411:
531 return 1;
532 default:
533 return -EINVAL;
534 }
535}
536
537static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
538{
539 u32 mask, shift, ret;
540 if (IS_I9XX(dev)) {
541 mask = 0x3f;
542 shift = 6;
543 } else {
544 mask = 0x1f;
545 shift = 5;
546 }
547 ret = ((offset + width + mask) >> shift) - (offset >> shift);
548 if (IS_I9XX(dev))
549 ret <<= 1;
550 ret -=1;
551 return ret << 2;
552}
553
554static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
555 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
556 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
557 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
558 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
559 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
560 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
561 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
562 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
563 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
564 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
565 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
566 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
567 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
568 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
569 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
570 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
571 0xb000, 0x3000, 0x0800, 0x3000, 0xb000};
572static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
573 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
574 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
575 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
576 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
577 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
578 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
579 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
580 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
581 0x3000, 0x0800, 0x3000};
582
583static void update_polyphase_filter(struct overlay_registers *regs)
584{
585 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
586 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
587}
588
589static bool update_scaling_factors(struct intel_overlay *overlay,
590 struct overlay_registers *regs,
591 struct put_image_params *params)
592{
593 /* fixed point with a 12 bit shift */
594 u32 xscale, yscale, xscale_UV, yscale_UV;
595#define FP_SHIFT 12
596#define FRACT_MASK 0xfff
597 bool scale_changed = false;
598 int uv_hscale = uv_hsubsampling(params->format);
599 int uv_vscale = uv_vsubsampling(params->format);
600
601 if (params->dst_w > 1)
602 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
603 /(params->dst_w);
604 else
605 xscale = 1 << FP_SHIFT;
606
607 if (params->dst_h > 1)
608 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
609 /(params->dst_h);
610 else
611 yscale = 1 << FP_SHIFT;
612
613 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
614 xscale_UV = xscale/uv_hscale;
615 yscale_UV = yscale/uv_vscale;
616 /* make the Y scale to UV scale ratio an exact multiply */
617 xscale = xscale_UV * uv_hscale;
618 yscale = yscale_UV * uv_vscale;
619 /*} else {
620 xscale_UV = 0;
621 yscale_UV = 0;
622 }*/
623
624 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
625 scale_changed = true;
626 overlay->old_xscale = xscale;
627 overlay->old_yscale = yscale;
628
629 regs->YRGBSCALE = ((yscale & FRACT_MASK) << 20)
630 | ((xscale >> FP_SHIFT) << 16)
631 | ((xscale & FRACT_MASK) << 3);
632 regs->UVSCALE = ((yscale_UV & FRACT_MASK) << 20)
633 | ((xscale_UV >> FP_SHIFT) << 16)
634 | ((xscale_UV & FRACT_MASK) << 3);
635 regs->UVSCALEV = ((yscale >> FP_SHIFT) << 16)
636 | ((yscale_UV >> FP_SHIFT) << 0);
637
638 if (scale_changed)
639 update_polyphase_filter(regs);
640
641 return scale_changed;
642}
643
644static void update_colorkey(struct intel_overlay *overlay,
645 struct overlay_registers *regs)
646{
647 u32 key = overlay->color_key;
648 switch (overlay->crtc->base.fb->bits_per_pixel) {
649 case 8:
650 regs->DCLRKV = 0;
651 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
652 case 16:
653 if (overlay->crtc->base.fb->depth == 15) {
654 regs->DCLRKV = RGB15_TO_COLORKEY(key);
655 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
656 } else {
657 regs->DCLRKV = RGB16_TO_COLORKEY(key);
658 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
659 }
660 case 24:
661 case 32:
662 regs->DCLRKV = key;
663 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
664 }
665}
666
667static u32 overlay_cmd_reg(struct put_image_params *params)
668{
669 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
670
671 if (params->format & I915_OVERLAY_YUV_PLANAR) {
672 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
673 case I915_OVERLAY_YUV422:
674 cmd |= OCMD_YUV_422_PLANAR;
675 break;
676 case I915_OVERLAY_YUV420:
677 cmd |= OCMD_YUV_420_PLANAR;
678 break;
679 case I915_OVERLAY_YUV411:
680 case I915_OVERLAY_YUV410:
681 cmd |= OCMD_YUV_410_PLANAR;
682 break;
683 }
684 } else { /* YUV packed */
685 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
686 case I915_OVERLAY_YUV422:
687 cmd |= OCMD_YUV_422_PACKED;
688 break;
689 case I915_OVERLAY_YUV411:
690 cmd |= OCMD_YUV_411_PACKED;
691 break;
692 }
693
694 switch (params->format & I915_OVERLAY_SWAP_MASK) {
695 case I915_OVERLAY_NO_SWAP:
696 break;
697 case I915_OVERLAY_UV_SWAP:
698 cmd |= OCMD_UV_SWAP;
699 break;
700 case I915_OVERLAY_Y_SWAP:
701 cmd |= OCMD_Y_SWAP;
702 break;
703 case I915_OVERLAY_Y_AND_UV_SWAP:
704 cmd |= OCMD_Y_AND_UV_SWAP;
705 break;
706 }
707 }
708
709 return cmd;
710}
711
712int intel_overlay_do_put_image(struct intel_overlay *overlay,
713 struct drm_gem_object *new_bo,
714 struct put_image_params *params)
715{
716 int ret, tmp_width;
717 struct overlay_registers *regs;
718 bool scale_changed = false;
23010e43 719 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
02e792fb
DV		 720 struct drm_device *dev = overlay->dev;
721
722 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
723 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
724 BUG_ON(!overlay);
725
02e792fb
DV		 726 ret = intel_overlay_release_old_vid(overlay);
727 if (ret != 0)
728 return ret;
729
730 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
731 if (ret != 0)
732 return ret;
733
734 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
735 if (ret != 0)
736 goto out_unpin;
737
738 if (!overlay->active) {
739 regs = intel_overlay_map_regs_atomic(overlay);
740 if (!regs) {
741 ret = -ENOMEM;
742 goto out_unpin;
743 }
744 regs->OCONFIG = OCONF_CC_OUT_8BIT;
745 if (IS_I965GM(overlay->dev))
746 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
747 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
748 OCONF_PIPE_A : OCONF_PIPE_B;
749 intel_overlay_unmap_regs_atomic(overlay);
750
751 ret = intel_overlay_on(overlay);
752 if (ret != 0)
753 goto out_unpin;
754 }
755
756 regs = intel_overlay_map_regs_atomic(overlay);
757 if (!regs) {
758 ret = -ENOMEM;
759 goto out_unpin;
760 }
761
762 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
763 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
764
765 if (params->format & I915_OVERLAY_YUV_PACKED)
766 tmp_width = packed_width_bytes(params->format, params->src_w);
767 else
768 tmp_width = params->src_w;
769
770 regs->SWIDTH = params->src_w;
771 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
772 params->offset_Y, tmp_width);
773 regs->SHEIGHT = params->src_h;
774 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
775 regs->OSTRIDE = params->stride_Y;
776
777 if (params->format & I915_OVERLAY_YUV_PLANAR) {
778 int uv_hscale = uv_hsubsampling(params->format);
779 int uv_vscale = uv_vsubsampling(params->format);
780 u32 tmp_U, tmp_V;
781 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
782 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
783 params->src_w/uv_hscale);
784 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
785 params->src_w/uv_hscale);
786 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
787 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
788 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
789 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
790 regs->OSTRIDE |= params->stride_UV << 16;
791 }
792
793 scale_changed = update_scaling_factors(overlay, regs, params);
794
795 update_colorkey(overlay, regs);
796
797 regs->OCMD = overlay_cmd_reg(params);
798
799 intel_overlay_unmap_regs_atomic(overlay);
800
801 intel_overlay_continue(overlay, scale_changed);
802
803 overlay->old_vid_bo = overlay->vid_bo;
23010e43 804 overlay->vid_bo = to_intel_bo(new_bo);
02e792fb
DV		 805
806 return 0;
807
808out_unpin:
809 i915_gem_object_unpin(new_bo);
810 return ret;
811}
812
813int intel_overlay_switch_off(struct intel_overlay *overlay)
814{
815 int ret;
816 struct overlay_registers *regs;
02e792fb
DV		 817 struct drm_device *dev = overlay->dev;
818
819 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
820 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
821
9bedb974
DV		 822 if (overlay->hw_wedged) {
823 ret = intel_overlay_recover_from_interrupt(overlay, 1);
824 if (ret != 0)
825 return ret;
826 }
827
02e792fb
DV		 828 if (!overlay->active)
829 return 0;
830
02e792fb
DV		 831 ret = intel_overlay_release_old_vid(overlay);
832 if (ret != 0)
833 return ret;
834
835 regs = intel_overlay_map_regs_atomic(overlay);
836 regs->OCMD = 0;
837 intel_overlay_unmap_regs_atomic(overlay);
838
839 ret = intel_overlay_off(overlay);
03f77ea5
DV		 840 if (ret != 0)
841 return ret;
842
12ca45fe 843 intel_overlay_off_tail(overlay);
02e792fb
DV		 844
845 return 0;
846}
847
848static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
849 struct intel_crtc *crtc)
850{
851 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
852 u32 pipeconf;
853 int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
854
855 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
856 return -EINVAL;
857
858 pipeconf = I915_READ(pipeconf_reg);
859
860 /* can't use the overlay with double wide pipe */
861 if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
862 return -EINVAL;
863
864 return 0;
865}
866
867static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
868{
869 struct drm_device *dev = overlay->dev;
870 drm_i915_private_t *dev_priv = dev->dev_private;
871 u32 ratio;
872 u32 pfit_control = I915_READ(PFIT_CONTROL);
873
874 /* XXX: This is not the same logic as in the xorg driver, but more in
875 * line with the intel documentation for the i965 */
876 if (!IS_I965G(dev) && (pfit_control & VERT_AUTO_SCALE)) {
877 ratio = I915_READ(PFIT_AUTO_RATIOS) >> PFIT_VERT_SCALE_SHIFT;
878 } else { /* on i965 use the PGM reg to read out the autoscaler values */
879 ratio = I915_READ(PFIT_PGM_RATIOS);
880 if (IS_I965G(dev))
881 ratio >>= PFIT_VERT_SCALE_SHIFT_965;
882 else
883 ratio >>= PFIT_VERT_SCALE_SHIFT;
884 }
885
886 overlay->pfit_vscale_ratio = ratio;
887}
888
889static int check_overlay_dst(struct intel_overlay *overlay,
890 struct drm_intel_overlay_put_image *rec)
891{
892 struct drm_display_mode *mode = &overlay->crtc->base.mode;
893
894 if ((rec->dst_x < mode->crtc_hdisplay)
895 && (rec->dst_x + rec->dst_width
896 <= mode->crtc_hdisplay)
897 && (rec->dst_y < mode->crtc_vdisplay)
898 && (rec->dst_y + rec->dst_height
899 <= mode->crtc_vdisplay))
900 return 0;
901 else
902 return -EINVAL;
903}
904
905static int check_overlay_scaling(struct put_image_params *rec)
906{
907 u32 tmp;
908
909 /* downscaling limit is 8.0 */
910 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
911 if (tmp > 7)
912 return -EINVAL;
913 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
914 if (tmp > 7)
915 return -EINVAL;
916
917 return 0;
918}
919
920static int check_overlay_src(struct drm_device *dev,
921 struct drm_intel_overlay_put_image *rec,
922 struct drm_gem_object *new_bo)
923{
924 u32 stride_mask;
925 int depth;
926 int uv_hscale = uv_hsubsampling(rec->flags);
927 int uv_vscale = uv_vsubsampling(rec->flags);
928 size_t tmp;
929
930 /* check src dimensions */
931 if (IS_845G(dev) || IS_I830(dev)) {
932 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY
933 || rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
934 return -EINVAL;
935 } else {
936 if (rec->src_height > IMAGE_MAX_HEIGHT
937 || rec->src_width > IMAGE_MAX_WIDTH)
938 return -EINVAL;
939 }
940 /* better safe than sorry, use 4 as the maximal subsampling ratio */
941 if (rec->src_height < N_VERT_Y_TAPS*4
942 || rec->src_width < N_HORIZ_Y_TAPS*4)
943 return -EINVAL;
944
945 /* check alingment constrains */
946 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
947 case I915_OVERLAY_RGB:
948 /* not implemented */
949 return -EINVAL;
950 case I915_OVERLAY_YUV_PACKED:
951 depth = packed_depth_bytes(rec->flags);
952 if (uv_vscale != 1)
953 return -EINVAL;
954 if (depth < 0)
955 return depth;
956 /* ignore UV planes */
957 rec->stride_UV = 0;
958 rec->offset_U = 0;
959 rec->offset_V = 0;
960 /* check pixel alignment */
961 if (rec->offset_Y % depth)
962 return -EINVAL;
963 break;
964 case I915_OVERLAY_YUV_PLANAR:
965 if (uv_vscale < 0 || uv_hscale < 0)
966 return -EINVAL;
967 /* no offset restrictions for planar formats */
968 break;
969 default:
970 return -EINVAL;
971 }
972
973 if (rec->src_width % uv_hscale)
974 return -EINVAL;
975
976 /* stride checking */
977 stride_mask = 63;
978
979 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
980 return -EINVAL;
981 if (IS_I965G(dev) && rec->stride_Y < 512)
982 return -EINVAL;
983
984 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
985 4 : 8;
986 if (rec->stride_Y > tmp*1024 || rec->stride_UV > 2*1024)
987 return -EINVAL;
988
989 /* check buffer dimensions */
990 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
991 case I915_OVERLAY_RGB:
992 case I915_OVERLAY_YUV_PACKED:
993 /* always 4 Y values per depth pixels */
994 if (packed_width_bytes(rec->flags, rec->src_width)
995 > rec->stride_Y)
996 return -EINVAL;
997
998 tmp = rec->stride_Y*rec->src_height;
999 if (rec->offset_Y + tmp > new_bo->size)
1000 return -EINVAL;
1001 break;
1002 case I915_OVERLAY_YUV_PLANAR:
1003 if (rec->src_width > rec->stride_Y)
1004 return -EINVAL;
1005 if (rec->src_width/uv_hscale > rec->stride_UV)
1006 return -EINVAL;
1007
1008 tmp = rec->stride_Y*rec->src_height;
1009 if (rec->offset_Y + tmp > new_bo->size)
1010 return -EINVAL;
1011 tmp = rec->stride_UV*rec->src_height;
1012 tmp /= uv_vscale;
1013 if (rec->offset_U + tmp > new_bo->size
1014 || rec->offset_V + tmp > new_bo->size)
1015 return -EINVAL;
1016 break;
1017 }
1018
1019 return 0;
1020}
1021
1022int intel_overlay_put_image(struct drm_device *dev, void *data,
1023 struct drm_file *file_priv)
1024{
1025 struct drm_intel_overlay_put_image *put_image_rec = data;
1026 drm_i915_private_t *dev_priv = dev->dev_private;
1027 struct intel_overlay *overlay;
1028 struct drm_mode_object *drmmode_obj;
1029 struct intel_crtc *crtc;
1030 struct drm_gem_object *new_bo;
1031 struct put_image_params *params;
1032 int ret;
1033
1034 if (!dev_priv) {
1035 DRM_ERROR("called with no initialization\n");
1036 return -EINVAL;
1037 }
1038
1039 overlay = dev_priv->overlay;
1040 if (!overlay) {
1041 DRM_DEBUG("userspace bug: no overlay\n");
1042 return -ENODEV;
1043 }
1044
1045 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1046 mutex_lock(&dev->mode_config.mutex);
1047 mutex_lock(&dev->struct_mutex);
1048
1049 ret = intel_overlay_switch_off(overlay);
1050
1051 mutex_unlock(&dev->struct_mutex);
1052 mutex_unlock(&dev->mode_config.mutex);
1053
1054 return ret;
1055 }
1056
1057 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1058 if (!params)
1059 return -ENOMEM;
1060
1061 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1062 DRM_MODE_OBJECT_CRTC);
915a428e
DC		 1063 if (!drmmode_obj) {
1064 ret = -ENOENT;
1065 goto out_free;
1066 }
02e792fb
DV		 1067 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1068
1069 new_bo = drm_gem_object_lookup(dev, file_priv,
1070 put_image_rec->bo_handle);
915a428e
DC		 1071 if (!new_bo) {
1072 ret = -ENOENT;
1073 goto out_free;
1074 }
02e792fb
DV		 1075
1076 mutex_lock(&dev->mode_config.mutex);
1077 mutex_lock(&dev->struct_mutex);
1078
03f77ea5
DV		 1079 if (overlay->hw_wedged) {
1080 ret = intel_overlay_recover_from_interrupt(overlay, 1);
1081 if (ret != 0)
1082 goto out_unlock;
1083 }
1084
02e792fb
DV		 1085 if (overlay->crtc != crtc) {
1086 struct drm_display_mode *mode = &crtc->base.mode;
1087 ret = intel_overlay_switch_off(overlay);
1088 if (ret != 0)
1089 goto out_unlock;
1090
1091 ret = check_overlay_possible_on_crtc(overlay, crtc);
1092 if (ret != 0)
1093 goto out_unlock;
1094
1095 overlay->crtc = crtc;
1096 crtc->overlay = overlay;
1097
1098 if (intel_panel_fitter_pipe(dev) == crtc->pipe
1099 /* and line to wide, i.e. one-line-mode */
1100 && mode->hdisplay > 1024) {
1101 overlay->pfit_active = 1;
1102 update_pfit_vscale_ratio(overlay);
1103 } else
1104 overlay->pfit_active = 0;
1105 }
1106
1107 ret = check_overlay_dst(overlay, put_image_rec);
1108 if (ret != 0)
1109 goto out_unlock;
1110
1111 if (overlay->pfit_active) {
1112 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1113 overlay->pfit_vscale_ratio);
1114 /* shifting right rounds downwards, so add 1 */
1115 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1116 overlay->pfit_vscale_ratio) + 1;
1117 } else {
1118 params->dst_y = put_image_rec->dst_y;
1119 params->dst_h = put_image_rec->dst_height;
1120 }
1121 params->dst_x = put_image_rec->dst_x;
1122 params->dst_w = put_image_rec->dst_width;
1123
1124 params->src_w = put_image_rec->src_width;
1125 params->src_h = put_image_rec->src_height;
1126 params->src_scan_w = put_image_rec->src_scan_width;
1127 params->src_scan_h = put_image_rec->src_scan_height;
1128 if (params->src_scan_h > params->src_h
1129 || params->src_scan_w > params->src_w) {
1130 ret = -EINVAL;
1131 goto out_unlock;
1132 }
1133
1134 ret = check_overlay_src(dev, put_image_rec, new_bo);
1135 if (ret != 0)
1136 goto out_unlock;
1137 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1138 params->stride_Y = put_image_rec->stride_Y;
1139 params->stride_UV = put_image_rec->stride_UV;
1140 params->offset_Y = put_image_rec->offset_Y;
1141 params->offset_U = put_image_rec->offset_U;
1142 params->offset_V = put_image_rec->offset_V;
1143
1144 /* Check scaling after src size to prevent a divide-by-zero. */
1145 ret = check_overlay_scaling(params);
1146 if (ret != 0)
1147 goto out_unlock;
1148
1149 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1150 if (ret != 0)
1151 goto out_unlock;
1152
1153 mutex_unlock(&dev->struct_mutex);
1154 mutex_unlock(&dev->mode_config.mutex);
1155
1156 kfree(params);
1157
1158 return 0;
1159
1160out_unlock:
1161 mutex_unlock(&dev->struct_mutex);
1162 mutex_unlock(&dev->mode_config.mutex);
bc9025bd 1163 drm_gem_object_unreference_unlocked(new_bo);
915a428e 1164out_free:
02e792fb
DV		 1165 kfree(params);
1166
1167 return ret;
1168}
1169
1170static void update_reg_attrs(struct intel_overlay *overlay,
1171 struct overlay_registers *regs)
1172{
1173 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1174 regs->OCLRC1 = overlay->saturation;
1175}
1176
1177static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1178{
1179 int i;
1180
1181 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1182 return false;
1183
1184 for (i = 0; i < 3; i++) {
1185 if (((gamma1 >> i * 8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1186 return false;
1187 }
1188
1189 return true;
1190}
1191
1192static bool check_gamma5_errata(u32 gamma5)
1193{
1194 int i;
1195
1196 for (i = 0; i < 3; i++) {
1197 if (((gamma5 >> i*8) & 0xff) == 0x80)
1198 return false;
1199 }
1200
1201 return true;
1202}
1203
1204static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1205{
1206 if (!check_gamma_bounds(0, attrs->gamma0)
1207 || !check_gamma_bounds(attrs->gamma0, attrs->gamma1)
1208 || !check_gamma_bounds(attrs->gamma1, attrs->gamma2)
1209 || !check_gamma_bounds(attrs->gamma2, attrs->gamma3)
1210 || !check_gamma_bounds(attrs->gamma3, attrs->gamma4)
1211 || !check_gamma_bounds(attrs->gamma4, attrs->gamma5)
1212 || !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1213 return -EINVAL;
1214 if (!check_gamma5_errata(attrs->gamma5))
1215 return -EINVAL;
1216 return 0;
1217}
1218
1219int intel_overlay_attrs(struct drm_device *dev, void *data,
1220 struct drm_file *file_priv)
1221{
1222 struct drm_intel_overlay_attrs *attrs = data;
1223 drm_i915_private_t *dev_priv = dev->dev_private;
1224 struct intel_overlay *overlay;
1225 struct overlay_registers *regs;
1226 int ret;
1227
1228 if (!dev_priv) {
1229 DRM_ERROR("called with no initialization\n");
1230 return -EINVAL;
1231 }
1232
1233 overlay = dev_priv->overlay;
1234 if (!overlay) {
1235 DRM_DEBUG("userspace bug: no overlay\n");
1236 return -ENODEV;
1237 }
1238
1239 mutex_lock(&dev->mode_config.mutex);
1240 mutex_lock(&dev->struct_mutex);
1241
1242 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1243 attrs->color_key = overlay->color_key;
1244 attrs->brightness = overlay->brightness;
1245 attrs->contrast = overlay->contrast;
1246 attrs->saturation = overlay->saturation;
1247
1248 if (IS_I9XX(dev)) {
1249 attrs->gamma0 = I915_READ(OGAMC0);
1250 attrs->gamma1 = I915_READ(OGAMC1);
1251 attrs->gamma2 = I915_READ(OGAMC2);
1252 attrs->gamma3 = I915_READ(OGAMC3);
1253 attrs->gamma4 = I915_READ(OGAMC4);
1254 attrs->gamma5 = I915_READ(OGAMC5);
1255 }
1256 ret = 0;
1257 } else {
1258 overlay->color_key = attrs->color_key;
1259 if (attrs->brightness >= -128 && attrs->brightness <= 127) {
1260 overlay->brightness = attrs->brightness;
1261 } else {
1262 ret = -EINVAL;
1263 goto out_unlock;
1264 }
1265 if (attrs->contrast <= 255) {
1266 overlay->contrast = attrs->contrast;
1267 } else {
1268 ret = -EINVAL;
1269 goto out_unlock;
1270 }
1271 if (attrs->saturation <= 1023) {
1272 overlay->saturation = attrs->saturation;
1273 } else {
1274 ret = -EINVAL;
1275 goto out_unlock;
1276 }
1277
1278 regs = intel_overlay_map_regs_atomic(overlay);
1279 if (!regs) {
1280 ret = -ENOMEM;
1281 goto out_unlock;
1282 }
1283
1284 update_reg_attrs(overlay, regs);
1285
1286 intel_overlay_unmap_regs_atomic(overlay);
1287
1288 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1289 if (!IS_I9XX(dev)) {
1290 ret = -EINVAL;
1291 goto out_unlock;
1292 }
1293
1294 if (overlay->active) {
1295 ret = -EBUSY;
1296 goto out_unlock;
1297 }
1298
1299 ret = check_gamma(attrs);
1300 if (ret != 0)
1301 goto out_unlock;
1302
1303 I915_WRITE(OGAMC0, attrs->gamma0);
1304 I915_WRITE(OGAMC1, attrs->gamma1);
1305 I915_WRITE(OGAMC2, attrs->gamma2);
1306 I915_WRITE(OGAMC3, attrs->gamma3);
1307 I915_WRITE(OGAMC4, attrs->gamma4);
1308 I915_WRITE(OGAMC5, attrs->gamma5);
1309 }
1310 ret = 0;
1311 }
1312
1313out_unlock:
1314 mutex_unlock(&dev->struct_mutex);
1315 mutex_unlock(&dev->mode_config.mutex);
1316
1317 return ret;
1318}
1319
1320void intel_setup_overlay(struct drm_device *dev)
1321{
1322 drm_i915_private_t *dev_priv = dev->dev_private;
1323 struct intel_overlay *overlay;
1324 struct drm_gem_object *reg_bo;
1325 struct overlay_registers *regs;
1326 int ret;
1327
1328 if (!OVERLAY_EXISTS(dev))
1329 return;
1330
1331 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1332 if (!overlay)
1333 return;
1334 overlay->dev = dev;
1335
ac52bc56 1336 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
02e792fb
DV		 1337 if (!reg_bo)
1338 goto out_free;
23010e43 1339 overlay->reg_bo = to_intel_bo(reg_bo);
02e792fb
DV		 1340
1341 if (OVERLAY_NONPHYSICAL(dev)) {
1342 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1343 if (ret) {
1344 DRM_ERROR("failed to pin overlay register bo\n");
1345 goto out_free_bo;
1346 }
1347 overlay->flip_addr = overlay->reg_bo->gtt_offset;
1348 } else {
1349 ret = i915_gem_attach_phys_object(dev, reg_bo,
1350 I915_GEM_PHYS_OVERLAY_REGS);
1351 if (ret) {
1352 DRM_ERROR("failed to attach phys overlay regs\n");
1353 goto out_free_bo;
1354 }
1355 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1356 }
1357
1358 /* init all values */
1359 overlay->color_key = 0x0101fe;
1360 overlay->brightness = -19;
1361 overlay->contrast = 75;
1362 overlay->saturation = 146;
1363
1364 regs = intel_overlay_map_regs_atomic(overlay);
1365 if (!regs)
1366 goto out_free_bo;
1367
1368 memset(regs, 0, sizeof(struct overlay_registers));
1369 update_polyphase_filter(regs);
1370
1371 update_reg_attrs(overlay, regs);
1372
1373 intel_overlay_unmap_regs_atomic(overlay);
1374
1375 dev_priv->overlay = overlay;
1376 DRM_INFO("initialized overlay support\n");
1377 return;
1378
1379out_free_bo:
1380 drm_gem_object_unreference(reg_bo);
1381out_free:
1382 kfree(overlay);
1383 return;
1384}
1385
1386void intel_cleanup_overlay(struct drm_device *dev)
1387{
1388 drm_i915_private_t *dev_priv = dev->dev_private;
1389
1390 if (dev_priv->overlay) {
1391 /* The bo's should be free'd by the generic code already.
1392 * Furthermore modesetting teardown happens beforehand so the
1393 * hardware should be off already */
1394 BUG_ON(dev_priv->overlay->active);
1395
1396 kfree(dev_priv->overlay);
1397 }
1398}
Clone of davem's net-next-2.6 tree