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i915: fix ironlake edp panel setup (v4)
[net-next-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
a4fc5ed6
KP		 30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "drm_crtc_helper.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
ab2c0672 37#include "drm_dp_helper.h"
a4fc5ed6 38
ae266c98 39
a4fc5ed6
KP		 40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43#define DP_LINK_CONFIGURATION_SIZE 9
44
32f9d658
ZW		 45#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
46
a4fc5ed6
KP		 47struct intel_dp_priv {
48 uint32_t output_reg;
49 uint32_t DP;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 51 bool has_audio;
c8110e52 52 int dpms_mode;
a4fc5ed6
KP		 53 uint8_t link_bw;
54 uint8_t lane_count;
55 uint8_t dpcd[4];
21d40d37 56 struct intel_encoder *intel_encoder;
a4fc5ed6
KP		 57 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo;
59};
60
61static void
21d40d37 62intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
a4fc5ed6
KP		 63 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
64
65static void
21d40d37 66intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
a4fc5ed6 67
32f9d658 68void
21d40d37 69intel_edp_link_config (struct intel_encoder *intel_encoder,
32f9d658
ZW		 70 int *lane_num, int *link_bw)
71{
21d40d37 72 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
32f9d658
ZW		 73
74 *lane_num = dp_priv->lane_count;
75 if (dp_priv->link_bw == DP_LINK_BW_1_62)
76 *link_bw = 162000;
77 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
78 *link_bw = 270000;
79}
80
a4fc5ed6 81static int
21d40d37 82intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
a4fc5ed6 83{
21d40d37 84 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 85 int max_lane_count = 4;
86
87 if (dp_priv->dpcd[0] >= 0x11) {
88 max_lane_count = dp_priv->dpcd[2] & 0x1f;
89 switch (max_lane_count) {
90 case 1: case 2: case 4:
91 break;
92 default:
93 max_lane_count = 4;
94 }
95 }
96 return max_lane_count;
97}
98
99static int
21d40d37 100intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
a4fc5ed6 101{
21d40d37 102 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 103 int max_link_bw = dp_priv->dpcd[1];
104
105 switch (max_link_bw) {
106 case DP_LINK_BW_1_62:
107 case DP_LINK_BW_2_7:
108 break;
109 default:
110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
116static int
117intel_dp_link_clock(uint8_t link_bw)
118{
119 if (link_bw == DP_LINK_BW_2_7)
120 return 270000;
121 else
122 return 162000;
123}
124
125/* I think this is a fiction */
126static int
885a5fb5 127intel_dp_link_required(struct drm_device *dev,
21d40d37 128 struct intel_encoder *intel_encoder, int pixel_clock)
a4fc5ed6 129{
885a5fb5
ZW		 130 struct drm_i915_private *dev_priv = dev->dev_private;
131
21d40d37 132 if (IS_eDP(intel_encoder))
885a5fb5
ZW		 133 return (pixel_clock * dev_priv->edp_bpp) / 8;
134 else
135 return pixel_clock * 3;
a4fc5ed6
KP		 136}
137
fe27d53e
DA		 138static int
139intel_dp_max_data_rate(int max_link_clock, int max_lanes)
140{
141 return (max_link_clock * max_lanes * 8) / 10;
142}
143
a4fc5ed6
KP		 144static int
145intel_dp_mode_valid(struct drm_connector *connector,
146 struct drm_display_mode *mode)
147{
55f78c43
ZW		 148 struct drm_encoder *encoder = intel_attached_encoder(connector);
149 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
21d40d37
EA		 150 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
151 int max_lanes = intel_dp_max_lane_count(intel_encoder);
a4fc5ed6 152
fe27d53e
DA		 153 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
154 which are outside spec tolerances but somehow work by magic */
155 if (!IS_eDP(intel_encoder) &&
156 (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
157 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
a4fc5ed6
KP		 158 return MODE_CLOCK_HIGH;
159
160 if (mode->clock < 10000)
161 return MODE_CLOCK_LOW;
162
163 return MODE_OK;
164}
165
166static uint32_t
167pack_aux(uint8_t *src, int src_bytes)
168{
169 int i;
170 uint32_t v = 0;
171
172 if (src_bytes > 4)
173 src_bytes = 4;
174 for (i = 0; i < src_bytes; i++)
175 v |= ((uint32_t) src[i]) << ((3-i) * 8);
176 return v;
177}
178
179static void
180unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
181{
182 int i;
183 if (dst_bytes > 4)
184 dst_bytes = 4;
185 for (i = 0; i < dst_bytes; i++)
186 dst[i] = src >> ((3-i) * 8);
187}
188
fb0f8fbf
KP		 189/* hrawclock is 1/4 the FSB frequency */
190static int
191intel_hrawclk(struct drm_device *dev)
192{
193 struct drm_i915_private *dev_priv = dev->dev_private;
194 uint32_t clkcfg;
195
196 clkcfg = I915_READ(CLKCFG);
197 switch (clkcfg & CLKCFG_FSB_MASK) {
198 case CLKCFG_FSB_400:
199 return 100;
200 case CLKCFG_FSB_533:
201 return 133;
202 case CLKCFG_FSB_667:
203 return 166;
204 case CLKCFG_FSB_800:
205 return 200;
206 case CLKCFG_FSB_1067:
207 return 266;
208 case CLKCFG_FSB_1333:
209 return 333;
210 /* these two are just a guess; one of them might be right */
211 case CLKCFG_FSB_1600:
212 case CLKCFG_FSB_1600_ALT:
213 return 400;
214 default:
215 return 133;
216 }
217}
218
a4fc5ed6 219static int
21d40d37 220intel_dp_aux_ch(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 221 uint8_t *send, int send_bytes,
222 uint8_t *recv, int recv_size)
223{
21d40d37 224 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 225 uint32_t output_reg = dp_priv->output_reg;
55f78c43 226 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6
KP		 227 struct drm_i915_private *dev_priv = dev->dev_private;
228 uint32_t ch_ctl = output_reg + 0x10;
229 uint32_t ch_data = ch_ctl + 4;
230 int i;
231 int recv_bytes;
232 uint32_t ctl;
233 uint32_t status;
fb0f8fbf 234 uint32_t aux_clock_divider;
e3421a18 235 int try, precharge;
a4fc5ed6
KP		 236
237 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 238 * and would like to run at 2MHz. So, take the
239 * hrawclk value and divide by 2 and use that
a4fc5ed6 240 */
e3421a18
ZW		 241 if (IS_eDP(intel_encoder)) {
242 if (IS_GEN6(dev))
243 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
244 else
245 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
246 } else if (HAS_PCH_SPLIT(dev))
f2b115e6 247 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 248 else
249 aux_clock_divider = intel_hrawclk(dev) / 2;
250
e3421a18
ZW		 251 if (IS_GEN6(dev))
252 precharge = 3;
253 else
254 precharge = 5;
255
fb0f8fbf
KP		 256 /* Must try at least 3 times according to DP spec */
257 for (try = 0; try < 5; try++) {
258 /* Load the send data into the aux channel data registers */
259 for (i = 0; i < send_bytes; i += 4) {
a419aef8 260 uint32_t d = pack_aux(send + i, send_bytes - i);
fb0f8fbf
KP		 261
262 I915_WRITE(ch_data + i, d);
263 }
264
265 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
266 DP_AUX_CH_CTL_TIME_OUT_400us |
267 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
e3421a18 268 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
fb0f8fbf
KP		 269 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
270 DP_AUX_CH_CTL_DONE |
271 DP_AUX_CH_CTL_TIME_OUT_ERROR |
272 DP_AUX_CH_CTL_RECEIVE_ERROR);
273
274 /* Send the command and wait for it to complete */
275 I915_WRITE(ch_ctl, ctl);
276 (void) I915_READ(ch_ctl);
277 for (;;) {
278 udelay(100);
279 status = I915_READ(ch_ctl);
280 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
281 break;
282 }
283
284 /* Clear done status and any errors */
eebc863e 285 I915_WRITE(ch_ctl, (status |
fb0f8fbf
KP		 286 DP_AUX_CH_CTL_DONE |
287 DP_AUX_CH_CTL_TIME_OUT_ERROR |
288 DP_AUX_CH_CTL_RECEIVE_ERROR));
289 (void) I915_READ(ch_ctl);
290 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 291 break;
292 }
293
a4fc5ed6 294 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 295 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 296 return -EBUSY;
a4fc5ed6
KP		 297 }
298
299 /* Check for timeout or receive error.
300 * Timeouts occur when the sink is not connected
301 */
a5b3da54 302 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 303 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 304 return -EIO;
305 }
1ae8c0a5
KP		 306
307 /* Timeouts occur when the device isn't connected, so they're
308 * "normal" -- don't fill the kernel log with these */
a5b3da54 309 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 310 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 311 return -ETIMEDOUT;
a4fc5ed6
KP		 312 }
313
314 /* Unload any bytes sent back from the other side */
315 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
316 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
317
318 if (recv_bytes > recv_size)
319 recv_bytes = recv_size;
320
321 for (i = 0; i < recv_bytes; i += 4) {
322 uint32_t d = I915_READ(ch_data + i);
323
324 unpack_aux(d, recv + i, recv_bytes - i);
325 }
326
327 return recv_bytes;
328}
329
330/* Write data to the aux channel in native mode */
331static int
21d40d37 332intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 333 uint16_t address, uint8_t *send, int send_bytes)
334{
335 int ret;
336 uint8_t msg[20];
337 int msg_bytes;
338 uint8_t ack;
339
340 if (send_bytes > 16)
341 return -1;
342 msg[0] = AUX_NATIVE_WRITE << 4;
343 msg[1] = address >> 8;
eebc863e 344 msg[2] = address & 0xff;
a4fc5ed6
KP		 345 msg[3] = send_bytes - 1;
346 memcpy(&msg[4], send, send_bytes);
347 msg_bytes = send_bytes + 4;
348 for (;;) {
21d40d37 349 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 350 if (ret < 0)
351 return ret;
352 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
353 break;
354 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
355 udelay(100);
356 else
a5b3da54 357 return -EIO;
a4fc5ed6
KP		 358 }
359 return send_bytes;
360}
361
362/* Write a single byte to the aux channel in native mode */
363static int
21d40d37 364intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 365 uint16_t address, uint8_t byte)
366{
21d40d37 367 return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
a4fc5ed6
KP		 368}
369
370/* read bytes from a native aux channel */
371static int
21d40d37 372intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 373 uint16_t address, uint8_t *recv, int recv_bytes)
374{
375 uint8_t msg[4];
376 int msg_bytes;
377 uint8_t reply[20];
378 int reply_bytes;
379 uint8_t ack;
380 int ret;
381
382 msg[0] = AUX_NATIVE_READ << 4;
383 msg[1] = address >> 8;
384 msg[2] = address & 0xff;
385 msg[3] = recv_bytes - 1;
386
387 msg_bytes = 4;
388 reply_bytes = recv_bytes + 1;
389
390 for (;;) {
21d40d37 391 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
a4fc5ed6 392 reply, reply_bytes);
a5b3da54
KP		 393 if (ret == 0)
394 return -EPROTO;
395 if (ret < 0)
a4fc5ed6
KP		 396 return ret;
397 ack = reply[0];
398 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
399 memcpy(recv, reply + 1, ret - 1);
400 return ret - 1;
401 }
402 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
403 udelay(100);
404 else
a5b3da54 405 return -EIO;
a4fc5ed6
KP		 406 }
407}
408
409static int
ab2c0672
DA		 410intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
411 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 412{
ab2c0672 413 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
a4fc5ed6
KP		 414 struct intel_dp_priv *dp_priv = container_of(adapter,
415 struct intel_dp_priv,
416 adapter);
21d40d37 417 struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
ab2c0672
DA		 418 uint16_t address = algo_data->address;
419 uint8_t msg[5];
420 uint8_t reply[2];
421 int msg_bytes;
422 int reply_bytes;
423 int ret;
424
425 /* Set up the command byte */
426 if (mode & MODE_I2C_READ)
427 msg[0] = AUX_I2C_READ << 4;
428 else
429 msg[0] = AUX_I2C_WRITE << 4;
430
431 if (!(mode & MODE_I2C_STOP))
432 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 433
ab2c0672
DA		 434 msg[1] = address >> 8;
435 msg[2] = address;
436
437 switch (mode) {
438 case MODE_I2C_WRITE:
439 msg[3] = 0;
440 msg[4] = write_byte;
441 msg_bytes = 5;
442 reply_bytes = 1;
443 break;
444 case MODE_I2C_READ:
445 msg[3] = 0;
446 msg_bytes = 4;
447 reply_bytes = 2;
448 break;
449 default:
450 msg_bytes = 3;
451 reply_bytes = 1;
452 break;
453 }
454
455 for (;;) {
21d40d37 456 ret = intel_dp_aux_ch(intel_encoder,
ab2c0672
DA		 457 msg, msg_bytes,
458 reply, reply_bytes);
459 if (ret < 0) {
3ff99164 460 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 461 return ret;
462 }
463 switch (reply[0] & AUX_I2C_REPLY_MASK) {
464 case AUX_I2C_REPLY_ACK:
465 if (mode == MODE_I2C_READ) {
466 *read_byte = reply[1];
467 }
468 return reply_bytes - 1;
469 case AUX_I2C_REPLY_NACK:
3ff99164 470 DRM_DEBUG_KMS("aux_ch nack\n");
ab2c0672
DA		 471 return -EREMOTEIO;
472 case AUX_I2C_REPLY_DEFER:
3ff99164 473 DRM_DEBUG_KMS("aux_ch defer\n");
ab2c0672
DA		 474 udelay(100);
475 break;
476 default:
477 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
478 return -EREMOTEIO;
479 }
480 }
a4fc5ed6
KP		 481}
482
483static int
55f78c43
ZW		 484intel_dp_i2c_init(struct intel_encoder *intel_encoder,
485 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 486{
21d40d37 487 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 488
d54e9d28 489 DRM_DEBUG_KMS("i2c_init %s\n", name);
a4fc5ed6
KP		 490 dp_priv->algo.running = false;
491 dp_priv->algo.address = 0;
492 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
493
494 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
495 dp_priv->adapter.owner = THIS_MODULE;
496 dp_priv->adapter.class = I2C_CLASS_DDC;
eebc863e
ZW		 497 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
498 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
a4fc5ed6 499 dp_priv->adapter.algo_data = &dp_priv->algo;
55f78c43 500 dp_priv->adapter.dev.parent = &intel_connector->base.kdev;
a4fc5ed6
KP		 501
502 return i2c_dp_aux_add_bus(&dp_priv->adapter);
503}
504
505static bool
506intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
507 struct drm_display_mode *adjusted_mode)
508{
21d40d37
EA		 509 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
510 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 511 int lane_count, clock;
21d40d37
EA		 512 int max_lane_count = intel_dp_max_lane_count(intel_encoder);
513 int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
a4fc5ed6
KP		 514 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
515
516 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
517 for (clock = 0; clock <= max_clock; clock++) {
fe27d53e 518 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 519
21d40d37 520 if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
885a5fb5 521 <= link_avail) {
a4fc5ed6
KP		 522 dp_priv->link_bw = bws[clock];
523 dp_priv->lane_count = lane_count;
524 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
28c97730
ZY		 525 DRM_DEBUG_KMS("Display port link bw %02x lane "
526 "count %d clock %d\n",
a4fc5ed6
KP		 527 dp_priv->link_bw, dp_priv->lane_count,
528 adjusted_mode->clock);
529 return true;
530 }
531 }
532 }
fe27d53e
DA		 533
534 if (IS_eDP(intel_encoder)) {
535 /* okay we failed just pick the highest */
536 dp_priv->lane_count = max_lane_count;
537 dp_priv->link_bw = bws[max_clock];
538 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
539 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
540 "count %d clock %d\n",
541 dp_priv->link_bw, dp_priv->lane_count,
542 adjusted_mode->clock);
543 return true;
544 }
a4fc5ed6
KP		 545 return false;
546}
547
548struct intel_dp_m_n {
549 uint32_t tu;
550 uint32_t gmch_m;
551 uint32_t gmch_n;
552 uint32_t link_m;
553 uint32_t link_n;
554};
555
556static void
557intel_reduce_ratio(uint32_t *num, uint32_t *den)
558{
559 while (*num > 0xffffff || *den > 0xffffff) {
560 *num >>= 1;
561 *den >>= 1;
562 }
563}
564
565static void
566intel_dp_compute_m_n(int bytes_per_pixel,
567 int nlanes,
568 int pixel_clock,
569 int link_clock,
570 struct intel_dp_m_n *m_n)
571{
572 m_n->tu = 64;
573 m_n->gmch_m = pixel_clock * bytes_per_pixel;
574 m_n->gmch_n = link_clock * nlanes;
575 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
576 m_n->link_m = pixel_clock;
577 m_n->link_n = link_clock;
578 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
579}
580
581void
582intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
583 struct drm_display_mode *adjusted_mode)
584{
585 struct drm_device *dev = crtc->dev;
586 struct drm_mode_config *mode_config = &dev->mode_config;
55f78c43 587 struct drm_encoder *encoder;
a4fc5ed6
KP		 588 struct drm_i915_private *dev_priv = dev->dev_private;
589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
590 int lane_count = 4;
591 struct intel_dp_m_n m_n;
592
593 /*
21d40d37 594 * Find the lane count in the intel_encoder private
a4fc5ed6 595 */
55f78c43
ZW		 596 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
597 struct intel_encoder *intel_encoder;
598 struct intel_dp_priv *dp_priv;
a4fc5ed6 599
d8201ab6 600 if (encoder->crtc != crtc)
a4fc5ed6
KP		 601 continue;
602
55f78c43
ZW		 603 intel_encoder = enc_to_intel_encoder(encoder);
604 dp_priv = intel_encoder->dev_priv;
605
21d40d37 606 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
a4fc5ed6
KP		 607 lane_count = dp_priv->lane_count;
608 break;
609 }
610 }
611
612 /*
613 * Compute the GMCH and Link ratios. The '3' here is
614 * the number of bytes_per_pixel post-LUT, which we always
615 * set up for 8-bits of R/G/B, or 3 bytes total.
616 */
617 intel_dp_compute_m_n(3, lane_count,
618 mode->clock, adjusted_mode->clock, &m_n);
619
c619eed4 620 if (HAS_PCH_SPLIT(dev)) {
5eb08b69
ZW		 621 if (intel_crtc->pipe == 0) {
622 I915_WRITE(TRANSA_DATA_M1,
623 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
624 m_n.gmch_m);
625 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
626 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
627 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
628 } else {
629 I915_WRITE(TRANSB_DATA_M1,
630 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
631 m_n.gmch_m);
632 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
633 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
634 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
635 }
a4fc5ed6 636 } else {
5eb08b69
ZW		 637 if (intel_crtc->pipe == 0) {
638 I915_WRITE(PIPEA_GMCH_DATA_M,
639 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
640 m_n.gmch_m);
641 I915_WRITE(PIPEA_GMCH_DATA_N,
642 m_n.gmch_n);
643 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
644 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
645 } else {
646 I915_WRITE(PIPEB_GMCH_DATA_M,
647 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
648 m_n.gmch_m);
649 I915_WRITE(PIPEB_GMCH_DATA_N,
650 m_n.gmch_n);
651 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
652 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
653 }
a4fc5ed6
KP		 654 }
655}
656
657static void
658intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
659 struct drm_display_mode *adjusted_mode)
660{
e3421a18 661 struct drm_device *dev = encoder->dev;
21d40d37
EA		 662 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
663 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
664 struct drm_crtc *crtc = intel_encoder->enc.crtc;
a4fc5ed6
KP		 665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
666
e3421a18 667 dp_priv->DP = (DP_VOLTAGE_0_4 |
9c9e7927
AJ		 668 DP_PRE_EMPHASIS_0);
669
670 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
671 dp_priv->DP |= DP_SYNC_HS_HIGH;
672 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
673 dp_priv->DP |= DP_SYNC_VS_HIGH;
a4fc5ed6 674
e3421a18
ZW		 675 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
676 dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
677 else
678 dp_priv->DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 679
680 switch (dp_priv->lane_count) {
681 case 1:
682 dp_priv->DP |= DP_PORT_WIDTH_1;
683 break;
684 case 2:
685 dp_priv->DP |= DP_PORT_WIDTH_2;
686 break;
687 case 4:
688 dp_priv->DP |= DP_PORT_WIDTH_4;
689 break;
690 }
691 if (dp_priv->has_audio)
692 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
693
694 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
695 dp_priv->link_configuration[0] = dp_priv->link_bw;
696 dp_priv->link_configuration[1] = dp_priv->lane_count;
697
698 /*
9962c925 699 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 700 */
9962c925 701 if (dp_priv->dpcd[0] >= 0x11 && (dp_priv->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
a4fc5ed6
KP		 702 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
703 dp_priv->DP |= DP_ENHANCED_FRAMING;
704 }
705
e3421a18
ZW		 706 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
707 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
a4fc5ed6 708 dp_priv->DP |= DP_PIPEB_SELECT;
32f9d658 709
21d40d37 710 if (IS_eDP(intel_encoder)) {
32f9d658
ZW		 711 /* don't miss out required setting for eDP */
712 dp_priv->DP |= DP_PLL_ENABLE;
713 if (adjusted_mode->clock < 200000)
714 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
715 else
716 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
717 }
a4fc5ed6
KP		 718}
719
f2b115e6 720static void ironlake_edp_backlight_on (struct drm_device *dev)
32f9d658
ZW		 721{
722 struct drm_i915_private *dev_priv = dev->dev_private;
723 u32 pp;
724
28c97730 725 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 726 pp = I915_READ(PCH_PP_CONTROL);
727 pp |= EDP_BLC_ENABLE;
728 I915_WRITE(PCH_PP_CONTROL, pp);
729}
730
f2b115e6 731static void ironlake_edp_backlight_off (struct drm_device *dev)
32f9d658
ZW		 732{
733 struct drm_i915_private *dev_priv = dev->dev_private;
734 u32 pp;
735
28c97730 736 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 737 pp = I915_READ(PCH_PP_CONTROL);
738 pp &= ~EDP_BLC_ENABLE;
739 I915_WRITE(PCH_PP_CONTROL, pp);
740}
a4fc5ed6
KP		 741
742static void
743intel_dp_dpms(struct drm_encoder *encoder, int mode)
744{
21d40d37
EA		 745 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
746 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
55f78c43 747 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 748 struct drm_i915_private *dev_priv = dev->dev_private;
749 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
750
751 if (mode != DRM_MODE_DPMS_ON) {
32f9d658 752 if (dp_reg & DP_PORT_EN) {
21d40d37
EA		 753 intel_dp_link_down(intel_encoder, dp_priv->DP);
754 if (IS_eDP(intel_encoder))
f2b115e6 755 ironlake_edp_backlight_off(dev);
32f9d658 756 }
a4fc5ed6 757 } else {
32f9d658 758 if (!(dp_reg & DP_PORT_EN)) {
21d40d37
EA		 759 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
760 if (IS_eDP(intel_encoder))
f2b115e6 761 ironlake_edp_backlight_on(dev);
32f9d658 762 }
a4fc5ed6 763 }
c8110e52 764 dp_priv->dpms_mode = mode;
a4fc5ed6
KP		 765}
766
767/*
768 * Fetch AUX CH registers 0x202 - 0x207 which contain
769 * link status information
770 */
771static bool
21d40d37 772intel_dp_get_link_status(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 773 uint8_t link_status[DP_LINK_STATUS_SIZE])
774{
775 int ret;
776
21d40d37 777 ret = intel_dp_aux_native_read(intel_encoder,
a4fc5ed6
KP		 778 DP_LANE0_1_STATUS,
779 link_status, DP_LINK_STATUS_SIZE);
780 if (ret != DP_LINK_STATUS_SIZE)
781 return false;
782 return true;
783}
784
785static uint8_t
786intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
787 int r)
788{
789 return link_status[r - DP_LANE0_1_STATUS];
790}
791
a4fc5ed6
KP		 792static uint8_t
793intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
794 int lane)
795{
796 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
797 int s = ((lane & 1) ?
798 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
799 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
800 uint8_t l = intel_dp_link_status(link_status, i);
801
802 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
803}
804
805static uint8_t
806intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
807 int lane)
808{
809 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
810 int s = ((lane & 1) ?
811 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
812 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
813 uint8_t l = intel_dp_link_status(link_status, i);
814
815 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
816}
817
818
819#if 0
820static char *voltage_names[] = {
821 "0.4V", "0.6V", "0.8V", "1.2V"
822};
823static char *pre_emph_names[] = {
824 "0dB", "3.5dB", "6dB", "9.5dB"
825};
826static char *link_train_names[] = {
827 "pattern 1", "pattern 2", "idle", "off"
828};
829#endif
830
831/*
832 * These are source-specific values; current Intel hardware supports
833 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
834 */
835#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
836
837static uint8_t
838intel_dp_pre_emphasis_max(uint8_t voltage_swing)
839{
840 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
841 case DP_TRAIN_VOLTAGE_SWING_400:
842 return DP_TRAIN_PRE_EMPHASIS_6;
843 case DP_TRAIN_VOLTAGE_SWING_600:
844 return DP_TRAIN_PRE_EMPHASIS_6;
845 case DP_TRAIN_VOLTAGE_SWING_800:
846 return DP_TRAIN_PRE_EMPHASIS_3_5;
847 case DP_TRAIN_VOLTAGE_SWING_1200:
848 default:
849 return DP_TRAIN_PRE_EMPHASIS_0;
850 }
851}
852
853static void
21d40d37 854intel_get_adjust_train(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 855 uint8_t link_status[DP_LINK_STATUS_SIZE],
856 int lane_count,
857 uint8_t train_set[4])
858{
859 uint8_t v = 0;
860 uint8_t p = 0;
861 int lane;
862
863 for (lane = 0; lane < lane_count; lane++) {
864 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
865 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
866
867 if (this_v > v)
868 v = this_v;
869 if (this_p > p)
870 p = this_p;
871 }
872
873 if (v >= I830_DP_VOLTAGE_MAX)
874 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
875
876 if (p >= intel_dp_pre_emphasis_max(v))
877 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
878
879 for (lane = 0; lane < 4; lane++)
880 train_set[lane] = v | p;
881}
882
883static uint32_t
884intel_dp_signal_levels(uint8_t train_set, int lane_count)
885{
886 uint32_t signal_levels = 0;
887
888 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
889 case DP_TRAIN_VOLTAGE_SWING_400:
890 default:
891 signal_levels |= DP_VOLTAGE_0_4;
892 break;
893 case DP_TRAIN_VOLTAGE_SWING_600:
894 signal_levels |= DP_VOLTAGE_0_6;
895 break;
896 case DP_TRAIN_VOLTAGE_SWING_800:
897 signal_levels |= DP_VOLTAGE_0_8;
898 break;
899 case DP_TRAIN_VOLTAGE_SWING_1200:
900 signal_levels |= DP_VOLTAGE_1_2;
901 break;
902 }
903 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
904 case DP_TRAIN_PRE_EMPHASIS_0:
905 default:
906 signal_levels |= DP_PRE_EMPHASIS_0;
907 break;
908 case DP_TRAIN_PRE_EMPHASIS_3_5:
909 signal_levels |= DP_PRE_EMPHASIS_3_5;
910 break;
911 case DP_TRAIN_PRE_EMPHASIS_6:
912 signal_levels |= DP_PRE_EMPHASIS_6;
913 break;
914 case DP_TRAIN_PRE_EMPHASIS_9_5:
915 signal_levels |= DP_PRE_EMPHASIS_9_5;
916 break;
917 }
918 return signal_levels;
919}
920
e3421a18
ZW		 921/* Gen6's DP voltage swing and pre-emphasis control */
922static uint32_t
923intel_gen6_edp_signal_levels(uint8_t train_set)
924{
925 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
926 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
927 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
928 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
929 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
930 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
931 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
932 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
933 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
934 default:
935 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
936 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
937 }
938}
939
a4fc5ed6
KP		 940static uint8_t
941intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
942 int lane)
943{
944 int i = DP_LANE0_1_STATUS + (lane >> 1);
945 int s = (lane & 1) * 4;
946 uint8_t l = intel_dp_link_status(link_status, i);
947
948 return (l >> s) & 0xf;
949}
950
951/* Check for clock recovery is done on all channels */
952static bool
953intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
954{
955 int lane;
956 uint8_t lane_status;
957
958 for (lane = 0; lane < lane_count; lane++) {
959 lane_status = intel_get_lane_status(link_status, lane);
960 if ((lane_status & DP_LANE_CR_DONE) == 0)
961 return false;
962 }
963 return true;
964}
965
966/* Check to see if channel eq is done on all channels */
967#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
968 DP_LANE_CHANNEL_EQ_DONE|\
969 DP_LANE_SYMBOL_LOCKED)
970static bool
971intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
972{
973 uint8_t lane_align;
974 uint8_t lane_status;
975 int lane;
976
977 lane_align = intel_dp_link_status(link_status,
978 DP_LANE_ALIGN_STATUS_UPDATED);
979 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
980 return false;
981 for (lane = 0; lane < lane_count; lane++) {
982 lane_status = intel_get_lane_status(link_status, lane);
983 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
984 return false;
985 }
986 return true;
987}
988
989static bool
21d40d37 990intel_dp_set_link_train(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 991 uint32_t dp_reg_value,
992 uint8_t dp_train_pat,
993 uint8_t train_set[4],
994 bool first)
995{
55f78c43 996 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 997 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 998 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 999 int ret;
1000
1001 I915_WRITE(dp_priv->output_reg, dp_reg_value);
1002 POSTING_READ(dp_priv->output_reg);
1003 if (first)
1004 intel_wait_for_vblank(dev);
1005
21d40d37 1006 intel_dp_aux_native_write_1(intel_encoder,
a4fc5ed6
KP		 1007 DP_TRAINING_PATTERN_SET,
1008 dp_train_pat);
1009
21d40d37 1010 ret = intel_dp_aux_native_write(intel_encoder,
a4fc5ed6
KP		 1011 DP_TRAINING_LANE0_SET, train_set, 4);
1012 if (ret != 4)
1013 return false;
1014
1015 return true;
1016}
1017
1018static void
21d40d37 1019intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
a4fc5ed6
KP		 1020 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
1021{
55f78c43 1022 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 1023 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1024 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1025 uint8_t train_set[4];
1026 uint8_t link_status[DP_LINK_STATUS_SIZE];
1027 int i;
1028 uint8_t voltage;
1029 bool clock_recovery = false;
1030 bool channel_eq = false;
1031 bool first = true;
1032 int tries;
e3421a18 1033 u32 reg;
a4fc5ed6
KP		 1034
1035 /* Write the link configuration data */
ab00a9ef 1036 intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET,
a4fc5ed6
KP		 1037 link_configuration, DP_LINK_CONFIGURATION_SIZE);
1038
1039 DP |= DP_PORT_EN;
e3421a18
ZW		 1040 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1041 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1042 else
1043 DP &= ~DP_LINK_TRAIN_MASK;
a4fc5ed6
KP		 1044 memset(train_set, 0, 4);
1045 voltage = 0xff;
1046 tries = 0;
1047 clock_recovery = false;
1048 for (;;) {
1049 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1050 uint32_t signal_levels;
1051 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1052 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1053 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1054 } else {
1055 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1056 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1057 }
a4fc5ed6 1058
e3421a18
ZW		 1059 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1060 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1061 else
1062 reg = DP | DP_LINK_TRAIN_PAT_1;
1063
1064 if (!intel_dp_set_link_train(intel_encoder, reg,
a4fc5ed6
KP		 1065 DP_TRAINING_PATTERN_1, train_set, first))
1066 break;
1067 first = false;
1068 /* Set training pattern 1 */
1069
1070 udelay(100);
21d40d37 1071 if (!intel_dp_get_link_status(intel_encoder, link_status))
a4fc5ed6
KP		 1072 break;
1073
1074 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1075 clock_recovery = true;
1076 break;
1077 }
1078
1079 /* Check to see if we've tried the max voltage */
1080 for (i = 0; i < dp_priv->lane_count; i++)
1081 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1082 break;
1083 if (i == dp_priv->lane_count)
1084 break;
1085
1086 /* Check to see if we've tried the same voltage 5 times */
1087 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1088 ++tries;
1089 if (tries == 5)
1090 break;
1091 } else
1092 tries = 0;
1093 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1094
1095 /* Compute new train_set as requested by target */
21d40d37 1096 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
a4fc5ed6
KP		 1097 }
1098
1099 /* channel equalization */
1100 tries = 0;
1101 channel_eq = false;
1102 for (;;) {
1103 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1104 uint32_t signal_levels;
1105
1106 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1107 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1108 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1109 } else {
1110 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1111 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1112 }
1113
1114 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1115 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1116 else
1117 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1118
1119 /* channel eq pattern */
e3421a18 1120 if (!intel_dp_set_link_train(intel_encoder, reg,
a4fc5ed6
KP		 1121 DP_TRAINING_PATTERN_2, train_set,
1122 false))
1123 break;
1124
1125 udelay(400);
21d40d37 1126 if (!intel_dp_get_link_status(intel_encoder, link_status))
a4fc5ed6
KP		 1127 break;
1128
1129 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1130 channel_eq = true;
1131 break;
1132 }
1133
1134 /* Try 5 times */
1135 if (tries > 5)
1136 break;
1137
1138 /* Compute new train_set as requested by target */
21d40d37 1139 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
a4fc5ed6
KP		 1140 ++tries;
1141 }
1142
e3421a18
ZW		 1143 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1144 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1145 else
1146 reg = DP | DP_LINK_TRAIN_OFF;
1147
1148 I915_WRITE(dp_priv->output_reg, reg);
a4fc5ed6 1149 POSTING_READ(dp_priv->output_reg);
21d40d37 1150 intel_dp_aux_native_write_1(intel_encoder,
a4fc5ed6
KP		 1151 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1152}
1153
1154static void
21d40d37 1155intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
a4fc5ed6 1156{
55f78c43 1157 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 1158 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1159 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 1160
28c97730 1161 DRM_DEBUG_KMS("\n");
32f9d658 1162
21d40d37 1163 if (IS_eDP(intel_encoder)) {
32f9d658
ZW		 1164 DP &= ~DP_PLL_ENABLE;
1165 I915_WRITE(dp_priv->output_reg, DP);
1166 POSTING_READ(dp_priv->output_reg);
1167 udelay(100);
1168 }
1169
e3421a18
ZW		 1170 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
1171 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1172 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1173 POSTING_READ(dp_priv->output_reg);
1174 } else {
1175 DP &= ~DP_LINK_TRAIN_MASK;
1176 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1177 POSTING_READ(dp_priv->output_reg);
1178 }
5eb08b69
ZW		 1179
1180 udelay(17000);
1181
21d40d37 1182 if (IS_eDP(intel_encoder))
32f9d658 1183 DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 1184 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1185 POSTING_READ(dp_priv->output_reg);
1186}
1187
a4fc5ed6
KP		 1188/*
1189 * According to DP spec
1190 * 5.1.2:
1191 * 1. Read DPCD
1192 * 2. Configure link according to Receiver Capabilities
1193 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1194 * 4. Check link status on receipt of hot-plug interrupt
1195 */
1196
1197static void
21d40d37 1198intel_dp_check_link_status(struct intel_encoder *intel_encoder)
a4fc5ed6 1199{
21d40d37 1200 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1201 uint8_t link_status[DP_LINK_STATUS_SIZE];
1202
21d40d37 1203 if (!intel_encoder->enc.crtc)
a4fc5ed6
KP		 1204 return;
1205
21d40d37
EA		 1206 if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1207 intel_dp_link_down(intel_encoder, dp_priv->DP);
a4fc5ed6
KP		 1208 return;
1209 }
1210
1211 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
21d40d37 1212 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
a4fc5ed6 1213}
a4fc5ed6 1214
5eb08b69 1215static enum drm_connector_status
f2b115e6 1216ironlake_dp_detect(struct drm_connector *connector)
5eb08b69 1217{
55f78c43
ZW		 1218 struct drm_encoder *encoder = intel_attached_encoder(connector);
1219 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
21d40d37 1220 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
5eb08b69
ZW		 1221 enum drm_connector_status status;
1222
1223 status = connector_status_disconnected;
21d40d37 1224 if (intel_dp_aux_native_read(intel_encoder,
5eb08b69
ZW		 1225 0x000, dp_priv->dpcd,
1226 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1227 {
1228 if (dp_priv->dpcd[0] != 0)
1229 status = connector_status_connected;
1230 }
a7de64e5
AJ		 1231 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv->dpcd[0],
1232 dp_priv->dpcd[1], dp_priv->dpcd[2], dp_priv->dpcd[3]);
5eb08b69
ZW		 1233 return status;
1234}
1235
a4fc5ed6
KP		 1236/**
1237 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1238 *
1239 * \return true if DP port is connected.
1240 * \return false if DP port is disconnected.
1241 */
1242static enum drm_connector_status
1243intel_dp_detect(struct drm_connector *connector)
1244{
55f78c43
ZW		 1245 struct drm_encoder *encoder = intel_attached_encoder(connector);
1246 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1247 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 1248 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1249 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1250 uint32_t temp, bit;
1251 enum drm_connector_status status;
1252
1253 dp_priv->has_audio = false;
1254
c619eed4 1255 if (HAS_PCH_SPLIT(dev))
f2b115e6 1256 return ironlake_dp_detect(connector);
5eb08b69 1257
a4fc5ed6
KP		 1258 switch (dp_priv->output_reg) {
1259 case DP_B:
1260 bit = DPB_HOTPLUG_INT_STATUS;
1261 break;
1262 case DP_C:
1263 bit = DPC_HOTPLUG_INT_STATUS;
1264 break;
1265 case DP_D:
1266 bit = DPD_HOTPLUG_INT_STATUS;
1267 break;
1268 default:
1269 return connector_status_unknown;
1270 }
1271
1272 temp = I915_READ(PORT_HOTPLUG_STAT);
1273
1274 if ((temp & bit) == 0)
1275 return connector_status_disconnected;
1276
1277 status = connector_status_disconnected;
21d40d37 1278 if (intel_dp_aux_native_read(intel_encoder,
a4fc5ed6
KP		 1279 0x000, dp_priv->dpcd,
1280 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1281 {
1282 if (dp_priv->dpcd[0] != 0)
1283 status = connector_status_connected;
1284 }
1285 return status;
1286}
1287
1288static int intel_dp_get_modes(struct drm_connector *connector)
1289{
55f78c43
ZW		 1290 struct drm_encoder *encoder = intel_attached_encoder(connector);
1291 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1292 struct drm_device *dev = intel_encoder->enc.dev;
32f9d658
ZW		 1293 struct drm_i915_private *dev_priv = dev->dev_private;
1294 int ret;
a4fc5ed6
KP		 1295
1296 /* We should parse the EDID data and find out if it has an audio sink
1297 */
1298
335af9a2 1299 ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
32f9d658
ZW		 1300 if (ret)
1301 return ret;
1302
1303 /* if eDP has no EDID, try to use fixed panel mode from VBT */
21d40d37 1304 if (IS_eDP(intel_encoder)) {
32f9d658
ZW		 1305 if (dev_priv->panel_fixed_mode != NULL) {
1306 struct drm_display_mode *mode;
1307 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1308 drm_mode_probed_add(connector, mode);
1309 return 1;
1310 }
1311 }
1312 return 0;
a4fc5ed6
KP		 1313}
1314
1315static void
1316intel_dp_destroy (struct drm_connector *connector)
1317{
a4fc5ed6
KP		 1318 drm_sysfs_connector_remove(connector);
1319 drm_connector_cleanup(connector);
55f78c43 1320 kfree(connector);
a4fc5ed6
KP		 1321}
1322
1323static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1324 .dpms = intel_dp_dpms,
1325 .mode_fixup = intel_dp_mode_fixup,
1326 .prepare = intel_encoder_prepare,
1327 .mode_set = intel_dp_mode_set,
1328 .commit = intel_encoder_commit,
1329};
1330
1331static const struct drm_connector_funcs intel_dp_connector_funcs = {
1332 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 1333 .detect = intel_dp_detect,
1334 .fill_modes = drm_helper_probe_single_connector_modes,
1335 .destroy = intel_dp_destroy,
1336};
1337
1338static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1339 .get_modes = intel_dp_get_modes,
1340 .mode_valid = intel_dp_mode_valid,
55f78c43 1341 .best_encoder = intel_attached_encoder,
a4fc5ed6
KP		 1342};
1343
1344static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1345{
55f78c43
ZW		 1346 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1347
1348 if (intel_encoder->i2c_bus)
1349 intel_i2c_destroy(intel_encoder->i2c_bus);
a4fc5ed6 1350 drm_encoder_cleanup(encoder);
55f78c43 1351 kfree(intel_encoder);
a4fc5ed6
KP		 1352}
1353
1354static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1355 .destroy = intel_dp_enc_destroy,
1356};
1357
c8110e52 1358void
21d40d37 1359intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 1360{
21d40d37 1361 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
c8110e52
KP		 1362
1363 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
21d40d37 1364 intel_dp_check_link_status(intel_encoder);
c8110e52 1365}
6207937d 1366
e3421a18
ZW		 1367/* Return which DP Port should be selected for Transcoder DP control */
1368int
1369intel_trans_dp_port_sel (struct drm_crtc *crtc)
1370{
1371 struct drm_device *dev = crtc->dev;
1372 struct drm_mode_config *mode_config = &dev->mode_config;
1373 struct drm_encoder *encoder;
1374 struct intel_encoder *intel_encoder = NULL;
1375
1376 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
d8201ab6 1377 if (encoder->crtc != crtc)
e3421a18
ZW		 1378 continue;
1379
1380 intel_encoder = enc_to_intel_encoder(encoder);
1381 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1382 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1383 return dp_priv->output_reg;
1384 }
1385 }
1386 return -1;
1387}
1388
a4fc5ed6
KP		 1389void
1390intel_dp_init(struct drm_device *dev, int output_reg)
1391{
1392 struct drm_i915_private *dev_priv = dev->dev_private;
1393 struct drm_connector *connector;
21d40d37 1394 struct intel_encoder *intel_encoder;
55f78c43 1395 struct intel_connector *intel_connector;
a4fc5ed6 1396 struct intel_dp_priv *dp_priv;
5eb08b69 1397 const char *name = NULL;
a4fc5ed6 1398
21d40d37 1399 intel_encoder = kcalloc(sizeof(struct intel_encoder) +
a4fc5ed6 1400 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
21d40d37 1401 if (!intel_encoder)
a4fc5ed6
KP		 1402 return;
1403
55f78c43
ZW		 1404 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1405 if (!intel_connector) {
1406 kfree(intel_encoder);
1407 return;
1408 }
1409
21d40d37 1410 dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
a4fc5ed6 1411
55f78c43 1412 connector = &intel_connector->base;
a4fc5ed6
KP		 1413 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1414 DRM_MODE_CONNECTOR_DisplayPort);
1415 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1416
eb1f8e4f
DA		 1417 connector->polled = DRM_CONNECTOR_POLL_HPD;
1418
32f9d658 1419 if (output_reg == DP_A)
21d40d37 1420 intel_encoder->type = INTEL_OUTPUT_EDP;
32f9d658 1421 else
21d40d37 1422 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a4fc5ed6 1423
652af9d7 1424 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 1425 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 1426 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 1427 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 1428 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 1429 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 1430
21d40d37
EA		 1431 if (IS_eDP(intel_encoder))
1432 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
6251ec0a 1433
21d40d37 1434 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1435 connector->interlace_allowed = true;
1436 connector->doublescan_allowed = 0;
1437
21d40d37 1438 dp_priv->intel_encoder = intel_encoder;
a4fc5ed6
KP		 1439 dp_priv->output_reg = output_reg;
1440 dp_priv->has_audio = false;
c8110e52 1441 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
21d40d37 1442 intel_encoder->dev_priv = dp_priv;
a4fc5ed6 1443
21d40d37 1444 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
a4fc5ed6 1445 DRM_MODE_ENCODER_TMDS);
21d40d37 1446 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
a4fc5ed6 1447
55f78c43 1448 drm_mode_connector_attach_encoder(&intel_connector->base,
21d40d37 1449 &intel_encoder->enc);
a4fc5ed6
KP		 1450 drm_sysfs_connector_add(connector);
1451
1452 /* Set up the DDC bus. */
5eb08b69 1453 switch (output_reg) {
32f9d658
ZW		 1454 case DP_A:
1455 name = "DPDDC-A";
1456 break;
5eb08b69
ZW		 1457 case DP_B:
1458 case PCH_DP_B:
b01f2c3a
JB		 1459 dev_priv->hotplug_supported_mask |=
1460 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1461 name = "DPDDC-B";
1462 break;
1463 case DP_C:
1464 case PCH_DP_C:
b01f2c3a
JB		 1465 dev_priv->hotplug_supported_mask |=
1466 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1467 name = "DPDDC-C";
1468 break;
1469 case DP_D:
1470 case PCH_DP_D:
b01f2c3a
JB		 1471 dev_priv->hotplug_supported_mask |=
1472 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1473 name = "DPDDC-D";
1474 break;
1475 }
1476
55f78c43 1477 intel_dp_i2c_init(intel_encoder, intel_connector, name);
32f9d658 1478
21d40d37
EA		 1479 intel_encoder->ddc_bus = &dp_priv->adapter;
1480 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1481
32f9d658
ZW		 1482 if (output_reg == DP_A) {
1483 /* initialize panel mode from VBT if available for eDP */
1484 if (dev_priv->lfp_lvds_vbt_mode) {
1485 dev_priv->panel_fixed_mode =
1486 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1487 if (dev_priv->panel_fixed_mode) {
1488 dev_priv->panel_fixed_mode->type |=
1489 DRM_MODE_TYPE_PREFERRED;
1490 }
1491 }
1492 }
1493
a4fc5ed6
KP		 1494 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1495 * 0xd. Failure to do so will result in spurious interrupts being
1496 * generated on the port when a cable is not attached.
1497 */
1498 if (IS_G4X(dev) && !IS_GM45(dev)) {
1499 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1500 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1501 }
1502}
Clone of davem's net-next-2.6 tree