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drm/i915: introduce intel_ring_buffer structure (V2)
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5a0e3ad6 34#include <linux/slab.h>
673a394b 35#include <linux/swap.h>
79e53945 36#include <linux/pci.h>
673a394b 37
e47c68e9
EA		 38static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 41static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
42 int write);
43static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
44 uint64_t offset,
45 uint64_t size);
46static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 47static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 48static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 unsigned alignment);
de151cf6 50static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 51static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 52static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 53static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
673a394b 56
31169714
CW		 57static LIST_HEAD(shrink_list);
58static DEFINE_SPINLOCK(shrink_list_lock);
59
79e53945
JB		 60int i915_gem_do_init(struct drm_device *dev, unsigned long start,
61 unsigned long end)
673a394b
EA		 62{
63 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 64
79e53945
JB		 65 if (start >= end ||
66 (start & (PAGE_SIZE - 1)) != 0 ||
67 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 68 return -EINVAL;
69 }
70
79e53945
JB		 71 drm_mm_init(&dev_priv->mm.gtt_space, start,
72 end - start);
673a394b 73
79e53945
JB		 74 dev->gtt_total = (uint32_t) (end - start);
75
76 return 0;
77}
673a394b 78
79e53945
JB		 79int
80i915_gem_init_ioctl(struct drm_device *dev, void *data,
81 struct drm_file *file_priv)
82{
83 struct drm_i915_gem_init *args = data;
84 int ret;
85
86 mutex_lock(&dev->struct_mutex);
87 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 88 mutex_unlock(&dev->struct_mutex);
89
79e53945 90 return ret;
673a394b
EA		 91}
92
5a125c3c
EA		 93int
94i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
95 struct drm_file *file_priv)
96{
5a125c3c 97 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 98
99 if (!(dev->driver->driver_features & DRIVER_GEM))
100 return -ENODEV;
101
102 args->aper_size = dev->gtt_total;
2678d9d6
KP		 103 args->aper_available_size = (args->aper_size -
104 atomic_read(&dev->pin_memory));
5a125c3c
EA		 105
106 return 0;
107}
108
673a394b
EA		 109
110/**
111 * Creates a new mm object and returns a handle to it.
112 */
113int
114i915_gem_create_ioctl(struct drm_device *dev, void *data,
115 struct drm_file *file_priv)
116{
117 struct drm_i915_gem_create *args = data;
118 struct drm_gem_object *obj;
a1a2d1d3
PP		 119 int ret;
120 u32 handle;
673a394b
EA		 121
122 args->size = roundup(args->size, PAGE_SIZE);
123
124 /* Allocate the new object */
ac52bc56 125 obj = i915_gem_alloc_object(dev, args->size);
673a394b
EA		 126 if (obj == NULL)
127 return -ENOMEM;
128
129 ret = drm_gem_handle_create(file_priv, obj, &handle);
bc9025bd 130 drm_gem_object_handle_unreference_unlocked(obj);
673a394b
EA		 131
132 if (ret)
133 return ret;
134
135 args->handle = handle;
136
137 return 0;
138}
139
eb01459f
EA		 140static inline int
141fast_shmem_read(struct page **pages,
142 loff_t page_base, int page_offset,
143 char __user *data,
144 int length)
145{
146 char __iomem *vaddr;
2bc43b5c 147 int unwritten;
eb01459f
EA		 148
149 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
150 if (vaddr == NULL)
151 return -ENOMEM;
2bc43b5c 152 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 153 kunmap_atomic(vaddr, KM_USER0);
154
2bc43b5c
FM		 155 if (unwritten)
156 return -EFAULT;
157
158 return 0;
eb01459f
EA		 159}
160
280b713b
EA		 161static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
162{
163 drm_i915_private_t *dev_priv = obj->dev->dev_private;
23010e43 164 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
280b713b
EA		 165
166 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
167 obj_priv->tiling_mode != I915_TILING_NONE;
168}
169
40123c1f
EA		 170static inline int
171slow_shmem_copy(struct page *dst_page,
172 int dst_offset,
173 struct page *src_page,
174 int src_offset,
175 int length)
176{
177 char *dst_vaddr, *src_vaddr;
178
179 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
180 if (dst_vaddr == NULL)
181 return -ENOMEM;
182
183 src_vaddr = kmap_atomic(src_page, KM_USER1);
184 if (src_vaddr == NULL) {
185 kunmap_atomic(dst_vaddr, KM_USER0);
186 return -ENOMEM;
187 }
188
189 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
190
191 kunmap_atomic(src_vaddr, KM_USER1);
192 kunmap_atomic(dst_vaddr, KM_USER0);
193
194 return 0;
195}
196
280b713b
EA		 197static inline int
198slow_shmem_bit17_copy(struct page *gpu_page,
199 int gpu_offset,
200 struct page *cpu_page,
201 int cpu_offset,
202 int length,
203 int is_read)
204{
205 char *gpu_vaddr, *cpu_vaddr;
206
207 /* Use the unswizzled path if this page isn't affected. */
208 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
209 if (is_read)
210 return slow_shmem_copy(cpu_page, cpu_offset,
211 gpu_page, gpu_offset, length);
212 else
213 return slow_shmem_copy(gpu_page, gpu_offset,
214 cpu_page, cpu_offset, length);
215 }
216
217 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
218 if (gpu_vaddr == NULL)
219 return -ENOMEM;
220
221 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
222 if (cpu_vaddr == NULL) {
223 kunmap_atomic(gpu_vaddr, KM_USER0);
224 return -ENOMEM;
225 }
226
227 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
228 * XORing with the other bits (A9 for Y, A9 and A10 for X)
229 */
230 while (length > 0) {
231 int cacheline_end = ALIGN(gpu_offset + 1, 64);
232 int this_length = min(cacheline_end - gpu_offset, length);
233 int swizzled_gpu_offset = gpu_offset ^ 64;
234
235 if (is_read) {
236 memcpy(cpu_vaddr + cpu_offset,
237 gpu_vaddr + swizzled_gpu_offset,
238 this_length);
239 } else {
240 memcpy(gpu_vaddr + swizzled_gpu_offset,
241 cpu_vaddr + cpu_offset,
242 this_length);
243 }
244 cpu_offset += this_length;
245 gpu_offset += this_length;
246 length -= this_length;
247 }
248
249 kunmap_atomic(cpu_vaddr, KM_USER1);
250 kunmap_atomic(gpu_vaddr, KM_USER0);
251
252 return 0;
253}
254
eb01459f
EA		 255/**
256 * This is the fast shmem pread path, which attempts to copy_from_user directly
257 * from the backing pages of the object to the user's address space. On a
258 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
259 */
260static int
261i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
262 struct drm_i915_gem_pread *args,
263 struct drm_file *file_priv)
264{
23010e43 265 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 266 ssize_t remain;
267 loff_t offset, page_base;
268 char __user *user_data;
269 int page_offset, page_length;
270 int ret;
271
272 user_data = (char __user *) (uintptr_t) args->data_ptr;
273 remain = args->size;
274
275 mutex_lock(&dev->struct_mutex);
276
4bdadb97 277 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 278 if (ret != 0)
279 goto fail_unlock;
280
281 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
282 args->size);
283 if (ret != 0)
284 goto fail_put_pages;
285
23010e43 286 obj_priv = to_intel_bo(obj);
eb01459f
EA		 287 offset = args->offset;
288
289 while (remain > 0) {
290 /* Operation in this page
291 *
292 * page_base = page offset within aperture
293 * page_offset = offset within page
294 * page_length = bytes to copy for this page
295 */
296 page_base = (offset & ~(PAGE_SIZE-1));
297 page_offset = offset & (PAGE_SIZE-1);
298 page_length = remain;
299 if ((page_offset + remain) > PAGE_SIZE)
300 page_length = PAGE_SIZE - page_offset;
301
302 ret = fast_shmem_read(obj_priv->pages,
303 page_base, page_offset,
304 user_data, page_length);
305 if (ret)
306 goto fail_put_pages;
307
308 remain -= page_length;
309 user_data += page_length;
310 offset += page_length;
311 }
312
313fail_put_pages:
314 i915_gem_object_put_pages(obj);
315fail_unlock:
316 mutex_unlock(&dev->struct_mutex);
317
318 return ret;
319}
320
07f73f69
CW		 321static int
322i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
323{
324 int ret;
325
4bdadb97 326 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 327
328 /* If we've insufficient memory to map in the pages, attempt
329 * to make some space by throwing out some old buffers.
330 */
331 if (ret == -ENOMEM) {
332 struct drm_device *dev = obj->dev;
07f73f69
CW		 333
334 ret = i915_gem_evict_something(dev, obj->size);
335 if (ret)
336 return ret;
337
4bdadb97 338 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 339 }
340
341 return ret;
342}
343
eb01459f
EA		 344/**
345 * This is the fallback shmem pread path, which allocates temporary storage
346 * in kernel space to copy_to_user into outside of the struct_mutex, so we
347 * can copy out of the object's backing pages while holding the struct mutex
348 * and not take page faults.
349 */
350static int
351i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
352 struct drm_i915_gem_pread *args,
353 struct drm_file *file_priv)
354{
23010e43 355 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 356 struct mm_struct *mm = current->mm;
357 struct page **user_pages;
358 ssize_t remain;
359 loff_t offset, pinned_pages, i;
360 loff_t first_data_page, last_data_page, num_pages;
361 int shmem_page_index, shmem_page_offset;
362 int data_page_index, data_page_offset;
363 int page_length;
364 int ret;
365 uint64_t data_ptr = args->data_ptr;
280b713b 366 int do_bit17_swizzling;
eb01459f
EA		 367
368 remain = args->size;
369
370 /* Pin the user pages containing the data. We can't fault while
371 * holding the struct mutex, yet we want to hold it while
372 * dereferencing the user data.
373 */
374 first_data_page = data_ptr / PAGE_SIZE;
375 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
376 num_pages = last_data_page - first_data_page + 1;
377
8e7d2b2c 378 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 379 if (user_pages == NULL)
380 return -ENOMEM;
381
382 down_read(&mm->mmap_sem);
383 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 384 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 385 up_read(&mm->mmap_sem);
386 if (pinned_pages < num_pages) {
387 ret = -EFAULT;
388 goto fail_put_user_pages;
389 }
390
280b713b
EA		 391 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
392
eb01459f
EA		 393 mutex_lock(&dev->struct_mutex);
394
07f73f69
CW		 395 ret = i915_gem_object_get_pages_or_evict(obj);
396 if (ret)
eb01459f
EA		 397 goto fail_unlock;
398
399 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
400 args->size);
401 if (ret != 0)
402 goto fail_put_pages;
403
23010e43 404 obj_priv = to_intel_bo(obj);
eb01459f
EA		 405 offset = args->offset;
406
407 while (remain > 0) {
408 /* Operation in this page
409 *
410 * shmem_page_index = page number within shmem file
411 * shmem_page_offset = offset within page in shmem file
412 * data_page_index = page number in get_user_pages return
413 * data_page_offset = offset with data_page_index page.
414 * page_length = bytes to copy for this page
415 */
416 shmem_page_index = offset / PAGE_SIZE;
417 shmem_page_offset = offset & ~PAGE_MASK;
418 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
419 data_page_offset = data_ptr & ~PAGE_MASK;
420
421 page_length = remain;
422 if ((shmem_page_offset + page_length) > PAGE_SIZE)
423 page_length = PAGE_SIZE - shmem_page_offset;
424 if ((data_page_offset + page_length) > PAGE_SIZE)
425 page_length = PAGE_SIZE - data_page_offset;
426
280b713b
EA		 427 if (do_bit17_swizzling) {
428 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
429 shmem_page_offset,
430 user_pages[data_page_index],
431 data_page_offset,
432 page_length,
433 1);
434 } else {
435 ret = slow_shmem_copy(user_pages[data_page_index],
436 data_page_offset,
437 obj_priv->pages[shmem_page_index],
438 shmem_page_offset,
439 page_length);
440 }
eb01459f
EA		 441 if (ret)
442 goto fail_put_pages;
443
444 remain -= page_length;
445 data_ptr += page_length;
446 offset += page_length;
447 }
448
449fail_put_pages:
450 i915_gem_object_put_pages(obj);
451fail_unlock:
452 mutex_unlock(&dev->struct_mutex);
453fail_put_user_pages:
454 for (i = 0; i < pinned_pages; i++) {
455 SetPageDirty(user_pages[i]);
456 page_cache_release(user_pages[i]);
457 }
8e7d2b2c 458 drm_free_large(user_pages);
eb01459f
EA		 459
460 return ret;
461}
462
673a394b
EA		 463/**
464 * Reads data from the object referenced by handle.
465 *
466 * On error, the contents of *data are undefined.
467 */
468int
469i915_gem_pread_ioctl(struct drm_device *dev, void *data,
470 struct drm_file *file_priv)
471{
472 struct drm_i915_gem_pread *args = data;
473 struct drm_gem_object *obj;
474 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 475 int ret;
476
477 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
478 if (obj == NULL)
479 return -EBADF;
23010e43 480 obj_priv = to_intel_bo(obj);
673a394b
EA		 481
482 /* Bounds check source.
483 *
484 * XXX: This could use review for overflow issues...
485 */
486 if (args->offset > obj->size || args->size > obj->size ||
487 args->offset + args->size > obj->size) {
bc9025bd 488 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 489 return -EINVAL;
490 }
491
280b713b 492 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 493 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 494 } else {
495 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
496 if (ret != 0)
497 ret = i915_gem_shmem_pread_slow(dev, obj, args,
498 file_priv);
499 }
673a394b 500
bc9025bd 501 drm_gem_object_unreference_unlocked(obj);
673a394b 502
eb01459f 503 return ret;
673a394b
EA		 504}
505
0839ccb8
KP		 506/* This is the fast write path which cannot handle
507 * page faults in the source data
9b7530cc 508 */
0839ccb8
KP		 509
510static inline int
511fast_user_write(struct io_mapping *mapping,
512 loff_t page_base, int page_offset,
513 char __user *user_data,
514 int length)
9b7530cc 515{
9b7530cc 516 char *vaddr_atomic;
0839ccb8 517 unsigned long unwritten;
9b7530cc 518
0839ccb8
KP		 519 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
520 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
521 user_data, length);
522 io_mapping_unmap_atomic(vaddr_atomic);
523 if (unwritten)
524 return -EFAULT;
525 return 0;
526}
527
528/* Here's the write path which can sleep for
529 * page faults
530 */
531
532static inline int
3de09aa3
EA		 533slow_kernel_write(struct io_mapping *mapping,
534 loff_t gtt_base, int gtt_offset,
535 struct page *user_page, int user_offset,
536 int length)
0839ccb8 537{
3de09aa3 538 char *src_vaddr, *dst_vaddr;
0839ccb8
KP		 539 unsigned long unwritten;
540
3de09aa3
EA		 541 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
542 src_vaddr = kmap_atomic(user_page, KM_USER1);
543 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
544 src_vaddr + user_offset,
545 length);
546 kunmap_atomic(src_vaddr, KM_USER1);
547 io_mapping_unmap_atomic(dst_vaddr);
0839ccb8
KP		 548 if (unwritten)
549 return -EFAULT;
9b7530cc 550 return 0;
9b7530cc
LT		 551}
552
40123c1f
EA		 553static inline int
554fast_shmem_write(struct page **pages,
555 loff_t page_base, int page_offset,
556 char __user *data,
557 int length)
558{
559 char __iomem *vaddr;
d0088775 560 unsigned long unwritten;
40123c1f
EA		 561
562 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
563 if (vaddr == NULL)
564 return -ENOMEM;
d0088775 565 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 566 kunmap_atomic(vaddr, KM_USER0);
567
d0088775
DA		 568 if (unwritten)
569 return -EFAULT;
40123c1f
EA		 570 return 0;
571}
572
3de09aa3
EA		 573/**
574 * This is the fast pwrite path, where we copy the data directly from the
575 * user into the GTT, uncached.
576 */
673a394b 577static int
3de09aa3
EA		 578i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
579 struct drm_i915_gem_pwrite *args,
580 struct drm_file *file_priv)
673a394b 581{
23010e43 582 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
0839ccb8 583 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 584 ssize_t remain;
0839ccb8 585 loff_t offset, page_base;
673a394b 586 char __user *user_data;
0839ccb8
KP		 587 int page_offset, page_length;
588 int ret;
673a394b
EA		 589
590 user_data = (char __user *) (uintptr_t) args->data_ptr;
591 remain = args->size;
592 if (!access_ok(VERIFY_READ, user_data, remain))
593 return -EFAULT;
594
595
596 mutex_lock(&dev->struct_mutex);
597 ret = i915_gem_object_pin(obj, 0);
598 if (ret) {
599 mutex_unlock(&dev->struct_mutex);
600 return ret;
601 }
2ef7eeaa 602 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 603 if (ret)
604 goto fail;
605
23010e43 606 obj_priv = to_intel_bo(obj);
673a394b 607 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 608
609 while (remain > 0) {
610 /* Operation in this page
611 *
0839ccb8
KP		 612 * page_base = page offset within aperture
613 * page_offset = offset within page
614 * page_length = bytes to copy for this page
673a394b 615 */
0839ccb8
KP		 616 page_base = (offset & ~(PAGE_SIZE-1));
617 page_offset = offset & (PAGE_SIZE-1);
618 page_length = remain;
619 if ((page_offset + remain) > PAGE_SIZE)
620 page_length = PAGE_SIZE - page_offset;
621
622 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
623 page_offset, user_data, page_length);
624
625 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 626 * source page isn't available. Return the error and we'll
627 * retry in the slow path.
0839ccb8 628 */
3de09aa3
EA		 629 if (ret)
630 goto fail;
673a394b 631
0839ccb8
KP		 632 remain -= page_length;
633 user_data += page_length;
634 offset += page_length;
673a394b 635 }
673a394b
EA		 636
637fail:
638 i915_gem_object_unpin(obj);
639 mutex_unlock(&dev->struct_mutex);
640
641 return ret;
642}
643
3de09aa3
EA		 644/**
645 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
646 * the memory and maps it using kmap_atomic for copying.
647 *
648 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
649 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
650 */
3043c60c 651static int
3de09aa3
EA		 652i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
653 struct drm_i915_gem_pwrite *args,
654 struct drm_file *file_priv)
673a394b 655{
23010e43 656 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3de09aa3
EA		 657 drm_i915_private_t *dev_priv = dev->dev_private;
658 ssize_t remain;
659 loff_t gtt_page_base, offset;
660 loff_t first_data_page, last_data_page, num_pages;
661 loff_t pinned_pages, i;
662 struct page **user_pages;
663 struct mm_struct *mm = current->mm;
664 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 665 int ret;
3de09aa3
EA		 666 uint64_t data_ptr = args->data_ptr;
667
668 remain = args->size;
669
670 /* Pin the user pages containing the data. We can't fault while
671 * holding the struct mutex, and all of the pwrite implementations
672 * want to hold it while dereferencing the user data.
673 */
674 first_data_page = data_ptr / PAGE_SIZE;
675 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
676 num_pages = last_data_page - first_data_page + 1;
677
8e7d2b2c 678 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 679 if (user_pages == NULL)
680 return -ENOMEM;
681
682 down_read(&mm->mmap_sem);
683 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
684 num_pages, 0, 0, user_pages, NULL);
685 up_read(&mm->mmap_sem);
686 if (pinned_pages < num_pages) {
687 ret = -EFAULT;
688 goto out_unpin_pages;
689 }
673a394b
EA		 690
691 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 692 ret = i915_gem_object_pin(obj, 0);
693 if (ret)
694 goto out_unlock;
695
696 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
697 if (ret)
698 goto out_unpin_object;
699
23010e43 700 obj_priv = to_intel_bo(obj);
3de09aa3
EA		 701 offset = obj_priv->gtt_offset + args->offset;
702
703 while (remain > 0) {
704 /* Operation in this page
705 *
706 * gtt_page_base = page offset within aperture
707 * gtt_page_offset = offset within page in aperture
708 * data_page_index = page number in get_user_pages return
709 * data_page_offset = offset with data_page_index page.
710 * page_length = bytes to copy for this page
711 */
712 gtt_page_base = offset & PAGE_MASK;
713 gtt_page_offset = offset & ~PAGE_MASK;
714 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
715 data_page_offset = data_ptr & ~PAGE_MASK;
716
717 page_length = remain;
718 if ((gtt_page_offset + page_length) > PAGE_SIZE)
719 page_length = PAGE_SIZE - gtt_page_offset;
720 if ((data_page_offset + page_length) > PAGE_SIZE)
721 page_length = PAGE_SIZE - data_page_offset;
722
723 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
724 gtt_page_base, gtt_page_offset,
725 user_pages[data_page_index],
726 data_page_offset,
727 page_length);
728
729 /* If we get a fault while copying data, then (presumably) our
730 * source page isn't available. Return the error and we'll
731 * retry in the slow path.
732 */
733 if (ret)
734 goto out_unpin_object;
735
736 remain -= page_length;
737 offset += page_length;
738 data_ptr += page_length;
739 }
740
741out_unpin_object:
742 i915_gem_object_unpin(obj);
743out_unlock:
744 mutex_unlock(&dev->struct_mutex);
745out_unpin_pages:
746 for (i = 0; i < pinned_pages; i++)
747 page_cache_release(user_pages[i]);
8e7d2b2c 748 drm_free_large(user_pages);
3de09aa3
EA		 749
750 return ret;
751}
752
40123c1f
EA		 753/**
754 * This is the fast shmem pwrite path, which attempts to directly
755 * copy_from_user into the kmapped pages backing the object.
756 */
3043c60c 757static int
40123c1f
EA		 758i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
759 struct drm_i915_gem_pwrite *args,
760 struct drm_file *file_priv)
673a394b 761{
23010e43 762 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 763 ssize_t remain;
764 loff_t offset, page_base;
765 char __user *user_data;
766 int page_offset, page_length;
673a394b 767 int ret;
40123c1f
EA		 768
769 user_data = (char __user *) (uintptr_t) args->data_ptr;
770 remain = args->size;
673a394b
EA		 771
772 mutex_lock(&dev->struct_mutex);
773
4bdadb97 774 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 775 if (ret != 0)
776 goto fail_unlock;
673a394b 777
e47c68e9 778 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 779 if (ret != 0)
780 goto fail_put_pages;
781
23010e43 782 obj_priv = to_intel_bo(obj);
40123c1f
EA		 783 offset = args->offset;
784 obj_priv->dirty = 1;
785
786 while (remain > 0) {
787 /* Operation in this page
788 *
789 * page_base = page offset within aperture
790 * page_offset = offset within page
791 * page_length = bytes to copy for this page
792 */
793 page_base = (offset & ~(PAGE_SIZE-1));
794 page_offset = offset & (PAGE_SIZE-1);
795 page_length = remain;
796 if ((page_offset + remain) > PAGE_SIZE)
797 page_length = PAGE_SIZE - page_offset;
798
799 ret = fast_shmem_write(obj_priv->pages,
800 page_base, page_offset,
801 user_data, page_length);
802 if (ret)
803 goto fail_put_pages;
804
805 remain -= page_length;
806 user_data += page_length;
807 offset += page_length;
808 }
809
810fail_put_pages:
811 i915_gem_object_put_pages(obj);
812fail_unlock:
813 mutex_unlock(&dev->struct_mutex);
814
815 return ret;
816}
817
818/**
819 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
820 * the memory and maps it using kmap_atomic for copying.
821 *
822 * This avoids taking mmap_sem for faulting on the user's address while the
823 * struct_mutex is held.
824 */
825static int
826i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
827 struct drm_i915_gem_pwrite *args,
828 struct drm_file *file_priv)
829{
23010e43 830 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 831 struct mm_struct *mm = current->mm;
832 struct page **user_pages;
833 ssize_t remain;
834 loff_t offset, pinned_pages, i;
835 loff_t first_data_page, last_data_page, num_pages;
836 int shmem_page_index, shmem_page_offset;
837 int data_page_index, data_page_offset;
838 int page_length;
839 int ret;
840 uint64_t data_ptr = args->data_ptr;
280b713b 841 int do_bit17_swizzling;
40123c1f
EA		 842
843 remain = args->size;
844
845 /* Pin the user pages containing the data. We can't fault while
846 * holding the struct mutex, and all of the pwrite implementations
847 * want to hold it while dereferencing the user data.
848 */
849 first_data_page = data_ptr / PAGE_SIZE;
850 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
851 num_pages = last_data_page - first_data_page + 1;
852
8e7d2b2c 853 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 854 if (user_pages == NULL)
855 return -ENOMEM;
856
857 down_read(&mm->mmap_sem);
858 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
859 num_pages, 0, 0, user_pages, NULL);
860 up_read(&mm->mmap_sem);
861 if (pinned_pages < num_pages) {
862 ret = -EFAULT;
863 goto fail_put_user_pages;
673a394b
EA		 864 }
865
280b713b
EA		 866 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
867
40123c1f
EA		 868 mutex_lock(&dev->struct_mutex);
869
07f73f69
CW		 870 ret = i915_gem_object_get_pages_or_evict(obj);
871 if (ret)
40123c1f
EA		 872 goto fail_unlock;
873
874 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
875 if (ret != 0)
876 goto fail_put_pages;
877
23010e43 878 obj_priv = to_intel_bo(obj);
673a394b 879 offset = args->offset;
40123c1f 880 obj_priv->dirty = 1;
673a394b 881
40123c1f
EA		 882 while (remain > 0) {
883 /* Operation in this page
884 *
885 * shmem_page_index = page number within shmem file
886 * shmem_page_offset = offset within page in shmem file
887 * data_page_index = page number in get_user_pages return
888 * data_page_offset = offset with data_page_index page.
889 * page_length = bytes to copy for this page
890 */
891 shmem_page_index = offset / PAGE_SIZE;
892 shmem_page_offset = offset & ~PAGE_MASK;
893 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
894 data_page_offset = data_ptr & ~PAGE_MASK;
895
896 page_length = remain;
897 if ((shmem_page_offset + page_length) > PAGE_SIZE)
898 page_length = PAGE_SIZE - shmem_page_offset;
899 if ((data_page_offset + page_length) > PAGE_SIZE)
900 page_length = PAGE_SIZE - data_page_offset;
901
280b713b
EA		 902 if (do_bit17_swizzling) {
903 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
904 shmem_page_offset,
905 user_pages[data_page_index],
906 data_page_offset,
907 page_length,
908 0);
909 } else {
910 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
911 shmem_page_offset,
912 user_pages[data_page_index],
913 data_page_offset,
914 page_length);
915 }
40123c1f
EA		 916 if (ret)
917 goto fail_put_pages;
918
919 remain -= page_length;
920 data_ptr += page_length;
921 offset += page_length;
673a394b
EA		 922 }
923
40123c1f
EA		 924fail_put_pages:
925 i915_gem_object_put_pages(obj);
926fail_unlock:
673a394b 927 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 928fail_put_user_pages:
929 for (i = 0; i < pinned_pages; i++)
930 page_cache_release(user_pages[i]);
8e7d2b2c 931 drm_free_large(user_pages);
673a394b 932
40123c1f 933 return ret;
673a394b
EA		 934}
935
936/**
937 * Writes data to the object referenced by handle.
938 *
939 * On error, the contents of the buffer that were to be modified are undefined.
940 */
941int
942i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
943 struct drm_file *file_priv)
944{
945 struct drm_i915_gem_pwrite *args = data;
946 struct drm_gem_object *obj;
947 struct drm_i915_gem_object *obj_priv;
948 int ret = 0;
949
950 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
951 if (obj == NULL)
952 return -EBADF;
23010e43 953 obj_priv = to_intel_bo(obj);
673a394b
EA		 954
955 /* Bounds check destination.
956 *
957 * XXX: This could use review for overflow issues...
958 */
959 if (args->offset > obj->size || args->size > obj->size ||
960 args->offset + args->size > obj->size) {
bc9025bd 961 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 962 return -EINVAL;
963 }
964
965 /* We can only do the GTT pwrite on untiled buffers, as otherwise
966 * it would end up going through the fenced access, and we'll get
967 * different detiling behavior between reading and writing.
968 * pread/pwrite currently are reading and writing from the CPU
969 * perspective, requiring manual detiling by the client.
970 */
71acb5eb
DA		 971 if (obj_priv->phys_obj)
972 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
973 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
3de09aa3
EA		 974 dev->gtt_total != 0) {
975 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
976 if (ret == -EFAULT) {
977 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
978 file_priv);
979 }
280b713b
EA		 980 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
981 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 982 } else {
983 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
984 if (ret == -EFAULT) {
985 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
986 file_priv);
987 }
988 }
673a394b
EA		 989
990#if WATCH_PWRITE
991 if (ret)
992 DRM_INFO("pwrite failed %d\n", ret);
993#endif
994
bc9025bd 995 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 996
997 return ret;
998}
999
1000/**
2ef7eeaa
EA		 1001 * Called when user space prepares to use an object with the CPU, either
1002 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 1003 */
1004int
1005i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1006 struct drm_file *file_priv)
1007{
a09ba7fa 1008 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1009 struct drm_i915_gem_set_domain *args = data;
1010 struct drm_gem_object *obj;
652c393a 1011 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 1012 uint32_t read_domains = args->read_domains;
1013 uint32_t write_domain = args->write_domain;
673a394b
EA		 1014 int ret;
1015
1016 if (!(dev->driver->driver_features & DRIVER_GEM))
1017 return -ENODEV;
1018
2ef7eeaa 1019 /* Only handle setting domains to types used by the CPU. */
21d509e3 1020 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1021 return -EINVAL;
1022
21d509e3 1023 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1024 return -EINVAL;
1025
1026 /* Having something in the write domain implies it's in the read
1027 * domain, and only that read domain. Enforce that in the request.
1028 */
1029 if (write_domain != 0 && read_domains != write_domain)
1030 return -EINVAL;
1031
673a394b
EA		 1032 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1033 if (obj == NULL)
1034 return -EBADF;
23010e43 1035 obj_priv = to_intel_bo(obj);
673a394b
EA		 1036
1037 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1038
1039 intel_mark_busy(dev, obj);
1040
673a394b 1041#if WATCH_BUF
cfd43c02 1042 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1043 obj, obj->size, read_domains, write_domain);
673a394b 1044#endif
2ef7eeaa
EA		 1045 if (read_domains & I915_GEM_DOMAIN_GTT) {
1046 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1047
a09ba7fa
EA		 1048 /* Update the LRU on the fence for the CPU access that's
1049 * about to occur.
1050 */
1051 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 1052 struct drm_i915_fence_reg *reg =
1053 &dev_priv->fence_regs[obj_priv->fence_reg];
1054 list_move_tail(&reg->lru_list,
a09ba7fa
EA		 1055 &dev_priv->mm.fence_list);
1056 }
1057
02354392
EA		 1058 /* Silently promote "you're not bound, there was nothing to do"
1059 * to success, since the client was just asking us to
1060 * make sure everything was done.
1061 */
1062 if (ret == -EINVAL)
1063 ret = 0;
2ef7eeaa 1064 } else {
e47c68e9 1065 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1066 }
1067
673a394b
EA		 1068 drm_gem_object_unreference(obj);
1069 mutex_unlock(&dev->struct_mutex);
1070 return ret;
1071}
1072
1073/**
1074 * Called when user space has done writes to this buffer
1075 */
1076int
1077i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *file_priv)
1079{
1080 struct drm_i915_gem_sw_finish *args = data;
1081 struct drm_gem_object *obj;
1082 struct drm_i915_gem_object *obj_priv;
1083 int ret = 0;
1084
1085 if (!(dev->driver->driver_features & DRIVER_GEM))
1086 return -ENODEV;
1087
1088 mutex_lock(&dev->struct_mutex);
1089 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1090 if (obj == NULL) {
1091 mutex_unlock(&dev->struct_mutex);
1092 return -EBADF;
1093 }
1094
1095#if WATCH_BUF
cfd43c02 1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1097 __func__, args->handle, obj, obj->size);
1098#endif
23010e43 1099 obj_priv = to_intel_bo(obj);
673a394b
EA		 1100
1101 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1102 if (obj_priv->pin_count)
1103 i915_gem_object_flush_cpu_write_domain(obj);
1104
673a394b
EA		 1105 drm_gem_object_unreference(obj);
1106 mutex_unlock(&dev->struct_mutex);
1107 return ret;
1108}
1109
1110/**
1111 * Maps the contents of an object, returning the address it is mapped
1112 * into.
1113 *
1114 * While the mapping holds a reference on the contents of the object, it doesn't
1115 * imply a ref on the object itself.
1116 */
1117int
1118i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv)
1120{
1121 struct drm_i915_gem_mmap *args = data;
1122 struct drm_gem_object *obj;
1123 loff_t offset;
1124 unsigned long addr;
1125
1126 if (!(dev->driver->driver_features & DRIVER_GEM))
1127 return -ENODEV;
1128
1129 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1130 if (obj == NULL)
1131 return -EBADF;
1132
1133 offset = args->offset;
1134
1135 down_write(&current->mm->mmap_sem);
1136 addr = do_mmap(obj->filp, 0, args->size,
1137 PROT_READ | PROT_WRITE, MAP_SHARED,
1138 args->offset);
1139 up_write(&current->mm->mmap_sem);
bc9025bd 1140 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1141 if (IS_ERR((void *)addr))
1142 return addr;
1143
1144 args->addr_ptr = (uint64_t) addr;
1145
1146 return 0;
1147}
1148
de151cf6
JB		 1149/**
1150 * i915_gem_fault - fault a page into the GTT
1151 * vma: VMA in question
1152 * vmf: fault info
1153 *
1154 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1155 * from userspace. The fault handler takes care of binding the object to
1156 * the GTT (if needed), allocating and programming a fence register (again,
1157 * only if needed based on whether the old reg is still valid or the object
1158 * is tiled) and inserting a new PTE into the faulting process.
1159 *
1160 * Note that the faulting process may involve evicting existing objects
1161 * from the GTT and/or fence registers to make room. So performance may
1162 * suffer if the GTT working set is large or there are few fence registers
1163 * left.
1164 */
1165int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1166{
1167 struct drm_gem_object *obj = vma->vm_private_data;
1168 struct drm_device *dev = obj->dev;
1169 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 1170 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1171 pgoff_t page_offset;
1172 unsigned long pfn;
1173 int ret = 0;
0f973f27 1174 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1175
1176 /* We don't use vmf->pgoff since that has the fake offset */
1177 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1178 PAGE_SHIFT;
1179
1180 /* Now bind it into the GTT if needed */
1181 mutex_lock(&dev->struct_mutex);
1182 if (!obj_priv->gtt_space) {
e67b8ce1 1183 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1184 if (ret)
1185 goto unlock;
07f4f3e8 1186
14b60391 1187 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1188
1189 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1190 if (ret)
1191 goto unlock;
de151cf6
JB		 1192 }
1193
1194 /* Need a new fence register? */
a09ba7fa 1195 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1196 ret = i915_gem_object_get_fence_reg(obj);
c715089f
CW		 1197 if (ret)
1198 goto unlock;
d9ddcb96 1199 }
de151cf6
JB		 1200
1201 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1202 page_offset;
1203
1204 /* Finally, remap it using the new GTT offset */
1205 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1206unlock:
de151cf6
JB		 1207 mutex_unlock(&dev->struct_mutex);
1208
1209 switch (ret) {
c715089f
CW		 1210 case 0:
1211 case -ERESTARTSYS:
1212 return VM_FAULT_NOPAGE;
de151cf6
JB		 1213 case -ENOMEM:
1214 case -EAGAIN:
1215 return VM_FAULT_OOM;
de151cf6 1216 default:
c715089f 1217 return VM_FAULT_SIGBUS;
de151cf6
JB		 1218 }
1219}
1220
1221/**
1222 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1223 * @obj: obj in question
1224 *
1225 * GEM memory mapping works by handing back to userspace a fake mmap offset
1226 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1227 * up the object based on the offset and sets up the various memory mapping
1228 * structures.
1229 *
1230 * This routine allocates and attaches a fake offset for @obj.
1231 */
1232static int
1233i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1234{
1235 struct drm_device *dev = obj->dev;
1236 struct drm_gem_mm *mm = dev->mm_private;
23010e43 1237 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 1238 struct drm_map_list *list;
f77d390c 1239 struct drm_local_map *map;
de151cf6
JB		 1240 int ret = 0;
1241
1242 /* Set the object up for mmap'ing */
1243 list = &obj->map_list;
9a298b2a 1244 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1245 if (!list->map)
1246 return -ENOMEM;
1247
1248 map = list->map;
1249 map->type = _DRM_GEM;
1250 map->size = obj->size;
1251 map->handle = obj;
1252
1253 /* Get a DRM GEM mmap offset allocated... */
1254 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1255 obj->size / PAGE_SIZE, 0, 0);
1256 if (!list->file_offset_node) {
1257 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1258 ret = -ENOMEM;
1259 goto out_free_list;
1260 }
1261
1262 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1263 obj->size / PAGE_SIZE, 0);
1264 if (!list->file_offset_node) {
1265 ret = -ENOMEM;
1266 goto out_free_list;
1267 }
1268
1269 list->hash.key = list->file_offset_node->start;
1270 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1271 DRM_ERROR("failed to add to map hash\n");
5618ca6a 1272 ret = -ENOMEM;
de151cf6
JB		 1273 goto out_free_mm;
1274 }
1275
1276 /* By now we should be all set, any drm_mmap request on the offset
1277 * below will get to our mmap & fault handler */
1278 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1279
1280 return 0;
1281
1282out_free_mm:
1283 drm_mm_put_block(list->file_offset_node);
1284out_free_list:
9a298b2a 1285 kfree(list->map);
de151cf6
JB		 1286
1287 return ret;
1288}
1289
901782b2
CW		 1290/**
1291 * i915_gem_release_mmap - remove physical page mappings
1292 * @obj: obj in question
1293 *
af901ca1 1294 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1295 * relinquish ownership of the pages back to the system.
1296 *
1297 * It is vital that we remove the page mapping if we have mapped a tiled
1298 * object through the GTT and then lose the fence register due to
1299 * resource pressure. Similarly if the object has been moved out of the
1300 * aperture, than pages mapped into userspace must be revoked. Removing the
1301 * mapping will then trigger a page fault on the next user access, allowing
1302 * fixup by i915_gem_fault().
1303 */
d05ca301 1304void
901782b2
CW		 1305i915_gem_release_mmap(struct drm_gem_object *obj)
1306{
1307 struct drm_device *dev = obj->dev;
23010e43 1308 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
901782b2
CW		 1309
1310 if (dev->dev_mapping)
1311 unmap_mapping_range(dev->dev_mapping,
1312 obj_priv->mmap_offset, obj->size, 1);
1313}
1314
ab00b3e5
JB		 1315static void
1316i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1317{
1318 struct drm_device *dev = obj->dev;
23010e43 1319 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ab00b3e5
JB		 1320 struct drm_gem_mm *mm = dev->mm_private;
1321 struct drm_map_list *list;
1322
1323 list = &obj->map_list;
1324 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1325
1326 if (list->file_offset_node) {
1327 drm_mm_put_block(list->file_offset_node);
1328 list->file_offset_node = NULL;
1329 }
1330
1331 if (list->map) {
9a298b2a 1332 kfree(list->map);
ab00b3e5
JB		 1333 list->map = NULL;
1334 }
1335
1336 obj_priv->mmap_offset = 0;
1337}
1338
de151cf6
JB		 1339/**
1340 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1341 * @obj: object to check
1342 *
1343 * Return the required GTT alignment for an object, taking into account
1344 * potential fence register mapping if needed.
1345 */
1346static uint32_t
1347i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1348{
1349 struct drm_device *dev = obj->dev;
23010e43 1350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1351 int start, i;
1352
1353 /*
1354 * Minimum alignment is 4k (GTT page size), but might be greater
1355 * if a fence register is needed for the object.
1356 */
1357 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1358 return 4096;
1359
1360 /*
1361 * Previous chips need to be aligned to the size of the smallest
1362 * fence register that can contain the object.
1363 */
1364 if (IS_I9XX(dev))
1365 start = 1024*1024;
1366 else
1367 start = 512*1024;
1368
1369 for (i = start; i < obj->size; i <<= 1)
1370 ;
1371
1372 return i;
1373}
1374
1375/**
1376 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1377 * @dev: DRM device
1378 * @data: GTT mapping ioctl data
1379 * @file_priv: GEM object info
1380 *
1381 * Simply returns the fake offset to userspace so it can mmap it.
1382 * The mmap call will end up in drm_gem_mmap(), which will set things
1383 * up so we can get faults in the handler above.
1384 *
1385 * The fault handler will take care of binding the object into the GTT
1386 * (since it may have been evicted to make room for something), allocating
1387 * a fence register, and mapping the appropriate aperture address into
1388 * userspace.
1389 */
1390int
1391i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1392 struct drm_file *file_priv)
1393{
1394 struct drm_i915_gem_mmap_gtt *args = data;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 struct drm_gem_object *obj;
1397 struct drm_i915_gem_object *obj_priv;
1398 int ret;
1399
1400 if (!(dev->driver->driver_features & DRIVER_GEM))
1401 return -ENODEV;
1402
1403 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1404 if (obj == NULL)
1405 return -EBADF;
1406
1407 mutex_lock(&dev->struct_mutex);
1408
23010e43 1409 obj_priv = to_intel_bo(obj);
de151cf6 1410
ab18282d
CW		 1411 if (obj_priv->madv != I915_MADV_WILLNEED) {
1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
1415 return -EINVAL;
1416 }
1417
1418
de151cf6
JB		 1419 if (!obj_priv->mmap_offset) {
1420 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1421 if (ret) {
1422 drm_gem_object_unreference(obj);
1423 mutex_unlock(&dev->struct_mutex);
de151cf6 1424 return ret;
13af1062 1425 }
de151cf6
JB		 1426 }
1427
1428 args->offset = obj_priv->mmap_offset;
1429
de151cf6
JB		 1430 /*
1431 * Pull it into the GTT so that we have a page list (makes the
1432 * initial fault faster and any subsequent flushing possible).
1433 */
1434 if (!obj_priv->agp_mem) {
e67b8ce1 1435 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1436 if (ret) {
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1439 return ret;
1440 }
14b60391 1441 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1442 }
1443
1444 drm_gem_object_unreference(obj);
1445 mutex_unlock(&dev->struct_mutex);
1446
1447 return 0;
1448}
1449
6911a9b8 1450void
856fa198 1451i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b 1452{
23010e43 1453 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1454 int page_count = obj->size / PAGE_SIZE;
1455 int i;
1456
856fa198 1457 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1458 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1459
856fa198
EA		 1460 if (--obj_priv->pages_refcount != 0)
1461 return;
673a394b 1462
280b713b
EA		 1463 if (obj_priv->tiling_mode != I915_TILING_NONE)
1464 i915_gem_object_save_bit_17_swizzle(obj);
1465
3ef94daa 1466 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1467 obj_priv->dirty = 0;
3ef94daa
CW		 1468
1469 for (i = 0; i < page_count; i++) {
3ef94daa
CW		 1470 if (obj_priv->dirty)
1471 set_page_dirty(obj_priv->pages[i]);
1472
1473 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1474 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1475
1476 page_cache_release(obj_priv->pages[i]);
1477 }
673a394b
EA		 1478 obj_priv->dirty = 0;
1479
8e7d2b2c 1480 drm_free_large(obj_priv->pages);
856fa198 1481 obj_priv->pages = NULL;
673a394b
EA		 1482}
1483
1484static void
ce44b0ea 1485i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
673a394b
EA		 1486{
1487 struct drm_device *dev = obj->dev;
1488 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1489 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1490
1491 /* Add a reference if we're newly entering the active list. */
1492 if (!obj_priv->active) {
1493 drm_gem_object_reference(obj);
1494 obj_priv->active = 1;
1495 }
1496 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1497 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1498 list_move_tail(&obj_priv->list,
1499 &dev_priv->mm.active_list);
5e118f41 1500 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1501 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1502}
1503
ce44b0ea
EA		 1504static void
1505i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1506{
1507 struct drm_device *dev = obj->dev;
1508 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1509 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ce44b0ea
EA		 1510
1511 BUG_ON(!obj_priv->active);
1512 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1513 obj_priv->last_rendering_seqno = 0;
1514}
673a394b 1515
963b4836
CW		 1516/* Immediately discard the backing storage */
1517static void
1518i915_gem_object_truncate(struct drm_gem_object *obj)
1519{
23010e43 1520 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bb6baf76 1521 struct inode *inode;
963b4836 1522
bb6baf76
CW		 1523 inode = obj->filp->f_path.dentry->d_inode;
1524 if (inode->i_op->truncate)
1525 inode->i_op->truncate (inode);
1526
1527 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1528}
1529
1530static inline int
1531i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1532{
1533 return obj_priv->madv == I915_MADV_DONTNEED;
1534}
1535
673a394b
EA		 1536static void
1537i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1538{
1539 struct drm_device *dev = obj->dev;
1540 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1541 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1542
1543 i915_verify_inactive(dev, __FILE__, __LINE__);
1544 if (obj_priv->pin_count != 0)
1545 list_del_init(&obj_priv->list);
1546 else
1547 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1548
99fcb766
DV		 1549 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1550
ce44b0ea 1551 obj_priv->last_rendering_seqno = 0;
673a394b
EA		 1552 if (obj_priv->active) {
1553 obj_priv->active = 0;
1554 drm_gem_object_unreference(obj);
1555 }
1556 i915_verify_inactive(dev, __FILE__, __LINE__);
1557}
1558
63560396
DV		 1559static void
1560i915_gem_process_flushing_list(struct drm_device *dev,
1561 uint32_t flush_domains, uint32_t seqno)
1562{
1563 drm_i915_private_t *dev_priv = dev->dev_private;
1564 struct drm_i915_gem_object *obj_priv, *next;
1565
1566 list_for_each_entry_safe(obj_priv, next,
1567 &dev_priv->mm.gpu_write_list,
1568 gpu_write_list) {
a8089e84 1569 struct drm_gem_object *obj = &obj_priv->base;
63560396
DV		 1570
1571 if ((obj->write_domain & flush_domains) ==
1572 obj->write_domain) {
1573 uint32_t old_write_domain = obj->write_domain;
1574
1575 obj->write_domain = 0;
1576 list_del_init(&obj_priv->gpu_write_list);
1577 i915_gem_object_move_to_active(obj, seqno);
1578
1579 /* update the fence lru list */
007cc8ac
DV		 1580 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1581 struct drm_i915_fence_reg *reg =
1582 &dev_priv->fence_regs[obj_priv->fence_reg];
1583 list_move_tail(&reg->lru_list,
63560396 1584 &dev_priv->mm.fence_list);
007cc8ac 1585 }
63560396
DV		 1586
1587 trace_i915_gem_object_change_domain(obj,
1588 obj->read_domains,
1589 old_write_domain);
1590 }
1591 }
1592}
8187a2b7 1593
5a5a0c64 1594uint32_t
b962442e
EA		 1595i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1596 uint32_t flush_domains)
673a394b
EA		 1597{
1598 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1599 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1600 struct drm_i915_gem_request *request;
1601 uint32_t seqno;
1602 int was_empty;
673a394b 1603
b962442e
EA		 1604 if (file_priv != NULL)
1605 i915_file_priv = file_priv->driver_priv;
1606
9a298b2a 1607 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1608 if (request == NULL)
1609 return 0;
1610
8187a2b7
ZN		 1611 seqno = dev_priv->render_ring.add_request(dev, &dev_priv->render_ring,
1612 file_priv, flush_domains);
673a394b 1613
44d98a61 1614 DRM_DEBUG_DRIVER("%d\n", seqno);
673a394b
EA		 1615
1616 request->seqno = seqno;
1617 request->emitted_jiffies = jiffies;
673a394b
EA		 1618 was_empty = list_empty(&dev_priv->mm.request_list);
1619 list_add_tail(&request->list, &dev_priv->mm.request_list);
b962442e
EA		 1620 if (i915_file_priv) {
1621 list_add_tail(&request->client_list,
1622 &i915_file_priv->mm.request_list);
1623 } else {
1624 INIT_LIST_HEAD(&request->client_list);
1625 }
673a394b 1626
ce44b0ea
EA		 1627 /* Associate any objects on the flushing list matching the write
1628 * domain we're flushing with our flush.
1629 */
63560396
DV		 1630 if (flush_domains != 0)
1631 i915_gem_process_flushing_list(dev, flush_domains, seqno);
ce44b0ea 1632
f65d9421
BG		 1633 if (!dev_priv->mm.suspended) {
1634 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1635 if (was_empty)
1636 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1637 }
673a394b
EA		 1638 return seqno;
1639}
1640
1641/**
1642 * Command execution barrier
1643 *
1644 * Ensures that all commands in the ring are finished
1645 * before signalling the CPU
1646 */
3043c60c 1647static uint32_t
673a394b
EA		 1648i915_retire_commands(struct drm_device *dev)
1649{
673a394b
EA		 1650 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1651 uint32_t flush_domains = 0;
673a394b
EA		 1652
1653 /* The sampler always gets flushed on i965 (sigh) */
1654 if (IS_I965G(dev))
1655 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1656 BEGIN_LP_RING(2);
1657 OUT_RING(cmd);
1658 OUT_RING(0); /* noop */
1659 ADVANCE_LP_RING();
1660 return flush_domains;
1661}
1662
1663/**
1664 * Moves buffers associated only with the given active seqno from the active
1665 * to inactive list, potentially freeing them.
1666 */
1667static void
1668i915_gem_retire_request(struct drm_device *dev,
1669 struct drm_i915_gem_request *request)
1670{
1671 drm_i915_private_t *dev_priv = dev->dev_private;
1672
1c5d22f7
CW		 1673 trace_i915_gem_request_retire(dev, request->seqno);
1674
673a394b
EA		 1675 /* Move any buffers on the active list that are no longer referenced
1676 * by the ringbuffer to the flushing/inactive lists as appropriate.
1677 */
5e118f41 1678 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1679 while (!list_empty(&dev_priv->mm.active_list)) {
1680 struct drm_gem_object *obj;
1681 struct drm_i915_gem_object *obj_priv;
1682
1683 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1684 struct drm_i915_gem_object,
1685 list);
a8089e84 1686 obj = &obj_priv->base;
673a394b
EA		 1687
1688 /* If the seqno being retired doesn't match the oldest in the
1689 * list, then the oldest in the list must still be newer than
1690 * this seqno.
1691 */
1692 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1693 goto out;
de151cf6 1694
673a394b
EA		 1695#if WATCH_LRU
1696 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1697 __func__, request->seqno, obj);
1698#endif
1699
ce44b0ea
EA		 1700 if (obj->write_domain != 0)
1701 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1702 else {
1703 /* Take a reference on the object so it won't be
1704 * freed while the spinlock is held. The list
1705 * protection for this spinlock is safe when breaking
1706 * the lock like this since the next thing we do
1707 * is just get the head of the list again.
1708 */
1709 drm_gem_object_reference(obj);
673a394b 1710 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1711 spin_unlock(&dev_priv->mm.active_list_lock);
1712 drm_gem_object_unreference(obj);
1713 spin_lock(&dev_priv->mm.active_list_lock);
1714 }
673a394b 1715 }
5e118f41
CW		 1716out:
1717 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1718}
1719
1720/**
1721 * Returns true if seq1 is later than seq2.
1722 */
22be1724 1723bool
673a394b
EA		 1724i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1725{
1726 return (int32_t)(seq1 - seq2) >= 0;
1727}
1728
1729uint32_t
1730i915_get_gem_seqno(struct drm_device *dev)
1731{
1732 drm_i915_private_t *dev_priv = dev->dev_private;
1733
1918ad77 1734 if (HAS_PIPE_CONTROL(dev))
e552eb70
JB		 1735 return ((volatile u32 *)(dev_priv->seqno_page))[0];
1736 else
1737 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
673a394b
EA		 1738}
1739
1740/**
1741 * This function clears the request list as sequence numbers are passed.
1742 */
1743void
1744i915_gem_retire_requests(struct drm_device *dev)
1745{
1746 drm_i915_private_t *dev_priv = dev->dev_private;
1747 uint32_t seqno;
1748
8187a2b7
ZN		 1749 struct intel_ring_buffer *ring = &(dev_priv->render_ring);
1750 if (!ring->status_page.page_addr
1751 || list_empty(&dev_priv->mm.request_list))
6c0594a3
KW		 1752 return;
1753
673a394b
EA		 1754 seqno = i915_get_gem_seqno(dev);
1755
1756 while (!list_empty(&dev_priv->mm.request_list)) {
1757 struct drm_i915_gem_request *request;
1758 uint32_t retiring_seqno;
1759
1760 request = list_first_entry(&dev_priv->mm.request_list,
1761 struct drm_i915_gem_request,
1762 list);
1763 retiring_seqno = request->seqno;
1764
1765 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1766 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1767 i915_gem_retire_request(dev, request);
1768
1769 list_del(&request->list);
b962442e 1770 list_del(&request->client_list);
9a298b2a 1771 kfree(request);
673a394b
EA		 1772 } else
1773 break;
1774 }
9d34e5db
CW		 1775
1776 if (unlikely (dev_priv->trace_irq_seqno &&
1777 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
8187a2b7
ZN		 1778
1779 ring->user_irq_put(dev, ring);
9d34e5db
CW		 1780 dev_priv->trace_irq_seqno = 0;
1781 }
673a394b
EA		 1782}
1783
1784void
1785i915_gem_retire_work_handler(struct work_struct *work)
1786{
1787 drm_i915_private_t *dev_priv;
1788 struct drm_device *dev;
1789
1790 dev_priv = container_of(work, drm_i915_private_t,
1791 mm.retire_work.work);
1792 dev = dev_priv->dev;
1793
1794 mutex_lock(&dev->struct_mutex);
1795 i915_gem_retire_requests(dev);
6dbe2772
KP		 1796 if (!dev_priv->mm.suspended &&
1797 !list_empty(&dev_priv->mm.request_list))
9c9fe1f8 1798 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1799 mutex_unlock(&dev->struct_mutex);
1800}
1801
5a5a0c64 1802int
48764bf4 1803i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
673a394b
EA		 1804{
1805 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1806 u32 ier;
673a394b
EA		 1807 int ret = 0;
1808
8187a2b7 1809 struct intel_ring_buffer *ring = &dev_priv->render_ring;
673a394b
EA		 1810 BUG_ON(seqno == 0);
1811
ba1234d1 1812 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1813 return -EIO;
1814
673a394b 1815 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
bad720ff 1816 if (HAS_PCH_SPLIT(dev))
036a4a7d
ZW		 1817 ier = I915_READ(DEIER) | I915_READ(GTIER);
1818 else
1819 ier = I915_READ(IER);
802c7eb6
JB		 1820 if (!ier) {
1821 DRM_ERROR("something (likely vbetool) disabled "
1822 "interrupts, re-enabling\n");
1823 i915_driver_irq_preinstall(dev);
1824 i915_driver_irq_postinstall(dev);
1825 }
1826
1c5d22f7
CW		 1827 trace_i915_gem_request_wait_begin(dev, seqno);
1828
673a394b 1829 dev_priv->mm.waiting_gem_seqno = seqno;
8187a2b7 1830 ring->user_irq_get(dev, ring);
48764bf4
DV		 1831 if (interruptible)
1832 ret = wait_event_interruptible(dev_priv->irq_queue,
1833 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1834 atomic_read(&dev_priv->mm.wedged));
1835 else
1836 wait_event(dev_priv->irq_queue,
1837 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1838 atomic_read(&dev_priv->mm.wedged));
1839
8187a2b7 1840 ring->user_irq_put(dev, ring);
673a394b 1841 dev_priv->mm.waiting_gem_seqno = 0;
1c5d22f7
CW		 1842
1843 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1844 }
ba1234d1 1845 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1846 ret = -EIO;
1847
1848 if (ret && ret != -ERESTARTSYS)
1849 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1850 __func__, ret, seqno, i915_get_gem_seqno(dev));
1851
1852 /* Directly dispatch request retiring. While we have the work queue
1853 * to handle this, the waiter on a request often wants an associated
1854 * buffer to have made it to the inactive list, and we would need
1855 * a separate wait queue to handle that.
1856 */
1857 if (ret == 0)
1858 i915_gem_retire_requests(dev);
1859
1860 return ret;
1861}
1862
48764bf4
DV		 1863/**
1864 * Waits for a sequence number to be signaled, and cleans up the
1865 * request and object lists appropriately for that event.
1866 */
1867static int
1868i915_wait_request(struct drm_device *dev, uint32_t seqno)
1869{
1870 return i915_do_wait_request(dev, seqno, 1);
1871}
1872
673a394b 1873
8187a2b7
ZN		 1874static void
1875i915_gem_flush(struct drm_device *dev,
1876 uint32_t invalidate_domains,
1877 uint32_t flush_domains)
1878{
1879 drm_i915_private_t *dev_priv = dev->dev_private;
1880 if (flush_domains & I915_GEM_DOMAIN_CPU)
1881 drm_agp_chipset_flush(dev);
1882 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1883 invalidate_domains,
1884 flush_domains);
1885}
1886
673a394b
EA		 1887/**
1888 * Ensures that all rendering to the object has completed and the object is
1889 * safe to unbind from the GTT or access from the CPU.
1890 */
1891static int
1892i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1893{
1894 struct drm_device *dev = obj->dev;
23010e43 1895 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1896 int ret;
1897
e47c68e9
EA		 1898 /* This function only exists to support waiting for existing rendering,
1899 * not for emitting required flushes.
673a394b 1900 */
e47c68e9 1901 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1902
1903 /* If there is rendering queued on the buffer being evicted, wait for
1904 * it.
1905 */
1906 if (obj_priv->active) {
1907#if WATCH_BUF
1908 DRM_INFO("%s: object %p wait for seqno %08x\n",
1909 __func__, obj, obj_priv->last_rendering_seqno);
1910#endif
1911 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1912 if (ret != 0)
1913 return ret;
1914 }
1915
1916 return 0;
1917}
1918
1919/**
1920 * Unbinds an object from the GTT aperture.
1921 */
0f973f27 1922int
673a394b
EA		 1923i915_gem_object_unbind(struct drm_gem_object *obj)
1924{
1925 struct drm_device *dev = obj->dev;
4a87b8ca 1926 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1927 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1928 int ret = 0;
1929
1930#if WATCH_BUF
1931 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1932 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1933#endif
1934 if (obj_priv->gtt_space == NULL)
1935 return 0;
1936
1937 if (obj_priv->pin_count != 0) {
1938 DRM_ERROR("Attempting to unbind pinned buffer\n");
1939 return -EINVAL;
1940 }
1941
5323fd04
EA		 1942 /* blow away mappings if mapped through GTT */
1943 i915_gem_release_mmap(obj);
1944
673a394b
EA		 1945 /* Move the object to the CPU domain to ensure that
1946 * any possible CPU writes while it's not in the GTT
1947 * are flushed when we go to remap it. This will
1948 * also ensure that all pending GPU writes are finished
1949 * before we unbind.
1950 */
e47c68e9 1951 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 1952 if (ret) {
e47c68e9
EA		 1953 if (ret != -ERESTARTSYS)
1954 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 1955 return ret;
1956 }
1957
5323fd04
EA		 1958 BUG_ON(obj_priv->active);
1959
96b47b65
DV		 1960 /* release the fence reg _after_ flushing */
1961 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1962 i915_gem_clear_fence_reg(obj);
1963
673a394b
EA		 1964 if (obj_priv->agp_mem != NULL) {
1965 drm_unbind_agp(obj_priv->agp_mem);
1966 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1967 obj_priv->agp_mem = NULL;
1968 }
1969
856fa198 1970 i915_gem_object_put_pages(obj);
a32808c0 1971 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 1972
1973 if (obj_priv->gtt_space) {
1974 atomic_dec(&dev->gtt_count);
1975 atomic_sub(obj->size, &dev->gtt_memory);
1976
1977 drm_mm_put_block(obj_priv->gtt_space);
1978 obj_priv->gtt_space = NULL;
1979 }
1980
1981 /* Remove ourselves from the LRU list if present. */
4a87b8ca 1982 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1983 if (!list_empty(&obj_priv->list))
1984 list_del_init(&obj_priv->list);
4a87b8ca 1985 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b 1986
963b4836
CW		 1987 if (i915_gem_object_is_purgeable(obj_priv))
1988 i915_gem_object_truncate(obj);
1989
1c5d22f7
CW		 1990 trace_i915_gem_object_unbind(obj);
1991
673a394b
EA		 1992 return 0;
1993}
1994
07f73f69
CW		 1995static struct drm_gem_object *
1996i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
1997{
1998 drm_i915_private_t *dev_priv = dev->dev_private;
1999 struct drm_i915_gem_object *obj_priv;
2000 struct drm_gem_object *best = NULL;
2001 struct drm_gem_object *first = NULL;
2002
2003 /* Try to find the smallest clean object */
2004 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
a8089e84 2005 struct drm_gem_object *obj = &obj_priv->base;
07f73f69 2006 if (obj->size >= min_size) {
963b4836
CW		 2007 if ((!obj_priv->dirty ||
2008 i915_gem_object_is_purgeable(obj_priv)) &&
07f73f69
CW		 2009 (!best || obj->size < best->size)) {
2010 best = obj;
2011 if (best->size == min_size)
2012 return best;
2013 }
2014 if (!first)
2015 first = obj;
2016 }
2017 }
2018
2019 return best ? best : first;
2020}
2021
4df2faf4
DV		 2022static int
2023i915_gpu_idle(struct drm_device *dev)
2024{
2025 drm_i915_private_t *dev_priv = dev->dev_private;
2026 bool lists_empty;
2027 uint32_t seqno;
2028
2029 spin_lock(&dev_priv->mm.active_list_lock);
2030 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
2031 list_empty(&dev_priv->mm.active_list);
2032 spin_unlock(&dev_priv->mm.active_list_lock);
2033
2034 if (lists_empty)
2035 return 0;
2036
2037 /* Flush everything onto the inactive list. */
2038 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2039 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2040 if (seqno == 0)
2041 return -ENOMEM;
2042
2043 return i915_wait_request(dev, seqno);
2044}
2045
673a394b 2046static int
07f73f69
CW		 2047i915_gem_evict_everything(struct drm_device *dev)
2048{
2049 drm_i915_private_t *dev_priv = dev->dev_private;
07f73f69
CW		 2050 int ret;
2051 bool lists_empty;
2052
07f73f69
CW		 2053 spin_lock(&dev_priv->mm.active_list_lock);
2054 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2055 list_empty(&dev_priv->mm.flushing_list) &&
2056 list_empty(&dev_priv->mm.active_list));
2057 spin_unlock(&dev_priv->mm.active_list_lock);
2058
9731129c 2059 if (lists_empty)
07f73f69 2060 return -ENOSPC;
07f73f69
CW		 2061
2062 /* Flush everything (on to the inactive lists) and evict */
4df2faf4 2063 ret = i915_gpu_idle(dev);
07f73f69
CW		 2064 if (ret)
2065 return ret;
2066
99fcb766
DV		 2067 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2068
ab5ee576 2069 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2070 if (ret)
2071 return ret;
2072
2073 spin_lock(&dev_priv->mm.active_list_lock);
2074 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2075 list_empty(&dev_priv->mm.flushing_list) &&
2076 list_empty(&dev_priv->mm.active_list));
2077 spin_unlock(&dev_priv->mm.active_list_lock);
2078 BUG_ON(!lists_empty);
2079
2080 return 0;
2081}
2082
673a394b 2083static int
07f73f69 2084i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2085{
2086 drm_i915_private_t *dev_priv = dev->dev_private;
2087 struct drm_gem_object *obj;
07f73f69 2088 int ret;
673a394b
EA		 2089
2090 for (;;) {
07f73f69
CW		 2091 i915_gem_retire_requests(dev);
2092
673a394b
EA		 2093 /* If there's an inactive buffer available now, grab it
2094 * and be done.
2095 */
07f73f69
CW		 2096 obj = i915_gem_find_inactive_object(dev, min_size);
2097 if (obj) {
2098 struct drm_i915_gem_object *obj_priv;
2099
673a394b
EA		 2100#if WATCH_LRU
2101 DRM_INFO("%s: evicting %p\n", __func__, obj);
2102#endif
23010e43 2103 obj_priv = to_intel_bo(obj);
07f73f69 2104 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2105 BUG_ON(obj_priv->active);
2106
2107 /* Wait on the rendering and unbind the buffer. */
07f73f69 2108 return i915_gem_object_unbind(obj);
673a394b
EA		 2109 }
2110
2111 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2112 * things, wait for the next to finish and hopefully leave us
2113 * a buffer to evict.
673a394b
EA		 2114 */
2115 if (!list_empty(&dev_priv->mm.request_list)) {
2116 struct drm_i915_gem_request *request;
2117
2118 request = list_first_entry(&dev_priv->mm.request_list,
2119 struct drm_i915_gem_request,
2120 list);
2121
2122 ret = i915_wait_request(dev, request->seqno);
2123 if (ret)
07f73f69 2124 return ret;
673a394b 2125
07f73f69 2126 continue;
673a394b
EA		 2127 }
2128
2129 /* If we didn't have anything on the request list but there
2130 * are buffers awaiting a flush, emit one and try again.
2131 * When we wait on it, those buffers waiting for that flush
2132 * will get moved to inactive.
2133 */
2134 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2135 struct drm_i915_gem_object *obj_priv;
673a394b 2136
9a1e2582
CW		 2137 /* Find an object that we can immediately reuse */
2138 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
a8089e84 2139 obj = &obj_priv->base;
9a1e2582
CW		 2140 if (obj->size >= min_size)
2141 break;
673a394b 2142
9a1e2582
CW		 2143 obj = NULL;
2144 }
673a394b 2145
9a1e2582
CW		 2146 if (obj != NULL) {
2147 uint32_t seqno;
673a394b 2148
9a1e2582
CW		 2149 i915_gem_flush(dev,
2150 obj->write_domain,
2151 obj->write_domain);
2152 seqno = i915_add_request(dev, NULL, obj->write_domain);
2153 if (seqno == 0)
2154 return -ENOMEM;
9a1e2582
CW		 2155 continue;
2156 }
673a394b
EA		 2157 }
2158
07f73f69
CW		 2159 /* If we didn't do any of the above, there's no single buffer
2160 * large enough to swap out for the new one, so just evict
2161 * everything and start again. (This should be rare.)
673a394b 2162 */
9731129c 2163 if (!list_empty (&dev_priv->mm.inactive_list))
ab5ee576 2164 return i915_gem_evict_from_inactive_list(dev);
9731129c 2165 else
07f73f69 2166 return i915_gem_evict_everything(dev);
ac94a962 2167 }
ac94a962
KP		 2168}
2169
6911a9b8 2170int
4bdadb97
CW		 2171i915_gem_object_get_pages(struct drm_gem_object *obj,
2172 gfp_t gfpmask)
673a394b 2173{
23010e43 2174 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2175 int page_count, i;
2176 struct address_space *mapping;
2177 struct inode *inode;
2178 struct page *page;
673a394b 2179
856fa198 2180 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2181 return 0;
2182
2183 /* Get the list of pages out of our struct file. They'll be pinned
2184 * at this point until we release them.
2185 */
2186 page_count = obj->size / PAGE_SIZE;
856fa198 2187 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2188 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2189 if (obj_priv->pages == NULL) {
856fa198 2190 obj_priv->pages_refcount--;
673a394b
EA		 2191 return -ENOMEM;
2192 }
2193
2194 inode = obj->filp->f_path.dentry->d_inode;
2195 mapping = inode->i_mapping;
2196 for (i = 0; i < page_count; i++) {
4bdadb97
CW		 2197 page = read_cache_page_gfp(mapping, i,
2198 mapping_gfp_mask (mapping) |
2199 __GFP_COLD |
2200 gfpmask);
1f2b1013
CW		 2201 if (IS_ERR(page))
2202 goto err_pages;
2203
856fa198 2204 obj_priv->pages[i] = page;
673a394b 2205 }
280b713b
EA		 2206
2207 if (obj_priv->tiling_mode != I915_TILING_NONE)
2208 i915_gem_object_do_bit_17_swizzle(obj);
2209
673a394b 2210 return 0;
1f2b1013
CW		 2211
2212err_pages:
2213 while (i--)
2214 page_cache_release(obj_priv->pages[i]);
2215
2216 drm_free_large(obj_priv->pages);
2217 obj_priv->pages = NULL;
2218 obj_priv->pages_refcount--;
2219 return PTR_ERR(page);
673a394b
EA		 2220}
2221
4e901fdc
EA		 2222static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2223{
2224 struct drm_gem_object *obj = reg->obj;
2225 struct drm_device *dev = obj->dev;
2226 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2227 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4e901fdc
EA		 2228 int regnum = obj_priv->fence_reg;
2229 uint64_t val;
2230
2231 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2232 0xfffff000) << 32;
2233 val |= obj_priv->gtt_offset & 0xfffff000;
2234 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2235 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2236
2237 if (obj_priv->tiling_mode == I915_TILING_Y)
2238 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2239 val |= I965_FENCE_REG_VALID;
2240
2241 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2242}
2243
de151cf6
JB		 2244static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2245{
2246 struct drm_gem_object *obj = reg->obj;
2247 struct drm_device *dev = obj->dev;
2248 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2249 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2250 int regnum = obj_priv->fence_reg;
2251 uint64_t val;
2252
2253 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2254 0xfffff000) << 32;
2255 val |= obj_priv->gtt_offset & 0xfffff000;
2256 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2257 if (obj_priv->tiling_mode == I915_TILING_Y)
2258 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2259 val |= I965_FENCE_REG_VALID;
2260
2261 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2262}
2263
2264static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2265{
2266 struct drm_gem_object *obj = reg->obj;
2267 struct drm_device *dev = obj->dev;
2268 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2269 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2270 int regnum = obj_priv->fence_reg;
0f973f27 2271 int tile_width;
dc529a4f 2272 uint32_t fence_reg, val;
de151cf6
JB		 2273 uint32_t pitch_val;
2274
2275 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2276 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2277 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2278 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2279 return;
2280 }
2281
0f973f27
JB		 2282 if (obj_priv->tiling_mode == I915_TILING_Y &&
2283 HAS_128_BYTE_Y_TILING(dev))
2284 tile_width = 128;
de151cf6 2285 else
0f973f27
JB		 2286 tile_width = 512;
2287
2288 /* Note: pitch better be a power of two tile widths */
2289 pitch_val = obj_priv->stride / tile_width;
2290 pitch_val = ffs(pitch_val) - 1;
de151cf6 2291
c36a2a6d
DV		 2292 if (obj_priv->tiling_mode == I915_TILING_Y &&
2293 HAS_128_BYTE_Y_TILING(dev))
2294 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2295 else
2296 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2297
de151cf6
JB		 2298 val = obj_priv->gtt_offset;
2299 if (obj_priv->tiling_mode == I915_TILING_Y)
2300 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2301 val |= I915_FENCE_SIZE_BITS(obj->size);
2302 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2303 val |= I830_FENCE_REG_VALID;
2304
dc529a4f
EA		 2305 if (regnum < 8)
2306 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2307 else
2308 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2309 I915_WRITE(fence_reg, val);
de151cf6
JB		 2310}
2311
2312static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2313{
2314 struct drm_gem_object *obj = reg->obj;
2315 struct drm_device *dev = obj->dev;
2316 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2317 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2318 int regnum = obj_priv->fence_reg;
2319 uint32_t val;
2320 uint32_t pitch_val;
8d7773a3 2321 uint32_t fence_size_bits;
de151cf6 2322
8d7773a3 2323 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2324 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2325 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2326 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2327 return;
2328 }
2329
e76a16de
EA		 2330 pitch_val = obj_priv->stride / 128;
2331 pitch_val = ffs(pitch_val) - 1;
2332 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2333
de151cf6
JB		 2334 val = obj_priv->gtt_offset;
2335 if (obj_priv->tiling_mode == I915_TILING_Y)
2336 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2337 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2338 WARN_ON(fence_size_bits & ~0x00000f00);
2339 val |= fence_size_bits;
de151cf6
JB		 2340 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2341 val |= I830_FENCE_REG_VALID;
2342
2343 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2344}
2345
ae3db24a
DV		 2346static int i915_find_fence_reg(struct drm_device *dev)
2347{
2348 struct drm_i915_fence_reg *reg = NULL;
2349 struct drm_i915_gem_object *obj_priv = NULL;
2350 struct drm_i915_private *dev_priv = dev->dev_private;
2351 struct drm_gem_object *obj = NULL;
2352 int i, avail, ret;
2353
2354 /* First try to find a free reg */
2355 avail = 0;
2356 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2357 reg = &dev_priv->fence_regs[i];
2358 if (!reg->obj)
2359 return i;
2360
23010e43 2361 obj_priv = to_intel_bo(reg->obj);
ae3db24a
DV		 2362 if (!obj_priv->pin_count)
2363 avail++;
2364 }
2365
2366 if (avail == 0)
2367 return -ENOSPC;
2368
2369 /* None available, try to steal one or wait for a user to finish */
2370 i = I915_FENCE_REG_NONE;
007cc8ac
DV		 2371 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2372 lru_list) {
2373 obj = reg->obj;
2374 obj_priv = to_intel_bo(obj);
ae3db24a
DV		 2375
2376 if (obj_priv->pin_count)
2377 continue;
2378
2379 /* found one! */
2380 i = obj_priv->fence_reg;
2381 break;
2382 }
2383
2384 BUG_ON(i == I915_FENCE_REG_NONE);
2385
2386 /* We only have a reference on obj from the active list. put_fence_reg
2387 * might drop that one, causing a use-after-free in it. So hold a
2388 * private reference to obj like the other callers of put_fence_reg
2389 * (set_tiling ioctl) do. */
2390 drm_gem_object_reference(obj);
2391 ret = i915_gem_object_put_fence_reg(obj);
2392 drm_gem_object_unreference(obj);
2393 if (ret != 0)
2394 return ret;
2395
2396 return i;
2397}
2398
de151cf6
JB		 2399/**
2400 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2401 * @obj: object to map through a fence reg
2402 *
2403 * When mapping objects through the GTT, userspace wants to be able to write
2404 * to them without having to worry about swizzling if the object is tiled.
2405 *
2406 * This function walks the fence regs looking for a free one for @obj,
2407 * stealing one if it can't find any.
2408 *
2409 * It then sets up the reg based on the object's properties: address, pitch
2410 * and tiling format.
2411 */
8c4b8c3f
CW		 2412int
2413i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2414{
2415 struct drm_device *dev = obj->dev;
79e53945 2416 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2417 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2418 struct drm_i915_fence_reg *reg = NULL;
ae3db24a 2419 int ret;
de151cf6 2420
a09ba7fa
EA		 2421 /* Just update our place in the LRU if our fence is getting used. */
2422 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 2423 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2424 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa
EA		 2425 return 0;
2426 }
2427
de151cf6
JB		 2428 switch (obj_priv->tiling_mode) {
2429 case I915_TILING_NONE:
2430 WARN(1, "allocating a fence for non-tiled object?\n");
2431 break;
2432 case I915_TILING_X:
0f973f27
JB		 2433 if (!obj_priv->stride)
2434 return -EINVAL;
2435 WARN((obj_priv->stride & (512 - 1)),
2436 "object 0x%08x is X tiled but has non-512B pitch\n",
2437 obj_priv->gtt_offset);
de151cf6
JB		 2438 break;
2439 case I915_TILING_Y:
0f973f27
JB		 2440 if (!obj_priv->stride)
2441 return -EINVAL;
2442 WARN((obj_priv->stride & (128 - 1)),
2443 "object 0x%08x is Y tiled but has non-128B pitch\n",
2444 obj_priv->gtt_offset);
de151cf6
JB		 2445 break;
2446 }
2447
ae3db24a
DV		 2448 ret = i915_find_fence_reg(dev);
2449 if (ret < 0)
2450 return ret;
de151cf6 2451
ae3db24a
DV		 2452 obj_priv->fence_reg = ret;
2453 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
007cc8ac 2454 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa 2455
de151cf6
JB		 2456 reg->obj = obj;
2457
4e901fdc
EA		 2458 if (IS_GEN6(dev))
2459 sandybridge_write_fence_reg(reg);
2460 else if (IS_I965G(dev))
de151cf6
JB		 2461 i965_write_fence_reg(reg);
2462 else if (IS_I9XX(dev))
2463 i915_write_fence_reg(reg);
2464 else
2465 i830_write_fence_reg(reg);
d9ddcb96 2466
ae3db24a
DV		 2467 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2468 obj_priv->tiling_mode);
1c5d22f7 2469
d9ddcb96 2470 return 0;
de151cf6
JB		 2471}
2472
2473/**
2474 * i915_gem_clear_fence_reg - clear out fence register info
2475 * @obj: object to clear
2476 *
2477 * Zeroes out the fence register itself and clears out the associated
2478 * data structures in dev_priv and obj_priv.
2479 */
2480static void
2481i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2482{
2483 struct drm_device *dev = obj->dev;
79e53945 2484 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2485 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
007cc8ac
DV		 2486 struct drm_i915_fence_reg *reg =
2487 &dev_priv->fence_regs[obj_priv->fence_reg];
de151cf6 2488
4e901fdc
EA		 2489 if (IS_GEN6(dev)) {
2490 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2491 (obj_priv->fence_reg * 8), 0);
2492 } else if (IS_I965G(dev)) {
de151cf6 2493 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
4e901fdc 2494 } else {
dc529a4f
EA		 2495 uint32_t fence_reg;
2496
2497 if (obj_priv->fence_reg < 8)
2498 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2499 else
2500 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2501 8) * 4;
2502
2503 I915_WRITE(fence_reg, 0);
2504 }
de151cf6 2505
007cc8ac 2506 reg->obj = NULL;
de151cf6 2507 obj_priv->fence_reg = I915_FENCE_REG_NONE;
007cc8ac 2508 list_del_init(&reg->lru_list);
de151cf6
JB		 2509}
2510
52dc7d32
CW		 2511/**
2512 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2513 * to the buffer to finish, and then resets the fence register.
2514 * @obj: tiled object holding a fence register.
2515 *
2516 * Zeroes out the fence register itself and clears out the associated
2517 * data structures in dev_priv and obj_priv.
2518 */
2519int
2520i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2521{
2522 struct drm_device *dev = obj->dev;
23010e43 2523 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
52dc7d32
CW		 2524
2525 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2526 return 0;
2527
10ae9bd2
DV		 2528 /* If we've changed tiling, GTT-mappings of the object
2529 * need to re-fault to ensure that the correct fence register
2530 * setup is in place.
2531 */
2532 i915_gem_release_mmap(obj);
2533
52dc7d32
CW		 2534 /* On the i915, GPU access to tiled buffers is via a fence,
2535 * therefore we must wait for any outstanding access to complete
2536 * before clearing the fence.
2537 */
2538 if (!IS_I965G(dev)) {
2539 int ret;
2540
2541 i915_gem_object_flush_gpu_write_domain(obj);
52dc7d32
CW		 2542 ret = i915_gem_object_wait_rendering(obj);
2543 if (ret != 0)
2544 return ret;
2545 }
2546
4a726612 2547 i915_gem_object_flush_gtt_write_domain(obj);
52dc7d32
CW		 2548 i915_gem_clear_fence_reg (obj);
2549
2550 return 0;
2551}
2552
673a394b
EA		 2553/**
2554 * Finds free space in the GTT aperture and binds the object there.
2555 */
2556static int
2557i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2558{
2559 struct drm_device *dev = obj->dev;
2560 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2561 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 2562 struct drm_mm_node *free_space;
4bdadb97 2563 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2564 int ret;
673a394b 2565
bb6baf76 2566 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2567 DRM_ERROR("Attempting to bind a purgeable object\n");
2568 return -EINVAL;
2569 }
2570
673a394b 2571 if (alignment == 0)
0f973f27 2572 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2573 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2574 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2575 return -EINVAL;
2576 }
2577
2578 search_free:
2579 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2580 obj->size, alignment, 0);
2581 if (free_space != NULL) {
2582 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2583 alignment);
2584 if (obj_priv->gtt_space != NULL) {
2585 obj_priv->gtt_space->private = obj;
2586 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2587 }
2588 }
2589 if (obj_priv->gtt_space == NULL) {
2590 /* If the gtt is empty and we're still having trouble
2591 * fitting our object in, we're out of memory.
2592 */
2593#if WATCH_LRU
2594 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2595#endif
07f73f69 2596 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2597 if (ret)
673a394b 2598 return ret;
9731129c 2599
673a394b
EA		 2600 goto search_free;
2601 }
2602
2603#if WATCH_BUF
cfd43c02 2604 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2605 obj->size, obj_priv->gtt_offset);
2606#endif
4bdadb97 2607 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2608 if (ret) {
2609 drm_mm_put_block(obj_priv->gtt_space);
2610 obj_priv->gtt_space = NULL;
07f73f69
CW		 2611
2612 if (ret == -ENOMEM) {
2613 /* first try to clear up some space from the GTT */
2614 ret = i915_gem_evict_something(dev, obj->size);
2615 if (ret) {
07f73f69 2616 /* now try to shrink everyone else */
4bdadb97
CW		 2617 if (gfpmask) {
2618 gfpmask = 0;
2619 goto search_free;
07f73f69
CW		 2620 }
2621
2622 return ret;
2623 }
2624
2625 goto search_free;
2626 }
2627
673a394b
EA		 2628 return ret;
2629 }
2630
673a394b
EA		 2631 /* Create an AGP memory structure pointing at our pages, and bind it
2632 * into the GTT.
2633 */
2634 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2635 obj_priv->pages,
07f73f69 2636 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2637 obj_priv->gtt_offset,
2638 obj_priv->agp_type);
673a394b 2639 if (obj_priv->agp_mem == NULL) {
856fa198 2640 i915_gem_object_put_pages(obj);
673a394b
EA		 2641 drm_mm_put_block(obj_priv->gtt_space);
2642 obj_priv->gtt_space = NULL;
07f73f69
CW		 2643
2644 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2645 if (ret)
07f73f69 2646 return ret;
07f73f69
CW		 2647
2648 goto search_free;
673a394b
EA		 2649 }
2650 atomic_inc(&dev->gtt_count);
2651 atomic_add(obj->size, &dev->gtt_memory);
2652
2653 /* Assert that the object is not currently in any GPU domain. As it
2654 * wasn't in the GTT, there shouldn't be any way it could have been in
2655 * a GPU cache
2656 */
21d509e3
CW		 2657 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2658 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2659
1c5d22f7
CW		 2660 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2661
673a394b
EA		 2662 return 0;
2663}
2664
2665void
2666i915_gem_clflush_object(struct drm_gem_object *obj)
2667{
23010e43 2668 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2669
2670 /* If we don't have a page list set up, then we're not pinned
2671 * to GPU, and we can ignore the cache flush because it'll happen
2672 * again at bind time.
2673 */
856fa198 2674 if (obj_priv->pages == NULL)
673a394b
EA		 2675 return;
2676
1c5d22f7 2677 trace_i915_gem_object_clflush(obj);
cfa16a0d 2678
856fa198 2679 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2680}
2681
e47c68e9
EA		 2682/** Flushes any GPU write domain for the object if it's dirty. */
2683static void
2684i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2685{
2686 struct drm_device *dev = obj->dev;
1c5d22f7 2687 uint32_t old_write_domain;
e47c68e9
EA		 2688
2689 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2690 return;
2691
2692 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2693 old_write_domain = obj->write_domain;
e47c68e9 2694 i915_gem_flush(dev, 0, obj->write_domain);
922a2efc 2695 (void) i915_add_request(dev, NULL, obj->write_domain);
99fcb766 2696 BUG_ON(obj->write_domain);
1c5d22f7
CW		 2697
2698 trace_i915_gem_object_change_domain(obj,
2699 obj->read_domains,
2700 old_write_domain);
e47c68e9
EA		 2701}
2702
2703/** Flushes the GTT write domain for the object if it's dirty. */
2704static void
2705i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2706{
1c5d22f7
CW		 2707 uint32_t old_write_domain;
2708
e47c68e9
EA		 2709 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2710 return;
2711
2712 /* No actual flushing is required for the GTT write domain. Writes
2713 * to it immediately go to main memory as far as we know, so there's
2714 * no chipset flush. It also doesn't land in render cache.
2715 */
1c5d22f7 2716 old_write_domain = obj->write_domain;
e47c68e9 2717 obj->write_domain = 0;
1c5d22f7
CW		 2718
2719 trace_i915_gem_object_change_domain(obj,
2720 obj->read_domains,
2721 old_write_domain);
e47c68e9
EA		 2722}
2723
2724/** Flushes the CPU write domain for the object if it's dirty. */
2725static void
2726i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2727{
2728 struct drm_device *dev = obj->dev;
1c5d22f7 2729 uint32_t old_write_domain;
e47c68e9
EA		 2730
2731 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2732 return;
2733
2734 i915_gem_clflush_object(obj);
2735 drm_agp_chipset_flush(dev);
1c5d22f7 2736 old_write_domain = obj->write_domain;
e47c68e9 2737 obj->write_domain = 0;
1c5d22f7
CW		 2738
2739 trace_i915_gem_object_change_domain(obj,
2740 obj->read_domains,
2741 old_write_domain);
e47c68e9
EA		 2742}
2743
6b95a207
KH		 2744void
2745i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2746{
2747 switch (obj->write_domain) {
2748 case I915_GEM_DOMAIN_GTT:
2749 i915_gem_object_flush_gtt_write_domain(obj);
2750 break;
2751 case I915_GEM_DOMAIN_CPU:
2752 i915_gem_object_flush_cpu_write_domain(obj);
2753 break;
2754 default:
2755 i915_gem_object_flush_gpu_write_domain(obj);
2756 break;
2757 }
2758}
2759
2ef7eeaa
EA		 2760/**
2761 * Moves a single object to the GTT read, and possibly write domain.
2762 *
2763 * This function returns when the move is complete, including waiting on
2764 * flushes to occur.
2765 */
79e53945 2766int
2ef7eeaa
EA		 2767i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2768{
23010e43 2769 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 2770 uint32_t old_write_domain, old_read_domains;
e47c68e9 2771 int ret;
2ef7eeaa 2772
02354392
EA		 2773 /* Not valid to be called on unbound objects. */
2774 if (obj_priv->gtt_space == NULL)
2775 return -EINVAL;
2776
e47c68e9
EA		 2777 i915_gem_object_flush_gpu_write_domain(obj);
2778 /* Wait on any GPU rendering and flushing to occur. */
2779 ret = i915_gem_object_wait_rendering(obj);
2780 if (ret != 0)
2781 return ret;
2782
1c5d22f7
CW		 2783 old_write_domain = obj->write_domain;
2784 old_read_domains = obj->read_domains;
2785
e47c68e9
EA		 2786 /* If we're writing through the GTT domain, then CPU and GPU caches
2787 * will need to be invalidated at next use.
2ef7eeaa 2788 */
e47c68e9
EA		 2789 if (write)
2790 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2791
e47c68e9 2792 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2793
e47c68e9
EA		 2794 /* It should now be out of any other write domains, and we can update
2795 * the domain values for our changes.
2796 */
2797 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2798 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2799 if (write) {
2800 obj->write_domain = I915_GEM_DOMAIN_GTT;
2801 obj_priv->dirty = 1;
2ef7eeaa
EA		 2802 }
2803
1c5d22f7
CW		 2804 trace_i915_gem_object_change_domain(obj,
2805 old_read_domains,
2806 old_write_domain);
2807
e47c68e9
EA		 2808 return 0;
2809}
2810
b9241ea3
ZW		 2811/*
2812 * Prepare buffer for display plane. Use uninterruptible for possible flush
2813 * wait, as in modesetting process we're not supposed to be interrupted.
2814 */
2815int
2816i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2817{
2818 struct drm_device *dev = obj->dev;
23010e43 2819 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
b9241ea3
ZW		 2820 uint32_t old_write_domain, old_read_domains;
2821 int ret;
2822
2823 /* Not valid to be called on unbound objects. */
2824 if (obj_priv->gtt_space == NULL)
2825 return -EINVAL;
2826
2827 i915_gem_object_flush_gpu_write_domain(obj);
2828
2829 /* Wait on any GPU rendering and flushing to occur. */
2830 if (obj_priv->active) {
2831#if WATCH_BUF
2832 DRM_INFO("%s: object %p wait for seqno %08x\n",
2833 __func__, obj, obj_priv->last_rendering_seqno);
2834#endif
2835 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2836 if (ret != 0)
2837 return ret;
2838 }
2839
2840 old_write_domain = obj->write_domain;
2841 old_read_domains = obj->read_domains;
2842
2843 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2844
2845 i915_gem_object_flush_cpu_write_domain(obj);
2846
2847 /* It should now be out of any other write domains, and we can update
2848 * the domain values for our changes.
2849 */
2850 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2851 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2852 obj->write_domain = I915_GEM_DOMAIN_GTT;
2853 obj_priv->dirty = 1;
2854
2855 trace_i915_gem_object_change_domain(obj,
2856 old_read_domains,
2857 old_write_domain);
2858
2859 return 0;
2860}
2861
e47c68e9
EA		 2862/**
2863 * Moves a single object to the CPU read, and possibly write domain.
2864 *
2865 * This function returns when the move is complete, including waiting on
2866 * flushes to occur.
2867 */
2868static int
2869i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2870{
1c5d22f7 2871 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2872 int ret;
2873
2874 i915_gem_object_flush_gpu_write_domain(obj);
2ef7eeaa 2875 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2876 ret = i915_gem_object_wait_rendering(obj);
2877 if (ret != 0)
2878 return ret;
2ef7eeaa 2879
e47c68e9 2880 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2881
e47c68e9
EA		 2882 /* If we have a partially-valid cache of the object in the CPU,
2883 * finish invalidating it and free the per-page flags.
2ef7eeaa 2884 */
e47c68e9 2885 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2886
1c5d22f7
CW		 2887 old_write_domain = obj->write_domain;
2888 old_read_domains = obj->read_domains;
2889
e47c68e9
EA		 2890 /* Flush the CPU cache if it's still invalid. */
2891 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2892 i915_gem_clflush_object(obj);
2ef7eeaa 2893
e47c68e9 2894 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2895 }
2896
2897 /* It should now be out of any other write domains, and we can update
2898 * the domain values for our changes.
2899 */
e47c68e9
EA		 2900 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2901
2902 /* If we're writing through the CPU, then the GPU read domains will
2903 * need to be invalidated at next use.
2904 */
2905 if (write) {
2906 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2907 obj->write_domain = I915_GEM_DOMAIN_CPU;
2908 }
2ef7eeaa 2909
1c5d22f7
CW		 2910 trace_i915_gem_object_change_domain(obj,
2911 old_read_domains,
2912 old_write_domain);
2913
2ef7eeaa
EA		 2914 return 0;
2915}
2916
673a394b
EA		 2917/*
2918 * Set the next domain for the specified object. This
2919 * may not actually perform the necessary flushing/invaliding though,
2920 * as that may want to be batched with other set_domain operations
2921 *
2922 * This is (we hope) the only really tricky part of gem. The goal
2923 * is fairly simple -- track which caches hold bits of the object
2924 * and make sure they remain coherent. A few concrete examples may
2925 * help to explain how it works. For shorthand, we use the notation
2926 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2927 * a pair of read and write domain masks.
2928 *
2929 * Case 1: the batch buffer
2930 *
2931 * 1. Allocated
2932 * 2. Written by CPU
2933 * 3. Mapped to GTT
2934 * 4. Read by GPU
2935 * 5. Unmapped from GTT
2936 * 6. Freed
2937 *
2938 * Let's take these a step at a time
2939 *
2940 * 1. Allocated
2941 * Pages allocated from the kernel may still have
2942 * cache contents, so we set them to (CPU, CPU) always.
2943 * 2. Written by CPU (using pwrite)
2944 * The pwrite function calls set_domain (CPU, CPU) and
2945 * this function does nothing (as nothing changes)
2946 * 3. Mapped by GTT
2947 * This function asserts that the object is not
2948 * currently in any GPU-based read or write domains
2949 * 4. Read by GPU
2950 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2951 * As write_domain is zero, this function adds in the
2952 * current read domains (CPU+COMMAND, 0).
2953 * flush_domains is set to CPU.
2954 * invalidate_domains is set to COMMAND
2955 * clflush is run to get data out of the CPU caches
2956 * then i915_dev_set_domain calls i915_gem_flush to
2957 * emit an MI_FLUSH and drm_agp_chipset_flush
2958 * 5. Unmapped from GTT
2959 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2960 * flush_domains and invalidate_domains end up both zero
2961 * so no flushing/invalidating happens
2962 * 6. Freed
2963 * yay, done
2964 *
2965 * Case 2: The shared render buffer
2966 *
2967 * 1. Allocated
2968 * 2. Mapped to GTT
2969 * 3. Read/written by GPU
2970 * 4. set_domain to (CPU,CPU)
2971 * 5. Read/written by CPU
2972 * 6. Read/written by GPU
2973 *
2974 * 1. Allocated
2975 * Same as last example, (CPU, CPU)
2976 * 2. Mapped to GTT
2977 * Nothing changes (assertions find that it is not in the GPU)
2978 * 3. Read/written by GPU
2979 * execbuffer calls set_domain (RENDER, RENDER)
2980 * flush_domains gets CPU
2981 * invalidate_domains gets GPU
2982 * clflush (obj)
2983 * MI_FLUSH and drm_agp_chipset_flush
2984 * 4. set_domain (CPU, CPU)
2985 * flush_domains gets GPU
2986 * invalidate_domains gets CPU
2987 * wait_rendering (obj) to make sure all drawing is complete.
2988 * This will include an MI_FLUSH to get the data from GPU
2989 * to memory
2990 * clflush (obj) to invalidate the CPU cache
2991 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2992 * 5. Read/written by CPU
2993 * cache lines are loaded and dirtied
2994 * 6. Read written by GPU
2995 * Same as last GPU access
2996 *
2997 * Case 3: The constant buffer
2998 *
2999 * 1. Allocated
3000 * 2. Written by CPU
3001 * 3. Read by GPU
3002 * 4. Updated (written) by CPU again
3003 * 5. Read by GPU
3004 *
3005 * 1. Allocated
3006 * (CPU, CPU)
3007 * 2. Written by CPU
3008 * (CPU, CPU)
3009 * 3. Read by GPU
3010 * (CPU+RENDER, 0)
3011 * flush_domains = CPU
3012 * invalidate_domains = RENDER
3013 * clflush (obj)
3014 * MI_FLUSH
3015 * drm_agp_chipset_flush
3016 * 4. Updated (written) by CPU again
3017 * (CPU, CPU)
3018 * flush_domains = 0 (no previous write domain)
3019 * invalidate_domains = 0 (no new read domains)
3020 * 5. Read by GPU
3021 * (CPU+RENDER, 0)
3022 * flush_domains = CPU
3023 * invalidate_domains = RENDER
3024 * clflush (obj)
3025 * MI_FLUSH
3026 * drm_agp_chipset_flush
3027 */
c0d90829 3028static void
8b0e378a 3029i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 3030{
3031 struct drm_device *dev = obj->dev;
23010e43 3032 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 3033 uint32_t invalidate_domains = 0;
3034 uint32_t flush_domains = 0;
1c5d22f7 3035 uint32_t old_read_domains;
e47c68e9 3036
8b0e378a
EA		 3037 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3038 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 3039
652c393a
JB		 3040 intel_mark_busy(dev, obj);
3041
673a394b
EA		 3042#if WATCH_BUF
3043 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3044 __func__, obj,
8b0e378a
EA		 3045 obj->read_domains, obj->pending_read_domains,
3046 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 3047#endif
3048 /*
3049 * If the object isn't moving to a new write domain,
3050 * let the object stay in multiple read domains
3051 */
8b0e378a
EA		 3052 if (obj->pending_write_domain == 0)
3053 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3054 else
3055 obj_priv->dirty = 1;
3056
3057 /*
3058 * Flush the current write domain if
3059 * the new read domains don't match. Invalidate
3060 * any read domains which differ from the old
3061 * write domain
3062 */
8b0e378a
EA		 3063 if (obj->write_domain &&
3064 obj->write_domain != obj->pending_read_domains) {
673a394b 3065 flush_domains |= obj->write_domain;
8b0e378a
EA		 3066 invalidate_domains |=
3067 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3068 }
3069 /*
3070 * Invalidate any read caches which may have
3071 * stale data. That is, any new read domains.
3072 */
8b0e378a 3073 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3074 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3075#if WATCH_BUF
3076 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3077 __func__, flush_domains, invalidate_domains);
3078#endif
673a394b
EA		 3079 i915_gem_clflush_object(obj);
3080 }
3081
1c5d22f7
CW		 3082 old_read_domains = obj->read_domains;
3083
efbeed96
EA		 3084 /* The actual obj->write_domain will be updated with
3085 * pending_write_domain after we emit the accumulated flush for all
3086 * of our domain changes in execbuffers (which clears objects'
3087 * write_domains). So if we have a current write domain that we
3088 * aren't changing, set pending_write_domain to that.
3089 */
3090 if (flush_domains == 0 && obj->pending_write_domain == 0)
3091 obj->pending_write_domain = obj->write_domain;
8b0e378a 3092 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3093
3094 dev->invalidate_domains |= invalidate_domains;
3095 dev->flush_domains |= flush_domains;
3096#if WATCH_BUF
3097 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3098 __func__,
3099 obj->read_domains, obj->write_domain,
3100 dev->invalidate_domains, dev->flush_domains);
3101#endif
1c5d22f7
CW		 3102
3103 trace_i915_gem_object_change_domain(obj,
3104 old_read_domains,
3105 obj->write_domain);
673a394b
EA		 3106}
3107
3108/**
e47c68e9 3109 * Moves the object from a partially CPU read to a full one.
673a394b 3110 *
e47c68e9
EA		 3111 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3112 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3113 */
e47c68e9
EA		 3114static void
3115i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b 3116{
23010e43 3117 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3118
e47c68e9
EA		 3119 if (!obj_priv->page_cpu_valid)
3120 return;
3121
3122 /* If we're partially in the CPU read domain, finish moving it in.
3123 */
3124 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3125 int i;
3126
3127 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3128 if (obj_priv->page_cpu_valid[i])
3129 continue;
856fa198 3130 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3131 }
e47c68e9
EA		 3132 }
3133
3134 /* Free the page_cpu_valid mappings which are now stale, whether
3135 * or not we've got I915_GEM_DOMAIN_CPU.
3136 */
9a298b2a 3137 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3138 obj_priv->page_cpu_valid = NULL;
3139}
3140
3141/**
3142 * Set the CPU read domain on a range of the object.
3143 *
3144 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3145 * not entirely valid. The page_cpu_valid member of the object flags which
3146 * pages have been flushed, and will be respected by
3147 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3148 * of the whole object.
3149 *
3150 * This function returns when the move is complete, including waiting on
3151 * flushes to occur.
3152 */
3153static int
3154i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3155 uint64_t offset, uint64_t size)
3156{
23010e43 3157 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3158 uint32_t old_read_domains;
e47c68e9 3159 int i, ret;
673a394b 3160
e47c68e9
EA		 3161 if (offset == 0 && size == obj->size)
3162 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3163
e47c68e9
EA		 3164 i915_gem_object_flush_gpu_write_domain(obj);
3165 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3166 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3167 if (ret != 0)
6a47baa6 3168 return ret;
e47c68e9
EA		 3169 i915_gem_object_flush_gtt_write_domain(obj);
3170
3171 /* If we're already fully in the CPU read domain, we're done. */
3172 if (obj_priv->page_cpu_valid == NULL &&
3173 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3174 return 0;
673a394b 3175
e47c68e9
EA		 3176 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3177 * newly adding I915_GEM_DOMAIN_CPU
3178 */
673a394b 3179 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3180 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3181 GFP_KERNEL);
e47c68e9
EA		 3182 if (obj_priv->page_cpu_valid == NULL)
3183 return -ENOMEM;
3184 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3185 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3186
3187 /* Flush the cache on any pages that are still invalid from the CPU's
3188 * perspective.
3189 */
e47c68e9
EA		 3190 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3191 i++) {
673a394b
EA		 3192 if (obj_priv->page_cpu_valid[i])
3193 continue;
3194
856fa198 3195 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3196
3197 obj_priv->page_cpu_valid[i] = 1;
3198 }
3199
e47c68e9
EA		 3200 /* It should now be out of any other write domains, and we can update
3201 * the domain values for our changes.
3202 */
3203 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3204
1c5d22f7 3205 old_read_domains = obj->read_domains;
e47c68e9
EA		 3206 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3207
1c5d22f7
CW		 3208 trace_i915_gem_object_change_domain(obj,
3209 old_read_domains,
3210 obj->write_domain);
3211
673a394b
EA		 3212 return 0;
3213}
3214
673a394b
EA		 3215/**
3216 * Pin an object to the GTT and evaluate the relocations landing in it.
3217 */
3218static int
3219i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3220 struct drm_file *file_priv,
76446cac 3221 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3222 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3223{
3224 struct drm_device *dev = obj->dev;
0839ccb8 3225 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 3226 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3227 int i, ret;
0839ccb8 3228 void __iomem *reloc_page;
76446cac
JB		 3229 bool need_fence;
3230
3231 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3232 obj_priv->tiling_mode != I915_TILING_NONE;
3233
3234 /* Check fence reg constraints and rebind if necessary */
f590d279
OA		 3235 if (need_fence && !i915_gem_object_fence_offset_ok(obj,
3236 obj_priv->tiling_mode))
76446cac 3237 i915_gem_object_unbind(obj);
673a394b
EA		 3238
3239 /* Choose the GTT offset for our buffer and put it there. */
3240 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3241 if (ret)
3242 return ret;
3243
76446cac
JB		 3244 /*
3245 * Pre-965 chips need a fence register set up in order to
3246 * properly handle blits to/from tiled surfaces.
3247 */
3248 if (need_fence) {
3249 ret = i915_gem_object_get_fence_reg(obj);
3250 if (ret != 0) {
3251 if (ret != -EBUSY && ret != -ERESTARTSYS)
3252 DRM_ERROR("Failure to install fence: %d\n",
3253 ret);
3254 i915_gem_object_unpin(obj);
3255 return ret;
3256 }
3257 }
3258
673a394b
EA		 3259 entry->offset = obj_priv->gtt_offset;
3260
673a394b
EA		 3261 /* Apply the relocations, using the GTT aperture to avoid cache
3262 * flushing requirements.
3263 */
3264 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3265 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3266 struct drm_gem_object *target_obj;
3267 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3268 uint32_t reloc_val, reloc_offset;
3269 uint32_t __iomem *reloc_entry;
673a394b 3270
673a394b 3271 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3272 reloc->target_handle);
673a394b
EA		 3273 if (target_obj == NULL) {
3274 i915_gem_object_unpin(obj);
3275 return -EBADF;
3276 }
23010e43 3277 target_obj_priv = to_intel_bo(target_obj);
673a394b 3278
8542a0bb
CW		 3279#if WATCH_RELOC
3280 DRM_INFO("%s: obj %p offset %08x target %d "
3281 "read %08x write %08x gtt %08x "
3282 "presumed %08x delta %08x\n",
3283 __func__,
3284 obj,
3285 (int) reloc->offset,
3286 (int) reloc->target_handle,
3287 (int) reloc->read_domains,
3288 (int) reloc->write_domain,
3289 (int) target_obj_priv->gtt_offset,
3290 (int) reloc->presumed_offset,
3291 reloc->delta);
3292#endif
3293
673a394b
EA		 3294 /* The target buffer should have appeared before us in the
3295 * exec_object list, so it should have a GTT space bound by now.
3296 */
3297 if (target_obj_priv->gtt_space == NULL) {
3298 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3299 reloc->target_handle);
673a394b
EA		 3300 drm_gem_object_unreference(target_obj);
3301 i915_gem_object_unpin(obj);
3302 return -EINVAL;
3303 }
3304
8542a0bb 3305 /* Validate that the target is in a valid r/w GPU domain */
16edd550
DV		 3306 if (reloc->write_domain & (reloc->write_domain - 1)) {
3307 DRM_ERROR("reloc with multiple write domains: "
3308 "obj %p target %d offset %d "
3309 "read %08x write %08x",
3310 obj, reloc->target_handle,
3311 (int) reloc->offset,
3312 reloc->read_domains,
3313 reloc->write_domain);
3314 return -EINVAL;
3315 }
40a5f0de
EA		 3316 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3317 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3318 DRM_ERROR("reloc with read/write CPU domains: "
3319 "obj %p target %d offset %d "
3320 "read %08x write %08x",
40a5f0de
EA		 3321 obj, reloc->target_handle,
3322 (int) reloc->offset,
3323 reloc->read_domains,
3324 reloc->write_domain);
491152b8
CW		 3325 drm_gem_object_unreference(target_obj);
3326 i915_gem_object_unpin(obj);
e47c68e9
EA		 3327 return -EINVAL;
3328 }
40a5f0de
EA		 3329 if (reloc->write_domain && target_obj->pending_write_domain &&
3330 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3331 DRM_ERROR("Write domain conflict: "
3332 "obj %p target %d offset %d "
3333 "new %08x old %08x\n",
40a5f0de
EA		 3334 obj, reloc->target_handle,
3335 (int) reloc->offset,
3336 reloc->write_domain,
673a394b
EA		 3337 target_obj->pending_write_domain);
3338 drm_gem_object_unreference(target_obj);
3339 i915_gem_object_unpin(obj);
3340 return -EINVAL;
3341 }
3342
40a5f0de
EA		 3343 target_obj->pending_read_domains |= reloc->read_domains;
3344 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3345
3346 /* If the relocation already has the right value in it, no
3347 * more work needs to be done.
3348 */
40a5f0de 3349 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3350 drm_gem_object_unreference(target_obj);
3351 continue;
3352 }
3353
8542a0bb
CW		 3354 /* Check that the relocation address is valid... */
3355 if (reloc->offset > obj->size - 4) {
3356 DRM_ERROR("Relocation beyond object bounds: "
3357 "obj %p target %d offset %d size %d.\n",
3358 obj, reloc->target_handle,
3359 (int) reloc->offset, (int) obj->size);
3360 drm_gem_object_unreference(target_obj);
3361 i915_gem_object_unpin(obj);
3362 return -EINVAL;
3363 }
3364 if (reloc->offset & 3) {
3365 DRM_ERROR("Relocation not 4-byte aligned: "
3366 "obj %p target %d offset %d.\n",
3367 obj, reloc->target_handle,
3368 (int) reloc->offset);
3369 drm_gem_object_unreference(target_obj);
3370 i915_gem_object_unpin(obj);
3371 return -EINVAL;
3372 }
3373
3374 /* and points to somewhere within the target object. */
3375 if (reloc->delta >= target_obj->size) {
3376 DRM_ERROR("Relocation beyond target object bounds: "
3377 "obj %p target %d delta %d size %d.\n",
3378 obj, reloc->target_handle,
3379 (int) reloc->delta, (int) target_obj->size);
3380 drm_gem_object_unreference(target_obj);
3381 i915_gem_object_unpin(obj);
3382 return -EINVAL;
3383 }
3384
2ef7eeaa
EA		 3385 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3386 if (ret != 0) {
3387 drm_gem_object_unreference(target_obj);
3388 i915_gem_object_unpin(obj);
3389 return -EINVAL;
673a394b
EA		 3390 }
3391
3392 /* Map the page containing the relocation we're going to
3393 * perform.
3394 */
40a5f0de 3395 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3396 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3397 (reloc_offset &
3398 ~(PAGE_SIZE - 1)));
3043c60c 3399 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3400 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3401 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3402
3403#if WATCH_BUF
3404 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3405 obj, (unsigned int) reloc->offset,
673a394b
EA		 3406 readl(reloc_entry), reloc_val);
3407#endif
3408 writel(reloc_val, reloc_entry);
0839ccb8 3409 io_mapping_unmap_atomic(reloc_page);
673a394b 3410
40a5f0de
EA		 3411 /* The updated presumed offset for this entry will be
3412 * copied back out to the user.
673a394b 3413 */
40a5f0de 3414 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3415
3416 drm_gem_object_unreference(target_obj);
3417 }
3418
673a394b
EA		 3419#if WATCH_BUF
3420 if (0)
3421 i915_gem_dump_object(obj, 128, __func__, ~0);
3422#endif
3423 return 0;
3424}
3425
673a394b
EA		 3426/* Throttle our rendering by waiting until the ring has completed our requests
3427 * emitted over 20 msec ago.
3428 *
b962442e
EA		 3429 * Note that if we were to use the current jiffies each time around the loop,
3430 * we wouldn't escape the function with any frames outstanding if the time to
3431 * render a frame was over 20ms.
3432 *
673a394b
EA		 3433 * This should get us reasonable parallelism between CPU and GPU but also
3434 * relatively low latency when blocking on a particular request to finish.
3435 */
3436static int
3437i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3438{
3439 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3440 int ret = 0;
b962442e 3441 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3442
3443 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3444 while (!list_empty(&i915_file_priv->mm.request_list)) {
3445 struct drm_i915_gem_request *request;
3446
3447 request = list_first_entry(&i915_file_priv->mm.request_list,
3448 struct drm_i915_gem_request,
3449 client_list);
3450
3451 if (time_after_eq(request->emitted_jiffies, recent_enough))
3452 break;
3453
3454 ret = i915_wait_request(dev, request->seqno);
3455 if (ret != 0)
3456 break;
3457 }
673a394b 3458 mutex_unlock(&dev->struct_mutex);
b962442e 3459
673a394b
EA		 3460 return ret;
3461}
3462
40a5f0de 3463static int
76446cac 3464i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3465 uint32_t buffer_count,
3466 struct drm_i915_gem_relocation_entry **relocs)
3467{
3468 uint32_t reloc_count = 0, reloc_index = 0, i;
3469 int ret;
3470
3471 *relocs = NULL;
3472 for (i = 0; i < buffer_count; i++) {
3473 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3474 return -EINVAL;
3475 reloc_count += exec_list[i].relocation_count;
3476 }
3477
8e7d2b2c 3478 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3479 if (*relocs == NULL) {
3480 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3481 return -ENOMEM;
76446cac 3482 }
40a5f0de
EA		 3483
3484 for (i = 0; i < buffer_count; i++) {
3485 struct drm_i915_gem_relocation_entry __user *user_relocs;
3486
3487 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3488
3489 ret = copy_from_user(&(*relocs)[reloc_index],
3490 user_relocs,
3491 exec_list[i].relocation_count *
3492 sizeof(**relocs));
3493 if (ret != 0) {
8e7d2b2c 3494 drm_free_large(*relocs);
40a5f0de 3495 *relocs = NULL;
2bc43b5c 3496 return -EFAULT;
40a5f0de
EA		 3497 }
3498
3499 reloc_index += exec_list[i].relocation_count;
3500 }
3501
2bc43b5c 3502 return 0;
40a5f0de
EA		 3503}
3504
3505static int
76446cac 3506i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3507 uint32_t buffer_count,
3508 struct drm_i915_gem_relocation_entry *relocs)
3509{
3510 uint32_t reloc_count = 0, i;
2bc43b5c 3511 int ret = 0;
40a5f0de 3512
93533c29
CW		 3513 if (relocs == NULL)
3514 return 0;
3515
40a5f0de
EA		 3516 for (i = 0; i < buffer_count; i++) {
3517 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3518 int unwritten;
40a5f0de
EA		 3519
3520 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3521
2bc43b5c
FM		 3522 unwritten = copy_to_user(user_relocs,
3523 &relocs[reloc_count],
3524 exec_list[i].relocation_count *
3525 sizeof(*relocs));
3526
3527 if (unwritten) {
3528 ret = -EFAULT;
3529 goto err;
40a5f0de
EA		 3530 }
3531
3532 reloc_count += exec_list[i].relocation_count;
3533 }
3534
2bc43b5c 3535err:
8e7d2b2c 3536 drm_free_large(relocs);
40a5f0de
EA		 3537
3538 return ret;
3539}
3540
83d60795 3541static int
76446cac 3542i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3543 uint64_t exec_offset)
3544{
3545 uint32_t exec_start, exec_len;
3546
3547 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3548 exec_len = (uint32_t) exec->batch_len;
3549
3550 if ((exec_start | exec_len) & 0x7)
3551 return -EINVAL;
3552
3553 if (!exec_start)
3554 return -EINVAL;
3555
3556 return 0;
3557}
3558
6b95a207
KH		 3559static int
3560i915_gem_wait_for_pending_flip(struct drm_device *dev,
3561 struct drm_gem_object **object_list,
3562 int count)
3563{
3564 drm_i915_private_t *dev_priv = dev->dev_private;
3565 struct drm_i915_gem_object *obj_priv;
3566 DEFINE_WAIT(wait);
3567 int i, ret = 0;
3568
3569 for (;;) {
3570 prepare_to_wait(&dev_priv->pending_flip_queue,
3571 &wait, TASK_INTERRUPTIBLE);
3572 for (i = 0; i < count; i++) {
23010e43 3573 obj_priv = to_intel_bo(object_list[i]);
6b95a207
KH		 3574 if (atomic_read(&obj_priv->pending_flip) > 0)
3575 break;
3576 }
3577 if (i == count)
3578 break;
3579
3580 if (!signal_pending(current)) {
3581 mutex_unlock(&dev->struct_mutex);
3582 schedule();
3583 mutex_lock(&dev->struct_mutex);
3584 continue;
3585 }
3586 ret = -ERESTARTSYS;
3587 break;
3588 }
3589 finish_wait(&dev_priv->pending_flip_queue, &wait);
3590
3591 return ret;
3592}
3593
673a394b 3594int
76446cac
JB		 3595i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3596 struct drm_file *file_priv,
3597 struct drm_i915_gem_execbuffer2 *args,
3598 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3599{
3600 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3601 struct drm_gem_object **object_list = NULL;
3602 struct drm_gem_object *batch_obj;
b70d11da 3603 struct drm_i915_gem_object *obj_priv;
201361a5 3604 struct drm_clip_rect *cliprects = NULL;
93533c29 3605 struct drm_i915_gem_relocation_entry *relocs = NULL;
76446cac 3606 int ret = 0, ret2, i, pinned = 0;
673a394b 3607 uint64_t exec_offset;
40a5f0de 3608 uint32_t seqno, flush_domains, reloc_index;
6b95a207 3609 int pin_tries, flips;
673a394b
EA		 3610
3611#if WATCH_EXEC
3612 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3613 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3614#endif
3615
4f481ed2
EA		 3616 if (args->buffer_count < 1) {
3617 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3618 return -EINVAL;
3619 }
c8e0f93a 3620 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3621 if (object_list == NULL) {
3622 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3623 args->buffer_count);
3624 ret = -ENOMEM;
3625 goto pre_mutex_err;
3626 }
673a394b 3627
201361a5 3628 if (args->num_cliprects != 0) {
9a298b2a
EA		 3629 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3630 GFP_KERNEL);
a40e8d31
OA		 3631 if (cliprects == NULL) {
3632 ret = -ENOMEM;
201361a5 3633 goto pre_mutex_err;
a40e8d31 3634 }
201361a5
EA		 3635
3636 ret = copy_from_user(cliprects,
3637 (struct drm_clip_rect __user *)
3638 (uintptr_t) args->cliprects_ptr,
3639 sizeof(*cliprects) * args->num_cliprects);
3640 if (ret != 0) {
3641 DRM_ERROR("copy %d cliprects failed: %d\n",
3642 args->num_cliprects, ret);
3643 goto pre_mutex_err;
3644 }
3645 }
3646
40a5f0de
EA		 3647 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3648 &relocs);
3649 if (ret != 0)
3650 goto pre_mutex_err;
3651
673a394b
EA		 3652 mutex_lock(&dev->struct_mutex);
3653
3654 i915_verify_inactive(dev, __FILE__, __LINE__);
3655
ba1234d1 3656 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3657 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3658 ret = -EIO;
3659 goto pre_mutex_err;
673a394b
EA		 3660 }
3661
3662 if (dev_priv->mm.suspended) {
673a394b 3663 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3664 ret = -EBUSY;
3665 goto pre_mutex_err;
673a394b
EA		 3666 }
3667
ac94a962 3668 /* Look up object handles */
6b95a207 3669 flips = 0;
673a394b
EA		 3670 for (i = 0; i < args->buffer_count; i++) {
3671 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3672 exec_list[i].handle);
3673 if (object_list[i] == NULL) {
3674 DRM_ERROR("Invalid object handle %d at index %d\n",
3675 exec_list[i].handle, i);
0ce907f8
CW		 3676 /* prevent error path from reading uninitialized data */
3677 args->buffer_count = i + 1;
673a394b
EA		 3678 ret = -EBADF;
3679 goto err;
3680 }
b70d11da 3681
23010e43 3682 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3683 if (obj_priv->in_execbuffer) {
3684 DRM_ERROR("Object %p appears more than once in object list\n",
3685 object_list[i]);
0ce907f8
CW		 3686 /* prevent error path from reading uninitialized data */
3687 args->buffer_count = i + 1;
b70d11da
KH		 3688 ret = -EBADF;
3689 goto err;
3690 }
3691 obj_priv->in_execbuffer = true;
6b95a207
KH		 3692 flips += atomic_read(&obj_priv->pending_flip);
3693 }
3694
3695 if (flips > 0) {
3696 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3697 args->buffer_count);
3698 if (ret)
3699 goto err;
ac94a962 3700 }
673a394b 3701
ac94a962
KP		 3702 /* Pin and relocate */
3703 for (pin_tries = 0; ; pin_tries++) {
3704 ret = 0;
40a5f0de
EA		 3705 reloc_index = 0;
3706
ac94a962
KP		 3707 for (i = 0; i < args->buffer_count; i++) {
3708 object_list[i]->pending_read_domains = 0;
3709 object_list[i]->pending_write_domain = 0;
3710 ret = i915_gem_object_pin_and_relocate(object_list[i],
3711 file_priv,
40a5f0de
EA		 3712 &exec_list[i],
3713 &relocs[reloc_index]);
ac94a962
KP		 3714 if (ret)
3715 break;
3716 pinned = i + 1;
40a5f0de 3717 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3718 }
3719 /* success */
3720 if (ret == 0)
3721 break;
3722
3723 /* error other than GTT full, or we've already tried again */
2939e1f5 3724 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3725 if (ret != -ERESTARTSYS) {
3726 unsigned long long total_size = 0;
3727 for (i = 0; i < args->buffer_count; i++)
3728 total_size += object_list[i]->size;
3729 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3730 pinned+1, args->buffer_count,
3731 total_size, ret);
3732 DRM_ERROR("%d objects [%d pinned], "
3733 "%d object bytes [%d pinned], "
3734 "%d/%d gtt bytes\n",
3735 atomic_read(&dev->object_count),
3736 atomic_read(&dev->pin_count),
3737 atomic_read(&dev->object_memory),
3738 atomic_read(&dev->pin_memory),
3739 atomic_read(&dev->gtt_memory),
3740 dev->gtt_total);
3741 }
673a394b
EA		 3742 goto err;
3743 }
ac94a962
KP		 3744
3745 /* unpin all of our buffers */
3746 for (i = 0; i < pinned; i++)
3747 i915_gem_object_unpin(object_list[i]);
b1177636 3748 pinned = 0;
ac94a962
KP		 3749
3750 /* evict everyone we can from the aperture */
3751 ret = i915_gem_evict_everything(dev);
07f73f69 3752 if (ret && ret != -ENOSPC)
ac94a962 3753 goto err;
673a394b
EA		 3754 }
3755
3756 /* Set the pending read domains for the batch buffer to COMMAND */
3757 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3758 if (batch_obj->pending_write_domain) {
3759 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3760 ret = -EINVAL;
3761 goto err;
3762 }
3763 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3764
83d60795
CW		 3765 /* Sanity check the batch buffer, prior to moving objects */
3766 exec_offset = exec_list[args->buffer_count - 1].offset;
3767 ret = i915_gem_check_execbuffer (args, exec_offset);
3768 if (ret != 0) {
3769 DRM_ERROR("execbuf with invalid offset/length\n");
3770 goto err;
3771 }
3772
673a394b
EA		 3773 i915_verify_inactive(dev, __FILE__, __LINE__);
3774
646f0f6e
KP		 3775 /* Zero the global flush/invalidate flags. These
3776 * will be modified as new domains are computed
3777 * for each object
3778 */
3779 dev->invalidate_domains = 0;
3780 dev->flush_domains = 0;
3781
673a394b
EA		 3782 for (i = 0; i < args->buffer_count; i++) {
3783 struct drm_gem_object *obj = object_list[i];
673a394b 3784
646f0f6e 3785 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3786 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3787 }
3788
3789 i915_verify_inactive(dev, __FILE__, __LINE__);
3790
646f0f6e
KP		 3791 if (dev->invalidate_domains | dev->flush_domains) {
3792#if WATCH_EXEC
3793 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3794 __func__,
3795 dev->invalidate_domains,
3796 dev->flush_domains);
3797#endif
3798 i915_gem_flush(dev,
3799 dev->invalidate_domains,
3800 dev->flush_domains);
99fcb766 3801 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
b962442e
EA		 3802 (void)i915_add_request(dev, file_priv,
3803 dev->flush_domains);
646f0f6e 3804 }
673a394b 3805
efbeed96
EA		 3806 for (i = 0; i < args->buffer_count; i++) {
3807 struct drm_gem_object *obj = object_list[i];
23010e43 3808 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3809 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3810
3811 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3812 if (obj->write_domain)
3813 list_move_tail(&obj_priv->gpu_write_list,
3814 &dev_priv->mm.gpu_write_list);
3815 else
3816 list_del_init(&obj_priv->gpu_write_list);
3817
1c5d22f7
CW		 3818 trace_i915_gem_object_change_domain(obj,
3819 obj->read_domains,
3820 old_write_domain);
efbeed96
EA		 3821 }
3822
673a394b
EA		 3823 i915_verify_inactive(dev, __FILE__, __LINE__);
3824
3825#if WATCH_COHERENCY
3826 for (i = 0; i < args->buffer_count; i++) {
3827 i915_gem_object_check_coherency(object_list[i],
3828 exec_list[i].handle);
3829 }
3830#endif
3831
673a394b 3832#if WATCH_EXEC
6911a9b8 3833 i915_gem_dump_object(batch_obj,
673a394b
EA		 3834 args->batch_len,
3835 __func__,
3836 ~0);
3837#endif
3838
673a394b 3839 /* Exec the batchbuffer */
8187a2b7
ZN		 3840 ret = dev_priv->render_ring.dispatch_gem_execbuffer(dev,
3841 &dev_priv->render_ring,
3842 args,
3843 cliprects,
3844 exec_offset);
673a394b
EA		 3845 if (ret) {
3846 DRM_ERROR("dispatch failed %d\n", ret);
3847 goto err;
3848 }
3849
3850 /*
3851 * Ensure that the commands in the batch buffer are
3852 * finished before the interrupt fires
3853 */
3854 flush_domains = i915_retire_commands(dev);
3855
3856 i915_verify_inactive(dev, __FILE__, __LINE__);
3857
3858 /*
3859 * Get a seqno representing the execution of the current buffer,
3860 * which we can wait on. We would like to mitigate these interrupts,
3861 * likely by only creating seqnos occasionally (so that we have
3862 * *some* interrupts representing completion of buffers that we can
3863 * wait on when trying to clear up gtt space).
3864 */
b962442e 3865 seqno = i915_add_request(dev, file_priv, flush_domains);
673a394b 3866 BUG_ON(seqno == 0);
673a394b
EA		 3867 for (i = 0; i < args->buffer_count; i++) {
3868 struct drm_gem_object *obj = object_list[i];
673a394b 3869
ce44b0ea 3870 i915_gem_object_move_to_active(obj, seqno);
673a394b
EA		 3871#if WATCH_LRU
3872 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3873#endif
3874 }
3875#if WATCH_LRU
3876 i915_dump_lru(dev, __func__);
3877#endif
3878
3879 i915_verify_inactive(dev, __FILE__, __LINE__);
3880
673a394b 3881err:
aad87dff
JL		 3882 for (i = 0; i < pinned; i++)
3883 i915_gem_object_unpin(object_list[i]);
3884
b70d11da
KH		 3885 for (i = 0; i < args->buffer_count; i++) {
3886 if (object_list[i]) {
23010e43 3887 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3888 obj_priv->in_execbuffer = false;
3889 }
aad87dff 3890 drm_gem_object_unreference(object_list[i]);
b70d11da 3891 }
673a394b 3892
673a394b
EA		 3893 mutex_unlock(&dev->struct_mutex);
3894
93533c29 3895pre_mutex_err:
40a5f0de
EA		 3896 /* Copy the updated relocations out regardless of current error
3897 * state. Failure to update the relocs would mean that the next
3898 * time userland calls execbuf, it would do so with presumed offset
3899 * state that didn't match the actual object state.
3900 */
3901 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3902 relocs);
3903 if (ret2 != 0) {
3904 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3905
3906 if (ret == 0)
3907 ret = ret2;
3908 }
3909
8e7d2b2c 3910 drm_free_large(object_list);
9a298b2a 3911 kfree(cliprects);
673a394b
EA		 3912
3913 return ret;
3914}
3915
76446cac
JB		 3916/*
3917 * Legacy execbuffer just creates an exec2 list from the original exec object
3918 * list array and passes it to the real function.
3919 */
3920int
3921i915_gem_execbuffer(struct drm_device *dev, void *data,
3922 struct drm_file *file_priv)
3923{
3924 struct drm_i915_gem_execbuffer *args = data;
3925 struct drm_i915_gem_execbuffer2 exec2;
3926 struct drm_i915_gem_exec_object *exec_list = NULL;
3927 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3928 int ret, i;
3929
3930#if WATCH_EXEC
3931 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3932 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3933#endif
3934
3935 if (args->buffer_count < 1) {
3936 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3937 return -EINVAL;
3938 }
3939
3940 /* Copy in the exec list from userland */
3941 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3942 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3943 if (exec_list == NULL || exec2_list == NULL) {
3944 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3945 args->buffer_count);
3946 drm_free_large(exec_list);
3947 drm_free_large(exec2_list);
3948 return -ENOMEM;
3949 }
3950 ret = copy_from_user(exec_list,
3951 (struct drm_i915_relocation_entry __user *)
3952 (uintptr_t) args->buffers_ptr,
3953 sizeof(*exec_list) * args->buffer_count);
3954 if (ret != 0) {
3955 DRM_ERROR("copy %d exec entries failed %d\n",
3956 args->buffer_count, ret);
3957 drm_free_large(exec_list);
3958 drm_free_large(exec2_list);
3959 return -EFAULT;
3960 }
3961
3962 for (i = 0; i < args->buffer_count; i++) {
3963 exec2_list[i].handle = exec_list[i].handle;
3964 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3965 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3966 exec2_list[i].alignment = exec_list[i].alignment;
3967 exec2_list[i].offset = exec_list[i].offset;
3968 if (!IS_I965G(dev))
3969 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3970 else
3971 exec2_list[i].flags = 0;
3972 }
3973
3974 exec2.buffers_ptr = args->buffers_ptr;
3975 exec2.buffer_count = args->buffer_count;
3976 exec2.batch_start_offset = args->batch_start_offset;
3977 exec2.batch_len = args->batch_len;
3978 exec2.DR1 = args->DR1;
3979 exec2.DR4 = args->DR4;
3980 exec2.num_cliprects = args->num_cliprects;
3981 exec2.cliprects_ptr = args->cliprects_ptr;
3982 exec2.flags = 0;
3983
3984 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3985 if (!ret) {
3986 /* Copy the new buffer offsets back to the user's exec list. */
3987 for (i = 0; i < args->buffer_count; i++)
3988 exec_list[i].offset = exec2_list[i].offset;
3989 /* ... and back out to userspace */
3990 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3991 (uintptr_t) args->buffers_ptr,
3992 exec_list,
3993 sizeof(*exec_list) * args->buffer_count);
3994 if (ret) {
3995 ret = -EFAULT;
3996 DRM_ERROR("failed to copy %d exec entries "
3997 "back to user (%d)\n",
3998 args->buffer_count, ret);
3999 }
76446cac
JB		 4000 }
4001
4002 drm_free_large(exec_list);
4003 drm_free_large(exec2_list);
4004 return ret;
4005}
4006
4007int
4008i915_gem_execbuffer2(struct drm_device *dev, void *data,
4009 struct drm_file *file_priv)
4010{
4011 struct drm_i915_gem_execbuffer2 *args = data;
4012 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4013 int ret;
4014
4015#if WATCH_EXEC
4016 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4017 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4018#endif
4019
4020 if (args->buffer_count < 1) {
4021 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4022 return -EINVAL;
4023 }
4024
4025 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4026 if (exec2_list == NULL) {
4027 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4028 args->buffer_count);
4029 return -ENOMEM;
4030 }
4031 ret = copy_from_user(exec2_list,
4032 (struct drm_i915_relocation_entry __user *)
4033 (uintptr_t) args->buffers_ptr,
4034 sizeof(*exec2_list) * args->buffer_count);
4035 if (ret != 0) {
4036 DRM_ERROR("copy %d exec entries failed %d\n",
4037 args->buffer_count, ret);
4038 drm_free_large(exec2_list);
4039 return -EFAULT;
4040 }
4041
4042 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4043 if (!ret) {
4044 /* Copy the new buffer offsets back to the user's exec list. */
4045 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4046 (uintptr_t) args->buffers_ptr,
4047 exec2_list,
4048 sizeof(*exec2_list) * args->buffer_count);
4049 if (ret) {
4050 ret = -EFAULT;
4051 DRM_ERROR("failed to copy %d exec entries "
4052 "back to user (%d)\n",
4053 args->buffer_count, ret);
4054 }
4055 }
4056
4057 drm_free_large(exec2_list);
4058 return ret;
4059}
4060
673a394b
EA		 4061int
4062i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4063{
4064 struct drm_device *dev = obj->dev;
23010e43 4065 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4066 int ret;
4067
4068 i915_verify_inactive(dev, __FILE__, __LINE__);
4069 if (obj_priv->gtt_space == NULL) {
4070 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4071 if (ret)
673a394b 4072 return ret;
22c344e9 4073 }
76446cac 4074
673a394b
EA		 4075 obj_priv->pin_count++;
4076
4077 /* If the object is not active and not pending a flush,
4078 * remove it from the inactive list
4079 */
4080 if (obj_priv->pin_count == 1) {
4081 atomic_inc(&dev->pin_count);
4082 atomic_add(obj->size, &dev->pin_memory);
4083 if (!obj_priv->active &&
21d509e3 4084 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 4085 !list_empty(&obj_priv->list))
4086 list_del_init(&obj_priv->list);
4087 }
4088 i915_verify_inactive(dev, __FILE__, __LINE__);
4089
4090 return 0;
4091}
4092
4093void
4094i915_gem_object_unpin(struct drm_gem_object *obj)
4095{
4096 struct drm_device *dev = obj->dev;
4097 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4098 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4099
4100 i915_verify_inactive(dev, __FILE__, __LINE__);
4101 obj_priv->pin_count--;
4102 BUG_ON(obj_priv->pin_count < 0);
4103 BUG_ON(obj_priv->gtt_space == NULL);
4104
4105 /* If the object is no longer pinned, and is
4106 * neither active nor being flushed, then stick it on
4107 * the inactive list
4108 */
4109 if (obj_priv->pin_count == 0) {
4110 if (!obj_priv->active &&
21d509e3 4111 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4112 list_move_tail(&obj_priv->list,
4113 &dev_priv->mm.inactive_list);
4114 atomic_dec(&dev->pin_count);
4115 atomic_sub(obj->size, &dev->pin_memory);
4116 }
4117 i915_verify_inactive(dev, __FILE__, __LINE__);
4118}
4119
4120int
4121i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4122 struct drm_file *file_priv)
4123{
4124 struct drm_i915_gem_pin *args = data;
4125 struct drm_gem_object *obj;
4126 struct drm_i915_gem_object *obj_priv;
4127 int ret;
4128
4129 mutex_lock(&dev->struct_mutex);
4130
4131 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4132 if (obj == NULL) {
4133 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4134 args->handle);
4135 mutex_unlock(&dev->struct_mutex);
4136 return -EBADF;
4137 }
23010e43 4138 obj_priv = to_intel_bo(obj);
673a394b 4139
bb6baf76
CW		 4140 if (obj_priv->madv != I915_MADV_WILLNEED) {
4141 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4142 drm_gem_object_unreference(obj);
4143 mutex_unlock(&dev->struct_mutex);
4144 return -EINVAL;
4145 }
4146
79e53945
JB		 4147 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4148 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4149 args->handle);
96dec61d 4150 drm_gem_object_unreference(obj);
673a394b 4151 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4152 return -EINVAL;
4153 }
4154
4155 obj_priv->user_pin_count++;
4156 obj_priv->pin_filp = file_priv;
4157 if (obj_priv->user_pin_count == 1) {
4158 ret = i915_gem_object_pin(obj, args->alignment);
4159 if (ret != 0) {
4160 drm_gem_object_unreference(obj);
4161 mutex_unlock(&dev->struct_mutex);
4162 return ret;
4163 }
673a394b
EA		 4164 }
4165
4166 /* XXX - flush the CPU caches for pinned objects
4167 * as the X server doesn't manage domains yet
4168 */
e47c68e9 4169 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4170 args->offset = obj_priv->gtt_offset;
4171 drm_gem_object_unreference(obj);
4172 mutex_unlock(&dev->struct_mutex);
4173
4174 return 0;
4175}
4176
4177int
4178i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4179 struct drm_file *file_priv)
4180{
4181 struct drm_i915_gem_pin *args = data;
4182 struct drm_gem_object *obj;
79e53945 4183 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 4184
4185 mutex_lock(&dev->struct_mutex);
4186
4187 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4188 if (obj == NULL) {
4189 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4190 args->handle);
4191 mutex_unlock(&dev->struct_mutex);
4192 return -EBADF;
4193 }
4194
23010e43 4195 obj_priv = to_intel_bo(obj);
79e53945
JB		 4196 if (obj_priv->pin_filp != file_priv) {
4197 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4198 args->handle);
4199 drm_gem_object_unreference(obj);
4200 mutex_unlock(&dev->struct_mutex);
4201 return -EINVAL;
4202 }
4203 obj_priv->user_pin_count--;
4204 if (obj_priv->user_pin_count == 0) {
4205 obj_priv->pin_filp = NULL;
4206 i915_gem_object_unpin(obj);
4207 }
673a394b
EA		 4208
4209 drm_gem_object_unreference(obj);
4210 mutex_unlock(&dev->struct_mutex);
4211 return 0;
4212}
4213
4214int
4215i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4216 struct drm_file *file_priv)
4217{
4218 struct drm_i915_gem_busy *args = data;
4219 struct drm_gem_object *obj;
4220 struct drm_i915_gem_object *obj_priv;
4221
673a394b
EA		 4222 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4223 if (obj == NULL) {
4224 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4225 args->handle);
673a394b
EA		 4226 return -EBADF;
4227 }
4228
b1ce786c 4229 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4230 /* Update the active list for the hardware's current position.
4231 * Otherwise this only updates on a delayed timer or when irqs are
4232 * actually unmasked, and our working set ends up being larger than
4233 * required.
4234 */
4235 i915_gem_retire_requests(dev);
4236
23010e43 4237 obj_priv = to_intel_bo(obj);
c4de0a5d
EA		 4238 /* Don't count being on the flushing list against the object being
4239 * done. Otherwise, a buffer left on the flushing list but not getting
4240 * flushed (because nobody's flushing that domain) won't ever return
4241 * unbusy and get reused by libdrm's bo cache. The other expected
4242 * consumer of this interface, OpenGL's occlusion queries, also specs
4243 * that the objects get unbusy "eventually" without any interference.
4244 */
4245 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4246
4247 drm_gem_object_unreference(obj);
4248 mutex_unlock(&dev->struct_mutex);
4249 return 0;
4250}
4251
4252int
4253i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4254 struct drm_file *file_priv)
4255{
4256 return i915_gem_ring_throttle(dev, file_priv);
4257}
4258
3ef94daa
CW		 4259int
4260i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4261 struct drm_file *file_priv)
4262{
4263 struct drm_i915_gem_madvise *args = data;
4264 struct drm_gem_object *obj;
4265 struct drm_i915_gem_object *obj_priv;
4266
4267 switch (args->madv) {
4268 case I915_MADV_DONTNEED:
4269 case I915_MADV_WILLNEED:
4270 break;
4271 default:
4272 return -EINVAL;
4273 }
4274
4275 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4276 if (obj == NULL) {
4277 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4278 args->handle);
4279 return -EBADF;
4280 }
4281
4282 mutex_lock(&dev->struct_mutex);
23010e43 4283 obj_priv = to_intel_bo(obj);
3ef94daa
CW		 4284
4285 if (obj_priv->pin_count) {
4286 drm_gem_object_unreference(obj);
4287 mutex_unlock(&dev->struct_mutex);
4288
4289 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4290 return -EINVAL;
4291 }
4292
bb6baf76
CW		 4293 if (obj_priv->madv != __I915_MADV_PURGED)
4294 obj_priv->madv = args->madv;
3ef94daa 4295
2d7ef395
CW		 4296 /* if the object is no longer bound, discard its backing storage */
4297 if (i915_gem_object_is_purgeable(obj_priv) &&
4298 obj_priv->gtt_space == NULL)
4299 i915_gem_object_truncate(obj);
4300
bb6baf76
CW		 4301 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4302
3ef94daa
CW		 4303 drm_gem_object_unreference(obj);
4304 mutex_unlock(&dev->struct_mutex);
4305
4306 return 0;
4307}
4308
ac52bc56
DV		 4309struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4310 size_t size)
4311{
c397b908 4312 struct drm_i915_gem_object *obj;
ac52bc56 4313
c397b908
DV		 4314 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4315 if (obj == NULL)
4316 return NULL;
673a394b 4317
c397b908
DV		 4318 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4319 kfree(obj);
4320 return NULL;
4321 }
673a394b 4322
c397b908
DV		 4323 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4324 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 4325
c397b908 4326 obj->agp_type = AGP_USER_MEMORY;
62b8b215 4327 obj->base.driver_private = NULL;
c397b908
DV		 4328 obj->fence_reg = I915_FENCE_REG_NONE;
4329 INIT_LIST_HEAD(&obj->list);
4330 INIT_LIST_HEAD(&obj->gpu_write_list);
c397b908 4331 obj->madv = I915_MADV_WILLNEED;
de151cf6 4332
c397b908
DV		 4333 trace_i915_gem_object_create(&obj->base);
4334
4335 return &obj->base;
4336}
4337
4338int i915_gem_init_object(struct drm_gem_object *obj)
4339{
4340 BUG();
de151cf6 4341
673a394b
EA		 4342 return 0;
4343}
4344
4345void i915_gem_free_object(struct drm_gem_object *obj)
4346{
de151cf6 4347 struct drm_device *dev = obj->dev;
23010e43 4348 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 4349
1c5d22f7
CW		 4350 trace_i915_gem_object_destroy(obj);
4351
673a394b
EA		 4352 while (obj_priv->pin_count > 0)
4353 i915_gem_object_unpin(obj);
4354
71acb5eb
DA		 4355 if (obj_priv->phys_obj)
4356 i915_gem_detach_phys_object(dev, obj);
4357
673a394b
EA		 4358 i915_gem_object_unbind(obj);
4359
7e616158
CW		 4360 if (obj_priv->mmap_offset)
4361 i915_gem_free_mmap_offset(obj);
de151cf6 4362
c397b908
DV		 4363 drm_gem_object_release(obj);
4364
9a298b2a 4365 kfree(obj_priv->page_cpu_valid);
280b713b 4366 kfree(obj_priv->bit_17);
c397b908 4367 kfree(obj_priv);
673a394b
EA		 4368}
4369
ab5ee576 4370/** Unbinds all inactive objects. */
673a394b 4371static int
ab5ee576 4372i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4373{
ab5ee576 4374 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4375
ab5ee576
CW		 4376 while (!list_empty(&dev_priv->mm.inactive_list)) {
4377 struct drm_gem_object *obj;
4378 int ret;
673a394b 4379
a8089e84
DV		 4380 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4381 struct drm_i915_gem_object,
4382 list)->base;
673a394b
EA		 4383
4384 ret = i915_gem_object_unbind(obj);
4385 if (ret != 0) {
ab5ee576 4386 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4387 return ret;
4388 }
4389 }
4390
673a394b
EA		 4391 return 0;
4392}
4393
29105ccc
CW		 4394int
4395i915_gem_idle(struct drm_device *dev)
4396{
4397 drm_i915_private_t *dev_priv = dev->dev_private;
4398 int ret;
28dfe52a 4399
29105ccc 4400 mutex_lock(&dev->struct_mutex);
1c5d22f7 4401
8187a2b7
ZN		 4402 if (dev_priv->mm.suspended ||
4403 dev_priv->render_ring.gem_object == NULL) {
29105ccc
CW		 4404 mutex_unlock(&dev->struct_mutex);
4405 return 0;
28dfe52a
EA		 4406 }
4407
29105ccc 4408 ret = i915_gpu_idle(dev);
6dbe2772
KP		 4409 if (ret) {
4410 mutex_unlock(&dev->struct_mutex);
673a394b 4411 return ret;
6dbe2772 4412 }
673a394b 4413
29105ccc
CW		 4414 /* Under UMS, be paranoid and evict. */
4415 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4416 ret = i915_gem_evict_from_inactive_list(dev);
4417 if (ret) {
4418 mutex_unlock(&dev->struct_mutex);
4419 return ret;
4420 }
4421 }
4422
4423 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4424 * We need to replace this with a semaphore, or something.
4425 * And not confound mm.suspended!
4426 */
4427 dev_priv->mm.suspended = 1;
4428 del_timer(&dev_priv->hangcheck_timer);
4429
4430 i915_kernel_lost_context(dev);
6dbe2772 4431 i915_gem_cleanup_ringbuffer(dev);
29105ccc 4432
6dbe2772
KP		 4433 mutex_unlock(&dev->struct_mutex);
4434
29105ccc
CW		 4435 /* Cancel the retire work handler, which should be idle now. */
4436 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4437
673a394b
EA		 4438 return 0;
4439}
4440
e552eb70
JB		 4441/*
4442 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4443 * over cache flushing.
4444 */
8187a2b7 4445static int
e552eb70
JB		 4446i915_gem_init_pipe_control(struct drm_device *dev)
4447{
4448 drm_i915_private_t *dev_priv = dev->dev_private;
4449 struct drm_gem_object *obj;
4450 struct drm_i915_gem_object *obj_priv;
4451 int ret;
4452
34dc4d44 4453 obj = i915_gem_alloc_object(dev, 4096);
e552eb70
JB		 4454 if (obj == NULL) {
4455 DRM_ERROR("Failed to allocate seqno page\n");
4456 ret = -ENOMEM;
4457 goto err;
4458 }
4459 obj_priv = to_intel_bo(obj);
4460 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4461
4462 ret = i915_gem_object_pin(obj, 4096);
4463 if (ret)
4464 goto err_unref;
4465
4466 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4467 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4468 if (dev_priv->seqno_page == NULL)
4469 goto err_unpin;
4470
4471 dev_priv->seqno_obj = obj;
4472 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4473
4474 return 0;
4475
4476err_unpin:
4477 i915_gem_object_unpin(obj);
4478err_unref:
4479 drm_gem_object_unreference(obj);
4480err:
4481 return ret;
4482}
4483
8187a2b7
ZN		 4484
4485static void
e552eb70
JB		 4486i915_gem_cleanup_pipe_control(struct drm_device *dev)
4487{
4488 drm_i915_private_t *dev_priv = dev->dev_private;
4489 struct drm_gem_object *obj;
4490 struct drm_i915_gem_object *obj_priv;
4491
4492 obj = dev_priv->seqno_obj;
4493 obj_priv = to_intel_bo(obj);
4494 kunmap(obj_priv->pages[0]);
4495 i915_gem_object_unpin(obj);
4496 drm_gem_object_unreference(obj);
4497 dev_priv->seqno_obj = NULL;
4498
4499 dev_priv->seqno_page = NULL;
673a394b
EA		 4500}
4501
8187a2b7
ZN		 4502int
4503i915_gem_init_ringbuffer(struct drm_device *dev)
4504{
4505 drm_i915_private_t *dev_priv = dev->dev_private;
4506 int ret;
4507 dev_priv->render_ring = render_ring;
4508 if (!I915_NEED_GFX_HWS(dev)) {
4509 dev_priv->render_ring.status_page.page_addr
4510 = dev_priv->status_page_dmah->vaddr;
4511 memset(dev_priv->render_ring.status_page.page_addr,
4512 0, PAGE_SIZE);
4513 }
4514 if (HAS_PIPE_CONTROL(dev)) {
4515 ret = i915_gem_init_pipe_control(dev);
4516 if (ret)
4517 return ret;
4518 }
4519 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4520 return ret;
4521}
4522
4523void
4524i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4525{
4526 drm_i915_private_t *dev_priv = dev->dev_private;
4527
4528 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4529 if (HAS_PIPE_CONTROL(dev))
4530 i915_gem_cleanup_pipe_control(dev);
4531}
4532
673a394b
EA		 4533int
4534i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4535 struct drm_file *file_priv)
4536{
4537 drm_i915_private_t *dev_priv = dev->dev_private;
4538 int ret;
4539
79e53945
JB		 4540 if (drm_core_check_feature(dev, DRIVER_MODESET))
4541 return 0;
4542
ba1234d1 4543 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4544 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4545 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4546 }
4547
673a394b 4548 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4549 dev_priv->mm.suspended = 0;
4550
4551 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4552 if (ret != 0) {
4553 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4554 return ret;
d816f6ac 4555 }
9bb2d6f9 4556
5e118f41 4557 spin_lock(&dev_priv->mm.active_list_lock);
673a394b 4558 BUG_ON(!list_empty(&dev_priv->mm.active_list));
5e118f41
CW		 4559 spin_unlock(&dev_priv->mm.active_list_lock);
4560
673a394b
EA		 4561 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4562 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4563 BUG_ON(!list_empty(&dev_priv->mm.request_list));
673a394b 4564 mutex_unlock(&dev->struct_mutex);
dbb19d30
KH		 4565
4566 drm_irq_install(dev);
4567
673a394b
EA		 4568 return 0;
4569}
4570
4571int
4572i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4573 struct drm_file *file_priv)
4574{
79e53945
JB		 4575 if (drm_core_check_feature(dev, DRIVER_MODESET))
4576 return 0;
4577
dbb19d30 4578 drm_irq_uninstall(dev);
e6890f6f 4579 return i915_gem_idle(dev);
673a394b
EA		 4580}
4581
4582void
4583i915_gem_lastclose(struct drm_device *dev)
4584{
4585 int ret;
673a394b 4586
e806b495
EA		 4587 if (drm_core_check_feature(dev, DRIVER_MODESET))
4588 return;
4589
6dbe2772
KP		 4590 ret = i915_gem_idle(dev);
4591 if (ret)
4592 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4593}
4594
4595void
4596i915_gem_load(struct drm_device *dev)
4597{
b5aa8a0f 4598 int i;
673a394b
EA		 4599 drm_i915_private_t *dev_priv = dev->dev_private;
4600
5e118f41 4601 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b
EA		 4602 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4603 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4604 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b
EA		 4605 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4606 INIT_LIST_HEAD(&dev_priv->mm.request_list);
a09ba7fa 4607 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
007cc8ac
DV		 4608 for (i = 0; i < 16; i++)
4609 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
673a394b
EA		 4610 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4611 i915_gem_retire_work_handler);
4612 dev_priv->mm.next_gem_seqno = 1;
4613
31169714
CW		 4614 spin_lock(&shrink_list_lock);
4615 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4616 spin_unlock(&shrink_list_lock);
4617
de151cf6 4618 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 4619 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4620 dev_priv->fence_reg_start = 3;
de151cf6 4621
0f973f27 4622 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4623 dev_priv->num_fence_regs = 16;
4624 else
4625 dev_priv->num_fence_regs = 8;
4626
b5aa8a0f
GH		 4627 /* Initialize fence registers to zero */
4628 if (IS_I965G(dev)) {
4629 for (i = 0; i < 16; i++)
4630 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4631 } else {
4632 for (i = 0; i < 8; i++)
4633 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4634 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4635 for (i = 0; i < 8; i++)
4636 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4637 }
673a394b 4638 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4639 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4640}
71acb5eb
DA		 4641
4642/*
4643 * Create a physically contiguous memory object for this object
4644 * e.g. for cursor + overlay regs
4645 */
4646int i915_gem_init_phys_object(struct drm_device *dev,
4647 int id, int size)
4648{
4649 drm_i915_private_t *dev_priv = dev->dev_private;
4650 struct drm_i915_gem_phys_object *phys_obj;
4651 int ret;
4652
4653 if (dev_priv->mm.phys_objs[id - 1] || !size)
4654 return 0;
4655
9a298b2a 4656 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4657 if (!phys_obj)
4658 return -ENOMEM;
4659
4660 phys_obj->id = id;
4661
e6be8d9d 4662 phys_obj->handle = drm_pci_alloc(dev, size, 0);
71acb5eb
DA		 4663 if (!phys_obj->handle) {
4664 ret = -ENOMEM;
4665 goto kfree_obj;
4666 }
4667#ifdef CONFIG_X86
4668 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4669#endif
4670
4671 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4672
4673 return 0;
4674kfree_obj:
9a298b2a 4675 kfree(phys_obj);
71acb5eb
DA		 4676 return ret;
4677}
4678
4679void i915_gem_free_phys_object(struct drm_device *dev, int id)
4680{
4681 drm_i915_private_t *dev_priv = dev->dev_private;
4682 struct drm_i915_gem_phys_object *phys_obj;
4683
4684 if (!dev_priv->mm.phys_objs[id - 1])
4685 return;
4686
4687 phys_obj = dev_priv->mm.phys_objs[id - 1];
4688 if (phys_obj->cur_obj) {
4689 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4690 }
4691
4692#ifdef CONFIG_X86
4693 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4694#endif
4695 drm_pci_free(dev, phys_obj->handle);
4696 kfree(phys_obj);
4697 dev_priv->mm.phys_objs[id - 1] = NULL;
4698}
4699
4700void i915_gem_free_all_phys_object(struct drm_device *dev)
4701{
4702 int i;
4703
260883c8 4704 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4705 i915_gem_free_phys_object(dev, i);
4706}
4707
4708void i915_gem_detach_phys_object(struct drm_device *dev,
4709 struct drm_gem_object *obj)
4710{
4711 struct drm_i915_gem_object *obj_priv;
4712 int i;
4713 int ret;
4714 int page_count;
4715
23010e43 4716 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4717 if (!obj_priv->phys_obj)
4718 return;
4719
4bdadb97 4720 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4721 if (ret)
4722 goto out;
4723
4724 page_count = obj->size / PAGE_SIZE;
4725
4726 for (i = 0; i < page_count; i++) {
856fa198 4727 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4728 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4729
4730 memcpy(dst, src, PAGE_SIZE);
4731 kunmap_atomic(dst, KM_USER0);
4732 }
856fa198 4733 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4734 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4735
4736 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4737out:
4738 obj_priv->phys_obj->cur_obj = NULL;
4739 obj_priv->phys_obj = NULL;
4740}
4741
4742int
4743i915_gem_attach_phys_object(struct drm_device *dev,
4744 struct drm_gem_object *obj, int id)
4745{
4746 drm_i915_private_t *dev_priv = dev->dev_private;
4747 struct drm_i915_gem_object *obj_priv;
4748 int ret = 0;
4749 int page_count;
4750 int i;
4751
4752 if (id > I915_MAX_PHYS_OBJECT)
4753 return -EINVAL;
4754
23010e43 4755 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4756
4757 if (obj_priv->phys_obj) {
4758 if (obj_priv->phys_obj->id == id)
4759 return 0;
4760 i915_gem_detach_phys_object(dev, obj);
4761 }
4762
4763
4764 /* create a new object */
4765 if (!dev_priv->mm.phys_objs[id - 1]) {
4766 ret = i915_gem_init_phys_object(dev, id,
4767 obj->size);
4768 if (ret) {
aeb565df 4769 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4770 goto out;
4771 }
4772 }
4773
4774 /* bind to the object */
4775 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4776 obj_priv->phys_obj->cur_obj = obj;
4777
4bdadb97 4778 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4779 if (ret) {
4780 DRM_ERROR("failed to get page list\n");
4781 goto out;
4782 }
4783
4784 page_count = obj->size / PAGE_SIZE;
4785
4786 for (i = 0; i < page_count; i++) {
856fa198 4787 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4788 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4789
4790 memcpy(dst, src, PAGE_SIZE);
4791 kunmap_atomic(src, KM_USER0);
4792 }
4793
d78b47b9
CW		 4794 i915_gem_object_put_pages(obj);
4795
71acb5eb
DA		 4796 return 0;
4797out:
4798 return ret;
4799}
4800
4801static int
4802i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4803 struct drm_i915_gem_pwrite *args,
4804 struct drm_file *file_priv)
4805{
23010e43 4806 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4807 void *obj_addr;
4808 int ret;
4809 char __user *user_data;
4810
4811 user_data = (char __user *) (uintptr_t) args->data_ptr;
4812 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4813
44d98a61 4814 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4815 ret = copy_from_user(obj_addr, user_data, args->size);
4816 if (ret)
4817 return -EFAULT;
4818
4819 drm_agp_chipset_flush(dev);
4820 return 0;
4821}
b962442e
EA		 4822
4823void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4824{
4825 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4826
4827 /* Clean up our request list when the client is going away, so that
4828 * later retire_requests won't dereference our soon-to-be-gone
4829 * file_priv.
4830 */
4831 mutex_lock(&dev->struct_mutex);
4832 while (!list_empty(&i915_file_priv->mm.request_list))
4833 list_del_init(i915_file_priv->mm.request_list.next);
4834 mutex_unlock(&dev->struct_mutex);
4835}
31169714 4836
1637ef41
CW		 4837static int
4838i915_gpu_is_active(struct drm_device *dev)
4839{
4840 drm_i915_private_t *dev_priv = dev->dev_private;
4841 int lists_empty;
4842
4843 spin_lock(&dev_priv->mm.active_list_lock);
4844 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4845 list_empty(&dev_priv->mm.active_list);
4846 spin_unlock(&dev_priv->mm.active_list_lock);
4847
4848 return !lists_empty;
4849}
4850
31169714
CW		 4851static int
4852i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4853{
4854 drm_i915_private_t *dev_priv, *next_dev;
4855 struct drm_i915_gem_object *obj_priv, *next_obj;
4856 int cnt = 0;
4857 int would_deadlock = 1;
4858
4859 /* "fast-path" to count number of available objects */
4860 if (nr_to_scan == 0) {
4861 spin_lock(&shrink_list_lock);
4862 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4863 struct drm_device *dev = dev_priv->dev;
4864
4865 if (mutex_trylock(&dev->struct_mutex)) {
4866 list_for_each_entry(obj_priv,
4867 &dev_priv->mm.inactive_list,
4868 list)
4869 cnt++;
4870 mutex_unlock(&dev->struct_mutex);
4871 }
4872 }
4873 spin_unlock(&shrink_list_lock);
4874
4875 return (cnt / 100) * sysctl_vfs_cache_pressure;
4876 }
4877
4878 spin_lock(&shrink_list_lock);
4879
1637ef41 4880rescan:
31169714
CW		 4881 /* first scan for clean buffers */
4882 list_for_each_entry_safe(dev_priv, next_dev,
4883 &shrink_list, mm.shrink_list) {
4884 struct drm_device *dev = dev_priv->dev;
4885
4886 if (! mutex_trylock(&dev->struct_mutex))
4887 continue;
4888
4889 spin_unlock(&shrink_list_lock);
4890
4891 i915_gem_retire_requests(dev);
4892
4893 list_for_each_entry_safe(obj_priv, next_obj,
4894 &dev_priv->mm.inactive_list,
4895 list) {
4896 if (i915_gem_object_is_purgeable(obj_priv)) {
a8089e84 4897 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 4898 if (--nr_to_scan <= 0)
4899 break;
4900 }
4901 }
4902
4903 spin_lock(&shrink_list_lock);
4904 mutex_unlock(&dev->struct_mutex);
4905
963b4836
CW		 4906 would_deadlock = 0;
4907
31169714
CW		 4908 if (nr_to_scan <= 0)
4909 break;
4910 }
4911
4912 /* second pass, evict/count anything still on the inactive list */
4913 list_for_each_entry_safe(dev_priv, next_dev,
4914 &shrink_list, mm.shrink_list) {
4915 struct drm_device *dev = dev_priv->dev;
4916
4917 if (! mutex_trylock(&dev->struct_mutex))
4918 continue;
4919
4920 spin_unlock(&shrink_list_lock);
4921
4922 list_for_each_entry_safe(obj_priv, next_obj,
4923 &dev_priv->mm.inactive_list,
4924 list) {
4925 if (nr_to_scan > 0) {
a8089e84 4926 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 4927 nr_to_scan--;
4928 } else
4929 cnt++;
4930 }
4931
4932 spin_lock(&shrink_list_lock);
4933 mutex_unlock(&dev->struct_mutex);
4934
4935 would_deadlock = 0;
4936 }
4937
1637ef41
CW		 4938 if (nr_to_scan) {
4939 int active = 0;
4940
4941 /*
4942 * We are desperate for pages, so as a last resort, wait
4943 * for the GPU to finish and discard whatever we can.
4944 * This has a dramatic impact to reduce the number of
4945 * OOM-killer events whilst running the GPU aggressively.
4946 */
4947 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4948 struct drm_device *dev = dev_priv->dev;
4949
4950 if (!mutex_trylock(&dev->struct_mutex))
4951 continue;
4952
4953 spin_unlock(&shrink_list_lock);
4954
4955 if (i915_gpu_is_active(dev)) {
4956 i915_gpu_idle(dev);
4957 active++;
4958 }
4959
4960 spin_lock(&shrink_list_lock);
4961 mutex_unlock(&dev->struct_mutex);
4962 }
4963
4964 if (active)
4965 goto rescan;
4966 }
4967
31169714
CW		 4968 spin_unlock(&shrink_list_lock);
4969
4970 if (would_deadlock)
4971 return -1;
4972 else if (cnt > 0)
4973 return (cnt / 100) * sysctl_vfs_cache_pressure;
4974 else
4975 return 0;
4976}
4977
4978static struct shrinker shrinker = {
4979 .shrink = i915_gem_shrink,
4980 .seeks = DEFAULT_SEEKS,
4981};
4982
4983__init void
4984i915_gem_shrinker_init(void)
4985{
4986 register_shrinker(&shrinker);
4987}
4988
4989__exit void
4990i915_gem_shrinker_exit(void)
4991{
4992 unregister_shrinker(&shrinker);
4993}
Clone of davem's net-next-2.6 tree